THS6302IRHFR

THS6302 THS6302 SBOS746A – JUNE 2016 – REVISED FEBRUARY 2021 SBOS746A – JUNE 2016 – REVISED FEBRUARY 2021 www.ti.com THS6302 Dual Port, G.Fast and G.mgFast DSL Line Driver 1 Features 3 Description • The THS6302 is a dual port, current-feedback architecture, differential line driver designed for G.Fast and a variety of digital subscriber line (DSL) systems. The device is targeted for use in G.Fast digital subscriber line systems that enable native discrete multitone modulation (DMT) signals and supports an 8-dBm line power up to 212 MHz with good linearity. • • • • • • • • • • Designed for G.Fast 106-MHz, 212-MHz DSL Profiles G.mgFast 424-MHz Compatible Supports legacy VDSL and ADSL2+ Applications Excellent MTPR for G.Fast and Legacy Applications (Line Power = 8 dBm): – ADSL2+ = 75 dB – VDSL-17a = 74 dB – VDSL-30a = 70 dB – G.Fast 106-MHz = 60 dB – G.Fast 212-MHz = 48 dB Multiple Power Modes for Different Profiles Adjustable Bias Current with External Resistor Differential Gain: 11 V/V Linear Output Current: 80 mA (Minimum) Low-Power Line Termination Mode: 100 kHz, VDSL2-17a bias mode 3.9 f > 100 kHz, VDSL2-30a bias mode 3.9 f > 100 kHz, G.Fast 106-MHz bias mode 3.7 f > 100 kHz, G.Fast 212-MHz bias mode 3.5 –152.5 Line power = 8 dBm, f ≤ 552 kHz 66 Line power = 8 dBm, f ≤ 1.104 MHz 66 Line power = 8 dBm, f ≤ 2.208 MHz 66 Line power = 8 dBm, f ≤ 14 MHz 72 Line power = 8 dBm, f ≤ 17.6 MHz 72 Line power = 8 dBm, f ≤ 30 MHz 70 Line power = 4 dBm, f ≤ 106 MHz 67 Line power = 8 dBm, f ≤ 106 MHz 58 Line power = 8 dBm, f ≤ 212 MHz, bias 10 dB V/µs f > 100 kHz, ADSL2+ bias mode ADSL2+ bias mode Crosstalk 320 ±0.001 VDSL2-17a bias mode, 4 kHz to 17.6 MHz Output-referred, bias 00 and bias Z0 MHz 50 nV/√ Hz dBm/ Hz dB dB dB dB dB 127 VDSL2-17a bias mode 92 VDSL2-30a bias mode 82 G.Fast 106-MHz bias mode 85 G.Fast 212-MHz bias mode 75 dB Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS6302 5 THS6302 www.ti.com SBOS746A – JUNE 2016 – REVISED FEBRUARY 2021 6.5 Electrical Characteristics (continued) At TA = 25°C, VS pin = 12 V, GND = 0 V, gain = 11 V/V, 100-Ω load, RSERIES = 47.5 Ω, RIREF = 75 kΩ, CIREF = 100 pF, G.Fast 106-MHz bias mode, PAR = 15 dB, and output power measured at input of transformer (1:1) with no assumed transformer insertion losses (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 11 11.5 V/V DC PERFORMANCE AV Differential gain At dc, no load, all modes 10.5 Differential output offset G.Fast 106-MHz bias mode –100 Maximum output swing Differential, at dc, 200-Ω load at amplifier output 18 ADSL2+ bias mode, sourcing, output offset < 20-mV deviation 40 ADSL2+ bias mode, sinking, output offset < 20-mV deviation 40 G.Fast 212-MHz bias mode, sourcing, output offset < 20-mV deviation 80 G.Fast 212-MHz bias mode, sinking, output offset < 20-mV deviation 80 Linear output current 100 mV VPP mA COMMON MODE Input CM bias voltage 5.9 6.0 6.1 V Output CM bias voltage 5.9 6.0 6.1 V POWER SUPPLY PSRR IQ Maximum supply voltage All modes Power-supply rejection ratio f = dc Quiescent current per channel 12.6 60 ADSL2+ bias mode 14.5 16.5 VDSL2 bias mode 19.5 22.0 VDSL2 high-power bias mode 28.0 32.0 G.Fast 106-MHz bias mode 23.0 25.5 G.Fast 106-MHz low-power bias mode 17.8 20.0 G.Fast 212-MHz bias mode 39.0 44.5 9.5 10.5 Line-termination high-power mode Line-termination low-power mode Dynamic power consumption 6 6.3 7.0 Power-down bias mode 1.35 1.7 ADSL2+ bias mode, line power = 8 dBm 219 VDSL2 bias mode, bias Z1 298 G.Fast 106-MHz bias mode, line power = 8 dBm 340 G.Fast 212-MHz bias mode, line power = 8 dBm 525 G.Fast 212-MHz bias mode, line power = 7 dBm 525 Line-termination high-power mode 115 Line-termination low-power mode 77 Power-down bias mode 19 Submit Document Feedback V dB mA mW Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS6302 THS6302 www.ti.com SBOS746A – JUNE 2016 – REVISED FEBRUARY 2021 6.6 Switching Characteristics Over operating free-air temperature range (unless otherwise noted). PARAMETER TEST CONDITIONS MIN VIH Minimum logic high level All digital pins, high VIL Maximum logic low level All digital pins, low VMID Logic mid range All digital pins, driven externally 1.2 VFloat Logic self-bias voltage All digital pins, floating 1.3 IIH Logic high-level leakage current All digital pins, logic level = 3.6 V IIL Logic low-level leakage current All digital pins, logic level = ground Turn-on switching time Turn-off switching time TYP MAX 2.3 –95 UNIT V 0.6 V 1.6 V 1.4 1.5 V 110 135 µA –75 Line-termination mode (bias 00) to G.Fast 212-MHz mode (bias 10) 64 Line-termination mode (bias Z0) to G.Fast 212-MHz mode (bias 10) 50 Power-down mode (bias ZZ) to G.Fast 212-MHz mode (bias 10) 60 G.Fast 212-MHz mode (bias 10) to line-termination mode (bias 00) 76 G.Fast 212-MHz mode (bias 10) to line-termination mode (bias Z0) 400 G.Fast 212-MHz mode (bias 10) to power-down mode (bias ZZ) 380 µA ns ns Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS6302 7 THS6302 www.ti.com SBOS746A – JUNE 2016 – REVISED FEBRUARY 2021 6.7 Typical Characteristics At TA = 25 °C, VS pin = 12 V, GND = 0 V, gain = 11 V/V, 100 Ω Load, RSERIES = 47.5 Ω, PAR = 15 dB, and output power measured at input of transformer (1:1) with no assumed transformer insertion losses (unless otherwise noted). -40 -45 Channel A Channel B -50 -55 -60 -65 -65 -70 25M 50M -75 1M 75M 100M 125M 150M 175M 200M 225M Frequency (Hz) D001 Bias11 Ch. A Bias11 Ch. B -55 -60 -70 1M Bias10 Ch. A Bias10 Ch. B -50 MTPR (dBc) MTPR (dBc) -45 20M Line power = 8 dBm 40M 60M 80M Frequency (Hz) 100M 120M D002 Line power = 8 dBm Figure 6-1. MTPR G.Fast 212-MHz Mode Figure 6-2. MTPR G.Fast 106-MHz Mode -70 -40 Bias01 Ch. A Bias01 Ch. B -45 Bias10 Ch. A Bias10 Ch. B Bias11 Ch. A Bias11 Ch. B BiasZ1 Ch. A BiasZ1 Ch. B Bias1Z Ch. A Bias1Z Ch. B -72 -55 MTPR (dBc) MTPR (dBc) -50 -60 -65 -74 -76 -70 -78 -75 -80 1M -80 20M 40M 60M 80M Frequency (Hz) 100M 1M 120M Line power = 4 dBm Figure 6-3. MTPR G.Fast 106-MHz Mode 15M 20M Frequency (Hz) 25M 30M 35M D004 Figure 6-4. MTPR VDSL-30a Mode -55 BiasZ1 Ch. A BiasZ1 Ch. B Bias1Z Ch. A Bias1Z Ch. B Bias0Z Ch. A Bias0Z Ch. B Bias01 Ch. A Bias01 Ch. B -60 MTPR (dBc) -65 MTPR (dBc) 10M Line power = 8 dBm -60 -70 -75 -65 -70 -80 -75 1M 5M 10M Frequency (Hz) 15M 20M 0.1M D005 Line power = 8 dBm 0.5M 1M 1.5M Frequency (Hz) 2M 2.5M D006 Line power = 8 dBm Figure 6-5. MTPR VDSL-17a Mode 8 5M D003 Figure 6-6. MTPR ADSL2+ Mode Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS6302 THS6302 www.ti.com SBOS746A – JUNE 2016 – REVISED FEBRUARY 2021 6.7 Typical Characteristics (continued) At TA = 25 °C, VS pin = 12 V, GND = 0 V, gain = 11 V/V, 100 Ω Load, RSERIES = 47.5 Ω, PAR = 15 dB, and output power measured at input of transformer (1:1) with no assumed transformer insertion losses (unless otherwise noted). 500 600 106 MHz Bias01 106 MHz Bias11 500 450 400 350 300 200 -10 400 350 300 250 -8 -6 -4 -2 0 2 Tx Power (dBm) 4 6 150 -10 8 -8 -6 -4 D007 Figure 6-7. G.Fast Modes Power Consumption -2 0 2 Tx Power (dBm) 4 6 8 D008 Figure 6-8. xDSL Modes Power Consumption -60 -60 Ch. A-to-B Ch. B-to-A -65 -65 Ch. A-to-B Ch. B-to-A -70 Crosstalk (dB) -70 Crosstalk (dB) VDSL17a Bias1Z VDSL30a BiasZ1 VDSL30a Bias1Z 200 250 -75 -80 -85 -75 -80 -85 -90 -90 -95 -95 -100 -100 1M 10M Frequency (Hz) 100M 1M 100M D010 Figure 6-10. Crosstalk G.Fast 106-MHz Mode -60 -60 -40° C 0° C -62 25° C 50° C 85° C -40° C 0° C -62 25° C 50° C 85° C -64 MTPR (dBc) -64 -66 -68 -66 -68 -70 -70 -72 -72 -74 1M 10M Frequency (Hz) D009 Figure 6-9. Crosstalk G.Fast 212-MHz Mode MTPR (dBc) ADSL2 Bias0Z ADSL2 Bias01 VDSL17a BiasZ1 450 Power Consumption (mW) Power Consumption (mW) 550 106 MHz Bias10 212 MHz Bias10 20M 40M 60M 80M Frequency (Hz) 100M 120M -74 1M D011 G.Fast 106-MHz channel A, line power = 8 dBm 20M 40M 60M 80M Frequency (Hz) 100M 120M D012 G.Fast 106-MHz channel B, line power = 8 dBm Figure 6-11. MTPR vs Temperature Figure 6-12. MTPR vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS6302 9 THS6302 www.ti.com SBOS746A – JUNE 2016 – REVISED FEBRUARY 2021 6.7 Typical Characteristics (continued) At TA = 25 °C, VS pin = 12 V, GND = 0 V, gain = 11 V/V, 100 Ω Load, RSERIES = 47.5 Ω, PAR = 15 dB, and output power measured at input of transformer (1:1) with no assumed transformer insertion losses (unless otherwise noted). 20 Normalized Voltage Gain (dB) Normalized Voltage Gain (dB) 20 0 -20 -40 -60 Bias10 Bias0Z Bias1Z Bias01 0 -20 -40 -60 BiasZ1 Bias11 Bias10 Bias0Z -80 Bias1Z Bias01 BiasZ1 Bias11 -80 1M 10M 100M Frequency (Hz) 1G 1M 10M 100M Frequency (Hz) D013 Figure 6-13. Normalized Small-Signal Frequency Response 1G D014 VOUT = 13 VPP Figure 6-14. Normalized Large-Signal Frequency Response -145 Bias00 BiasZ0 125 100 75 50 25 -147 -148 -149 -150 -151 -152 -153 -154 -155 100k 1M 10M Frequency (Hz) 100M 0 1G Figure 6-15. Terminal Modes Output Impedance 11.5 BiasZ1 Bias11 1.5 10.75 1.25 10.5 1 Sinking 10.25 0.75 10 0 10 20 30 40 50 60 Current (mA) 70 80 90 0.5 100 Bias1Z Bias01 BiasZ1 Bias11 4.2 Sourcing 8.4 4 8.2 3.8 Sinking 8 3.6 7.8 0 10 D017 20 30 40 50 60 Current (mA) 70 80 90 3.4 100 D018 Mid-scale input Full-scale input Figure 6-17. Output Voltage vs Current 10 D016 8.6 Output Sourcing (V) 11 300M 4.4 Bias10 Bias0Z 1.75 Sourcing 250M 8.8 Output Sinking (V) 11.25 Bais1Z Bias01 100M 150M 200M Frequency (Hz) Figure 6-16. Terminal Modes Noise Floor 2 Bias10 Bias0Z 50M D015 Output Sinking (V) 0 10k Ouput Sourcing (V) Bias00 AB BiasZ0 AB Bias00 CD BiasZ0 CD -146 Output Noise at Line (dBm/Hz) Output Impedance Magnitude (:) 150 Figure 6-18. Output Voltage vs Current Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS6302 THS6302 www.ti.com SBOS746A – JUNE 2016 – REVISED FEBRUARY 2021 6.7 Typical Characteristics (continued) At TA = 25 °C, VS pin = 12 V, GND = 0 V, gain = 11 V/V, 100 Ω Load, RSERIES = 47.5 Ω, PAR = 15 dB, and output power measured at input of transformer (1:1) with no assumed transformer insertion losses (unless otherwise noted). 6.6 6.6 Bias10 Bias0Z BiasZ1 Bias11 Bias00 Ch. A Bias00 Ch. B 6.4 Channel A Output Voltage (V) Output Voltage (V) 6.4 Bias1Z Bias01 6.2 6 5.8 5.6 BiasZ0 Ch. A BiasZ0 Ch. B 6.2 6 5.8 5.6 5.4 Channel B -60 -40 -20 0 20 40 Output Current (mA) 60 80 5.2 -100 -80 100 -60 Zero input Figure 6-19. Output Voltage vs Current 1 2 0.5 1.5 0 1 -0.5 0.5 -1 0 60 80 100 120 Time (ns) 140 160 180 Bias Level Voltage (V) 2.5 40 2 0.5 1.5 0 1 -0.5 0.5 -1.5 200 -1 0 0 80 2 0.5 1.5 0 1 -0.5 0.5 -1 0 560 640 Bias mode ZZ to mode 10 Figure 6-23. Mode Switching Time 720 -1.5 800 Quiescent Current per Channel (mA) 1 Output Voltage (V) Bias Level Voltage (V) 2.5 320 400 480 Time (ns) 320 400 480 Time (ns) 560 640 720 -1.5 800 D022 44 Bias Level Signal Differential Output 1.5 240 240 Figure 6-22. Mode Switching Time 2 160 160 Bias mode Z0 to mode 10 Figure 6-21. Mode Switching Time 80 D020 1 D021 3.5 0 100 2.5 Bias mode 00 to mode 10 3 80 2 Bias Level Signal Differential Output 1.5 3 Output Voltage (V) Bias Level Voltage (V) 3.5 Bias Level Signal Differential Output 1.5 20 60 Figure 6-20. Output Voltage vs Current 2 0 -20 0 20 40 Output Current (mA) Terminal modes 3.5 3 -40 D019 Output Voltage (V) 5.4 -100 -80 43 42 41 40 39 38 37 36 35 34 -40 -30 -20 -10 D023 0 10 20 30 40 50 60 70 80 90 Temperature (qC) D024 10 devices, channels A and B, G.Fast 212-MHz bias (mode 10) Figure 6-24. Quiescent Current vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS6302 11 THS6302 www.ti.com SBOS746A – JUNE 2016 – REVISED FEBRUARY 2021 6.7 Typical Characteristics (continued) At TA = 25 °C, VS pin = 12 V, GND = 0 V, gain = 11 V/V, 100 Ω Load, RSERIES = 47.5 Ω, PAR = 15 dB, and output power measured at input of transformer (1:1) with no assumed transformer insertion losses (unless otherwise noted). 24 Quiescent Current per Channel (mA) Quiescent Current per Channel (mA) 28 27 26 25 24 23 22 21 20 19 18 -40 -30 -20 -10 0 Figure 6-25. Quiescent Current vs Temperature 20 19 18 17 16 15 0 10 20 30 40 50 60 70 80 90 Temperature (qC) D026 Figure 6-26. Quiescent Current vs Temperature 14 Quiescent Current per Channel (mA) Quiescent Current per Channel (mA) 21 10 devices, channels A and B, VDSL bias (mode Z1) 20 19 18 17 16 15 14 13 12 11 10 -40 -30 -20 -10 22 14 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 Temperature (qC) D025 10 devices, channels A and B, G.Fast 106-MHz bias (mode 11) 23 0 12 11 10 9 8 7 6 5 4 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 Temperature (qC) D027 10 devices, channels A and B, ADSL bias (mode 0Z) 13 0 10 20 30 40 50 60 70 80 90 Temperature (qC) D028 10 devices, channels A and B, line-termination high-power bias (mode 00) Figure 6-27. Quiescent Current vs Temperature Figure 6-28. Quiescent Current vs Temperature 3 Quiescent Current per Channel (mA) Quiescent Current per Channel (mA) 10 9 8 7 6 5 4 3 2 1 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (qC) D029 10 devices, channels A and B, line-termination low-power bias (mode Z0) Figure 6-29. Quiescent Current vs Temperature 12 2.5 2 1.5 1 0.5 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (qC) D030 10 devices, channels A and B, power-down (mode ZZ) Figure 6-30. Quiescent Current vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS6302 THS6302 www.ti.com SBOS746A – JUNE 2016 – REVISED FEBRUARY 2021 6.7 Typical Characteristics (continued) At TA = 25 °C, VS pin = 12 V, GND = 0 V, gain = 11 V/V, 100 Ω Load, RSERIES = 47.5 Ω, PAR = 15 dB, and output power measured at input of transformer (1:1) with no assumed transformer insertion losses (unless otherwise noted). 1250 Number of Units 1000 750 500 250 0 0 10 20 30 40 Differential Output Offset (mV) 50 60 D032 Figure 6-31. Output Offset Voltage Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS6302 13 THS6302 www.ti.com SBOS746A – JUNE 2016 – REVISED FEBRUARY 2021 7 Detailed Description 7.1 Overview The THS6302 is a dual-port, current-feedback architecture, differential line driver designed for G.Fast and xDSL systems. The device is targeted for use in G.Fast digital subscriber line (DSL) systems that enable native discrete multitone modulation (DMT) signals and supports an 8-dBm line power up to 212 MHz with good linearity. The device consists of a unique architecture consisting of two amplifiers per channel in a noninverting configuration with an internally-fixed gain of 11 V/V. The THS6302 is designed to drive the high-performance G.Fast 212-MHz DSL profile, but is also backwards-comparable to drive lower frequency profiles. The device features selectable bias modes for the G.Fast 106-MHz profile, VDSL profiles, and ADSL profiles. These modes reduce the quiescent current of the device based on the frequency requirements of the various DSL profiles to maximize power efficiency. Along with adjustable bias modes, the device features two line-termination modes that maintain an output impedance match with low power consumption. The line-termination modes allow for the device to be in a low-power state without causing distortion on a shared signal line. For further flexibility, the THS6302 features an IREF pin that is used to further adjust the quiescent current of the device. A resistor connected to this pin can be changed to increase or decrease the device current to meet performance requirements and uses the lowest amount of power possible. 7.2 Functional Block Diagram THS6302 VINA+ VOUTA+ Channel A VOUTAVINAM11, M12 IREF M21, M22 Bias, Control VINB+ VOUTB+ Channel B VOUTBVINB- Copyright © 2016, Texas Instruments Incorporated 14 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS6302 THS6302 www.ti.com SBOS746A – JUNE 2016 – REVISED FEBRUARY 2021 7.3 Feature Description The THS6302 is a dual-channel line driver that has a high current drive and a differential input and output amplifier in each channel. Figure 7-1 shows an example circuit for channel A of the THS6302 configured to drive the G.Fast 212-MHz DSL profile. The bias control pins (M12 and M11) are set to ground and 3.3 V, respectively, to put the device in the G.Fast 212-MHz bias mode. This bias optimizes the internal power consumption of the device to meet performance specifications of the G.Fast 212-MHz profile and can be changed to meet several different DSL profiles and other modes listed in Table 7-1. The IREF pin is biased with a 75-kΩ (RIREF) resistor that adjusts the device quiescent current to a nominal state. RIREF can be increased to lower the quiescent current or deceased to raise the quiescent current of the device for fine-tuning. CIREF provides decoupling for the IREF pin and is typically 100 pF. The THS6302 has a 10-kΩ, internally-set differential input impedance and low output impedance. In Figure 7-1 the input impedance is matched to 100 Ω by using a 100-Ω resistor connected differentially across the inputs. This value can easily be changed by using a different resistor to create the desired impedance at the input. Remember that the impedance in the device is actually the parallel combination of 10 kΩ and the external input resistor. For low impedances, this effect is minimal, but must be considered if the matched input impedance is increased. The output impedance of the THS6302 in Figure 7-1 is set by the two RSERIES resistors to match 100 Ω. The internal output resistance is very low (< 2 Ω per output), so the output impedance is primarily set by the RSERIES resistors. These resistors can be adjusted to match various output impedance values. 12 V 0.1 PF VS M11 M12 3.3 V ½ THS6302 VINA+ 100Differential 100 Input Rseries 47.5 VOUTA- Rseries 47.5 Channel A VINAIREF RIREF 75 k VOUTA+ CIREF 100 pF 1:1 100Differential to Line GND (Thermal Pad) Copyright © 2016, Texas Instruments Incorporated Figure 7-1. G.Fast 212-MHz Driving Mode Example Circuit 7.4 Device Functional Modes The THS6302 features nine different device operational modes to accommodate the G.Fast, xDSL, line termination, and power-down scenarios, as listed in Table 7-1. Each channel of the device is controlled by a 2pin parallel interface that uses three-level logic to control the device state. The G.Fast and xDSL modes change the quiescent current of the device to meet signal performance requirements and maintain the lowest power possible, which allows for legacy DSL compatibility with maximum power efficiency. The two line-termination modes maintain a low impedance at the output when placing the device in a low-power state. The linetermination modes allow for the muxing of multiple devices to one output line by putting the non-driving devices in a state that does not add distortion to the line. A power-down mode is also included to digitally shut down the device for the highest level of power savings. Table 7-1 lists the device power modes and the typical quiescent currents for each mode. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS6302 15 THS6302 www.ti.com SBOS746A – JUNE 2016 – REVISED FEBRUARY 2021 7.5 Programming The THS6302 programming is controlled by two pins for each channel. These pins use three-level logic to create nine different combinations for each pair of pins. The pins have a high state (1) when the pin voltage is greater than 2.3 V, a low state (0) when the pin voltage is less than 0.6 V, and an open state (Z) where the pin floats at approximately 1.4 V or can be driven between 1.2 V and 1.6 V. The pins are labeled Mxy where x is the channel number that the pin is associated with and y is the pin number. Table 7-1 shows the logic combinations for the two pins and the corresponding power modes. Table 7-1. Bias Modes Truth Table BIAS CONTROL PINS Mx1 16 Mx2 BIAS MODE DESCRIPTION TYPICAL QUIESCENT CURRENT 0 0 Line termination, high power 9.5 mA Z 0 Line termination, low power 6.3 mA 1 0 G.Fast 212 MHz 39 mA 0 Z ADSL2+ 14.5 mA Z Z Power down 1.35 mA 1 Z Alternate VDSL (high power) 28.0 mA 0 1 Alternate G.Fast 106 MHz (low power) 17.8 mA Z 1 VDSL 19.5 mA 1 1 G.Fast 106 MHz 23.0 mA Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS6302 THS6302 www.ti.com SBOS746A – JUNE 2016 – REVISED FEBRUARY 2021 8 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 8.1 Application Information THS6302 is a dual-port, very-high-bit-rate linear xDSL, G.Fast, and G.mgFast differential line driver where the device drives a twisted pair cable. The signal is typically generated by a DAC in the DSL ASIC at low signal swings that is amplified by the G.Fast line driver. The G.Fast system is ac-coupled when transmitting information above the audio band. On the input of the line driver, this ac-coupling translates into the series capacitors to isolate the dc voltage coming from the DAC output common-mode voltage. On the output, a transformer is used to help isolate the 48 V present between the tip and ring of the telephone line. The transformer can be set to any useful ratio. In practice, the transformer-turn ratio is set between 1:1 and 1:1.4 for the device. Synthetic impedance at the output of the line driver is common in many xDSL applications. However, to support high AC performance needed for typical G.Fast and G.mgFast applications, THS6302 is an internally fixed-gain device and often synthetic impedance configuration is not recommeded to maintain the AC performance. Note: the resulting load detected by the amplifier may affect the amplifier linearity or output voltage swing capabilities. 8.2 Typical Application Figure 8-1 shows a typical application circuit for THS6302. Only one channel circuit of THS6302 is shown; the other channel is often a duplicate of this channel in most applications. 12 V VS 0.1 PF M11 M12 Digital Inte rface ½ THS6302 VINA+ AWG or DSL ASIC Passive matchin g & filte r ne twork Rse ries VOUTA+ Channel A VINA- IRE F RIREF 75 k CIREF 100 pF 1:n Rse ries Secondary Protection To L ine Loa d VOUTAGND (Thermal Pad ) Figure 8-1. Typical G.Fast Line Driver Configuration Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS6302 17 THS6302 www.ti.com SBOS746A – JUNE 2016 – REVISED FEBRUARY 2021 8.2.1 Design Requirements Table 8-1 provides design requirements for a G.Fast line driver, which is met by the THS6302 device. Table 8-1. Design Requirements PARAMETER CONDITION G.Fast, 212-MHz and 106-MHz transmit profile MTPR information using bias control for line power = 8 dBm and PAR = 15 dB Legacy DSL profile support Yes Supply voltage 12 V Input interface AC coupled Output transformer ratio 1:1 Surge protection External as needed 8.2.2 Detailed Design Procedure The G.Fast signal input to the THS6302 comes from a high-speed DAC in the DSL ASIC whose interleaving spurs are filtered out using either a 3rd- or 5th-order filter. Digital pre-emphasis can be employed in the DAC output such that the differential line driver compensates for the transmission line cable losses at long distance and high frequency. The THS6302 is operated on a 12-V single supply. Resulting from the single-supply operation, the device input is AC-coupled using a capacitor that blocks any DC current flowing out of the inputs to the adjacent circuitry. The AC-coupling capacitor forms a high-pass filter with the device input impedance. This pole must be set at a frequency low enough to not interfere with the desired xDSL or G.Fast signal. The THS6302 differential outputs usually drive a 1:n output transformer with a transformer turns ratio that can be changed depending upon the application. The output transformer selected must have low insertion loss in the desired frequency band in order to maintain good multi-tone power rejection (MTPR) for a given line power. The load is expected to be a transmission line with 100-Ω characteristic impedance on the primary side (line load side) of the transformer. Referred to the transformer secondary, the load seen by the amplifier is 1/n2 with 1:n being the transformer turn ratio. Practical limitations force the transformer-turn ratio to be between 1:1 and 1:1.6. At the lighter load seen by the amplifier (1:1), the voltage swing is limited by the class AB output stage and the maximum achievable swing of the amplifier. At the heaviest load (1:1.6), the voltage swing is limited by the current drive capability of the amplifier. For surge protection, consider adding a gas discharge tube (GDT) on the primary side of the output transformer. The gas discharge tube is required to shunt the large current that could flow through the cables during lightning surge, and protect the device outputs. The secondary protection is also normally added after the series resistance on the secondary transformer side. The secondary protection could be in the form of back to back switching diodes, which also help limit the residual surge current flowing into the device outputs. For the power-supply bypass, consider using X7R or X5R because of the better stability of these materials over temperature. 18 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS6302 THS6302 www.ti.com SBOS746A – JUNE 2016 – REVISED FEBRUARY 2021 8.2.3 Application Performance Plots Figure 8-2 and Figure 8-3 show the MTPR results for 212-MHz and 106-MHz G.Fast profiles, respectivley. -40 -45 Channel A Channel B -50 -50 MTPR (dBc) MTPR (dBc) -45 -55 -60 -65 -65 -70 25M 50M 75M 100M 125M 150M 175M 200M 225M Frequency (Hz) D001 Bias11 Ch. A Bias11 Ch. B -55 -60 -70 1M Bias10 Ch. A Bias10 Ch. B -75 1M 1-in-64 missing tones 20M 40M 60M 80M Frequency (Hz) 100M 120M D002 1-in-64 missing tones Figure 8-2. MTPR G.Fast 212-MHz Figure 8-3. MTPR G.Fast 106-MHz 9 Power Supply Recommendations The THS6302 is recommended to operate using a total supply voltage of 12 V. If a lower or higher supply voltage is required, select one that is between 11.4 V and 12.6 V for optimal performance. Use supply decoupling capacitors on the power-supply pins to minimize distortion caused by parasitic signals on the power supply. This usage is especially important in applications where many devices share a single power-supply bus. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS6302 19 THS6302 www.ti.com SBOS746A – JUNE 2016 – REVISED FEBRUARY 2021 10 Layout 10.1 Layout Guidelines Achieving optimum performance with a high-frequency amplifier such as the THS6302 requires careful attention to board layout parasitics and external component types. Recommendations that optimize performance include: 1. Minimize parasitic capacitance to any ac ground for all signal I/O pins. Excessive parasitic capacitance on the input pin can cause instability. In the line driver application, the parasitic capacitance forms a pole with the load detected by the amplifier and can reduce the effective bandwidth of the application circuit, thus leading to degraded performance. To reduce unwanted capacitance, open a window around the signal I/O pins in all ground and power planes around those pins. Otherwise, make sure that ground and power planes are unbroken elsewhere on the board. 2. Minimize the distance (< 0.25 in.) from the power-supply pins to high-frequency 0.1-µF decoupling capacitors. At the device pins, make sure that the ground and power-plane layout are not in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and decoupling capacitors. Always decouple the power-supply connections with these capacitors. 3. Careful selection and placement of external components preserves the high-frequency performance of the device. Use very-low reactance-type resistors. Surface-mount resistors function best and allow a tighter overall layout. Metal-film or carbon composition, axially-leaded resistors also provide good high-frequency performance. Again, keep the leads and printed circuit board traces as short as possible. Never use wirewound type resistors in a high-frequency application. 4. Connections to other wideband devices on the board can be made with short, direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Use relatively wide traces (50 mils to 100 mils), preferably with ground and power planes opened up around them. 5. Do not socket a high-speed part such as the THS6302. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network that makes achieving a smooth, stable frequency response almost impossible. Best results are obtained by soldering the device onto the board. 10.2 Layout Example Channel A Outputs Differential Inputs Thermal Pad Decoupling Capacitors Channel B Outputs Figure 10-1. Example Layout 20 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS6302 THS6302 www.ti.com SBOS746A – JUNE 2016 – REVISED FEBRUARY 2021 11 Device and Documentation Support 11.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 11.3 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS6302 21 PACKAGE OPTION ADDENDUM www.ti.com 19-Dec-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) THS6302IRHFR ACTIVE VQFN RHF 28 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 THS6302 IRHF (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of