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THS8200
SLES032E – JUNE 2002 – REVISED SEPTEMBER 2014
THS8200 All-Format Oversampled Component Video/PC Graphics D/A System With Three
11-Bit DACs, CGMS Data Insertion
1 Device Overview
1.1
Features
1
• Overall
– Three 11-Bit 205-MSPS Digital-to-Analog
Converters (DACs) With Integrated Bi-Level or
Tri-Level Sync Insertion
– Support for All ATSC Video Formats (Including
1080P) and PC Graphics Formats (up to UXGA
at 75 Hz)
• Input
– Flexible 10-, 15-, 16-, 20-, 24-, or 30-Bit Digital
Video Input Interface With Support for YCbCr or
RGB Data, Either 4:4:4 or 4:2:2 Sampled
– Video Synchronization by Hsync or Vsync
Dedicated Inputs or by Extraction of Embedded
SAV and EAV Codes According to ITU-R.BT601
(SDTV) or SMPTE 274M and SMPTE 296M
(HDTV)
– Glueless Interface to TI DVI 1.0 (With HDCP)
Receivers. Can Receive Video-Over-DVI
Formats According to the EIA-861 Specification
and Convert to YPbPr or RGB Component
Formats With Separate Syncs or Embedded
Composite Sync.
• Video Processing
– Programmable Clip/Shift/Multiply Function for
Operation With Full-Range or ITU-R.BT601
Video Range Input Data
– Programmable Digital Fine-Gain Controller on
Each Analog Output Channel, for Accurate
Channel Matching and Programmable WhiteBalance Control
– Built-In 4:2:2 to 4:4:4 Video Interpolation Filter
– Built-In 2x Oversampling SDTV and HDTV
Interpolation Filter for Improved Video
Frequency Characteristic
– Fully Programmable Digital Color Space
Conversion Circuit
1.2
•
•
– Fully Programmable Display Timing Generator
to Supply All SDTV and HDTV Composite Sync
Timing Formats, Progressive and Interlaced
– Fully Programmable Hsync and Vsync Outputs
– Vertical Blanking Interval (VBI) Override or Data
Pass-Through for VBI Data Transparency
– Programmable CGMS Data Generation and
Insertion
• Output
– Digital
• ITU-R BT.656 Digital Video Output Port
– Analog
• Analog Component Output from SoftwareSwitchable 700-mV or 1.3-V Compliant
Output DACs at 37.5-Ω Load
• Programmable Video/Sync Ratio (7:3 or
10:4)
• Programmable Video Pedestal
• General
– Built-In Video Color Bar Test Pattern Generator
– Fast Mode I2C Control Interface
– Configurable Master or Slave Timing Mode
• Configuration Modes Allow the Device to Act
as a Master Timing Source for Requesting
Data From, for Example, the Video Frame
Buffer (Master Mode Only Available for PC
Graphics Output Modes).
• Alternatively, the Device Can Slave to an
External Timing Master.
– DAC and Chip Power-Down Modes
– Low-Power 1.8-V and 3.3-V Operation
– 80-Pin PowerPAD™ Plastic Quad Flatpack
Package With Efficient Heat Dissipation and
Small Physical Size
Applications
DVD Players
Digital-TV, Interactive-TV, or Internet Set-Top
Boxes
•
•
•
Personal Video Recorders
HDTV Display or Projection Systems
Digital Video Systems
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
THS8200
SLES032E – JUNE 2002 – REVISED SEPTEMBER 2014
1.3
www.ti.com
Description
The THS8200 device is a complete video back-end D/A solution for DVD players, personal video
recorders and set-top boxes, or any system requiring the conversion of digital component video signals
into the analog domain.
The THS8200 device can accept a variety of digital input formats, in 4:4:4 and 4:2:2 formats, over an
interface of three, two, or one 10‑bit ports. The device synchronizes to incoming video data either through
dedicated Hsync and Vsync inputs or through extraction of the sync information from embedded sync
(SAV and EAV) codes inside the video stream. Alternatively, when the THS8200 is configured for
generating PC graphics output, the device also provides a master timing mode in which it requests video
data from an external (memory) source.
The THS8200 device contains a display timing generator that is completely programmable for all standard
and nonstandard video formats up to the maximum supported pixel clock of 205 MSPS. Therefore, the
device supports all component video and PC graphics (VESA) formats. A fully programmable 3x3
matrixing operation is included for color space conversion. All video formats, up to the HDTV 1080I and
720P formats, can also be internally 2x oversampled. Oversampling relaxes the need for sharp external
analog reconstruction filters behind the DAC and improves the video frequency characteristic.
The output compliance range can be set through external adjustment resistors, and there is a choice of
two settings to accommodate both component video or PC graphics (700-mV) and composite video
(1.3‑V) outputs without hardware changes. An internal programmable clip/shift/multiply function on the
video data assures standards-compliant video output ranges for either full 10-bit or reduced ITU-R.BT601
style video input. To avoid nonlinearities after scaling of the video range, the DACs have 11-bit resolution
internally. Furthermore, a bi-level or tri-level sync with programmable amplitude (to support both 700mV:300-mV and 714-mV:286-mV video:sync ratios) can be inserted either on the green/luma channel only
or on all three output channels. This sync insertion is generated from additional current sources in the
DACs such that the full DAC resolution remains available for the video range and preserves 100% of the
11-bit dynamic range of the DAC for video data.
The THS8200 optionally supports the pass-through of ancillary data embedded in the input video stream
or can insert ancillary data into the 525P analog component output according to the CGMS data
specification.
Device Information (1)
PART NUMBER
THS8200PFP
(1)
(2)
2
PACKAGE
BODY SIZE (2)
HTQFP (80)
12 mm x 12 mm
For the most current part, package, and ordering information for all available devices, see the Package
Option Addendum in Section 10, or see the TI web site at www.ti.com.
The package size shown here is nominal. For the package dimensions with tolerances, see the
Mechanical Data in Section 10.
Device Overview
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1.4
SLES032E – JUNE 2002 – REVISED SEPTEMBER 2014
Functional Block Diagram
Figure 1-1 shows the functional block diagram.
digbypass
gy_in
dig_m ux
dg_bias
dly
ifir
D ata M anag er
rcr_in
hs_in
vs_in
Space
ifir
Convertor
ifir
Clip
Scale
dg
Multiplier
ifir
dig_m ux
bcb_in
ifir
Color
4:2:2 to 4:4:4
ifir12_bypass
db_bias
db
ifir35_bypass
dr_bias
dr
sav
Display
T im in g
Generator
eav
scl_in
dtg_data
Three Channel DACs
dr_bias
dg_bias
db_bias
databus_in
scl_out
scl_en
I2C
Slave
sda_in
databus_out
address
addr_en
hs_out
vs_out
cscouts
sda_out
sda_en
ready
Test B lock
csmouts
ifirouts
do[9:0]
dlclko
digbypass
ts tm o d e
arst_func_n
clkin
dmanouts
clk_h
cdrv
2X
cgen
clkin
clk_f
clk_fx2
Clock Generator
Offset Binary Signals
Figure 1-1. Functional Block Diagram
Device Overview
Copyright © 2002–2014, Texas Instruments Incorporated
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THS8200
SLES032E – JUNE 2002 – REVISED SEPTEMBER 2014
www.ti.com
Table of Contents
1
2
3
Device Overview ......................................... 1
6.2
Input Interface Formats
1.1
Features .............................................. 1
6.3
Clock Generator (CGEN)/Clock Driver (CDRV)..... 29
1.2
Applications ........................................... 1
6.4
Color Space Conversion (CSC) ..................... 29
1.3
Description ............................................ 2
6.5
Clip/Shift/Multiplier (CSM) ........................... 31
1.4
Functional Block Diagram ............................ 3
6.6
Interpolating Finite Impulse Response Filter (IFIR) . 34
Revision History ......................................... 4
Terminal Configuration and Functions .............. 5
6.7
Display Timing Generator (DTG) .................... 38
6.8
D/A Conversion...................................... 58
Terminal Functions ................................... 6
6.9
Test Functions
Specifications
6.10
Power Down......................................... 64
4.1
............................................ 8
Absolute Maximum Ratings .......................... 8
Handling Ratings ..................................... 8
Recommended Operating Conditions ................ 8
Power Consumption Summary ....................... 9
Power Supply ....................................... 13
Digital Inputs, DC Characteristics ................... 14
Analog (DAC) Outputs .............................. 15
Nonlinearity .......................................... 16
6.11
CGMS Insertion ..................................... 64
6.12
I2C Interface ......................................... 64
3.1
4
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
9
............................................
63
66
7.1
I2C Register Map .................................... 66
7.2
Register Descriptions................................ 71
7.3
THS8200 Preset Mode Line Type Definitions ....... 84
Application Information ............................... 87
8.1
Video vs Computer Graphics Application ........... 87
8.2
DVI to Analog YPbPr/RGB Application
8.3
Master vs Slave Timing Modes ..................... 88
.............
87
Device and Documentation Support ............... 90
Device Support ...................................... 90
9.2
Documentation Support ............................. 91
9.3
Trademarks.......................................... 91
Functional Overview ................................... 21
9.4
Electrostatic Discharge Caution ..................... 91
Data Manager (DMAN) .............................. 21
9.5
Glossary ............................................. 91
5.1
6
8
I C Registers
......................................
25
9.1
4.11
5
Analog Output Bandwidth (sinx/x corrected) at fS =
205 MSPS ........................................... 19
Output Compliance vs Full-Scale Adjustment
Resistor Value....................................... 19
Vertical Sync of the HDTV 1080I Format Preset in
First and Second Field, and Horizontal Line
Waveform Detail .................................... 20
7
2
.............................
Detailed Functional Description ..................... 24
6.1
Data Manager (DMAN).............................. 24
10 Mechanical, Packaging, and Orderable
Information .............................................. 91
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (February 2010) to Revision E
•
•
•
•
•
•
•
•
•
•
•
4
Page
Renamed Section 1 .................................................................................................................. 1
Added Device Information table and removed Ordering Information table ................................................... 2
Added Section 1.4 and moved functional block diagram to it ................................................................... 3
Corrected typo in I2CA pin name ................................................................................................... 6
Moved and renamed Section 4 ..................................................................................................... 8
Added Section 4.2 and moved Tstg to it ............................................................................................ 8
Moved and renamed Section 4.4 ................................................................................................... 9
Corrected the UNIT for ts and tH parameters .................................................................................... 14
Corrected typo in TYP value of INL with Test Conditions of "Best-fit" and "Video" ........................................ 15
Added Section 9 ..................................................................................................................... 90
Added Section 10 ................................................................................................................... 91
Revision History
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SLES032E – JUNE 2002 – REVISED SEPTEMBER 2014
3 Terminal Configuration and Functions
Figure 3-1 shows the pinout for the PFP package.
RESETB
DVDD
DVSS
GY0
GY1
GY2
GY3
GY4
GY5
GY6
GY7
GY8
GY9
FID
VDD_IO
GND_IO
VS_IN
HS_IN
RCr0
RCr1
PFP PACKAGE
(TOP VIEW)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 464544
HS_OUT
VS_OUT
SDA
SCL
DO9
DO8
DO7
DO6
DO5
VDD_IO
D1CLKO
GND_IO
DO4
DO3
DO2
DO1
DO0
DVSS
DVDD
N.C.
43 42 41
61
40
62
39
63
38
64
37
65
36
66
35
67
34
68
33
69
32
70
31
71
30
72
29
73
28
74
27
75
26
76
25
77
24
78
23
79
22
80
2 3
4 5
6
21
7 8 9 10 11 12 13 14 15 16 17 18 19 20
N.C.
GND_DLL
CLKIN
VDD_DLL
I2CA
PBKG
FSADJ1
FSADJ2
COMP2
COMP1
AVDD
AVSS
AGY
AVDD
ABPb
AVSS
ARPr
AVDD
VDD_IO
GND_IO
1
RCr2
RCr3
RCr4
RCr5
RCr6
RCr7
RCr8
RCr9
DVDD
DVSS
BCb0
BCb1
BCb2
BCb3
BCb4
BCb5
BCb6
BCb7
BCb8
BCb9
Figure 3-1. 80-Pin PFP Package (Top View)
Terminal Configuration and Functions
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THS8200
SLES032E – JUNE 2002 – REVISED SEPTEMBER 2014
3.1
www.ti.com
Terminal Functions
Table 3-1 describes the signals for the device.
Table 3-1. Terminal Functions
TERMINAL
I/O
(1)
DESCRIPTION
NAME
NO.
ABPb
15
O
Analog output of DAC2. See AGY.
ARPr
17
O
Analog output of DAC3. See AGY.
AGY
13
O
Analog output of DAC1. With the proper setting of FSADJ, this output is capable of driving
1.3-V full scale into a 37.5-Ω load.
AVDD
11, 14, 18
PWR
Analog power supply, nominal 3.3 V
AVSS
12, 16
PWR
Analog ground
21 - 30
I
10-bit video data input port. All 10 bits or the 8 MSB of this port can be connected to the video
data source. In 30-bit mode, the B data of RGB, or the Cb data of YCbCr, should be connected
to this port. In 10-bit input mode, this port is unused. In 20-bit input mode, this port is used for
CbCr input data.
CLKIN
3
I
Main clock input. Video input data on the GY[9:0]/BCb[9:0]/RCr[9:0] ports should be
synchronized to CLKIN. Depending on the input data format, CLKIN is supplied to THS8200 at
1x or 2x the pixel clock frequency.
COMP1
10
P
Compensation pin for the internal reference amplifier. A 0.1-µF capacitor should be connected
between COMP1 and analog power supply AVDD.
COMP2
9
P
Compensation pin for the internal reference amplifier. A 0.1-µF capacitor should be connected
between COMP2 and analog power supply AVDD.
D1CLKO
71
O
Video ITU-R.BT656-compliant clock output. This clock output is off by default and should be
activated by an I2C register setting.
DO[9:5]
DO[4:0]
65-69
73-77
O
ITU-R.BT656 compliant video data output port. Only available when ITU-R.BT656 input format
is used. Can be used to connect to external PAL/NTSC video encoder. This port is off by
default and should be activated by an I2C register setting.
DVDD
32, 59, 79
PWR
Digital core power, nominal 1.8 V
DVSS
31, 58, 78
PWR
Digital core ground
47
I
Field identification signal for interlaced video formats. In slave timing mode, this is an input from
the video data source. In master timing mode this signal is unused, as only progressive-scan
VESA formats are supported in master mode.
P
Full scale adjustment control 1. A resistor should be connected between FSADJ1 and analog
ground AGND to control the full-scale output current of the DAC output channels. The
data_fsadj I2C programming register can be used to select between two full-scale ranges,
determined by FSADJ1 or FSADJ2.
For 700-mV video output (1 Vpp including sync), the nominal value is 2.99 kΩ ; for 1.0-Vpp
video output (1.3 Vpp including sync) output the nominal value is 2.08 kΩ.
Full scale adjustment control 2. See FSADJ1.
BCb[9:0]
FID
FSADJ1
7
FSADJ2
8
P
GND_DLL
2
PWR
Ground of clock doubler. Should be connected to analog ground.
GND_IO
20, 45, 72
PWR
I/O ring ground
GY[9:0]
48-57
I
HS_IN
43
I/O
Horizontal source synchronization. In slave timing mode, this is an input from the video data
source. In master timing mode, this is an output to the video data source with programmable
timing and polarity, serving as a horizontal data qualification signal to the video source.
HS_OUT
61
O
Horizontal sync output (to display). Irrespective of slave/master timing mode configuration, this
is always an output with timing generated by the DTG.
I2CA
5
I
I2C device address LSB selection
N.C.
1, 80
I
Manufacturing test input. Must be tied to GND for normal operation.
6
PWR
33-42
I
PBKG (VSS)
RCr[9:0]
(1)
6
10-bit video data input port. All 10 bits or the 8 MSB of this port can be connected to the video
data source. The G data of RGB or the Y data of YCbCr should be connected to this port. Port
used in 10-bit mode for CbYCrY video input data; in 20-bit input mode for Y data.
Substrate ground. Should be connected to analog ground.
10-bit video data input port. All 10-bits or the 8 MSB of this port can be connected to the video
data source. In 30-bit mode, the R data of RGB or the Cr data of YCbCr should be connected to
this port. In the 10- /20-bit input mode, this port is unused. For some input formats this port is
unused.
I = input, O = output, B = bidirectional, PWR = power or ground, P = passive
Terminal Configuration and Functions
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SLES032E – JUNE 2002 – REVISED SEPTEMBER 2014
Table 3-1. Terminal Functions (continued)
TERMINAL
NAME
NO.
I/O
(1)
DESCRIPTION
RESETB
60
I
Software reset pin (active low). The minimum reset duration is 200 ns.
SCL
64
B
Serial clock line of I2C bus interface. Open-collector. Maximum specified clock speed is
400 kHz (fast I2C).
SDA
63
B
Serial data line of I2C bus interface. Open-collector.
VDD_DLL
4
PWR
Power supply of clock doubler, 1.8 V nominal
19, 46, 70
PWR
I/O ring power, 1.8 V or 3.3 V nominal
VS_IN
44
I/O
Vertical source synchronization. In slave timing mode, this is an input from the video data
source. In master timing mode, this is an output to the video data source with programmable
timing and polarity, serving as a vertical data qualification signal to the video source.
VS_OUT
62
O
Vertical sync output (to display). Regardless of slave/master timing mode configuration, this is
always an output with timing generated by the DTG.
VDD_IO
Terminal Configuration and Functions
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SLES032E – JUNE 2002 – REVISED SEPTEMBER 2014
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4 Specifications
4.1
Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)
Supply voltage range
(1)
MIN
MAX
AVDD to AVSS, VDD_IO to GND_IO
−0.5
4.5
V
DVDD to DVSS, VDD_DLL to DVSS
−0.5
2.5
V
−0.5
VDD_IO + 0.5
V
0
70
°C
Digital input voltage range to DVSS
TA
(1)
Operating free-air temperature range
UNIT
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
4.2
Tstg
4.3
Handling Ratings
Storage temperature range
MIN
MAX
UNIT
–55
150
°C
Recommended Operating Conditions
over operating free-air temperature range, TA
MIN
NOM
MAX
3
3.3
3.6
UNIT
POWER SUPPLY
AVDD
Supply voltage
DVDD, VDD_DLL
1.65
1.8
2
VDD_IO
1.65
1.8 or 3.3
3.6
VDD_IO = 1.8 V
0.95
VDD_IO
VDD_IO = 3.3 V
2.3
VDD_IO
VDD_IO = 1.8 V
DVSS
0.4
VDD_IO = 3.3 V
DVSS
1.15
V
DIGITAL AND REFERENCE INPUTS
VIH
High-level input voltage
VIL
Low-level input voltage
fclk
Clock frequency
10
205
tw(CLKH)
Pulse duration, clock high
40%
60%
tw(CLKL)
Pulse duration, clock low
40%
60%
RFS
FSADJ resistor
8
VOC = 700 mV
2.99
VOC = 1 V
2.08
Specifications
V
V
MHz
kΩ
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4.4
SLES032E – JUNE 2002 – REVISED SEPTEMBER 2014
Power Consumption Summary
Table 4-1. Power for 700-mV DAC Output Compliance + 350-mV Bias at AVDD = 3.3 V, DVDD = 1.8 V,
VDD_IO = 3.3 V, VDD_DLL = 3.3 V, 1-MHz Tone on All Channels
f (MHz)
POWER (mW),
DLL BYPASSED
POWER (mW),
DLL USED
IAVDD (mA)
IDVDD (mA)
IVDD_IO (mA)
IVDD_DLL (mA)
20
329.91
332.88
93.2
10.4
1.1
0.9
30
338.52
351.72
93.2
15
1.2
4
80
382.47
399.63
93.2
38.5
1.7
5.2
160
450.51
93.2
75.2
2.3
200
476.01
93.2
89
2.5
500
400
DLL
Bypassed
P - Power - mW
DLL Used
300
200
100
V = 700 mV
VIO = 3.3 V
V(BIAS) = 350 mV
0
20
30
80
160
200
f - Frequency - MHz
Figure 4-1. Power vs Frequency
Specifications
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Table 4-2. Power for 700-mV DAC Output Compliance + 350-mV Bias at AVDD = 3.3 V, DVDD = 1.8 V,
VDD_IO = 1.8 V, VDD_DLL = 3.3 V, 1-MHz Tone on All Channels
f (MHz)
POWER (mW),
DLL BYPASSED
POWER (mW),
DLL USED
IAVDD (mA)
IDVDD (mA)
IVDD_IO (mA)
IVDD_DLL (mA)
20
328.26
331.23
93.2
10.4
1.1
0.9
30
336.72
349.92
93.2
15
1.2
4
397.08
5.2
80
379.92
93.2
38.5
1.7
160
447.06
93.2
75.2
2.3
200
472.26
93.2
89
2.5
500
400
DLL
Bypassed
P - Power - mW
DLL Used
300
200
100
V = 700 mV
VIO = 1.8 V
V(BIAS) = 350 mV
0
20
30
80
160
200
f - Frequency - MHz
Figure 4-2. Power vs Frequency
10
Specifications
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Table 4-3. Power for 1.25-V Output Compliance Without Bias at AVDD = 3.3 V, DVDD = 1.8 V,
VDD_IO = 3.3 V, VDD_DLL = 3.3 V, 1-MHz Tone on All Channels
f (MHz)
POWER (mW),
DLL BYPASSED
POWER (mW),
DLL USED
IAVDD (mA)
IDVDD (mA)
IVDD_IO (mA)
IVDD_DLL (mA)
20
556.95
559.92
162
10.4
1.1
0.9
30
565.56
578.76
162
15
1.2
4
626.67
5.2
80
609.51
162
38.5
1.7
160
677.55
162
75.2
2.3
200
703.05
162
89
2.5
800
700
DLL Bypassed
DLL Used
P - Power - mW
600
500
400
300
200
V = 1.25 V
VIO = 3.3 V
V(BIAS) = 0 V
100
0
20
30
80
160
200
f - Frequency - MHz
Figure 4-3. Power vs Frequency
Specifications
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Table 4-4. Power for 1.25-V Output Compliance Without Bias at AVDD = 3.3 V, DVDD = 1.8 V,
VDD_IO = 1.8 V, VDD_DLL = 3.3 V, 1-MHz Tone on All Channels
f (MHz)
POWER (mW),
DLL BYPASSED
POWER (mW),
DLL USED
IAVDD (mA)
IDVDD (mA)
IVDD_IO (mA)
IVDD_DLL (mA)
20
555.30
558.27
162
10.4
1.1
0.9
30
563.76
576.96
162
15
1.2
4
624.12
5.2
80
606.96
162
38.5
1.7
160
674.10
162
75.2
2.3
200
699.30
162
89
2.5
800
700
DLL Used
P - Power - mW
600
DLL
Bypassed
500
400
300
200
V = 1.25 V
VIO = 1.8 V
V(BIAS) = 0 V
100
0
20
30
80
160
200
f - Frequency - MHz
Figure 4-4. Power vs Frequency
12
Specifications
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4.5
SLES032E – JUNE 2002 – REVISED SEPTEMBER 2014
Power Supply
1-MHz FS ramp simultaneously applied to all three channels
over recommended operating conditions with fCLK = 205 MHz, RFS = RFS(nom) (unless otherwise noted)
PARAMETER
IAVDD
IDVDD
IVDD_IO
IVDD_DLL
PD
Operating analog
supply current
Operating digital
supply current
Operating I/O
supply current
Operating DLL
supply current
Power disspiation
TEST CONDITIONS
MIN
TYP
MAX
94
98
AVDD = 3.3 V, DVDD = 1.8 V,
VDD_DLL = 1.8 V,
VDD_IO = 3.3 V,
CLK = 80 MHz
Video + no bias (700 mV)
94
98
Generic + no bias (1.25 V)
162
170
AVDD = 3.3 V, DVDD = 1.8 V,
VDD_DLL = 1.8 V
(DLL bypassed),
VDD_IO = 1.8 V,
CLK = 200 MHz
Video + no bias (700 mV)
94
98
Video + bias (1.05 V)
94
98
Generic + no bias (1.25 V)
162
170
AVDD = 3.3 V, DVDD = 1.8 V,
VDD_DLL = 1.8 V,
VDD_IO = 3.3 V,
CLK = 80 MHz
Video + no bias (700 mV)
38
45
Video + bias (1.05 V)
38
45
Generic + no bias (1.25 V)
38
45
AVDD = 3.3 V, DVDD = 1.8 V,
VDD_DLL = 1.8 V
(DLL bypassed),
VDD_IO = 1.8 V,
CLK = 200 MHz
Video + no bias (700 mV)
89
95
Video + bias (1.05 V)
89
95
Generic + no bias (1.25 V)
89
95
AVDD = 3.3 V, DVDD = 1.8 V,
VDD_DLL = 1.8 V,
VDD_IO = 3.3 V,
CLK = 80 MHz
Video + no bias (700 mV)
1.7
2.2
Video + bias (1.05 V)
1.7
2.2
Generic + no bias (1.25 V)
1.7
2.2
AVDD = 3.3 V, DVDD = 1.8 V,
VDD_DLL = 1.8 V
(DLL bypassed),
VDD_IO = 1.8 V,
CLK = 200 MHz
Video + no bias (700 mV)
1.7
2.2
Video + bias (1.05 V)
1.7
2.2
Generic + no bias (1.25 V)
1.7
2.2
AVDD = 3.3 V, DVDD = 1.8 V,
VDD_DLL = 1.8 V,
VDD_IO = 3.3 V,
CLK = 80 MHz
Video + no bias (700 mV)
4.9
5.6
Video + bias (1.05 V)
4.9
5.6
Generic + no bias (1.25 V)
4.9
5.6
AVDD = 3.3 V, DVDD = 1.8 V,
VDD_DLL = 1.8 V
(DLL bypassed),
VDD_IO = 1.8 V,
CLK = 200 MHz
Video + no bias (700 mV)
4.9
5.6
Video + bias (1.05 V)
4.9
5.6
Generic + no bias (1.25 V)
4.9
5.6
AVDD = 3.3 V, DVDD = 1.8 V,
VDD_DLL = 1.8 V,
VDD_IO = 3.3 V,
CLK = 80 MHz
Video + no bias (700 mV)
398
430
Video + bias (1.05 V)
398
430
Generic + no bias (1.25 V)
641
660
AVDD = 3.3 V, DVDD = 1.8 V,
VDD_DLL = 1.8 V
(DLL bypassed),
VDD_IO = 1.8 V,
CLK = 200 MHz
Video + no bias (700 mV)
489
500
Video + bias (1.05 V)
489
500
Generic + no bias (1.25 V)
700
735
Video + bias (1.05 V)
Specifications
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UNIT
mA
mA
mA
mA
mW
13
THS8200
SLES032E – JUNE 2002 – REVISED SEPTEMBER 2014
4.6
www.ti.com
Digital Inputs, DC Characteristics
over recommended operating conditions with fCLK = 205 MHz, RFS = RFS(nom) (unless otherwise noted)
PARAMETER
IIH
High-level input current
IIL
Low-level input current
IIL(CLK)
Low-level input current, CLK
IIH(CLK)
High-level input current, CLK
CI
Input capacitance
GY, RCr, BCb data inputs setup time
tH
GY, RCr, BCb data inputs hold time
ts
HS_IN, VS_IN, FID inputs setup time
td(D)
HS_IN, VS_IN, FID inputs hold time
Digital process delay
(2)
(3)
14
TYP
VDD_IO = 3.3 V,
Digital inputs and CLK at 0 V for IIL,
Digital inputs and CLK at 3.6 V for IIH
(2)
5
VDD_IO = 1.8 V
1.5
VDD_IO = 3.3 V
1.5
VDD_IO = 1.8 V
0.5
VDD_IO = 3.3 V
0.5
VDD_IO = 3.3 V
(1)
1.5
VDD_IO = 3.3 V
(1)
0.5
MAX
UNIT
1
µA
−1
µA
1
µA
−1
µA
pF
ns
ns
ns
ns
10-bit/20-bit 4:2:2 with CSM, CSC, 2x
interpolation active
73
(3)
30-bit 4:4:4
33
(3)
VESA clock mode (DLL, CSM, CSC, FIRs
bypassed)
(1)
MIN
TA = 25°C
ts
tH
TEST CONDITIONS
pixels
9
The HS_IN, VS_IN, and FID input setup and hold times are valid for 3.3-V I/O operation only. These sync inputs are not recommended
for use with 1.8-V I/O logic levels.
Defined as the delay on Y pixel data, starting from the rising edge of CLKIN, until the clock period.
CSC contribution: 8 pixels, CSM contribution: 1 pixel, 2x interpolation filter contribution: 18 pixels
Specifications
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4.7
SLES032E – JUNE 2002 – REVISED SEPTEMBER 2014
Analog (DAC) Outputs
over recommended operating conditions with fCLK = 205 MHz, RFS = RFS(nom) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DAC resolution
MIN
TYP
10
(11 bit
internal)
10
(11 bit
internal)
MAX
bits
+0.5/-1.2
+2/-2
Integral nonlinearity
Best-fit
VDD_IO = 3.3 V,
CLK = 500 kHz
Video (0.7 + 0.35 V bias)
INL
Generic (1.25 + 0 V bias)
+1/-2.1
+5/-5
DNL
Differential nonlinearity
VDD_IO = 3.3 V,
CLK = 500 kHz
Video (0.7 + 0.35 V bias)
+0.2/−0.3
+1/−1
Generic (1.25 + 0 V bias)
+0.3/-0.5
+1/−1
PSRR
Power supply ripple
rejection ratio of DAC
output (full scale)
f = dc to 100 kHz
XTALK
KIMBAL
Crosstalk between
channels (2)
Imbalance between DACs
DAC output compliance
voltage (video only)
VOC
(1)
CLK = 205 MHz, -1 dB
sine wave applied to active
channels, offset bias
applied to all channels
when turned on, 37.5-Ω
load on all channels
CLK = 80 MHz
RL = 37.5 Ω
(4)
40
UNIT
LSB
LSB
42
1-MHz sine wave,
offset bias off
49
1-MHz sine wave,
offset bias on
42
10-MHz sine wave,
offset bias off
49
10-MHz sine wave,
offset bias on
42
30-MHz sine wave,
offset bias off
48
30-MHz sine wave,
offset bias on
40.5
dB
dB
(3)
±2%
Video mode (bias offset
can be added)
Generic mode (bias offset
cannot be added)
0.7
0.72
1.25
1.3
V
CO
DAC output capacitance
(pin capacitance)
tri
DAC output current rise
time
10 to 90% of full scale, CLK = 80 MHz
3.5
4.2
ns
tfi
DAC output current fall
time
10 to 90% of full scale, CLK = 80 MHz
3.5
4.2
ns
td
Analog output delay
Measured from falling edge of CLKIN to 50% of fullscale transition (5)
6.5
ns
tsa
Analog output settling time
Measured from 50% of full scale transition on output to
output settling, within 2% (6)
6.6
ns
SFDR
Spurious-free dynamic
range
1 MHz, −1 dB FS digital sine input
-55
10 MHz, −1 dB FS digital sine input
-43
BW
Bandwidth (3 dB)
Eglitch
Glitch energy
(1)
(2)
(3)
(4)
(5)
(6)
5
Full-scale code transition at 205 MSPS
pF
dB
90
MHz
25
pVs
PSRR is defined as 20 × log(ripple voltage at DAC output / ripple voltage at AVDD input). Limits from characterization only.
Crosstalk spec applies to each possible pair of the 3 DAC outputs. Limit from characterization only.
The imbalance between DACs applies to all possible pairs of the three DACs.
Nominal values at RFS = RFS(nom). Limit from characterization only. Excludes bias offset.
This value excludes the digital process delay, tD(D). Limit from characterization only. Data is clocked in on the rising edge of CLKIN.
Analog outputs become available on the falling edge of CLKIN.
Limit from characterization only.
Specifications
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4.8
Nonlinearity
Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) for 700 mV Without Bias
INL - Integral Nonlinearity - LSB
4.8.1
www.ti.com
0.6
V = 700 mV
V(BIAS) = 0 V
0.4
0.2
0.0
0
-0.2
-0.4
-0.6
0
64
128 192 256
320 384
448 512
576 640 704 768
832 896
960 1024
832 896
960 1024
Code
DNL - Differential Nonlinearity - LSB
Figure 4-5. Integral Nonlinearity vs Code
0.3
V = 700 mV
V(BIAS) = 0 V
0.2
0.1
0.0
0
-0.1
-0.2
-0.3
0
64
128 192 256
320 384
448 512
576 640 704 768
Code
Figure 4-6. Differential Nonlinearity vs Code
16
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Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) for 700 mV + 350-mV Bias
INL - Integral Nonlinearity - LSB
4.8.2
SLES032E – JUNE 2002 – REVISED SEPTEMBER 2014
0.8
0.6
0.4
0.2
0.0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
V = 700 mV
V(BIAS) = 350 mV
0
64
128 192 256
320 384
448 512
576 640 704 768
832 896
960 1024
832 896
960 1024
Code
DNL - Differential Nonlinearity - LSB
Figure 4-7. Integral Nonlinearity vs Code
0.3
V = 700 mV
V(BIAS) = 350 mV
0.2
0.1
0.0
0
-0.1
-0.2
-0.3
-0.4
0
64
128 192 256
320 384
448 512
576 640 704 768
Code
Figure 4-8. Differential Nonlinearity vs Code
Specifications
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THS8200
SLES032E – JUNE 2002 – REVISED SEPTEMBER 2014
Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) for 1.25 V Without Bias
INL - Integral Nonlinearity - LSB
4.8.3
www.ti.com
1.0
V = 1.25 V
V(BIAS) = 0 V
0.5
0.0
0
-0.5
-1.0
-1.5
-2.0
0
64
128 192 256
320 384
448 512
576 640 704 768
832 896
960 1024
832 896
960 1024
Code
DNL - Differential Nonlinearity - LSB
Figure 4-9. Integral Nonlinearity vs Code
0.15
0.10
0.05
0.00
0
-0.05
-0.10
-0.15
-0.20
-0.25
V = 1.25 V, V (BIAS) = 0 V
-0.30
0
64
128 192 256
320 384
448 512
576 640 704 768
Code
Figure 4-10. Differential Nonlinearity vs Code
18
Specifications
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4.9
SLES032E – JUNE 2002 – REVISED SEPTEMBER 2014
Analog Output Bandwidth (sinx/x corrected) at fS = 205 MSPS
1
0
-1
-2
Amplitude - dB
-3
-4
-5
-6
-7
-8
-9
fS = 205 MSPS
-10
0
10
20
30
40
50
60 70
80
90 100 110
f(O) - Output Frequency - MHz
Figure 4-11. Amplitude vs Output Frequency
VO - Output Voltage - mV
4.10 Output Compliance vs Full-Scale Adjustment Resistor Value
1300
1250
1200
1150
1100
1050
1000
950
900
850
800
750
700
650
600
550
500
RL = 37.5 Ω
450
V
(BIAS) = 0 V
400
350
1.2 1.7 2.2 2.7
3.2
3.7
4.2
4.7
5.2
5.7
R(fs) - Full Scale Resistance - kW
Figure 4-12. Output Voltage vs Full-Scale Resistance
Specifications
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4.11 Vertical Sync of the HDTV 1080I Format Preset in First and Second Field, and
Horizontal Line Waveform Detail
Vertical Blanking, First Field
Vertical Blanking, Second Field
Active Video Line
Figure 4-13. THS8200 Output Waveforms for 1080I: Vertical Blanking in First and Second Fields, and
Active Video
20
Specifications
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SLES032E – JUNE 2002 – REVISED SEPTEMBER 2014
5 Functional Overview
5.1
Data Manager (DMAN)
The data manager is the block that transforms the selected input video data format present on the chip
input buses to an internal 10-bit three-channel representation. Supported input formats include 10-/8-bit
ITU-R.BT656 with embedded sync codes, 15-/16- or 24-/30-bit RGB with external sync, 20-/16-bit
SMPTE274M/296M with embedded sync codes, as well as 20-/16-bit YCbCr 4:2:2 with external sync. The
user can optionally include a 4:2:2 to 4:4:4 interpolation on the color data path. When a format with
embedded sync is selected, DMAN also extracts H(Hsync), V(Vsync), F(FieldID) identifiers from the ITUR.BT656 (SDTV) or SMPTE274M/296M (HDTV) data stream for internal synchronization of the DTG.
Alternatively, the device synchronizes to HS_IN, VS_IN, FID inputs.
5.1.1
Interpolating Finite Impulse Responses Filter (IFIR)
The interpolating FIR is used to upsample the input data by 2x. In the THS8200 there are five IFIRs. The
first two are used only when the input data is in 4:2:2 format for conversion to a 4:4:4 internal
representation on both color difference channels. The last three IFIRs are used to upsample the internal
data to the DACs on all three channels in case 2x video interpolation is enabled. By 2x oversampling the
video data, the requirements for the analog reconstruction filter at the DAC outputs are relaxed so it can
be built with fewer components, thereby also improving the overall video frequency characteristic (less
group delay variation). All of the IFIRs can be bypassed or switched in by programming the appropriate
I2C registers. The coefficients of all IFIRs are fixed.
5.1.2
Color-Space Conversion (CSC)
The color-space converter block is used to convert input video data in one type of color space to output
video data in another color space (for example, RGB to YCbCr, or YCbCr to RGB). This block contains a
3×3 matrix multiplier/adder and a 3×1 adder. All multiplier and adder coefficients can be programmed
through the I2C interface to support any linear matrixing+offset operation on the video data.
5.1.3
Clip/Shift/Multiplier (CSM)
The clip-shift-multiply block optionally clips the input code range at a programmed low/high code, shifts the
input video data downwards, and multiplies the input by a programmable coefficient in the range 0−1.999.
This allows for operation with a reduced input code range such as prescribed in the ITU-R.BT601
recommendation. Each channel can be independently programmed to accommodate different digital
ranges for each of the three input channels. For example, for standard video signals the Y channel has a
digital input range of 64−940, whereas the two other channels have an input range of 64−960. All three
channels must have a DAC output range of 0−700 mV, so normally the analog voltage corresponding to 1
LSB would have to change to account for the different digital inputs. This might cause matching errors.
Therefore in the THS8200 the DAC LSB does not change; rather LSB conversion is done by scaling the
digital inputs to the DAC's full input range. Furthermore, the CSM output is 11 bits wide and is sent to the
11-bit DACs. The extra bit of resolution resolves nonlinearities introduced by the scaling process. The
clipping function can be switched off to allow for super-white/super-black excursions.
5.1.4
Digital Multiplexer (DIGMUX)
This multiplexer in front of the DACs can select between video signals at 1x or 2x the pixel clock rate. It is
also used to switch in blanking/sync level data generated by the display timing generator (DTG) block and
test pattern data (for example, color bars, I2C-controlled DAC levels) or to perform data insertion (CGMS)
during vertical blanking.
Functional Overview
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5.1.5
www.ti.com
Display Timing Generator (DTG)
The display timing generator is responsible for the generation of the correct frame format including all
sync, equalization and serration pulses. In master timing mode, the DTG is synchronized to external
synchronization inputs, either from the dedicated device terminals HS_IN, VS_IN, and FID or is
synchronized to the identifiers extracted from the input data stream, as selected by the DMAN mode. In
master timing mode, the DTG generates the required field/frame format based on the externally applied
pixel clock input.
When active data is not being passed to the DACs, that is, during the horizontal/vertical blanking intervals,
the DTG generates the correct digital words for blank, sync levels and other level excursions, such as preand post-serration pulses and equalization pulses.
Horizontal timings, as well as amplitudes of negative and positive sync, HDTV broad pulses and SDTV
pre- and post-equalization and serration pulses, are all I2C-programmable to accommodate, for example,
the generation of both EIA.770-1 (10:4 video/sync ratio) and EIA.770-2 (7:3 video/sync ratio) compliant
analog component video outputs, and to support nonstandard video timing formats.
In addition or as an alternative to the composite sync inserted on green/luma channel or all analog
outputs, output video timing can be carried by dedicated Hsync/Vsync output signals as well. The position,
duration and polarity of Hsync and Vsync outputs are fully programmable to support, for example, the
centering of the active video window within the picture frame.
The DTG also controls the data multiplexer in the DIGMUX block. DIGMUX can be programmed to pass
device input data only on active video lines (inserting DTG-generated blanking level during blanking
intervals). Alternatively, the DTG can pass device input data also during some VBI lines (ancillary data in
the input stream is passed transparently on some VBI lines). Finally, the device can also generate its own
ancillary data and insert it into the analog outputs according to the CGMS data format for the 525P video
format.
5.1.6
Clock Generator (CGEN)
The clock generator is an analog delay-locked loop (DLL) based circuit and provides a 2x clock from the
CLKIN input. The 2x clock is used by the CDRV block for 2x video interpolation. Some video formats also
require a 1/2 rate clock used for 4:2:2 to 4:4:4 conversion.
5.1.7
Clock Driver (CDRV)
The clock drive block generates all on-chip clocks. Its inputs are control signals from the digital logic, the
original CLKIN, and the 2x clock from CGEN. Outputs include a half-rate clock, full-rate clock, and a 2x
full-rate clock. The clocks are used for both optional on-chip interpolation processes: 4:2:2 to 4:4:4
interpolation and 1x to 2x video oversampling.
5.1.8
I2C Host Interface (I2CSLAVE)
The I2C interface controls and programs the internal I2C registers. The THS8200 I2C interface
implementation supports the fast I2C specification (SCL: 400 kHz) and allows the writing and reading of
registers. An auto-increment addressing feature simplifies block register programming. The I2C interface
works without a clock present on CLKIN.
5.1.9
Test Block (TST)
The test block controls all the test functions of the THS8200. In addition to manufacturing test modes, this
block contains several user test modes including a DAC internal ramp generator and a 75% SMPTE video
color bar generator.
22
Functional Overview
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5.1.10 D/A Converters (DACs)
THS8200 contains three DACs operating at up to 205 MSPS and with an internal resolution of 11 bits.
Each DAC contains an integrated video sync inserter. The syncs are inserted by means of additional
current source circuits either on the green/luma (Y) channel only or on all the DAC output channels, to be
compliant with both consumer (EIA, sync-on-G/Y) as well as professional (SMPTE, sync-on-all) standards.
The DAC speed supports all ATSC formats, including 1080p, as well as all PC graphics (VESA) formats
up to UXGA at 75 Hz (202.5 MSPS).
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6 Detailed Functional Description
6.1
Data Manager (DMAN)
Table 6-1. Supported Input Formats
INPUT INTERFACE
TIMING CONTROL
SYNCHRONIZATION
EMBEDDED
TIMING
DEDICATED
TIMING
X (4:2:2)
X
X
X
X (4:4:4)
X (4:2:2)
X
X
X
[PRESET]
HDTV-SMPTE274M
progressive (1080I)
X (4:4:4)
X (4:2:2)
X
X
[GENERIC] HDTV
X (4:4:4)
X (4:2:2)
X
X
[PRESET]
SDTV-ITU.1358 (525P)
X (4:4:4)
X (4:2:2)
X
(2)
X
X
(3)
X
[PRESET]
SDTV-ITU-R.BT470
(525I)
X (4:4:4)
X (4:2:2)
X
(4)
X
X
(3)
X
[PRESET]
SDTV-ITU-R.BT470
(625i)
X (4:4:4)
X (4:2:2)
X
(4)
X
X
(3)
X
[GENERIC] SDTV
X (4:4:4)
X (4:2:2)
30 BIT
20 BIT
[PRESET]
HDTV-SMPTE296M
progressive (720P)
X (4:4:4)
[PRESET]
HDTV-SMPTE274M
progressive (1080P)
[PRESET] VESA
(1)
(2)
(3)
(4)
(5)
X
(5)
10 BIT
(1)
16 BIT
15 BIT
X
X
(5)
X
(5)
MASTER
X
X
X
SLAVE
X
X
X
When the device is configured to receive data over a 10-bit interface, the ITU-R.BT656 output bus on the THS8200 can be enabled by
an I2C register bit to send the received data to an external device. In other DMAN modes, this output should remain off (data_tristate656
register).
SMPTE293M-compliant
Dedicated timing not supported with 10-bit interface.
ITU-R.BT656-compliant
Because PC graphics data is normally only 8 bits wide, only 3×8 bits (8 MSBs of each bus) are used. Color space converter bypass is
required for modes with pixel clock > 150 MSPS.
Table 6-1 summarizes all supported video mode configurations.
Each video mode is characterized by three attributes:
• Input Interface: Data is accepted over 10-, 20- or 30-bit interface (or 8- ,16-, 24-bit interface for 8-bit
data when using 8 MSBs of each input data bus and connecting 2 LSBs to ground). This selection is
controlled by the dman_cntl register.
• Timing control: Video timing is either embedded in the data stream or supplied by dedicated timing
signals. In the latter case additional Hsync (HS_IN), Vsync (VS_IN) and FieldID (FID) input signals are
required to synchronize the video data source and THS8200 in the case of slave timing mode. This
selection is controlled by the dtg2_embedded_timing register.
• Synchronization: Video timing either is supplied to the device (slave) or the THS8200 requests video
data from the source (master). This selection is controlled by the chip_ms register.
NOTE
Device operation with combinations of settings for the dman_cntl, dtg2_embedded_timing
and chip_ms registers that result in operating modes not marked in Table 6-1 is not assured.
See detailed register map description for actual register settings.
24
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Furthermore, Table 6-1 shows for which modes presets are defined. When in a preset video mode, the
line-type/breakpoint-pairs that define the frame format (see Section 6.7) are preprogrammed. Therefore
the user does not need to define the table with line type/breakpoint settings, nor does the field and frame
size need to be programmed. However, when in preset mode, the horizontal parameters (all dtg1_spec_x
registers for the line types used by the preset setting, and dtg1_total_pixels registers) still need to be
programmed. Presets are available for most popular DTV video formats. Alternatively, generic modes for
SDTV, HDTV or VESA can be selected, which allow full programmability of the field/frame sizes and DTG
parameters.
Note from the table that:
• If embedded timing is used, the device is always in slave mode, because the data stream supplied to
THS8200 contains the video timing information.
• Master operation is only supported for PC graphics (VESA) formats.
• In HDTV modes with embedded timing, data is supplied to the device over a 20-bit interface, as
defined in SMPTE274/296M.
• In SDTV modes with embedded timing, data is supplied to the device over a 10-bit interface. When the
video format is interlaced, this interface is known as ITU-R.BT656 (525I, 625I). When the video format
is progressive, only 525P is supported with embedded timing. The 625P interface can be supported
with dedicated timing, using the SDTV generic mode.
• In generic modes with dedicated timing, both 20 bits (4:2:2) and 30 bits (4:4:4) are supported.
• In PC graphics modes (VESA generic), input data is either over the 30-bit interface or over the 16-/15bit interface and always has dedicated timing. Note that the 16-bit interface is not equivalent to a 2x8bit version of the 20-bit interface; see Section 6.2 for details.
6.2
Input Interface Formats
The following figures define the input video format for each input mode, as selected by the
data_dman_cntl register setting. Video data is always clocked in at the rising edge of CLKIN.
NOTE
For 8-bit operation with 10-bit input buses, connect only the 8 MSBs of each input bus used,
and tie the 2 LSBs to ground.
•
30-bit YCbCr/RGB 4:4:4
CLKIN
GY[9:0]/[9:2]
G0/Y0
G1/Y1
G2/Y2
G3/Y3
G4/Y4
G5/Y5
G6/Y6
G7/Y7
BCb[9:0]/[9:2]
B0/Cb0 B1/Cb1 B2/Cb2 B3/Cb3 B4/Cb4 B5/Cb5 B6/Cb6 B7/Cb7
RCr[9:0]/[9:2]
R0/Cr0
R1/Cr1
R2/Cr2
R3/Cr3
R4/Cr4
R5/Cr5
R6/Cr6
R7/Cr7
Figure 6-1. 24-/30-Bit RGB or YCbCr Data Format
•
20-bit YCbCr 4:2:2
CLKIN is equal to the 1x pixel clock. The pixel clock equals the rate of the Y input and is 2x the rate of
the 2 other channels in this input format where Cb and Cr are multiplexed onto the same input bus.
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CLKIN
GY[9]
Y7(0)
Y7(1)
Y7(2)
Y7(3)
Y7(0)
Y7(1)
Y7(2)
Y7(3)
GY[8]
Y6(0)
Y6(1)
Y6(2)
Y6(3)
Y6(0)
Y6(1)
Y6(2)
Y6(3)
GY[7]
Y5(0)
Y5(1)
Y5(2)
Y5(3)
Y5(0)
Y5(1)
Y5(2)
Y5(3)
GY[6]
Y4(0)
Y4(1)
Y4(2)
Y4(3)
Y4(0)
Y4(1)
Y4(2)
Y4(3)
GY[5]
Y3(0)
Y3(1)
Y3(2)
Y3(3)
Y3(0)
Y3(1)
Y3(2)
Y3(3)
GY[4]
Y2(0)
Y2(1)
Y2(2)
Y2(3)
Y2(0)
Y2(1)
Y2(2)
Y2(3)
GY[3]
Y1(0)
Y1(1)
Y1(2)
Y1(3)
Y1(0)
Y1(1)
Y1(2)
Y1(3)
GY[2]
Y1(0)
Y1(1)
Y1(2)
Y1(3)
Y1(0)
Y1(1)
Y1(2)
Y1(3)
BCb[9]
Cb7(0)
Cr7(0)
Cb7(2)
Cr7(2)
Cb7(0)
Cb7'(1)
Cb7(2)
Cb7'(3)
BCb[8]
Cb6(0)
Cr6(0)
Cb6(2)
Cr6(2)
Cb6(0)
Cb6'(1)
Cb6(2)
Cb6'(3)
BCb[7]
Cb5(0)
Cr5(0)
Cb5(2)
Cr5(2)
Cb5(0)
Cb5'(1)
Cb5(2)
Cb5'(3)
BCb[6]
Cb4(0)
Cr4(0)
Cb4(2)
Cr4(2)
Cb4(0)
Cb4'(1)
Cb4(2)
Cb4'(3)
BCb[5]
Cb3(0)
Cr3(0)
Cb3(2)
Cr3(2)
Cb3(0)
Cb3'(1)
Cb3(2)
Cb3'(3)
BCb[4]
Cb2(0)
Cr2(0)
Cb2(2)
Cr2(2)
Cb2(0)
Cb2'(1)
Cb2(2)
Cb2'(3)
BCb[3]
Cb1(0)
Cr1(0)
Cb1(2)
Cr1(2)
Cb1(0)
Cb1'(1)
Cb1(2)
Cb1'(3)
BCb[2]
Cb0(0)
Cr0(0)
Cb0(2)
Cr0(2)
Cb0(0)
Cb0'(1)
Cb0(2)
Cb0'(3)
Data Manager
TO CH1
TO CH2
RCr[9]
X
X
X
X
Cr7(0)
Cr7'(1)
Cr7(2)
Cr7'(3)
RCr[8]
X
X
X
X
Cr6(0)
Cr6'(1)
Cr6(2)
Cr6'(3)
RCr[7]
X
X
X
X
Cr5(0)
Cr5'(1)
Cr5(2)
Cr5'(3)
RCr[6]
X
X
X
X
Cr4(0)
Cr4'(1)
Cr4(2)
Cr4'(3)
RCr[5]
X
X
X
X
Cr3(0)
Cr3'(1)
Cr3(2)
Cr3'(3)
RCr[4]
X
X
X
X
Cr2(0)
Cr2'(1)
Cr2(2)
Cr2'(3)
RCr[3]
X
X
X
X
Cr1(0)
Cr1'(0)
Cr1(2)
Cr1'(3)
RCr[2]
X
X
X
X
Cr0(0)
Cr0'(1)
Cr0(2)
Cr0'(3)
TO CH3
Figure 6-2. 20-/16-Bit YCbCr 4:2:2 Data Format (16-Bit Operation Shown)
When dedicated timing is used in this mode, there is a fixed relationship between the first active period
of HS_IN (that is, the first CLKIN rising edge seeing HS_IN active) and a Cb color component
assumed present during that clock period on the bus receiving CbCr samples. When embedded timing
is used in this mode, the SAV/EAV structure also unambiguously defines the CbCr sequence,
according to SMPTE274M/296M for HDTV.
NOTE
The figure shows the case when only 8 bits of each 10-bit input bus are used.
•
26
10-bit YCbCr 4:2:2 (ITU mode)
CLKIN is equal to 2x the pixel clock since all components are multiplexed on a single 10-bit bus with a
4-multiple sequence: CbYCrY. Therefore the pixel clock (that is, the Y input rate) is 1/2 of CLKIN and
the Cb and Cr rate are 1/4 of CLKIN.
When dedicated timing is used in this mode, there is a fixed relationship between the first active period
Detailed Functional Description
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•
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of HS_IN (that is, the first CLKIN rising edge seeing HS active) and a Cb color component assumed
present during that clock period on the input bus. When embedded timing is used in this mode, the
SAV/EAV structure also unambiguously defines the CbCr sequence, according to ITU-R.BT656 (for
625I and 525I) and SMPTE293M (for 525P).
16-bit RGB 4:4:4
CLKIN
GY[9]
R7(0)
R7(1)
R7(2)
R7(3)
G7(0)
G7(1)
G7(2)
G7(3)
GY[8]
R6(0)
R6(1)
R6(2)
R6(3)
G6(0)
G6(1)
G6(2)
G6(3)
GY[7]
R5(0)
R5(1)
R5(2)
R5(3)
G5(0)
G5(1)
G5(2)
G5(3)
GY[6]
R4(0)
R4(1)
R4(2)
R4(3)
G4(0)
G4(1)
G4(2)
G4(3)
GY[5]
R3(0)
R3(1)
R3(2)
R3(3)
G3(0)
G3(1)
G3(2)
G3(3)
GY[4]
G7(0)
G7(1)
G7(2)
G7(3)
G2(0)
G2(1)
G2(2)
G2(3)
GY[3]
G6(0)
G6(1)
G6(2)
G6(3)
0
0
0
0
GY[2]
G5(0)
G5(1)
G5(2)
G5(3)
0
0
0
0
BCb[9]
G4(0)
G4(1)
G4(2)
G4(3)
B7(0)
B7(1)
B7(2)
B7(3)
BCb[8]
G3(0)
G3(1)
G3(2)
G3(3)
B6(0)
B6(1)
B6(2)
B6(3)
BCb[7]
G2(0)
G2(1)
G2(2)
G2(3)
B5(0)
B5(1)
B5(2)
B5(3)
BCb[6]
B7(0)
B7(1)
B7(2)
B7(3)
B4(0)
B4(1)
B4(2)
B4(3)
BCb[5]
B6(0)
B6(1)
B6(2)
B6(3)
B3(0)
B3(1)
B3(2)
B3(3)
BCb[4]
B5(0)
B5(1)
B5(2)
B5(3)
0
0
0
0
BCb[3]
B4(0)
B4(1)
B4(2)
B4(3)
0
0
0
0
BCb[2]
B3(0)
B3(1)
B3(2)
B3(3)
0
0
0
0
RCr[9]
X
X
X
X
R7(0)
R7(1)
R7(2)
R7(3)
RCr[8]
X
X
X
X
R6(0)
R6(1)
R6(2)
R6(3)
RCr[7]
X
X
X
X
R5(0)
R5(1)
R5(2)
R5(3)
RCr[6]
X
X
X
X
R4(0)
R4(1)
R4(2)
R4(3)
RCr[5]
X
X
X
X
R3(0)
R3(1)
R3(2)
R3(3)
RCr[4]
X
X
X
X
0
0
0
0
RCr[3]
X
X
X
X
0
0
0
0
RCr[2]
X
X
X
X
0
0
0
0
Data Manager
TO CH1
TO CH2
TO CH3
•
Figure 6-3. 16-Bit RGB 4:4:4 Data Format
CLKIN is equal to 1x the pixel clock. This format is only supported in VESA mode and can be used for
PC graphics applications that do not require full 8-bit resolution on each color component.
15-bit RGB 4:4:4
Detailed Functional Description
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CLKIN
GY[9]
X
X
X
X
G7(0)
G7(1)
G7(2)
G7(3)
GY[8]
R7(0)
R7(1)
R7(2)
R7(3)
G6(0)
G6(1)
G6(2)
G6(3)
GY[7]
R6(0)
R6(1)
R6(2)
R6(3)
G5(0)
G5(1)
G5(2)
G5(3)
GY[6]
R5(0)
R5(1)
R5(2)
R5(3)
G4(0)
G4(1)
G4(2)
G4(3)
GY[5]
R4(0)
R4(1)
R4(2)
R4(3)
G3(0)
G3(1)
G3(2)
G3(3)
GY[4]
R3(0)
R3(1)
R3(2)
R3(3)
0
0
0
0
GY[3]
G7(0)
G7(1)
G7(2)
G7(3)
0
0
0
0
GY[2]
G6(0)
G6(1)
G6(2)
G6(3)
0
0
0
0
BCb[9]
G5(0)
G5(1)
G5(2)
G5(3)
B7(0)
B7(1)
B7(2)
B7(3)
BCb[8]
G4(0)
G4(1)
G4(2)
G4(3)
B6(0)
B6(1)
B6(2)
B6(3)
BCb[7]
G3(0)
G3(1)
G3(2)
G3(3)
B5(0)
B5(1)
B5(2)
B5(3)
BCb[6]
B7(0)
B7(1)
B7(2)
B7(3)
B4(0)
B4(1)
B4(2)
B4(3)
BCb[5]
B6(0)
B6(1)
B6(2)
B6(3)
B3(0)
B3(1)
B3(2)
B3(3)
BCb[4]
B5(0)
B5(1)
B5(2)
B5(3)
0
0
0
0
BCb[3]
B4(0)
B4(1)
B4(2)
B4(3)
0
0
0
0
BCb[2]
B3(0)
B3(1)
B3(2)
B3(3)
0
0
0
0
RCr[9]
X
X
X
X
R7(0)
R7(1)
R7(2)
R7(3)
RCr[8]
X
X
X
X
R6(0)
R6(1)
R6(2)
R6(3)
RCr[7]
X
X
X
X
R5(0)
R5(1)
R5(2)
R5(3)
RCr[6]
X
X
X
X
R4(0)
R4(1)
R4(2)
R4(3)
RCr[5]
X
X
X
X
R3(0)
R3(1)
R3(2)
R3(3)
RCr[4]
X
X
X
X
0
0
0
0
RCr[3]
X
X
X
X
0
0
0
0
RCr[2]
X
X
X
X
0
0
0
0
Data Manager
TO CH1
TO CH2
TO CH3
Figure 6-4. 15-Bit RGB 4:4:4 Data Format
CLKIN is equal to 1x the pixel clock. This format is only supported in VESA mode and can be used for
PC graphics applications that do not require full 8-bit resolution on each color component.
28
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6.3
SLES032E – JUNE 2002 – REVISED SEPTEMBER 2014
Clock Generator (CGEN)/Clock Driver (CDRV)
The clock generator/clock driver blocks generate all on-chip clocks for 4:2:2 to 4:4:4 and 2x video
oversampling. The DMAN setting controls whether the input data is 4:2:2 or 4:4:4 sampled, and whether a
30-, 20- or 10-bit interface is used. This selection affects the clock input frequency assumed to be present
on CLKIN.
• 30-bit 4:4:4: 1x pixel clock. 4:2:2 to 4:4:4 interpolation should be bypassed. Optional 2x oversampling
is available for formats with pixel clock up to 80 MHz.
• 20-bit 4:2:2: 1x pixel clock. 4:2:2 to 4:4:4 interpolation should be switched in, and is available for
formats with pixel clock up to 150 MHz. Optional 2x oversampling available for formats with pixel clock
up to 80 MHz.
• 10-bit 4:2:2 (ITU): 1/2x pixel clock. 4:2:2 to 4:4:4 interpolation should be switched in, and is available
for formats with pixel clock up to 150 MHz. Optional 2x oversampling is available for formats with pixel
clock up to 80 MHz.
The internal DLL (delay-locked loop) generates the higher clock frequencies. The user should program the
input frequency range selection register, dll_freq_sel, according to the frequency present on CLK_IN when
using either or both interpolation/oversampling stages.
The 4:2:2 to 4:4:4 stage is switched in or bypassed, depending on the setting of data_ifir12_bypass
register (interpolation only on chroma channels). This feature should only be used with YCbCr 4:2:2 input.
The THS8200 can perform color space conversion to RGB depending on the CSC setting. The
dtg2_rgbmode_on register should be set corresponding to the color space representation of the DAC
output.
The 2x oversampling stage is switched in or bypassed, depending on the setting of data_ifir35_bypass
register.
The user should not enable the 2x oversampling stage when the CLK_IN frequency exceeds 80 MHz, as
is the case for the higher PC graphics formats and 1080P HDTV. In this case the DLL should be bypassed
using the vesa_clk register to disable the 2x frequency generation. As explained in the detailed register
map description for this register, it is still possible to support 20-bit 4:2:2 input in this mode (for example,
for 1080P).
A second bypass mode operation exists for the DLL, enabled by the dll_bypass register. When this
bypass mode is active, the CLKIN input is assumed to be 2x pixel frequency.
6.4
Color Space Conversion (CSC)
THS8200 contains a fully-programmable 3×3 multiply/add and 3×1 adder block that can be switched in for
all video formats up to a pixel clock frequency of 150 MHz. Color space conversion is thus available for all
DTV modes, including 1080P and VESA modes up to SXGA at 75 Hz (135 MSPS). The operation is done
after optional 4:2:2 to 4:4:4 conversion, and thus on the 1x pixel clock video data prior to optional 2x video
oversampling. The CSC block can be switched in or bypassed depending on the setting of register
csc_bypass.
Each of the nine floating point multiplier coefficients of the 3×3 multiply/add is represented as the
combination of a 6-bit signed binary integer part, and a 10-bit fractional part. The integer part is a signed
magnitude representation with the MSB as the sign bit. The fractional part is a magnitude representation;
see the following example.
The register nomenclature is: csc_ c where:
• identifies which input channel is multiplied by this coefficient (r = red/Cr, g = green/Y,
b = blue/Cb input).
• identifies the integer (i) or fractional (f) part of the coefficient.
• identifies the output channel from the color space converter: 1 = Yd/Gd, 2 = Cb/Bd, 3 = Cr/Rd.
Detailed Functional Description
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For the offset values, a value of 1/4 of the desired digital offset needs to be programmed in the individual
offset register, so a typical offset of 512 (offset over 1/2 of the video range) requires programming a value
of 128 decimal into the offset registers, where again defines the output channel affected,
with similar convention as shown previously.
Saturation logic can be switched in to avoid overflow and underflow on the result after color space
conversion using the csc_uof_cntl register.
An example of how to program the CSC follows. This also explains the numeric data formats.
CSC configuration example: HDTV RGB to HDTV YCbCr
The formulas for RGB to YCbCr conversion are:
• Yd = 0.2126 × Rd + 0.7152 × Gd + 0.0722 × Bd
• Cb = −0.1172 × Rd – 0.3942 × Gd + 0.5114 × Bd + 512
• Cr = 0.5114 × Rd – 0.4646 × Gd – 0.0468 × Bd + 512
To
1.
2.
3.
program the red coefficient of channel 1 (Y) with the value of 0.2126 the following must be done:
Realize that this is a positive value so the sign bit of the integer part is 0 (bit 5 of csc_ric1 = 0).
Note that there is no integer portion of the coefficient (bit 4−bit 0 = 00000).
The binary representation of the fractional part can be constructed directly from the binary equivalent
of the fractional part multiplied by 1024 (0.2126 × 1024 = 217.7), rounded to the nearest integer (218)
and represented as a binary 10-bit number (00 1101 1010).
Using the above method all the registers for the CSC blocks can be programmed with the correct value for
RGB to YCbCr conversion. Below is a complete list of register values for the above conversion.
0.2126 → csc_ric1 = 00 0000
csc_rfc1 = 00 1101 1010
0.7152 → csc_gic1 = 00 0000
csc_gfc1 = 10 1101 1100
0.0722 → csc_bic1 = 00 0000
csc_bfc1 = 00 0100 1010
−0.1172 → csc_ric2 = 10 0000
csc_rfc2 = 00 0111 1000
−0.3942 → csc_gic2 = 10 0000
csc_gfc2 = 01 1001 0100
0.5114 → csc_bic2 = 00 0000
csc_bfc2 = 10 0000 1100
0.5114 → csc_ric3 = 00 0000
csc_rfc3 = 10 0000 1100
−0.4646 → csc_gic3 = 10 0000
csc_gfc3 = 01 1101 1100
−0.0468 → csc_bic3 = 10 0000
csc_bfc3 = 00 0011 0000
For the offsets necessary in the second and third equation, the csc_offset registers need to be
programmed. Add 512 to the Cb and Cr channels. The value to be programmed is 1/4 of this offset in a
signed magnitude representation, thus 128 or csc_offset2 = csc_offset3 = 00 1000 0000.
Packing these individual registers into the I2C register map, the programmed values are:
30
SUBADDRESS
REGISTER NAME
VALUE
0x04
csc_r11
0000 0000
0x05
csc_r12
1101 1010
0x06
csc_r21
1000 0000
0x07
csc_r22
0111 1000
0x08
csc_r31
0000 0010
0x09
csc_r32
0000 1100
0x0A
csc_g11
0000 0010
0x0B
csc_g12
1101 1100
0x0C
csc_g21
1000 0001
0x0D
csc_g22
1001 0100
Detailed Functional Description
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SUBADDRESS
REGISTER NAME
VALUE
0x0E
csc_g31
1000 0001
0x0F
csc_g32
1101 1100
0x10
csc_b11
0000 0000
0x11
csc_b12
0100 1010
0x12
csc_b21
0000 0010
0x13
csc_b22
0000 1100
0x14
csc_b31
1000 0000
0x15
csc_b32
0011 0000
0x16
csc_offs1
0000 0000
0x17
csc_offs12
0000 1000
0x18
csc_offs23
0000 0010
0x19
csc_offs3
0000 0000
CSC configuration example: HDTV YCbCr to HDTV RGB
• Gd = –0.4577 × Cr + Yd – 0.1831 × Cb +328 (= 0.6408 × 128 × 4)
• Bd = 0 × Cr + Yd + 1.8142 × Cb – 929 (= −1.8142 × 128 × 4)
• Rd = 1.5396 × Cr +Yd +0 × Cb – 788 (= −1.5396 × 128 × 4)
In a similar manner, it can be calculated that the programming array is in this case:
6.5
SUBADDRESS
REGISTER NAME
VALUE
0x04
csc_r11
1000 0001
0x05
csc_r12
1101 0101
0x06
csc_r21
0000 0000
0x07
csc_r22
0000 0000
0x08
csc_r31
0000 0110
0x09
csc_r32
0010 1001
0x0A
csc_g11
0000 0100
0x0B
csc_g12
0000 0000
0x0C
csc_g21
0000 0100
0x0D
csc_g22
1000 0000
0x0E
csc_g31
0000 0100
0x0F
csc_g32
0000 0000
0x10
csc_b11
1000 0000
0x11
csc_b12
1011 1011
0x12
csc_b21
0000 0111
0x13
csc_b22
0100 0010
0x14
csc_b31
0000 0000
0x15
csc_b32
0000 0000
0x16
csc_offs1
0001 0100
0x17
csc_offs12
1010 1110
0x18
csc_offs23
1000 1011
0x19
csc_offs3
0001 0100
Clip/Shift/Multiplier (CSM)
There are limits on the code range of the video data if sampled according to ITU or SMPTE standards. In
other words, the full 10-bit range [0:1023] is not used to represent video pixels. For example, typically 64
decimal is the lowest code allowed to represent a video signal and corresponds to the blanking level.
Similarly for Y, typically the maximum code is 940 decimal. Excursions outside this range can be the result
of digital video processing.
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THS8200 can handle such instantaneous excursions in either of two ways: by limiting the input codes to
programmable max/min values, or by allowing such excursions to occur.
Depending on which approach is chosen, the user can scale up the video data in the CSM to make sure
the full-scale dynamic range of the DAC is used for optimal performance when using limiting. Alternatively,
the instantaneous excursions outside the code range can be output by the DAC in the analog output
signal (allowing super-white/black in analog output) when this clipping is disabled.
The CSM block allows the user to specify the behavior of THS8200 with such reduced-swing input video
codes. It consists of the following:
1. An optional clipping of the input video data at a high and low limit, where the limits are individually
programmable per channel.
2. A downward shift of the input video data, where the shift amount is individually programmable per
channel.
3. A multiply (magnitude scaling) function of the video data, where the multiplier coefficient is individually
programmable per channel.
6.5.1
Clipping
Clipping (limiting) of the video input data can be turned on or off on a per-channel basis, and selectively at
the high and/or low end, by programming the csm___clip_on registers. The
high/low clipping values can be programmed on a per-channel basis using registers
csm_clip__.
Figure 6-5 shows a typical situation to clip ITU-R.BT601 sampled video signals.
Ramping Analog Output With Clipping Effect on Top and Bottom
817.3 mV
Analog Output From DACs
751.1 mV
Output After
Clipping
Output Before
Clipping
51.1 mV
0 64
255
511
767
940
1023
Input Digital Codes
Figure 6-5. Effect of Clipping on Analog Output
6.5.2
Shifting
Next the video data can be shifted over a programmable amount downward. The number of codes over
which to shift the input video data is set per channel by programming csm_shift_. Shifting of
the input video data can be done downwards over 0..255 codes inside the CSM.
32
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Ramping Analog Output With Clipping Effect on Top and Bottom
817.3 mV
Analog Output From DACs
751.1 mV
700.0 mV
Output After
Clipping
Output After
Clipping and
Shifting
51.1 mV
0 64
255
511
767
876 940
1023
Input Digital Codes
Figure 6-6. Effect of Shifting on Clipped Analog Output
Figure 6-5 and Figure 6-6 also show the analog output from the DAC if the full-scale video range over the
[64..940] input would correspond to the normal 700-mV range for component video. This full-scale range
is set by the selected FSADJ full-scale setting (register data_fsadj).
6.5.3
Multiplying
When the 10-bit range is not fully used for video, scale the input video data to use the full 10-bit dynamic
range of the DACs. Care should be taken not to overflow/underflow the available range after scaling.
This multiplying control serves two purposes:
• Use of the full 10-bit DAC range for inputs of reduced range.
• Individual fine gain control per channel to compensate for gain errors and provide white balance
control.
Ramping Analog Output With 1:1.1 AC Range Fine Scaling
817.3 mV
770.0 mV
Analog Output From DACs
700.0 mV
Range After
Scaling Up 1:1.1
DC Shifted
Original AC Range
0
255
511
767
876
1023
964
Input Digital Codes
Figure 6-7. Effect of Scaling the Analog Video Output
Detailed Functional Description
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Figure 6-7 illustrates a shifted analog ramping output. The multiplication factor could be calculated to scale
this output range to the full 10-bit range of the DAC. Note that this scaling can be programmed individually
per channel using registers csm_mult_. The range of the multiplication is 0..1.999, coded as a
binary weighted 11-bit value, thus: csm_mult_ = (Desired scale ( 0 to 1.999) / 1.999) × 2047.
Note that this approach allows to scale input code ranges that are different on each channel to an identical
full-scale DAC output compliance, as is required for ITU-R.BT601 sampled signals where Y video data is
represented in the range [64..940] and both Cb,Cr color difference channels are coded within the range
[64..960]. All three channels need to generate a 700-mV nominal analog output compliance. Using a
combination of FSADJ—adjusting the full-scale current of all DAC channels simultaneously in the analog
domain—and digital CSM control, different trade-offs can be made for DAC output amplitude control,
including channel matching.
As discussed in Section 6.7, the user also controls the DAC output levels during blanking, negative and
positive sync, pre- and post-equalization, and serration pulses. Using a combination of CSM and DTG
programming, it is therefore possible to accommodate many video standards, including those that require
a video blank-to-black level setup, as well as differing video/sync ratios (for example, 10:4 or 7:3).
Finally, using the selectable full-scale adjustment from the FSADJ1 or FSADJ2 terminals, it is possible to
switch between two analog output compliance settings with no hardware changes.
Physically, the CSM output is represented internally as an 11-bit value to improve the DAC linearity at the
10-bit level after scaling. Each DAC internally is of 11-bit resolution.
6.6
Interpolating Finite Impulse Response Filter (IFIR)
For relaxing the requirements of the reconstruction filter behind the DAC in the analog domain, and to take
advantage of the high-speed capability of the DACs in THS8200, a 2x digital up-sampling and
interpolation filter module is integrated.
Figure 6-8 through Figure 6-11 show the YRGB and CbCr filtering requirements for HDTV
(SMPTE274M/296M standards) and SDTV (ITU-R.BT601 standard), respectively.
1+ d
1
1- d
M ag n itu d e
-6 dB
-40 dB
-50 dB
0.20 fs
0.25 fs
0.30 fs
0.37 fs
Frequency
NOTE: δ = 0.05 dB. fs=74.25 MSPS for 1080I and 720P HDTV formats.
Figure 6-8. PB and PR Filter Requirements Based on SMPTE 296M/274M
34
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1+ d
1
1- d
M ag n itu d e
-12 dB
40 dB
50 dB
0.40 fs
0.50 fs
0.60 fs
0.73 fs
Frequency
NOTE: δ = 0.05 dB. fs=74.25 MSPS for 1080I and 720P HDTV formats.
Figure 6-9. Y and RGB Filter Requirements Based on SMPTE 296M/274M
1+ d
1
1- d
M ag n itu d e
-12 dB
-40 dB
5.75
6.75
8.0
Frequency (MHz)
NOTE: δ = 0.05 dB
Figure 6-10. Y and RGB Filter Requirements Based on ITU-R.BT601
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1+ d
1
1- d
M ag n itu d e
-6 dB
-40 dB
2.75
3.375
4.0
Frequency (MHz)
NOTE: δ = 0.05 dB
Figure 6-11. Cb and Cr Filter Requirements Based on ITU-R.BT601
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Figure 6-12 through Figure 6-14 illustrate the frequency and phase responses of the interpolating filters.
The actual response using the finite-word length coefficients present in THS8200 is shown. The same
filter characteristic is used for SDTV/HDTV modes and for both 4:2:2 to 4:4:4 interpolation (2 filters, one
on each of Cb and Cr channels, switched in when a 4:2:2 input mode is selected on DMAN to interpolate
chrominance from 1/2 to 1x pixel clock rate) as well as for 2x video oversampling (3 filters, one on each
DAC channel, switched in when 2x interpolation is activated).
xxx
0
0.01
10
9
0.008
8
0.006
20
7
0.004
Magnitude - dB
Magnitude - dB
30
40
50
60
6
0.002
5
0
4
0.002
3
0.004
70
2
0.006
80
0.0081
90
0.0
0.5
1.0
1.5
2.0
3.0
2.5
0
0.01
.
0 00
3.5
0.25
0.50
0.75
1.00
1.25
1.50
f - Frequency - Rad
Figure 6-13. IFIR Pass-Band Frequency Response
f - Frequency - Rad
Figure 6-12. IFIR Frequency Response
4
3
Magnitude - dB
2
1
0
1
2
3
4 .
00
0.5
1.0
1.5
2.0
2.5
3.0
f - Frequency - Rad
Figure 6-14. IFIR Phase Response
Each of the two interpolation stages can be switched in or bypassed:
• Register data_ifir12_bypass controls the 4:2:2 to 4:4:4 filter bank (these filters should be set active
when a 4:2:2 input mode is selected on DMAN).
• Register data_ifir35_bypass controls the 1x to 2x interpolation stage and can be set active for optional
2x interpolation when an input format with pixel clock < 80 MSPS is present.
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6.7
6.7.1
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Display Timing Generator (DTG)
Overview of Functionality
THS8200 can generate dedicated Hsync/Vsync/FieldID video synchronization outputs, as well as a
composite sync inserted on either the G/Y or all analog output channels. Both types of output
synchronization can be available simultaneously and programmed independently. Synchronization
patterns are fully programmable to accommodate all standard VESA (PC graphics) and ATSC (DTV)
formats as well as nonstandard formats.
For the purpose of output video timing generation, the device is configured in HDTV, SDTV or VESA
mode (dtg1_mode register). Depending on the selected DTG mode, a number of line types are available
to generate the full video frame format. The timing and position of horizontal and vertical syncs, the
position of horizontal and vertical blanking intervals, and the structure, position and width of equalization
pulses, pre- and post-serration pulses within the vertical blanking interval are user-programmable.
The DTG determines:
• the frame format/field format (number of pixels/line, number of lines/field1, number of lines/field2,
number of fields/frame = 1 for progressive or 2 for interlaced formats) and its synchronization to the
input data source.
– Registers: dtg1_total_pixels, dtg1_linecnt, dtg1_frame_size, dtg1_field_size
• in slave mode, whether HS_IN, VS_IN, FID (dedicated sync inputs) are used for input video
synchronization or video timing is extracted from embedded SAV/EAV codes, as well as the relative
position of the video frame with respect to these synchronization signals.
– Registers: dtg2_embedded_timing, dtg2_hs_in_dly, dtg2_vs_in_dly
• the I/O direction of the HS_IN and VS_IN input signals (master vs slave mode), and the polarity of the
HS_IN, VS_IN, and FID signals.
– Registers: dtg2_hs_pol, dtg2_vs_pol, dtg2_fid_pol
• the position and width of the HS_OUT, VS_OUT output signals, and their polarity.
– Registers: dtg2_hlength, dtg2_hdly, dtg2_vlength1, dtg2_vdly1, dtg2_vlength2, dtg2_vdly2,
dtg2_vsout_pol, dtg2_hsout_pol
• field reversal within DTG.
– Register: dtg1_field_flip
• the active video window: width and position of horizontal blanking interval, width and position of vertical
blanking interval.
– Registers: dtg2_bp, dtg2_linetype and the dtg1_spec_x registers, see DTG Line Type
Overview (Section 6.7.3).
• the composite sync format: horizontal line timing includes serration, interlaced sync and broad pulses
on each line in vertical blanking interval, width of vertical sync.
– Registers: dtg1_mode, dtg1_spec_
• the behavior of the composite sync insertion: inserted on G/Y-channel only, or inserted on all channels,
or no composite sync insertion; the amplitudes of the inserted negative and positive sync, the
amplitudes of all serration pulses and broad pulses during the vertical blanking interval.
– Registers: dtg1__sync_high, dtg1__sync_low
• the DAC output amplitude during blanking and whether video data is passed or not during the active
video portion of lines within the vertical blanking interval that contain no vertical sync, serration, or
broad pulses.
– Registers: dtg1__blank, dtg1_pass_through
• the width of each color bar of the color bar test pattern.
– Registers: dtg1_vesa_cbar_size
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Functional Description
The user should program the DTG with the correct parameters for the current video format. The DTG
contains a line and a pixel counter, and a state machine to determine which user−defined line waveform to
output for each line on the analog outputs. The pixel counter counts horizontally up to the total number of
pixels per line, programmed in 'dtg1_total_pixels'. The line counter counts up to 'dtg1_field_size' lines in
the first field, and continues its count up to 'dtg1_frame_size' lines in the total frame (field1+field2).
The current field is derived from the even/odd field ID signal, which is sampled at the start of the Vsync
period. The source for the internal FID signal can be either the signal to the FID terminal, or can be
internally derived from relative Hsync/Vsync alignment on the corresponding terminals, as selected by
'dtg2_fid_de_cntl' and the current DTG mode (VESA vs. SDTV/HDTV). See register map description of
'dtg2_fid_de_cntl' for more details. Derivation of FID from Hsync/Vsync input alignment is done according
to the EIA−861 specification. There is a tolerance implemented on Hsync/Vsync transition misalignment.
When the active edge of the Vsync transition occurs within ±63 clock cycles from the active edge of
Hsync, both signals are interpreted as aligned, which signals field 1. Because of this timing window, the
internal FieldID signal is generated later than the start of Vsync period. Since the signal is internally
sampled at the start of the Vsync period to determine the current field, the field interpretation is opposite.
Use the 'field_flip' register to correct this through field reversal.
If the video format is progressive, only field1 exists and no FID signal is needed. However the DTG will
only startup when a field 1 condition is detected i.e when FID is detected low at the start of the Vsync
period. Thus in the case of a progressive video format, and when using the device with external FID input,
the user must make sure to keep the FID terminal low.
It is also needed for proper DTG synchronization that the programmed Hsync and Vsync input polarities
are correct. Since Hsync, Vsync polarities change for different VESA PC formats, the device has built−in
support to detect the incoming sync polarities. This is done by comparing the width of Hsync high
('misc_ppl') to the total line length ('dtg2_pixel_cnt') to derive the Hsync duty cycle and thus its polarity.
Upon this detection, the user can program the detected incoming polarity for DTG input synchronization
('dtg2_hs_pol') – it is not set automatically by the device. The procedure is similar for Vsync polarity
detection, using registers 'misc_lpf', 'dtg2_line_cnt' and 'dtg2_vs_pol'.
The DTG synchronization can be separated into three functions:
• Internal synchronization: How the DTG is synchronized with respect to the internal horizontal and
vertical counters.
• Source synchronization: How the horizontal and vertical counters are synchronized to the
HS_IN/VS_IN/FID or SAV/EAV signals.
• Output synchronization: how the output timings HS_OUT, VS_OUT, and the composite sync output
are synchronized to the DTG and the horizontal and vertical counters.
The DTG is based on a state machine that can generate a set of line types which can override the values
on the DAC inputs. The DTG output is multiplexed into the data path by the DIGMUX. The selected video
format preset setting, or the programmed (line type, breakpoint) table in case a generic mode is selected
in dtg1_mode, determines which line type is generated for a particular line, and where this DTG output is
used to override the normal DAC inputs. Internally, a fixed preconfigured number of line types exists from
which the user can select.
Also, for each set of line types (there are two different sets of line types possible) the user can program
the horizontal duration of each predefined excursion (negative sync, positive sync, back porch, front porch,
broad pulse, interlaced sync, etc.) and also the amplitude (for example, negative sync amplitude, positive
sync amplitude, blank amplitude).
The setting of dtg1_mode determines:
• Internal synchronization: The 0H reference (horizontal reset of the DTG) is different between SDTV
and HDTV.
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6.7.2.1
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Output synchronization: The available set of output synchronization line types depends on these
modes. The user can choose from a number of predefined line types for each mode. In each mode,
the user is able to program the timings along the line. However some timings are hard coded by the
selected DTG_mode (for example, rise/fall times for sync are different; see DTG Line Type Overview,
Section 6.7.3) and not all line types can be selected in each DTG mode (for example, HDTV allows trilevel sync, while SDTV only allows generation of bi-level negative syncs).
Predefined DTG Video Formats (Presets)
While the DTG has the flexibility to generate a wide array of video output formats and their
synchronization signals, the most common video formats have predefined settings for the field and frame
sizes and for (line type, breakpoint) settings.
When selecting a video format preset, the horizontal timings of the line types still need to be programmed.
The preset only fixes the (line type, breakpoint) table.
6.7.2.2
Internal Synchronization
The pixel and line counters of the DTG are reset by internal signals. In slave mode (THS8200 slaves to
external video input source) these signals are derived from either the embedded SAV/EAV codes or the
dedicated Hsync/Vsync/FID inputs. In master mode, these counters are in free-run and the HS_IN/VS_IN
signals are generated by the THS8200 based on the programmed field/frame parameters. Master mode is
only available for progressive-scan VESA modes. FID is not generated in master mode.
The user can delay, in both horizontal and vertical directions, the 0-reference of the DTG by programming
the input delay registers. Physically, the horizontal and vertical DTG startup values are altered. The effect
is that, when a vertical or horizontal sync is received, either from dedicated inputs or from embedded
SAV/EAV codes, the output frame starts at position (x,y). This ensures that, for example, the output video
frame can be centered on the display.
Based on the 0-reference of the DTG, the line types are generated and the DIGMUX will select between
the video input and the DTG output for each line type. All horizontal timings of the different line types are
programmable, including the portion of the video line seen as active video. A complete overview of all
available line types in either SDTV or HDTV mode is presented in Section 6.7.3.
Additionally, Hsync/Vsync outputs can be generated, synchronized to the THS8200 DAC outputs. These
outputs are programmable in width, position and polarity, based on the horizontal/vertical pixel counters,
and thus independently of the DTG reference. This ensures that independent synchronization is possible
between the composite sync output inserted into the DAC output(s) and the dedicated Hsync/Vsync
outputs. Because of their programmability, these output signals could be used for other purposes as well;
for example, Vsync could be programmed as a signal active during the VBI.
Figure 6-15 shows how the internal pixel and line counters are synchronized to internal HS and VS signals
in slave mode. HS and VS are internal signals derived from either HS_IN, VS_IN, or from embedded
SAV/EAV codes in the input video data. Since the 0-reference of the DTG is determined by these
counters, the dtg2_vs_in_dly and dtg2_hs_in_dly register settings influence both HS_OUT, VS_OUT and
composite sync output timing. The dtg2_vdly and dtg2_hdly settings, on the other hand, only affect
HS_OUT and VS_OUT, because they are downstream of the pixel counter. Likewise, dtg2_hlength and
dtg2_vlength only affect these dedicated sync output signals.
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dtg2_hs_in_dly
HS (Input)
>
RESET
Counter
=
RESET
Pixel
> Counter
=
dtg2_hdly
>
RESET
Counter
<
HS_Out
<
VS_Out
dtg2_vs_in_dly
dtg2_hlength
VS (Input)
>
RESET
Counter
=
RESET
Line
> Counter
dtg2_vdly
or
dtg2_vdly2
=
>
RESET
Counter
dtg2_vlength
or
dtg2_vlength2
Figure 6-15. THS8200 DTG VS/HS Output Generation
Note that both independent sets of delay registers allow accommodation of different input timing
references in slave mode. When the device is configured in master mode, the delay registers can
compensate for different external (frame memory) synchronization requirements.
6.7.2.3
Output Synchronization: Composite Sync
The composite sync is generated from a programmed sequence of (line type, breakpoint) combinations,
either user-programmed (in generic mode) or preset (in preset mode). The line type determines the
waveform shape at the output of the DAC(s) with programmable amplitudes and timings.
On each line, at the horizontal reference point of the DTG, the DTG decides where to start/stop the DTGgenerated data and where to pass input video data. For example, during an active video line, ancillary
data can be embedded in the digital stream outside the active video portion of the line, that it might be
necessary to convert to analog. Alternatively, during a nonactive video line, where normally the predefined
line type would be inserted, ancillary data might need to be passed during the active video portion of the
line.
The amplitudes of positive, negative sync excursions and of the negative serration, pre- and postequalization and broad pulses are independently programmable between G/Y and BPb, RPr channels.
Therefore sync insertion can be programmed on only the G/Y output or on all DAC outputs.
To limit the number of selection bits to select the line type, and because of the fact that a set of line types
can be defined that is mutually exclusive for SDTV and HDTV video modes, there are two DTG video
modes: SDTV and HDTV. There is a third DTG mode (VESA) which does not use the line type/breakpoint
state machine and only generates Hsync/Vsync outputs.
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Output Synchronization: Hsync/Vsync Outputs
These are the HS_OUT and VS_OUT signals, of which the width, position and polarity are programmable
in all DTG modes.
6.7.3
DTG Line Type Overview
6.7.3.1
HDTV Mode
When an HDTV mode is selected in dtg1_mode (preset or generic), a tri-level sync is inserted on the
analog output at the start of every video line. The amplitudes during negative and positive excursions are
programmable, as well as the horizontal timing parameters (width, position) of both excursions.
The transition time for negative-to-blank and blank-to-positive excursions during VBI is fixed to 2T,
generating a tri-level sync negative-to-positive excursion of 4T. The line type is programmed in registers
dtg2_linetype and is output by the DTG from the vertical field/frame position corresponding to the line
number programmed in register dtg2_breakpoint, until the line number listed in the next breakpoint
register is reached. An example for 1080I is shown in Figure 6-25.
The DTG overrides the input video data except where specified below for the specific line types.
The horizontal timings shown in Figure 6-16 and Figure 6-17 correspond to the dtg1_spec_ registers.
Note that the f spec is fixed.
42
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f
f
f
Sp/2
V/2
V/2
Sp
Sp/2
Sm/2
Sm
Sm/2
a
c
b
d
e
OH Line Sync Timing References
90%
10%
f1
f2
f
Figure 6-16. Tri-Level Line-Synchronizing Signal Waveform
Detailed Functional Description
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Blank Level (FULL_NTSP)
1 Line
OH
OH
f
f
Broad Pulse (FULL_BTSP)
d
h1
k
1 Line
OH
OH
Interlaced Sync (NTSP_NTSP)
f
f
f
a
c
g
g
1 Line
OH
OH
Interlaced Sync and Broad Pulse in 2nd Half (NTSP_BTSP)
f
f
f
f
a
f
c
g
d
h
k
1 Line
OH
OH
Broad Pulses and Interlaced Sync (BTSP_BTSP)
f
f
f
f
f
f
f
a
d
h
c
k
d
h
k
g
1 Line
OH
OH
Broad Pulse in 1st Half With Interlaced Sync (BTSP_NTSP)
f
f
f
f
f
a
d
h
c
k
g
g
1 Line
OH
OH
In addition: Active video linetype (ACTIVE_VIDEO)
Figure 6-17. THS8200 VBI Line Types in HDTV Mode
44
Detailed Functional Description
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Active Video
2
5
1
3
6
4
7
9
8
STATE
DURATION
1
Fixed at 2T
2
dtg1_spec_c-4
3
Fixed at 4T
4
dtg1_spec_e dtg1_spec_c-2
5
dtg1_total_pixels dtg1_spec_e dtg1_spec_b
6
dtg1_spec_b dtg1_spec_a-2
7
Fixed at 4T
8
dtg1_spec_a-4
9
Fixed at 2T
Figure 6-18. HDTV Line Type ACTIVE_VIDEO
6.7.3.3
FULL NTSP (Full Normal Tri-Level Sync Pulse)
Device input data is passed during state #5 if dtg1_pass_through is on.
2
1
3
4
5
6
7
9
8
STATE
DURATION
1
Fixed at 2T
2
dtg1_spec_c-4
3
Fixed at 4T
4
dtg1_spec_e dtg1_spec_c-2
5
dtg1_total_pixels dtg1_spec_e dtg1_spec_b
6
dtg1_spec_b dtg1_spec_a-2
7
Fixed at 4T
8
dtg1_spec_a-4
9
Fixed at 2T
Figure 6-19. HDTV Line Type FULL_NSTP
Detailed Functional Description
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NTSP NTSP (Normal Tri-Level Sync Pulse/Normal Tri-Level Sync Pulse)
2
13
3
1
4
5
7
6
12
8
14
15
16
17
18
19
11
9
22
20
10
21
STATE
DURATION
1/12
Fixed at 2T
2/13
dtg1_spec_c-4
3/14
Fixed at 4T
4/15
dtg1_spec_d_lsb dtg1_spec_c-4
5/16
Fixed at 4T
6/17
dtg1_total_pixels/2 dtg1_spec_k dtg1_spec_d-4
7/18
Fixed at 4T
8/19
dtg1_spec_k—dtg1_spec_a-12
9/20
Fixed at 4T
10/21
dtg1_spec_a-4
11/22
Fixed at 2T
Figure 6-20. HDTV Line Type NTSP_NTSP
6.7.3.5
BTSP BTSP (Broad Pulse and Tri-Level Sync Pulse/Broad Pulse and Tri-Level Sync Pulse)
2
1
13
3
12
8
4
5
7
6
14
19
15
11
9
16
10
17
18
20
22
21
STATE
DURATION
1/12
Fixed at 2T
2/13
dtg1_spec_c-4
3/14
Fixed at 4T
4/15
dtg1_spec_d_lsb dtg1_spec_c-4
5/16
Fixed at 4T
6/17
dtg1_total_pixels/2 dtg1_spec_k dtg1_spec_d-4
7/18
Fixed at 4T
8/19
dtg1_spec_k dtg1_spec_a-12
9/20
Fixed at 4T
10/21
dtg1_spec_a-4
11/22
Fixed at 2T
Figure 6-21. HDTV Line Type BTSP_BTSP
46
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NTSP BTSP (Normal Tri-Level Sync Pulse/ Broad Pulse and Tri-Level Sync Pulse)
2
1
13
3
4
5
7
6
12
8
14
19
15
11
9
16
17
18
20
10
22
21
STATE
DURATION
1/12
Fixed at 2T
2/13
dtg1_spec_c-4
3/14
Fixed at 4T
4/15
dtg1_spec_d dtg1_spec_c-4
5/16
Fixed at 4T
6/17
dtg1_total_pixels/2 dtg1_spec_k dtg1_spec_d-4
7/18
Fixed at 4T
8/19
dtg1_spec_k dtg1_spec_a-12
9/20
Fixed at 4T
10/21
dtg1_spec_a-4
11/22
Fixed at 2T
Figure 6-22. HDTV Line Type NTSP_BTSP
6.7.3.7
BTSP NTSP (Broad Pulse and Tri-Level Sync Pulse/Normal Tri-Level Sync Pulse)
2
1
13
3
12
8
4
5
7
6
14
15
16
11
9
10
STATE
DURATION
1/12
Fixed at 2T
2/13
dtg1_spec_c-4
3/14
Fixed at 4T
4/15
dtg1_spec_d dtg1_spec_c-4
5/16
Fixed at 4T
6/17
dtg1_total_pixels/2 dtg1_spec_k dtg1_spec_d-4
7/18
Fixed at 4T
8/19
dtg1_spec_k dtg1_spec_a-12
9/20
Fixed at 4T
10/21
dtg1_spec_a-4
11/22
Fixed at 2T
17
18
19
20
22
21
Figure 6-23. HDTV Line Type BTSP_NTSP
Detailed Functional Description
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Full BTSP (Full Broad Pulse and Tri-Level Sync Pulse)
2
1
3
8
4
5
7
6
9
11
10
STATE
DURATION
1/12
Fixed at 2T
2/13
dtg1_spec_c-4
3/14
Fixed at 4T
4/15
dtg1_spec_d dtg1_spec_c-4
5/16
Fixed at 4T
6/17
dtg1_total_pixels/2 dtg1_spec_k dtg1_spec_d-4
7/18
Fixed at 4T
8/19
dtg1_spec_k dtg1_spec_a-12
9/20
Fixed at 4T
10/21
dtg1_spec_a-4
11/22
Fixed at 2T
Figure 6-24. HDTV Line Type FULL_BTSP
Example: 1080I/P
THS8200 is put into 1080I mode by programming dtg1_mode = 0001. Figure 6-25 shows the required
output format of both fields for 1080I and 1080P.
When in 1080I preset mode, the (line type, breakpoint) table and frame and field size registers are filled
out as follows internally:
Breakpoints
Line Type
6
BTSP_BTSP
7
NTSP_NTSP
21
FULL_NTSP
561
ACTIVE_VIDEO
563
FULL_NTSP
564
NTSP_BTSP
568
BTSP_BTSP
569
BTSP_NTSP
584
FULL_NTSP
1124
ACTIVE_VIDEO
1126
FULL_NTSP
frame_size = 10001100101; 1125d
field_size = 01000110011; 563d
From line 1 to 5, line type BTSP_BTSP is generated. When the line counter reaches line 6, the DTG
switches to line type NTSP_NTSP, etc. Note that the dtg1_spec_ registers need to be filled out with
the correct values to set the horizontal line timings.
48
Detailed Functional Description
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Interlace
Second Field
Interlace
First Field
Progressive
No. 560
No. 1123
No. 1121
No. 561
No. 563
No. 1125
1/2 H
No. 562
No. 1124
No. 1125
OV
No. 1
No. 1
No. 564
No. 565
Second Field
No. 2
First Field
No. 2
22 H
45 H
No. 566
5H
23 H
No. 3
5H
No. 3
5H
First Field Sync Timing Reference
No. 4
No. 4
No. 567
No. 5
No. 5
No. 568
No. 6
No. 6
No. 569
1/2 H
No. 7
No. 7
No. 584
No. 21
No. 42
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THS8200
Figure 6-25. Field/Frame Synchronizing Signal Waveform (1080I and 1080P Formats)
Detailed Functional Description
49
THS8200
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6.7.3.9
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SDTV Mode
In SDTV mode, the start of a video line is signaled by the leading edge of a negative-going bi-level sync.
f
f
90% of Amplitude
50% of Amplitude
10% of Amplitude
V
f
f
90% of Amplitude
Sm
50% of Amplitude
b
a
10% of Amplitude
d
Figure 6-26. Horizontal Synchronization Signal Waveform
50
Detailed Functional Description
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1 Line
NEQ_NEQ
FULL_BSP
BSP_BSP
FULL_NSP
NEQ_BSP
BSP_NEQ
FULL_NEQ
Active Video
NSP_ACTIVE
Active Video
ACTIVE_NEQ
Active Video
ACTIVE_VIDEO
c
k
c
k1
a
d
d1
h
h
g
i
NOTE: All Rise/Fall times are equal to f = 2T
Figure 6-27. THS8200 VBI Line Types in SDTV Mode
Detailed Functional Description
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6.7.3.10 NEQ_NEQ (Negative Equalization Pulse/Negative Equalization Pulse)
4
9
5
10
3
8
1
6
2
7
STATE
DURATION
1
Fixed at 1T
2
dtg1_spec_c
3
Fixed at 2T
4
dtg1_spec_g dtg1_spec_c-4
5
Fixed at 1T
6
Fixed at 1T
7
dtg1_spec_c
8
Fixed at 2T
9
dtg1_spec_g dtg1_spec_c-4
10
Fixed at 1T
Figure 6-28. SDTV Line Type NEQ_NEQ
6.7.3.11 FULL_BSP (Full Broad Sync Pulse)
4
5
3
1
2
STATE
DURATION
1
Fixed at 1T
2
dtg1_spec_i
3
Fixed at 2T
4
dtg1_total_pixels dtg1_spec_i-4
5
Fixed at 1T
Figure 6-29. SDTV Line Type FULL_BSP
52
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6.7.3.12 BSP_BSP (Broad Sync Pulse/Broad Sync Pulse)
4
9
10
5
3
1
8
6
2
7
STATE
DURATION
1
Fixed at 1T
2
dtg1_spec_h
3
Fixed at 2T
4
dtg1_spec_g dtg1_spec_h-4
5
Fixed at 1T
6
Fixed at 1T
7
dtg1_spec_h
8
Fixed at 2T
9
dtg1_spec_g dtg1_spec_h-4
10
Fixed at 1T
Figure 6-30. SDTV Line Type BSP_BSP
6.7.3.13 FULL_NSP (Full Normal Sync Pulse)
Device input data is passed during states number 4 and number 5 if dtg1_pass_through is on.
4
5
6
3
1
2
dtg1_spec_g
STATE
DURATION
1
Fixed at 1T
2
dtg1_spec_a
3
Fixed at 2T
4
dtg1_spec_g dtg1_spec_a-4
5
dtg1_spec_g
6
Fixed at 1T
dtg1_spec_g
Figure 6-31. SDTV Line Type FULL_NSP
Detailed Functional Description
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6.7.3.14 NEQ_BSP (Negative Equalization Pulse/Broad Sync Pulse)
4
9
10
5
3
8
1
6
7
2
STATE
DURATION
1
Fixed at 1T
2
dtg1_spec_c
3
Fixed at 2T
4
dtg1_spec_g dtg1_spec_c-4
5
Fixed at 1T
6
Fixed at 1T
7
dtg1_spec_h
8
Fixed at 2T
9
dtg1_spec_g dtg1_spec_h-4
10
Fixed at 1T
Figure 6-32. SDTV Line Type NEQ_BSP
6.7.3.15 BSP_NEQ (Broad Sync Pulse/Negative Equalization Pulse)
9
4
10
5
8
3
6
1
7
2
STATE
DURATION
1
Fixed at 1T
2
dtg1_spec_h
3
Fixed at 2T
4
dtg1_spec_g dtg1_spec_h-4
5
Fixed at 1T
6
Fixed at 1T
7
dtg1_spec_c
8
Fixed at 2T
9
dtg1_spec_g dtg1_spec_c-4
10
Fixed at 1T
Figure 6-33. SDTV Line Type BSP_NEQ
54
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6.7.3.16 FULL_NEQ (Full Negative Equalization Pulse)
4
5
6
3
1
2
dtg1_spec_g
dtg1_spec_g
STATE
DURATION
1
Fixed at 1T
2
dtg1_spec_c
3
Fixed at 2T
4
dtg1_spec_g dtg1_spec_c-4
5
dtg1_spec_g
6
Fixed at 1T
Figure 6-34. SDTV Line Type FULL_NEQ
6.7.3.17 NSP_ACTIVE (Normal Sync Pulse/Active Video)
Video data is always passed during state number 5.
5
4
6
7
3
1
2
STATE
DURATION
1
Fixed at 1T
2
dtg1_spec_a
3
Fixed at 2T
4
dtg1_spec_g dtg1_spec_a+ dtg1_spec_d1-3
5
dtg1_spec_g dtg1_spec_d1 dtg1_spec_k
6
dtg1_spec_k1
7
Fixed at 1T
Figure 6-35. SDTV Line Type NSP_ACTIVE
Detailed Functional Description
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6.7.3.18 ACTIVE_NEQ (Active Video/Negative Equalization Pulse)
Video data is always passed during state number 5.
5
4
6
11
7
12
3
1
10
8
2
9
STATE
DURATION
1
Fixed at 1T
2
dtg1_spec_a
3
Fixed at 2T
4
dtg1_spec_d dtg1_spec_a-3
5
dtg1_spec_g dtg1_spec_d dtg1_spec_k1
6
dtg1_spec_k-1
7
Fixed at 1T
8
Fixed at 1T
9
dtg1_spec_c
10
Fixed at 2T
11
dtg1_spec_g dtg1_spec_c-4
12
Fixed at 1T
Figure 6-36. SDTV Line Type ACTIVE_NEQ
6.7.3.19 ACTIVE VIDEO
Video data is always passed during state number 5.
5
4
6
7
3
1
2
STATE
DURATION
1
Fixed at 1T
2
dtg1_spec_a
3
Fixed at 2T
4
dtg1_spec_d dtg1_spec_a-3
5
dtg1_total_pixels dtg1_spec_d dtg1_spec_k
6
dtg1_spec_k-1
7
Fixed at 1T
Figure 6-37. SDTV Line Type ACTIVE_VIDEO
56
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Example:525I
j
l
Second Field
OE1
m
n
First Field
Signal at the Beginning of Each First Field
j
l
First Field
OE2
m
n
Second Field
NOTE: l = m = n = 3
j = 20
Figure 6-38. Field/Frame Synchronizing Signal Waveform (525I Format)
Detailed Functional Description
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When the 525I preset is selected, the following line type sequence is active:
Breakpoints
Line Type
4
NEQ_NEQ
7
BSP_BSP
10
NEQ_NEQ
20
FULL_NSP
263
ACTIVE_VIDEO
264
ACTIVE_NEQ
266
NEQ_NEQ
267
NEQ_BSP
269
BSP_BSP
270
BSP_NEQ
272
NEQ_NEQ
273
FULL_NEQ
282
FULL_NSP
283
NSP_ACTIVE
526
ACTIVE_VIDEO
frame_size = 1000001101; 525d
field_size = 00100000111; 263d
It can be seen this corresponds to the frame format shown, with 263 lines in digital field1 and 262 lines in
digital field2.
6.8
D/A Conversion
THS8200 contains three DACs with an internal resolution of 11 bits, and maximum speed of 205 MSPS.
This allows operation with all (H)DTV formats including 1080P, and PC graphics formats up to UXGA at
75 Hz.
The DAC output compliance can be selected between two full-scale ranges using the data_fsadj register.
DIGMUX selects DTG output data during nonvideo line types, except when dtg1_passthrough is active: in
this case video input data still is passed during the active video portion of certain line types, as identified in
Section 6.7.3 on the DTG line types.
THS8200 supports output in either RGB or YPbPr color spaces. When using RGB output, the
dtg2_rgb_mode_on register needs to be set. In this case an offset is added to all DAC output channels to
provide headroom for the negative sync. Nominally the blanking level is at 350 mV, and the 700 mV swing
extends upwards. Therefore peak white corresponds to 1.05 V. When YPbPr mode is selected on this
register, the offset is only added to the Y channel output; Pb and Pr outputs now have a video range from
0 to 700 mV with 0 V corresponding to internal DAC input code 0 (note that due to the CSM block this
could correspond to another device input code). The Cb and Cr chroma difference channels are thus
assumed to be offset binary encoded, not 2s complement.
Finally, the DTG mode determines whether the DIGMUX switches in output data from the DTG. For
example, in VESA mode the DACs are always driven by the video input bus. When the DTG overrides the
video input bus in SDTV or HDTV modes, the actual amplitude levels output by the DACs during this time
are user-programmable using the dtg1__blank , dtg1__sync_low, and dtg1__high registers.
58
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The following sections described some of the analog component video output formats that can be
generated from THS8200.
6.8.1
RGB Output Without Sync Signal Insertion/General-Purpose Application DAC
In this mode, no sync signal is inserted on any of the analog outputs. HS_OUT and VS_OUT signals are
generated for output video synchronization. This mode is commonly used in computer graphics video
output.
Two levels of full-scale output can be selected by software. For video applications, the nominal voltage
levels are 0.7 V and 1.305 V.
For component video applications, the nominal voltage level is 0.7 V; 1.305 V is used in NTSC/PAL
composite video display. For composite video applications, the digital video stream must be encoded in an
external digital NTSC/PAL encoder. The THS8200 only converts the digital composite signal to analog
composite video. Figure 6-39 illustrates analog outputs without sync insertion.
When the THS8200 is programmed in this mode, it can also be used as a general-purpose DAC due to
the linear response to the DAC input codes. Optionally, the CSM block can be bypassed to avoid any
processing on the device input codes.
1023
Analog Output
Codes Input to DACs
0.700 V/1.305 V
0.000 V/0.000 V
0
Figure 6-39. RGB Without Sync Insertion or Composite Video Output
Detailed Functional Description
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Figure 6-40 shows the linear DAC I/O relationship for either of the two nominal full-scale settings.
Ramping Output With Different Full-Scale Ranges
Analog Outputs From DACs
1.305 V
0.700 V
0
255
511
767
1023
Input Digital Codes
Figure 6-40. Ramping Output With Different Full-Scale Ranges
6.8.2
SMPTE-Compatible RGB Output With Sync Signal Inserted on G (Green) Channel
In this mode, a tri-level (HDTV modes)/bi-level (SDTV modes) sync signal is inserted into the G channel.
The nominal analog output voltage range, which is from the sync tip to the peak of active video, is from
0.0 V to 1.050 V. During the active video period, the peak-to-peak ac value (dynamic range) is 700 mV
(from 350 mV to 1050 mV). The blank levels on all three channels correspond to the bottom code 64 and
are at 350 mV. Figure 6-41 and Figure 6-42illustrate the analog video output signals, both the output from
the G channel with a tri-level or a bi-level sync pulse inserted, as well as the outputs from R and B
channels. No sync signal is inserted during the sync period on R and B channels.
Alternatively, sync can be inserted on all three channels on THS8200 by appropriately programming the
sync amplitude levels. On those channels where no sync is inserted, the blank levels are maintained at a
350-mV dc level.
The range of active video codes on the R, G, and B channels is from 64 to 940. By definition, code 64
corresponds to blank-level output, and code 940 corresponds to peak analog output. Input codes outside
this region can either be clipped by THS8200 or can be passed, depending on the CSM setting. When
passed, the user should make sure not to overdrive the DAC outputs outside the DAC output compliance
range if instantaneously high output codes would occur.
60
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G Channel Output Waveform
E’G
940
Codes to DACs
Analog Output
1050 mV
650 mV
350 mV
64
350 mV DC Level Added
During Active Video Period
Blank Level
50 mV
0 mV
Active Video Period
Figure 6-41. G-Channel Output Waveform
R and B Channel Output Waveform
E’RE’B
940
Codes to DACs
Analog Output
1050 mV
64
350 mV
350 mV DC Level Added
During Active Video Period
Blank Level
0 mV
Active Video Period
Figure 6-42. R- and B-Channel Output Waveform
6.8.3
SMPTE-Compatible Analog-Level Output With Sync Inserted on All RGB Channels
This is another SMPTE-compatible RGB output. This mode is very similar to the mode described in
Section 6.8.2, except the sync signals are inserted on all three channels. Now all three channels have the
same analog output format, during both the active video period and the sync period.
R, G, and B Channel Output Waveform
E’R, E’ G, E’ B
940
Codes to DACs
Analog Output
1050 mV
650 mV
64
350 mV
350 mV DC Level Added
During Active Video Period
Blank Level
50 mV
0 mV
Active Video Period
Figure 6-43. R-, G-, and B-Channel Output Waveform
Detailed Functional Description
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6.8.4
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SMPTE-Compatible YPbPr Output With Sync Signal Inserted on Y Channel Only
In this mode, the output color space is YCrCb. The sync signal is inserted on the Y channel only.
Y Channel Output Waveform
E’Y
940
Codes to DACs
Analog Output
1050 mV
650 mV
64
350 mV
350 mV DC Level Added
During Active Video Period
Blank Level
50 mV
0 mV
Active Video Period
Figure 6-44. Y-Channel Output Waveform
The input code range of the Y channel is from 64 to 940, but the range of input codes of Cr and Cb is from
64 to 960.
Analog Output of Cr and Cb Channels Without Sync Insertion
960
350 mV
512
Blank Level
Codes to DACs
Analog Output
E’cr, E’ cb
700 mV
64
0 mV
Active Video Period
Blanking Interval
Figure 6-45. Analog Output of Cr and Cb Channels Without Sync Insertion
The blanking level of all channels is at 350 mV. Note that for the Pb and Pr output channels, there is no dc
offset added, so DAC input code 0 now corresponds to 0 V dc output. Whether or not offset is added to
the DAC outputs is determined from the setting of the dtg2_rgb_mode_on register.
6.8.5
SMPTE-Compatible YPbPr Output With Sync Signal Inserted on All Channels
In this mode, sync signals are inserted on all three channels Y, Cr, and Cb. The Y channel output is
identical to that of Section 6.8.4. The Pb and Pr channel outputs are shown below. The range of input
codes to the Y channel is from 64 to 940. The range of input codes to the CrCb channels is from 64 to
960.
62
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Analog Output of Cr and Cb Channels With Sync Insertion
960
896
350 mV
512
50 mV
0 mV
Blank Level
128
64
Codes to DACs
Analog Output
E’cr, E’ cb
700 mV
650 mV
Active Video Period
Blanking Interval
OH
Figure 6-46. Analog Output of Cr and Cb Channels With Sync Insertion
The ac dynamic range during the active video period is the same on all channels, 700 mV. This means
that two different code ranges are mapped to the same analog output range. Because three DACs in the
THS8200 share a common full-scale adjust resistor, therefore, different input codes to the DAC result in
different analog outputs. To map two code ranges into a same analog output, the input code range must
be scaled in the CSM block.
6.8.6
Summary of Supported Video Formats
RGB WITHOUT
SYNC
RGB SYNC ON G
RGB SYNC
ON ALL
YPbPr SYNC ON Y
YPbPr SYNC ON ALL
0 to 1023
64 to 940
64 to 940
64 to 940 on Y;
64 to 960 on Cr and Cb
64 to 940 on Y;
64 to 960 on Cr and Cb
Peak level
700 mV or 1305 mV
1050 mV
1050 mV
1050 mV
1050 mV
Blank level
0V
350 mV
350 mV
350 mV
350 mV
0
350 mV
350 mV
350 mV
350 mV
Range of input
codes
DC level shift
during active
video period
6.9
Test Functions
The user can activate a 75% SMPTE color bar test pattern when the device is configured in VESA mode
using the vesa_colorbars register setting. The width of each color bar can be programmed using the
dtg1_vesa_cbar_size register.
The digital logic in front of the DACs can be completely bypassed and the DACs can be driven directly
with levels programmed from the I2C interface by activating the dac_i2c_cntl register. In this case the
dac_cntl registers set the DAC input codes. A fast or slow ramp signal can be internally generated and
sent to the DACs using tst_fastramp and tst_slowramp registers. This could be useful for a static DAC
linearity test.
Alternatively, the input bus can directly drive the DACs when the tst_digbypass register is activated for
tests at full speed.
The delay of the Y channel can be changed in YCbCr modes with respect to Cb and Cr channels by
programming the tst_ydelay register.
Detailed Functional Description
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Finally, there is a digital output port with data encoded according to ITU-R.BT656. This is a loop-through
of the original input bus, prior to any THS8200 internal processing, and thus only provides standard data
when input to the THS8200 is provided in a 10-bit ITU-R BT.656 format. This output bus could be used to
connect to a separate NTSC/PAL video encoder. The data_clk656_on register activates the clock output
on this bus and the data_tristate656 register disables the output bus. It is recommended to disable this
output when not in use.
6.10 Power Down
THS8200 implements two power-down modes: dac_pwdn powers down the DAC channels but keeps all
digital logic active; chip_pwdn powers down the digital logic except the I2C interface. Activating both
registers enforces a complete analog/digital power down except for the I2C interface.
6.11 CGMS Insertion
The THS8200 can embed data within the vertical blanking interval, encoded according to the EIA-805 data
insertion standard. CGMS is an implementation of the EIA-805 standard that defines data insertion in
component video interface (CVI) video signals.
The THS8200 supports CGMS data insertion on line 41 of every frame in the 525P format. The data is
inserted on the Y channel only; Pb and Pr channels remain at the blanking level. CGMS data insertion is
enabled by activating the cgms_en register and programming the cgms_header and cgms_payload
registers appropriately. The user needs to program header and payload data in the correct format, as no
additional data encoding is done prior to insertion into the analog DAC output. The THS8200 only
performs a play-out function for the programmed data. The CGMS encoding block assumes that a full 10bit video range is used to determine the 70% of peak-white amplitude of a logic 1 bit, as prescribed by
EIA-805. The CSM does not affect the amplitude of the CGMS data insertion.
CGMS is inserted on line 41 as prescribed by EIA 770 standards for progressive format display of SDTV.
Fourteen bits can be inserted on this line, consisting of 6 bits header and 8 bits payload. The user can
directly program these bits into the corresponding THS8200 registers. Care should be taken to format this
data according to CGMS semantics; the user is referred to the original standards to determine
header/payload data programming. To avoid the transmission of invalid data, the data transmitted is
updated only when the CGMS register with the highest subaddress is programmed with cgms_en active.
CGMS insertion is possible in either 1x or 2x interpolated video modes of the THS8200. While EIA-805
allows the inserted data to change on every frame, and also allows data packets that would span multiple
lines (and therefore also multiple frames, since only 1 line/frame is used for insertion), the THS8200 does
not support multiline data insertion because it is not required for CGMS.
6.12 I2C Interface
The THS8200 contains a slave-only I2C interface on which both write and read are supported. The register
map shows which registers support read/write (R/W) and which are read-only (R). The device supports
normal and fast I2C modes (SCL up to 400 kHz). The I2C interface is also operational when no input clock
is received on CLKIN.
To discriminate between write and read operations, the device is addressed at separate device addresses.
There is an automatic internal sub-address increment counter to efficiently write/read multiple bytes in the
register map during one write/read operation. Furthermore, bit1 of the I2C device address is dependent
upon the setting of the I2CA pin, as follows:
• If address-selecting pin I2CA = 0, then
– write address is 40h (0100 0000)
– read address is 41h (0100 0001)
• If address-selecting pin I2CA = 1, then
– write address is 42h (0100 0010)
– read address is 43h (0100 0011)
64
Detailed Functional Description
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The I2C interface supports fast I2C, that is, SCL up to 400 kHz.
WRITE FORMAT
S
Slave address(w)
A
Sub-address
A
Data0
A
S
Start condition
Slave address(w)
0100 0000 (0x40) if I2CA = 0, or 0100 0010 (0x42) if I2CA = 1
A
Acknowledge, generated by the THS8200
Sub-address
Sub-address of the first register to write, length: 1 byte
Data0
First byte of the data
DataN-1
Nth byte of the data
P
Stop condition
......
DataN-1
A
P
READ FORMAT
First write the sub-address, where the data must be read out to the THS8200 in the format as follows:
S
Slave address(w)
S
Slave address(r)
A
A
DataN
Sub-address
AM
Data(N+1)
AM
A
......
P
NAM
S
Start condition
Slave address(r)
0100 0001 (0x41) if I2CA = 0, or 0100 0011 (0x43) if I2CA = 1
A
Acknowledge, generated by the THS8200; if the transmission is successful, then A = 0, else A = 1
AM
Acknowledge, generated by a master
NAM
Not acknowledge, generated by a master
Sub-address
Sub-address of the first register to read, length: 1 byte
Data0
First byte of the data read
DataN+1
Nth byte of the data read
P
Stop condition
P
In both write and read operations, the sub-address is incremented automatically when multiple bytes are
written/read. Therefore, only the first sub-address needs to be supplied to the THS8200.
Detailed Functional Description
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7 I2C Registers
7.1
I2C Register Map
R/W registers can be written and read.
R registers are read-only.
Table 7-1. I2C Register Map
REGISTER
NAME
R/W
SUBADDRESS
BIT7
BIT6
BIT5
BIT4
0x00
BIT3
BIT2
BIT1
BIT0
ver2
ver1
ver0
chip_ms
arst_
func_n
Reserved
0x01
SYSTEM
version
R
0x02
ver7
ver6
ver5
vesa_color
dll_bypass
bars
chip_ctl
R/W
0x03
vesa_clk
csc_r11
R/W
0x04
csc_ric1(5:0)
csc_r12
R/W
0x05
csc_rfc1(7:0)
csc_r21
R/W
0x06
csc_ric2(5:0)
csc_r22
R/W
0x07
csc_rfc2(7:0)
csc_r31
R/W
0x08
csc_ric3(5:0)
csc_r32
R/W
0x09
csc_rfc3(7:0)
csc_g11
R/W
0x0a
csc_gic1(5:0)
csc_g12
R/W
0x0b
csc_gfc1(7:0)
csc_g21
R/W
0x0c
csc_gic2(5:0)
csc_g22
R/W
0x0d
csc_gfc2(7:0)
csc_g31
R/W
0x0e
csc_gic3(5:0)
csc_g32
R/W
0x0f
csc_gfc3(7:0)
csc_b11
R/W
0x10
csc_bic1(5:0)
csc_b12
R/W
0x11
csc_bfc1(7:0)
csc_b21
R/W
0x12
csc_bic2(5:0)
csc_b22
R/W
0x13
csc_bfc2(7:0)
csc_b31
R/W
0x14
csc_bic3(5:0)
csc_b32
R/W
0x15
csc_bfc3(7:0)
csc_offs1
R/W
0x16
csc_offset1(9:2)
csc_offs12
R/W
0x17
csc_offset1(1:0)
csc_offs23
R/W
0x18
csc_offset2(3:0)
csc_offs3
R/W
0x19
csc_offset3(5:0)
ver4
dll_freq_
sel
ver3
dac_pwdn
chip_pwdn
COLOR SPACE CONVERSION
csc_rfc1(9:8)
csc_rfc2(9:8)
csc_rfc3(9:8)
csc_gfc1(9:8)
csc_gfc2(9:8)
csc_gfc3(9:8)
csc_bfc1(9:8)
csc_bfc2(9:8)
csc_bfc3(9:8)
csc_offset2(9:4)
csc_offset3(9:6)
csc_
bypass
c_uof_cnt l
tst_
fastramp
tst_
slowramp
TEST
tst_cntl1
R/W
0x1a
st_
digbpass
tst_cntl2
R/W
0x1b
tst_ydelay(1:0)
0x1c
data_
data_fsadj
clk6 56_on
tst_offset
Reserved
Reserved
Reserved
Reserved
Reserved
DATA PATH
data_cntl
R/W
data_ifir12
_bypass
data_ifir35 data_
_bypass
tristate656
data_dman_cntl(2:0)
DISPLAY TIMING GENERATION, PART 1
dtg1_y_
sync1_lsb
66
R/W
0x1d
dtg1_y_blank(7:0)
I2C Registers
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Table 7-1. I2C Register Map (continued)
REGISTER
NAME
R/W
SUBADDRESS
dtg1_y_
sync2_lsb
R/W
0x1e
dtg1_y_sync_low(7:0)
dtg1_y_
sync3_lsb
R/W
0x1f
dtg1_y_sync_high(7:0)
dtg1_cbcr_
sync1_lsb
R/W
0x20
dtg1_cbcr_blank(7:0)
dtg1_cbcr_
sync2_lsb
R/W
0x21
dtg1_cbcr_sync_low(7:0)
dtg1_cbcr_
sync3_lsb
R/W
0x22
dtg1_cbcr_sync_high(7:0)
dtg1_y_
sync_msb
R/W
0x23
Reserved
Reserved
dtg1_y_blank(9:8)
dtg1_y_sync_low(9:8)
dtg1_y_sync_high(9:8)
dtg1_cbcr_
sync_msb
R/W
0x24
Reserved
Reserved
dtg1_cbcr_blank(9:8)
dtg1_cbcr_sync_low
(9:8 )
dtg1_cbcr_
sync_high(9:8)
dtg1_spec_a
R/W
0x25
dtg1_spec_a(7:0)
dtg1_spec_b
R/W
0x26
dtg1_spec_b(7:0)
dtg1_spec_c
R/W
0x27
dtg1_spec_c(7:0)
dtg1_spec_
d_lsb
R/W
0x28
dtg1_spec_d(7:0)
dtg1_spec_ d1
R/W
0x29
dtg1_spec_d1(7:0)
dtg1_spec_
e_lsb
R/W
0x2a
dtg1_spec_e(7:0)
dtg1_spec_
deh_msb
R/W
0x2b
dtg1_
dtg1_spec
spe c_d(8) _e(8)
Reserved
Reserved
Reserved
dtg1_spec_h(9:8)
dtg1_spec_
h_lsb
R/W
0x2c
dtg1_spec_h(7:0)
dtg1_spec_
i_msb
R/W
0x2d
Reserved
Reserved
Reserved
dtg1_spec_i(11:8)
dtg1_spec_
i_lsb
R/W
0x2e
dtg1_spec_i(7:0)
dtg1_spec_
k_lsb
R/W
0x2f
dtg1_spec_k(7:0)
dtg1_spec_
k_msb
R/W
0x30
Reserved
Reserved
Reserved
Reserved
dtg1_spec_ k1
R/W
0x31
dtg1_spec_k1(7:0)
dtg1_spec_
g_lsb
R/W
0x32
dtg1_spec_g(7:0)
dtg1_spec_
g_msb
R/W
0x33
Reserved
Reserved
Reserved
Reserved
dtg1_spec_g(11:8)
dtg1_total_
pixels_msb
R/W
0x34
Reserved
Reserved
Reserved
dtg1_total_pixels(12:8)
dtg1_total_
pixels_lsb
R/W
0x35
dtg1_total_pixels(7:0)
dtg1_fieldflip_
linecnt_ msb
R/W
0x36
dtg1_field
_flip
Reserved
Reserved
Reserved
dtg1_
linecnt_lsb
R/W
0x37
dtg1_linecnt(7:0)
dtg1_mode
R/W
0x38
dtg1_on
Reserved
Reserved
dtg1_pass
_through
dtg1_mode(3:0)
dtg1_frame_
field_size_msb
R/W
0x39
Reserved
dtg1_frame_size(10:8)
dtg1_frame_
size_lsb
R/W
0x3a
dtg1_frame_size(7:0)
BIT7
BIT6
Reserved
Reserved
Reserved
BIT5
BIT4
BIT3
Reserved
BIT2
Reserved
BIT1
BIT0
dtg1_spec_k(10:8)
dtg1_linecnt(10:8)
dtg1_field_size(10:8)
I2C Registers
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Table 7-1. I2C Register Map (continued)
REGISTER
NAME
R/W
SUBADDRESS
dtg1_field_
size_lsb
R/W
0x3b
dtg1_field_size(7:0)
dtg1_vesa_
cbar_size
R/W
0x3c
dtg1_vesa_cbar_size(7:0)
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
DAC
dac_i2c_
cntl
dac_cntl_msb
R/W
0x3d
Reserved
dac1_cntl_lsb
R/W
0x3e
dac1_cntl(7:0)
dac2_cntl_lsb
R/W
0x3f
dac2_cntl(7:0)
dac3_cntl_lsb
R/W
0x40
dac3_cntl(7:0)
dac1_cntl(9:8)
dac2_cntl(9:8)
dac3_cntl(9:8)
CLIP/SHIFT/MULTIPLIER
csm_clip_
gy_low
R/W
0x41
csm_clip_gy_low(7:0)
csm_clip_
bcb_low
R/W
0x42
csm_clip_bcb_low(7:0)
csm_clip_
rcr_low
R/W
0x43
csm_clip_rcr_low(7:0)
csm_clip_
gy_high
R/W
0x44
csm_clip_gy_high(7:0)
csm_clip_
bcb_high
R/W
0x45
csm_clip_bcb_high(7:0)
csm_clip_
rcr_high
R/W
0x46
csm_clip_rcr_high(7:0)
csm_shift_gy
R/W
0x47
csm_shift_gy(7:0)
csm_shift_bcb
R/W
0x48
csm_shift_bcb(7:0)
csm_shift_rcr
R/W
0x49
csm_shift_rcr(7:0)
csm_gy_
cntl_mult_ msb
R/W
0x4a
csm_mult
_ gy_on
csm_gy_
csm_shift_
high_clip_
gy_on
on
csm_mult_
bcb_rcr_ msb
R/W
0x4b
Reserved
csm_mult_bcb(10:8)
csm_mult_
gy_lsb
R/W
0x4c
csm_mult_gy(7:0)
csm_mult_
bcb_lsb
R/W
0x4d
csm_mult_bcb(7:0)
csm_mult_
rcr_lsb
R/W
0x4e
csm_mult_rcr(7:0)
csm_rcr_
bcb_cntl
R/W
0x4f
csm_mult
_ rcr_on
csm_gy_
low_clip_
on
csm_of_
cntl
csm_rcr_
csm_mult_ csm_shift_ csm_shift_
high_clip_
bcb_on
rcr_on
bcb_on
on
csm_mult_gy(10:8)
Reserved
csm_mult_rcr(10:8)
csm_rcr_
low_clip_
on
csm_bcb_
high_clip_
on
csm_bcb _
low_clip_
on
DISPLAY TIMING GENERATION, PART 2
68
dtg2_bp1_
2_msb
R/W
0x50
Reserved
dtg2_bp1(10:8)
Reserved
dtg2_bp2(10:8)
dtg2_bp3_
4_msb
R/W
0x51
Reserved
dtg2_bp3(10:8)
Reserved
dtg2_bp4(10:8)
dtg2_bp5_
6_msb
R/W
0x52
Reserved
dtg2_bp5(10:8)
Reserved
dtg2_bp6(10:8)
dtg2_bp7_
8_msb
R/W
0x53
Reserved
dtg2_bp7(10:8)
Reserved
dtg2_bp8(10:8)
dtg2_bp9_
10_msb
R/W
0x54
Reserved
dtg2_bp9(10:8)
Reserved
dtg2_bp10(10:8)
dtg2_bp11_
12_msb
R/W
0x55
Reserved
dtg2_bp11(10:8)
Reserved
dtg2_bp12(10:8)
I2C Registers
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Table 7-1. I2C Register Map (continued)
REGISTER
NAME
R/W
SUBADDRESS
dtg2_bp13_
14_msb
R/W
0x56
Reserved
dtg2_bp13(10:8)
Reserved
dtg2_bp14(10:8)
dtg2_bp15_
16_msb
R/W
0x57
Reserved
dtg2_bp15(10:8)
Reserved
dtg2_bp16(10:8)
dtg2_bp1_lsb
R/W
0x58
dtg2_bp1(7:0)
dtg2_bp2_lsb
R/W
0x59
dtg2_bp2(7:0)
dtg2_bp3_lsb
R/W
0x5a
dtg2_bp3(7:0)
dtg2_bp4_lsb
R/W
0x5b
dtg2_bp4(7:0)
dtg2_bp5_lsb
R/W
0x5c
dtg2_bp5(7:0)
dtg2_bp6_lsb
R/W
0x5d
dtg2_bp6(7:0)
dtg2_bp7_lsb
R/W
0x5e
dtg2_bp7(7:0)
dtg2_bp8_lsb
R/W
0x5f
dtg2_bp8(7:0)
dtg2_bp9_lsb
R/W
0x60
dtg2_bp9(7:0)
dtg2_bp10_ lsb
R/W
0x61
dtg2_bp10(7:0)
dtg2_bp11_ lsb
R/W
0x62
dtg2_bp11(7:0)
dtg2_bp12_ lsb
R/W
0x63
dtg2_bp12(7:0)
dtg2_bp13_ lsb
R/W
0x64
dtg2_bp13(7:0)
dtg2_bp14_ lsb
R/W
0x65
dtg2_bp14(7:0)
dtg2_bp15_ lsb
R/W
0x66
dtg2_bp15(7:0)
dtg2_bp16_ lsb
R/W
0x67
dtg2_bp16(7:0)
dtg2_ linetype1
R/W
0x68
dtg2_linetype1(3:0)
dtg2_linetype2(3:0)
dtg2_ linetype2
R/W
0x69
dtg2_linetype3(3:0)
dtg2_linetype4(3:0)
dtg2_ linetype3
R/W
0x6a
dtg2_linetype5(3:0)
dtg2_linetype6(3:0)
dtg2_ linetype4
R/W
0x6b
dtg2_linetype7(3:0)
dtg2_linetype8(3:0)
dtg2_ linetype5
R/W
0x6c
dtg2_linetype9(3:0)
dtg2_linetype10(3:0)
dtg2_ linetype6
R/W
0x6d
dtg2_linetype11(3:0)
dtg2_linetype12(3:0)
dtg2_ linetype7
R/W
0x6e
dtg2_linetype13(3:0)
dtg2_linetype14(3:0)
dtg2_ linetype8
R/W
0x6f
dtg2_linetype15(3:0)
dtg2_linetype16(3:0)
dtg2_hlength_
lsb
R/W
0x70
dtg2_hlength(7:0)
dtg2_
hlength_msb_
hdly_msb
R/W
0x71
dtg2_hlength(9:8)
dtg2_hdly_lsb
R/W
0x72
dtg2_hdly(7:0)
dtg2_
vlength1_lsb
R/W
0x73
dtg2_vlength1(7:0)
dtg2_
vlength1_msb_
vdly1_msb
R/W
0x74
dtg2_vlength1(9:8)
BIT7
BIT6
dtg2_vdly1_lsb
R/W
0x75
dtg2_vdly1(7:0)
dtg2_vlength2_
lsb
R/W
0x76
dtg2_vlength2(7:0)
dtg2_
vlength2_msb_
vdly2_msb
R/W
0x77
dtg2_vlength2(9:8)
dtg2_vdly2_lsb
R/W
0x78
dtg2_vdly2(7:0)
dtg2_hs_
in_dly_msb
R/W
0x79
Reserved
dtg2_hs_
in_dly_lsb
R/W
0x7a
dtg2_hs_in_dly(7:0)
Reserved
BIT5
BIT4
BIT3
BIT2
BIT1
Reserved
dtg2_hdly(12:8)
Reserved
Reserved
Reserved
dtg2_vdly1(10:8)
Reserved
Reserved
Reserved
dtg2_vlength2(9:8)
Reserved
dtg2_hs_in_dly(12:8)
BIT0
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Table 7-1. I2C Register Map (continued)
REGISTER
NAME
R/W
SUBADDRESS
dtg2_vs_in_
dly_msb
R/W
0x7b
Reserved
dtg2_vs_in_
dly_lsb
R/W
0x7c
dtg2_vs_in_dly(7:0)
dtg2_pixel_
cnt_msb
R
0x7d
dtg2_pixel_cnt(15:8)
dtg2_pixel_
cnt_lsb
R
0x7e
dtg2_pixel_cnt(7:0)
dtg2_line_
cnt_msb
R
0x7f
dtg2_ip_
fmt
dtg2_line_
cnt_msb
R
0x80
dtg2_line_cnt(7:0)
0x81
Reserved
0x82
dtg2_fid_
de_cntl
dtg2_cntl
R/W
BIT7
BIT6
BIT5
Reserved
Reserved
BIT4
Reserved
BIT3
Reserved
Reserved
dtg2_rgb_
mode_on
BIT2
BIT1
BIT0
dtg2_vs_in_dly(10:8)
dtg2_line_cnt(10:8)
dtg2_emb
edded_
timing
dtg2_
vsout_pol
dtg2_h
sout_pol
dtg2_fid_
pol
dtg2_vs_
pol
dtg2_hs_
pol
CGMS CONTROL
cgms_cntl_
header
R/W
0x83
Reserved
cgms_en
cgms_header(5:0)
cgms_payload_
msb
R/W
0x84
Reserved
Reserved
cgms_payload(13:8)
cgms_
payload_lsb
R/W
0x85
cgms_payload(7:0)
misc_ppl_lsb
R
0x86
misc_ppl(7:0)
misc_ppl_msb
R
0x87
misc_ppl(7:0)
misc_lpf_lsb
R
0x88
misc_lpf(7:0)
misc_lpf_msb
R
0x89
misc_lpf(15:8)
70
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7.2
SLES032E – JUNE 2002 – REVISED SEPTEMBER 2014
Register Descriptions
Between { } are shown the name(s), subaddress(es) and bit position(s) where each register can be found
in the register map.
The default register value is shown between [ ] in binary format, and hexadecimal (h) and/or decimal (d)
notation where listed.
7.2.1
System Control (Sub-Addresses 0x02−0x03)
ver(7:0):
Device version
{version 0x02(7..0)}
[0000 0000]
The user can read this register to find out which version of THS8200 is in the system.
vesa_clk:
Clock mode selection
{chip_ctl 0x03(7)}
[0]
0 : Normal operation
1 : All clocks become identical, except for the half-rate clock, and the DLL is bypassed. This is used in VESA mode to support a direct
205-MHz input clock. No internal 2x interpolation is available. This mode should be used for all formats that require a >80 MSPS pixel
clock because the internal DLL for 2x clock generation is specified only up to 80 MSPS.
The half-rate clock is still internally generated if needed to allow, for example, 148-MHz 20-bit input (1080P).
dll_bypass:
DLL bypass
{chip_ctl 0x03(6)}
[0]
0 : DLL used for clock generation; normal operation with internally generated 2x clock. This mode should be selected for most video
formats when a 1x clock is available on the device clock input, and either 1x or 2x DAC operation is desired internally (as selected by
register data_ifir35_bypass)
1 : DLL bypassed for clock generation. In this case the clock input on the CLKIN pin is used directly as the 2x clock, rather than the
internally generated signal from the DLL.
vesa_colorbars:
Color bar test pattern
{chip_ctl 0x03(5)}
[0]
0 : normal operation
1 : Device generates color bar pattern; external video inputs are ignored. The color bar pattern is only supported in VESA PC graphics
mode, with the device configured in master mode
(chip_ms = 1).
dll_freq_sel:
dll_freq_sel:
{chip_ctl 0x03(4)}
[0]
Sets a frequency range for the DLL 2x clock generation. The DLL should not be used at >80 MHz. In this case the vesa_clk register
should be enabled. As a consequence, 2x video interpolation is not available for formats with >80 MHz pixel clock.
0 : high frequency range: pixel clock from 40−80 MHz
1 : low frequency range: pixel clock from 10−40 MHz
dac_pwdn:
dac_pwdn:
{chip_ctl 0x03(3)}
[0]
0 : normal operation
1 : DACs go into power-down state.
chip_pwdn:
Chip power down
{chip_ctl 0x03(2)}
[0]
0 : normal operation
1 : power down of all digital logic except I2C
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chip_ms:
Chip mode select
{chip_ctl 0x03(1)}
[0]
0 : slave mode. Device synchronizes to incoming video sync signals, either embedded in ITU-R.BT656 interface or received from
dedicated timing signals.
1 : master mode. Device requests video data and generates video input timing signals to external (memory) device, according to the
programmed frame/field format. Master mode is only available when the DTG is operating in VESA mode (PC graphics signals).
arst_func_n:
Chip software reset
{chip_ctl 0x03(0)}
[1]
0 : functional block goes into reset state. I2C registers retain values.
Note: the user needs to issue a software reset after input video is disconnected from the input bus and reconnected (for example after
a video format change), to synchronize the internal display timing generator to the input video source properly.
1 : normal operation
7.2.2
Color Space Conversion Control (Sub-Addresses 0x04−0x19)
Signed magnitude: MSB is sign bit, remaining bits are binary representation of magnitude. This is not a 2s
complement notation.
Magnitude: Binary representation of magnitude.
csc_ric1(5:0):
R/Cr input channel – G/Y output channel coefficient, integer part
{csc_r11 0x04(7:2)}
[00 0000]
6-bit integer portion of coefficient that is multiplied with R/Cr input, to produce G/Y output (signed magnitude format)
csc_rfc1(9:0):
R/Cr input channel – G/Y output channel, fractional part
{csc_r11 0x04(1:0) and
[00 0000 0000]
csc_r12 0x05(7:0)}
10-bit fractional portion of coefficient that is multiplied with R/Cr input, to produce G/Y output (magnitude format)
csc_ric2(5:0):
R/Cr input channel – B/Cb output channel, integer part
{csc_r21 0x06(7:2)}
{csc_r21 0x06(7:2)}
6-bit integer portion of coefficient that is multiplied with R/Cr input, to produce B/Cb output (signed magnitude format)
csc_rfc2(9:0):
R/Cr input channel – B/Cb output channel, fractional part
{csc_r21 0x06(1:0) and
[00 0000 0000]
csc_r22 0x07(7:0)}
10-bit fractional portion of coefficient that is multiplied with R/Cr input, to produce B/Cb output (magnitude format)
csc_ric3(5:0):
R/Cr input channel – R/Cr output channel, integer part
{csc_r31 0x08(7:2)}
[000000]
6-bit integer portion of coefficient that is multiplied with R/Cr input, to produce R/Cr output (signed magnitude format)
csc_rfc3(9:0):
R/Cr input channel − R/Cr output channel, fractional part
{csc_r31 0x08(1:0) and
[00 0000 0000]
csc_r32 0x09(7:0)}
10-bit fractional portion of coefficient that is multiplied with R/Cr input, to produce R/Cr output (magnitude format)
72
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csc_gic1(5:0):
G/Y input channel – G/Y output channel, integer part
{csc_g11 0x0A(7:2)}
[00 0000]
6-bit fractional portion of coefficient that is multiplied with R/Cr input, to produce R/Cr output (magnitude format)
csc_gfc1(9:0):
G/Y input channel – G/Y output channel, fractional part
{csc_g11 0x0A(1:0) and
[00 0000 0000]
csc_g12 0x0B(7:0)}
10-bit fractional portion of coefficient that is multiplied with G/Y input, to produce G/Y output (magnitude format)
csc_gic2(5:0):
G/Y input channel – B/Cb output channel, integer part
{csc_g21 0x0C(7:2)}
[00 0000]
6-bit integer portion of coefficient that is multiplied with G/Y input, to produce G/Y output (magnitude format)
csc_gfc2(9:0):
G/Y input channel – B/Cb output channel, fractional part
{csc_g21 0x0C(1:0) and
[00 0000 0000]
csc_g22 0x0D(7:0)}
10-bit fractional portion of coefficient that is multiplied with G/Y input, to produce B/Cb output (magnitude format)
csc_gic3(5:0):
G/Y input channel – R/Cr output channel, integer part
{csc_g31 0x0E(7:2)}
{csc_g31 0x0E(7:2)}
6-bit integer portion of coefficient that is multiplied with G/Y input, to produce R/Cr output (signed magnitude format)
csc_gfc3(9:0)
G/Y input channel – R/Cr output channel, fractional part
{csc_g31 0x0E(1:0) and
[00 0000 0000]
csc_g32 0x0F(7:0)}
10-bit fractional portion of coefficient that is multiplied with G/Y input, to produce R/Cr output (magnitude format)
csc_bic1(5:0):
B/Cb input channel – G/Y output channel, integer part
{csc_b11 0x10(7:2)}
[00 0000]
6-bit integer portion of coefficient that is multiplied with B/Cb input, to produce G/Y output (signed magnitude format)
csc_bfc1(9:0):
B/Cb input channel – G/Y output channel, fractional part
{csc_b11 0x10(1:0) and
[00 0000 0000]
csc_b12 0x11(7:0)}
10-bit fractional portion of coefficient that is multiplied with B/Cb input, to produce G/Y output (magnitude format)
csc_bic2(5:0):
B/Cb input channel – B/Cb output channel, integer part
{csc_b21 0x12(7:2)}
[00 0000]
6-bit integer portion of coefficient that is multiplied with B/Cb input, to produce B/Cb output (signed magnitude format)
I2C Registers
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csc_bfc2(9:0):
B/Cb input channel – B/Cb output channel, fractional part
{csc_b21 0x12(1:0) and
[00 0000 0000]
csc_b22 0x13(7:0)}
10-bit fractional portion of coefficient that is multiplied with B/Cb input, to produce B/Cb output (magnitude format)
csc_bic3(5:0):
B/Cb input channel – R/Cr output channel, integer part
{csc_b31 0x14(7:2)}
[00 0000]
6-bit integer portion of coefficient that is multiplied with B/Cb input, to produce R/Cr output (signed magnitude format)
csc_bfc3(9:0):
B/Cb input channel – R/Cr output channel, fractional part
{csc_b31 0x14(1:0) and
[00 0000 0000]
csc_b32 0x15(7:0)}
10-bit fractional portion of coefficient that is multiplied with B/Cb input, to produce R/Cr output (magnitude format)
csc_offset1(9:0):
DAC channel 1 offset
{csc_offs1 0x16(7:0) and
[00 0000 0000]
csc_offs12 0x17(7:6)}
Offset value for G/Y output (signed magnitude format)
csc_offset2(9:0):
DAC channel 2 offset
{csc_offs12 0x17(5:0) and
[00 0000 0000]
csc_offs23 0x18(7:4)}
Offset value for B/Cb output (signed magnitude format)
csc_offset3(9:0):
DAC channel 3 offset
{csc_offs23 0x18(3:0) and
[00 0000 0000]
csc_offs3 0x19(7:2)}
Offset value for R/Cr output (signed magnitude format)
csc_bypass:
Bypass for CSC block
{csc_offs3 0x19(1)}
[1]
0 : Color space conversion (CSC) not bypassed
1 : CSC bypassed
csc_uof_cntl:
Under-/overflow control for CSC block
{csc_offs3 0x19(1)}
[0]
Controls over-/underflow protection logic on color space converter
0 : Under-/overflow protection off
1 : Under-/overflow protection on
7.2.3
Test Control (Sub-Addresses 0x1A−0x1B)
tst_digbypass:
Bypass to DAC inputs
{tst_cntl1 0x1A(7)}
[0]
0 : Normal operation; nonbypass
1 : Digital logic bypassed to directly control DACs from input bus
tst_offset:
Bypass for DAC offsets
{tst_cntl1 0x1A(6)}
[0]
0 : Normal operation; logic not bypassed
1 : Programmed offsets are always added to DAC codes regardless of mode or dtg_state
74
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tst_ydelay(1:0):
Y delay path control
{tst_cntl2 0x1B(7:6)}
[00]
Adjusts the delay of the Y channel during YCbCr modes
tst_fastramp:
DAC test control, fast ramp
{tst_cntl2 0x1B(1)}
[0]
0 : Normal operation
1 : DAC outputs a ramp at 2x clock rate.
tst_slowramp:
DAC test control, slow ramp
{tst_cntl2 0x1B(0)}
[0]
0 : Normal operation
1 : DAC outputs a ramp at 2x clock rate divided by 64,000. This mode has a higher priority than the one set by tst_fastramp
7.2.4
Data Path Control (Sub-Address 0x1C)
data_clk656_on:
{data_cntl 0x1C(7)}
0 : D1CLKO output off
1 : D1CLKO output on
ITU-R.BT656 output clock control
[0]
data_fsadj:
Full-scale adjust control
{data_cntl 0x1C(6)}
[0]
Selects which full-scale setting to use. See FSADJ terminal description for nominal full-scale adjust resistor values.
0 : Use full-scale setting from resistor connected to FSADJ2 terminal
1 : Use full-scale setting from resistor connected to FSADJ1 terminal
data_ifir12_bypass:
Bypass control 4:2:2 to 4:4:4
{data_cntl 0x1C(5)}
[0]
0 : Interpolation filters before the CSC are in the data path, enabling 4:2:2 to 4:4:4 conversion internally. This mode should be used
when the input data is in 4:2:2 format
1 : Interpolation filters before the CSC are bypassed. This mode should be used when the input data is in 4:4:4 format.
data_ifir35_bypass:
Bypass control 2x interpolation
{data_cntl 0x1C(4)}
[0]
0 : interpolation filters after the CSC are in the data path; enabling 1x to 2x interpolation of the video data.
1 : interpolation filters after the CSC are bypassed. This mode should be used when 1x DAC operation is desired.
data_tristate656:
ITU-R.BT656 output bus
{data_cntl 0x1C(3)}
[0]
0 : the ITU-R.BT656 output bus is active.
1 : the ITU-R.BT656 output bus is in the high-impedance state.
data_dman_cntl(2:0):
Data manager control
{data_cntl 0x1C(2:0)}
[011]
Selects the format for the input data manager, as follows:
dman_cntl
MODE
000
30-bit YCbCr/RGB 4:4:4
001
16-bit RGB 4:4:4
010
15-bit RGB 4:4:4
011
20-bit YCbCr 4:2:2
100
10-bit YCbCr 4:2:2 (ITU mode)
Others
(Reserved)
I2C Registers
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7.2.5
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Display Timing Generator Control, Part 1 (Sub-Addresses 0x1D−0x3C)
dtg1_y_blank(9:0):
Y channel blanking level amplitude control
{dtg1_y_sync_msb 0x23(5:4) and
[10 0000 0000]
dtg1_y_sync1_lsb 0x1D(7:0)}
Sets the amplitude of the blanking level for the Y channel
dtg1_y_sync_low(9:0):
Y channel low sync level amplitude control
{dtg1_y_sync_msb 0x23(3:2) and
[00 0000 0000]
dtg1_y_sync2_lsb 0x1E(7:0)}
Sets the amplitude of the negative sync and equalization/serration/broad pulses for the Y channel
dtg1_y_sync_high(9:0):
Y channel high sync level amplitude control
{dtg1_y_sync_msb 0x23(1:0) and
[11 0000 0000]
dtg1_y_sync3_lsb 0x1F(7:0)}
Sets the amplitude of the positive sync for the Y channel
dtg1_cbcr_blank(9:0):
Cb/Cr channel blanking level amplitude control
{dtg1_cbcr_sync_msb 0x24(5:4) and
[10 0000 0000]
dtg1_cbcr_sync1_lsb 0x20(7:0)}
Sets the amplitude of the blanking level for the Cb and Cr channels
dtg1_cbcr_sync_low (9:0):
Cb/Cr channel low sync level amplitude control
{dtg1_cbcr_sync_msb 0x24(3:2) and
[00 0000 0000]
dtg1_cbcr_sync2_lsb 0x21(7:0)}
Sets the amplitude of the negative sync and equalization/serration/broad pulses for the Cb and Cr channels
dtg1_cbcr_sync_high(9:0):
Cb/Cr channel high sync level amplitude control
{dtg1_cbcr_sync_msb 0x24(1:0) and
[11 0000 0000]
dtg1_cbcr_sync3_lsb 0x22(7:0)}
Sets the amplitude of the positive sync for the Cb and Cr channels
dtg1_spec_a(7:0):
Negative HSync width
{dtg1_spec_a 0x25(7:0)}
[0010 1100] = [44d]
Width of negative excursion of tri-level (HDTV mode) or bi-level (SDTV mode) sync
dtg1_spec_b(7:0):
End of active video to 0H
{dtg1_spec_b 0x26(7:0)}
[0101 1000] = [88d]
Distance from end of active video to start of negative sync (SDTV mode) or to negative-to-positive transition of tri-level sync (HDTV
mode)
dtg1_spec_c(7:0):
Positive Hsync width (HDTV)/Equalization pulse (SDTV) width
{dtg1_spec_c 0x27(7:0)}
[0010 1100] = [44d]
Width of positive excursion of tri-level (HDTV mode). Width of equalization pulses (SDTV mode)
dtg1_spec_d(8:0):
Sync to active video(SDTV)/sync to broad pulse(HDTV)
{dtg1_spec_deh_msb 0x2B(7) and
[0 1000 0100] = [132d]
dtg1_spec_d_lsb 0x28(7:0)}
Distance from leading edge of Hsync to start of active video (SDTV mode) or from negative-to-positive transition of tri-level sync to
start of broad pulse (HDTV mode)
dtg1_spec_d1(7:0):
Center equalization pulse to active video (SDTV)
{dtg1_spec_d1 0x29(7:0)}
[0000 0000]
Distance from equalization pulse at center of line to active video (SDTV mode)
76
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dtg1_spec_e(8:0):
Sync to active video (HDTV)/Color bar start (VESA)
{dtg1_spec_deh_msb 0x2B(6) and
[0 1100 0000] = [192d]
dtg1_spec_e_lsb 0x2A(7:0)}
Distance from negative-to-positive transition of tri-level sync to start of active video (HDTV mode). In case color bars are activated in
VESA mode, this parameter specifies the start of the color bar with respect to the horizontal sync
dtg1_spec_h(9:0):
{dtg1_spec_deh_msb 0x2B(1:0) and
dtg1_spec_h_lsb 0x2C(7:0)}
Duration of broad pulse (SDTV mode)
dtg1_spec_i(11:0):
{dtg1_spec_i_msb 0x2D(3:0) and
dtg1_spec_i_lsb 0x2E(7:0)}
Duration of full-line broad pulse (SDTV mode)
Broad pulse duration (SDTV)
[00 0000 0000]
Full-line broad pulse duration (SDTV)
[0000 0000 0000]
dtg1_spec_k(10:0):
End of active video to sync (SDTV)/end of broad pulse to sync (HDTV)
{dtg1_spec_k_msb 0x30(2:0) and
[000 0101 1000] = [88d]
dtg1_spec_k_lsb 0x2F(7:0)}
Distance from end of active video to leading edge of sync (SDTV) or from end of broad pulse to negative-to-positive transition of trilevel sync (HDTV)
dtg1_spec_k1(7:0):
End of active video in first half of line to center equalization pulse (SDTV)
{dtg1_spec_k1 0x31(7:0)}
[00000000]
Distance from end of active video in first half of line to center equalization pulse for SDTV line type ACTIVE_NEQ
dtg1_spec_g(11:0):
1/2 of line length (SDTV)
{dtg1_spec_g_msb 0x33(3:0) and
[0000 0101 1000] = [88d]
dtg1_spec_g_lsb 0x32(7:0)}
Half the line length. Only used in the calculations of SDTV line types.
dtg1_total_pixels(12:0):
Total pixels per line (SDTV/HDTV/VESA)
{dtg1_total_pixels_msb 0x34(4:0) and
[0 0101 0010 0000] = [1312d]
dtg1_total_pixels_lsb 0x35(7:0)}
Total number of pixels per line. Used in all DTG modes.
dtg1_field_flip:
FID/F polarity select
{dtg1_fieldflip_linecnt_msb 0x36(7)}
[0]
0 : DTG is initialized to field1 at active VS edge when a 0 is received on FID signal or F bit
1 : DTG is initialized to field1 at active VS edge when a 1 is received on FID signal or F bit
dtg1_linecnt(10:0):
DTG start line number
{dtg1_fieldflip_linecnt_msb 0x36(2:0) and
[000 0000 0001]
dtg1_linecnt_lsb 0x37(7:0)}
Sets the starting line number for the DTG when Vsync input or V-bit is asserted (vertical display control)
dtg1_on:
{dtg1_mode 0x38(7)}
0 : DTG output held to dtg_y_blank value
1 : DTG on
DTG on/off
[1]
dtg1_pass_through:
DTG pass-through
{dtg1_mode 0x38(4)}
[0]
0 : Video data blocked during certain line types
1 : Video data passed during certain line types
See DTG Line Types Overview (Section 6.7.3) for details.
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dtg1_mode(3:0):
DTG mode selection
{dtg1_mode 0x38(3:0)}
[0110]
Selects the operation mode of the DTG according to the following table. Each setting is either an SDTV, HDTV or VESA format, as
shown:
dtg1_mode
MODE
0000
ATSC mode 1080P (SMPTE 274M progressive) [HDTV]
0001
ATSC mode 1080I (SMPTE274M interlaced) [HDTV]
0010
ATSC mode 720P (SMPTE296M progressive) [HDTV]
0011
Generic mode for HDTV [HDTV]
0100
ATSC mode 480I (SDTV 525 lines interlaced) [SDTV]
0101
ATSC mode 480P (SDTV 525 lines progressive) [SDTV]
0110
VESA master [VESA]
0111
VESA slave [VESA]
1000
SDTV 625 interlaced [SDTV]
1001
Generic mode for SDTV [SDTV]
Others
[Null]
dtg1_frame_size(10:0):
Generic mode frame size
{dtg1_frame_field_size_msb 0x39(6:4) and
[011 0000 0000]
dtg1_framesize_lsb 0x3A(7:0)}
Determines number of lines per frame when in generic mode
dtg1_field_size(10:0):
Generic mode field size
{dtg1_frame_field_size_msb 0x39(2:0) and
[000 0010 0000]
dtg1_fieldsize_lsb 0x3B(7:0)}
Determines number of lines in field 1 when in generic mode. This number should be programmed higher than frame_size for
progressive scan formats.
dtg1_vesa_cbar_size(7:0):
Color bar pattern, width
{dtg1_vesa_cbar_size 0x3C(7:0)}
[1000 0000]
Sets the width of each color bar in the color bar test pattern. This test pattern is only available when the DTG is in VESA mode.
7.2.6
DAC Control (Sub-Addresses 0x3D−0x40)
dac_i2c_cntl:
DAC I2C control
{dac_cntl_msb 0x3D(6)}
[0]
0 : DAC normal operation
1 : DAC inputs are fixed to values of registers
78
dac1_cntl(9:0):
{dac_cntl_msb 0x3D(5:4) and
dac1_cntl_lsb 0x3E(7:0)}
Direct input to G/Y DAC
DAC1 input value
[00 0000 0000]
dac2_cntl(9:0):
{dac_cntl_msb 0x3D(3:2) and
dac2_cntl_lsb 0x3F(7:0)}
Direct input to B/Cb DAC
DAC2 input value
[00 0000 0000]
dac3_cntl(9:0):
{dac_cntl_msb 0x3D(1:0) and
dac3_cntl_lsb 0x40(7:0)}
Direct input to R/Cr DAC
DAC3 input value
[00 0000 0000]
I2C Registers
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Clip/Shift/Multiplier Control (Sub-Addresses 0x41−0x4F)
csm_clip_gy_low(7:0):
G/Y low clipping value
{csm_clip_gy_low 0x41(7:0)}
[0100 0000]
Sets the value at which low end clipping occurs on G/Y channel, if clipping is enabled. Range is 0−255.
csm_clip_bcb_low(7:0):
B/Cb low clipping value
{csm_clip_bcb_low 0x42(7:0)}
[0100 0000]
Sets the value at which low end clipping occurs on B/Cb channel, if clipping is enabled. Range is 0−255.
csm_clip_rcr_low(7:0):
R/Cr low clipping value
{csm_clip_rcr_low 0x43(7:0)}
[0100 0000]
Sets the value at which low end clipping occurs on R/Cr channel, if clipping is enabled. Range is 0−255.
csm_clip_gy_high(7:0):
G/Y high clipping value
{csm_clip_gy_high 0x44(7:0)}
[0101 0011]
Sets the value at which high end clipping occurs on G/Y channel, if clipping is enabled.
High clip value = 1023-csm_clip_gy_high
csm_clip_bcb_high(7:0):
B/Cb high clipping value
{csm_clip_bcb_high 0x45(7:0)}
[0011 1111]
Sets the value at which high end clipping occurs on B/Cb channel, if clipping is enabled.
High clip value = 1023−csm_clip_bcb_high
csm_clip_rcr_high(7:0):
R/Cr high clipping value
{csm_clip_rcr_high 0x46(7:0)}
[0011 1111]
Sets the value at which high end clipping occur on R/Cr channel, if clipping is enabled.
High clip value = 1023−csm_clip_rcr_highs
csm_shift_gy(7:0):
G/Y shift value
{csm_shift_gy 0x47(7:0)}
[0100 0000]
Value that G/Y data is shifted downwards. Range 0−255. Note: it is possible to shift the data so much that a roll over condition occurs.
csm_shift_bcb(7:0):
B/Cb shift value
{csm_shift_bcb 0x48(7:0)}
[0100 0000]
Value that B/Cb data is shifted downwards. Range: 0−255. Note: It is possible to shift the data so much that a roll over condition
occurs.
csm_shift_rcr(7:0):
R/Cr shift value
{csm_shift_rcr 0x49(7:0)}
[0100 0000]
Value that B/Cb data is shifted downwards. Range: 0−255. Note: It is possible to shift the data so much that a roll over condition
occurs.
csm_mult_gy_on:
{csm_gy_cntl_mult_msb 0x4A(7)}
0 : Scaling for G/Y channel off
1 : Scaling for G/Y channel on
G/Y scaling on/off
[0]
csm_shift_gy_on:
{csm_gy_cntl_mult_msb 0x4A(6)}
0 : Shifting for G/Y channel off
1 : Shifting for G/Y channel on
G/Y shifting on/off
[0]
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csm_gy_high_clip_on:
{csm_gy_cntl_mult_msb 0x4A(5)}
0 : G/Y data clipping at high end off
1 : G/Y data clipping at high end on
G/Y high-end clipping on/off
[0]
csm_gy_low_clip_on:
{csm_gy_cntl_mult_msb 0x4A(4)}
0 : G/Y data clipping at low end off
1 : G/Y data clipping at low end on
G/Y low-end clipping on/off
[0]
csm_of_cntl:
CSM overflow control
{csm_gy_cntl_mult_msb 0x4A(3)}
[1]
Controls overflow protection of the CSM multiplier
0 : Overflow protection off
1 : Overflow protection on
Numerical format of the CSM mult registers:
The 11-bit value is a binary weighted value in the range 0−1.999.
Thus: csm_mult_(10:0) = [(multiplier in range 0..1.999)/1.999] × 2047.
csm_mult_gy(10:0):
G/Y scaling value
{csm_gy_cntl_mult_msb 0x4A(2:0) and
[000 0000 0000]
csm_mult_gy_lsb 0x4C(7:0)}
Multiplication factor for G/Y channel in CSM. Range: 0−1.999.
Note: it is possible to scale the input so much that a rollover occurs.
csm_mult_bcb(10:0):
B/Cb scaling value
{csm_mult_bcb_rcr_msb 0x4B(6:4) and
[000 0000 0000]
csm_mult_bcb_lsb 0x4D(7:0)}
Multiplication factor for B/Cb channel in CSM. Range: 0−1.999.
Note: it is possible to scale the input so much that a rollover occurs.
csm_mult_rcr(10:0):
R/Cr scaling value
{csm_mult_bcb_rcr_msb 0x4B(2:0) and
[000 0000 0000]
csm_mult_rcr_lsb 0x4E(7:0)}
Multiplication factor for R/Cr channel in CSM. Range: 0−1.999.
Note: it is possible to scale the input so much that a rollover occurs.
80
csm_mult_rcr_on:
{csm_rcr_bcb_cntl 0x4F(7)}
0 : Scaling for R/Cr channel off
1 : Scaling for R/Cr channel on
R/Cr scaling on/off
[0]
csm_mult_bcb_on:
{csm_rcr_bcb_cntl 0x4F(6)}
0 : Scaling for B/Cb channel of
1 : Scaling for B/Cb channel on
B/Cb scaling on/off
[0]
csm_shift_rcr_on:
{csm_rcr_bcb_cntl 0x4F(5)}
0 : Shifting for R/Cr channel off
1 : Shifting for R/Cr channel on
R/Cr shifting on/off
[0]
I2C Registers
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csm_shift_bcb_on:
{csm_rcr_bcb_cntl 0x4F(4)}
0 : Shifting for B/Cb channel off
1 : Shifting for B/Cb channel on
B/Cb shifting on/off
[0]
csm_rcr_high_clip_on:
{csm_rcr_bcb_cntl 0x4F(3)}
0 : R/Cr data clipping at high end off
1 : R/Cr data clipping at high end on
R/Cr high-end clipping on/off
[0]
csm_rcr_low_clip_on:
{csm_rcr_bcb_cntl 0x4F(2)}
0 : R/Cr data clipping at low end off
1 : R/Cr data clipping at low end on
R/Cr low-end clipping on/off
[0]
csm_bcb_high_clip_on:
{csm_rcr_bcb_cntl 0x4F(1)}
0 : B/Cb data clipping at high end off
1 : B/Cb data clipping at high end on
B/Cb high-end clipping on/off
[0]
csm_bcb_low_clip_on:
{csm_rcr_bcb_cntl 0x4F(0)}
0 : B/Cb data clipping at low end off
1 : B/Cb data clipping at low end on
B/Cb low-end clipping on/off
[0]
7.2.8
Display Timing Generator Control, Part 2 (Sub-Addresses 0x50−0x82)
dtg2_bp(10:0):
breakpoint line number
{see register map table}
[000 0000 0000]
DTG outputs line type dtg2_linetype until line number of dtg2_bp is reached. (n = 1..16)
dtg2_linetype(3:0):
Line type for dtg2_bp
{see register map table}
[0000]
The DTG outputs a line format corresponding to the table below until the next breakpoint line number is reached. (n = 1..16)
LINE TYPE
MODE
0000
ACTIVE_VIDEO
0001
FULL_NTSP
0010
FULL_BTSP
0011
NTSP_NTSP
0100
BTSP_BTSP
0101
NTSP_BTSP
0110
BTSP_NTSP
0111
ACTIVE_NEQ
1000
NSP_ACTIVE
1001
FULL_NSP
1010
FULL_BSP
1011
FULL_NEQ
1100
NEQ_NEQ
1101
BSP_BSP
1110
BSP_NEQ
1111
NEQ_BSP
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dtg2_hlength(9:0):
{dtg2_hlength_msb_hdly_msb 0x71(7:6) and
dtg2_hlength_lsb 0x70(7:0)}
Sets the duration of the HS_OUT output signal
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HS_OUT duration
[00 0110 0000]
dtg2_hdly(12:0):
HS_OUT delay
{dtg2_hlength_msb_hdly_msb 0x71(4:0) and
[0 0000 0000 0010]
dtg2_hdly_lsb 0x72(7:0)}
Sets the pixel value that the HS_OUT signal is asserted on.
Note: when programmed to a value higher than the total number of pixels per line, there will be no HS_OUT output.
dtg2_vlength1(9:0):
VS_OUT duration, field 1
{dtg2_vlength1_msb_vdly1_msb 0x74(7:6) and [00 0000 0011]
dtg2_vlength1_lsb 0x73(7:0)}
Sets the duration of the VS_OUT output signal during progressive scan video modes or during the vertical blank interval of field 1 in
interlaced video modes.
dtg2_vdly1(10:0):
VS_OUT delay, field 1
{dtg2_vlength1_msb_vdly1_msb 0x74(2:0) and [000 0000 0011]
dtg2_vdly1_lsb 0x75(7:0)}
Sets the line number that the VS_OUT signal is asserted on for progressive video modes or for field 1 of interlaced video modes.
Note: when programmed to a value higher than the total number of lines per frame, there is no VS_OUT output.
dtg2_vlength2(9:0):
VS_OUT duration, field 2
{dtg2_vlength2_msb_vdly2_msb 0x77(7:6) and [00 0000 0000]
dtg2_vlength2_lsb 0x76(7:0)}
Sets the duration of the VS_OUT output signal during the vertical blank interval of field 2 in interlaced video modes. In progressive
video modes, this register must be set to all 0.
dtg2_vdly2(10:0):
VS_OUT delay, field 2
{dtg2_vlength2_msb_vdly2_msb 0x77(2:0) and [111 1111 1111]
dtg2_vdly2_lsb 0x78(7:0)}
Sets the line number that the VS_OUT signal is asserted on for field 2 of interlaced scan video modes. For progressive scan video
modes, this register must be set to all 1.
dtg2_hs_in_dly(12:0):
DTG horizontal delay
{dtg2_hs_in_dly_msb 0x79(4:0) and
[0 0000 0011 1101]
dtg2_hs_in_dly_lsb 0x7A(7:0)}
Sets the number of pixels that the DTG startup is horizontally delayed with respect to HS input for dedicated timing modes or EAV
input for embedded timing modes.
Note: It is possible to delay startup past the end of a line when this delay is programmed higher than the total number of pixels per
line.
dtg2_vs_in_dly(10:0):
DTG vertical delay
{dtg2_vs_in_dly_msb 0x7B(2:0) and
[000 0000 0011]
dtg2_vs_in_dly_lsb 0x7C(7:0)}
Sets the number of lines that the DTG startup is vertically delayed with respect to VS input for dedicated timing modes or the line
counter value for embedded timing.
Note: It is possible to delay startup past the end of a frame when this delay is programmed higher than the total number of lines per
frame.
dtg2_pixel_cnt(15:0):
Pixel count readback
{dtg2_pixel_cnt_msb 0x7D(7:0) and
dtg2_pixel_cnt_lsb 0x7E(7:0)}
Reports the number of clock 1x rising edges between consecutive Hsync input pulses
82
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dtg2_ip_fmt:
Interlaced/progressive-scan indicator
{dtg2_line_cnt_msb 0x7F(7)}
Indicates whether current video frame is progressive (0) or interlaced (1)
dtg2_line_cnt(10:0):
Line count readback
{dtg2_lined_cnt_msb 0x7F(2:0) and dtg2_line_cnt_lsb 0x80(7:0)}
Reports the number of Hsync input pulses between consecutive dtg_start signals (that is, over one frame period)
dtg2_fid_de_cntl:
FID (field-ID)/DE (data enable)input selection for FID terminal
{dtg2_cntl 0x82(7)}
[0]
Controls interpretation of signal on FID terminal
0 : Signal interpeted as FieldID
1 : If the DTG is programmed to the VESA mode, the FID pin becomes a data-enable input pin. Data enable is assumed high during
the active video window, and low outside this area. This is compatible with the DE signal from TI DVI receivers. Data is passed
through the THS8200 only when data enable is high. Otherwise, the input data is overridden by the THS8200 internally programmed
blanking value. If the DTG is programmed in the SDTV or HDTV video mode with dedicated timing signals, a 1 in this register location
causes the THS8200 to generate an internal FieldID value from the relative alignment of Hsync and Vsync inputs, rather than using
the signal on the FID input pin (which is ignored). This is for EIA-861 compliant operation for video-over-DVI 1.0 (with HDCP) where
there is no dedicated FID signal available but the even/odd field ID is determined from Hsync/Vsync alignment.
dtg2_rgb_mode_on:
RGB/YPbPr mode selection
{dtg2_cntl 0x82(6)}
[1]
This selection affects the relative blank vs video level position: on R,G,B, and Y channels an offset is added to the DAC outputs
0 : YPbPr mode (blanking at bottom range for Y – mid-range for Pb, Pr channels)
1 : RGB mode (blanking at bottom ranges for all channels)
dtg2_embedded_timing:
Video sync input source
{dtg2_cntl 0x82(5)}
[0]
0 : Timing of video input bus is derived from HS, VS, and FID dedicated inputs
1 : Timing of video input bus is assumed embedded in video data using SAV/EAV code sequences.
dtg2_vsout_pol:
{dtg2_cntl 0x82(4)}
0 : Negative polarity
1 : Positive polarity
VS_OUT polarity
[1]
dtg2_hsout_pol:
{dtg2_cntl 0x82(3)}
0 : Negative polarity
1 : Positive polarity
HS_OUT polarity
[1]
dtg2_fid_pol:
{dtg2_cntl 0x82(2)}
0 : Negative polarity
1 : Positive polarity
FID polarity
[1]
dtg2_vs_pol:
{dtg2_cntl 0x82(1)}
0 : Negative polarity
1 : Positive polarity
VS_IN polarity
[1]
dtg2_hs_pol:
{dtg2_cntl 0x82(0)}
0 : Negative polarity
1 : Positive polarity
HS_IN polarity
[1]
I2C Registers
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misc_ppl(15:0):
HS high
{misc_ppl_msb 0x87(7:0) and misc_ppl_lsb 0x86(7:0)}
Reports the number of clock cycles HS was held high
misc_lpf(15:0):
VS high
{misc_lpf_msb 0x89(7:0) and misc_lpf_lsb 0x88(7:0)}
Reports the number of HS counts that VS was held high.
7.2.9
CGMS Control (Sub-Addresses 0x83−0x85)
cgms_en:
CGMS enable
{cgms_cntl_header 0x83(6)}
[0]
0 : No CGMS data inserted
1 : CGMS data inserted on line 41 in SDTV mode
cgms_header:
{cgms_cntl_header 0x83(5:0)}
CGMS header
[00 0000]
cgms_payload(13:0):
{cgms_payload_msb 0x84(5:0) and
cgms_payload_lsb 0x85(7:0)}
CGMS payload data
CGMS payload
[00 0000 0000 0000]
7.3
THS8200 Preset Mode Line Type Definitions
The following are the (line type, breakpoint) combinations that are preprogrammed when selecting the
corresponding DTG preset setting.
7.3.1
SMPTE_274P (1080P)
Breakpoints
Line Type
6
FULL_BTSP
42
FULL_NTSP
1122
ACTIVE_VIDEO
1126
FULL_NTSP
frame_size = 10001100101; 1125d
field_size = 11111111111; not needed
7.3.2
274M Interlaced (1080I)
Breakpoints
Line Type
6
BTSP_BTSP
7
NTSP_NTSP
21
FULL_NTSP
561
ACTIVE_VIDEO
563
FULL_NTSP
564
NTSP_BTSP
568
BTSP_BTSP
569
BTSP_NTSP
584
FULL_NTSP
1124
ACTIVE_VIDEO
1126
FULL_NTSP
frame_size = 10001100101; 1125d
field_size = 01000110011; 563d
84
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7.3.3
SLES032E – JUNE 2002 – REVISED SEPTEMBER 2014
296M Progressive (720P)
Breakpoints
Line Type
6
FULL_BTSP
26
FULL_NTSP
746
ACTIVE_VIDEO
751
FULL_NTSP
frame_size = 01011101110; 750d
field_size = 11111111111; not needed
7.3.4
SDTV 525 Interlaced Mode
Breakpoints
Line Type
4
NEQ_NEQ
7
BSP_BSP
10
NEQ_NEQ
20
FULL_NSP
263
ACTIVE_VIDEO
264
ACTIVE_NEQ
266
NEQ_NEQ
267
NEQ_BSP
269
BSP_BSP
270
BSP_NEQ
272
NEQ_NEQ
273
FULL_NEQ
282
FULL_NSP
283
NSP_ACTIVE
526
ACTIVE_VIDEO
frame_size = 1000001101; 525d
field_size = 00100000111; 263d
7.3.5
SDTV 525 Progressive Mode
Breakpoints
Line Type
10
FULL_NSP
16
FULL_BSP
46
FULL_NSP
526
ACTIVE_VIDEO
frame_size = 01000001101; 525d
field_size = 11111111111; not needed
I2C Registers
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7.3.6
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SDTV 625 Interlaced Mode
Breakpoints
Line Type
3
BSP_BSP
4
BSP_NEQ
6
NEQ_NEQ
23
FULL_NSP
24
NSP_ACTIVE
311
ACTIVE_VIDEO
313
NEQ_NEQ
314
NEQ_BSP
316
BSP_BSP
318
NEQ_NEQ
319
FULL_NEQ
336
FULL_NSP
623
ACTIVE_VIDEO
624
ACTIVE_NEQ
626
NEQ_NEQ
frame_size = 01001110001; 625d
field_size = 00100111000; 312d
86
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8 Application Information
8.1
Video vs Computer Graphics Application
THS8200 is a highly integrated and flexible universal analog component video/graphics generator that can
be used in any application requiring D/A conversion of video/graphics signals.
In a typical video application (for example, DVD player, set-top box), the THS8200 receives its input from
an MPEG decoder or media processor engine and converts the signal into the analog domain, thereby
generating the correct timing/frame format for the selected format.
Its ITU-R.BT656 output port could be used to connect to an NTSC/PAL video encoder, such as the Texas
Instruments TVP6000, for regular composite/S-video output.
Note that because the DAC speed is rated up to 205 MSPS, all popular SDTV and HDTV formats,
including 1080I and 720P, are supported in both 1x and 2x interpolated modes. The 1080P is supported at
the 1x rate.
MPEG Decoder
or
Media
Processor
Signal Receiver
(From Satellite,
Cable, DVD Disk)
R/Y
THS8200
CCIR656
HDTV
Monitor
G/Pb
B/Pr
NTSC/PAL
Video Encoder
SDTV
(NTSC/PAL)
Figure 8-1. Typical Video Application
Because of its programmable Hsync/Vsync outputs, the on-chip support for RGB as well as YCbCr color
spaces and its internal color space conversion circuit, and the DAC operational speed of 205 MSPS, all
PC graphics formats are supported as well, up to UXGA at 75 Hz. Video interpolation is now bypassed so
that the full 205 MSPS can be used for the 1x pixel clock.
R
3-D/2-D
Graphics
Controller
24 Bits
THS8200
G
B
VESA
Compatible
CRT Monitor
HS_OUT
VS_OUT
Figure 8-2. Computer Graphics Application
8.2
DVI to Analog YPbPr/RGB Application
Together with a DVI receiver, this device forms a two-chip solution to convert video or graphics formats
sent over a DVI interface to an analog RGB or YPbPr format using embedded composite sync or separate
Hsync, Vsync. THS8200 connects gluelessly to a DVI receiver using its data input bus and HS_IN and
VS_IN terminals. TI DVI 1.0 (with HDCP) receivers provide a data enable (DE) signal that is high during
the active video window. The THS8200 can be configured to interpret this DE signal on its FID terminal to
automatically insert a user-programmable blanking-level amplitude outside the active video window on its
analog outputs; this blanking level can be correctly positioned for either RGB or YPbPr analog outputs.
The user can optionally perform color space conversion in the THS8200 and adjust offset and gain ranges
through the device's CSM block.
Application Information
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When sending (interlaced) video over DVI, the EIA-861 specification describes a method to derive the
fieldID signal—not directly available from a DVI1.0 (with HDCP) receiver—from the relative alignment of
the Hsync and Vsync signals. The THS8200 can be configured to derive internally the correct even/odd
field identification from Hsync/Vsync alignment according to this specification, instead of using the FieldID
signal on its FID input terminal. This avoids the need for additional glue logic in a DVI application.
8.3
Master vs Slave Timing Modes
In slave timing mode, the THS8200 output display timing is synchronized to the video data source. Display
timing output signals are based on input sync signals, either fed to the device on the dedicated Hsync,
Vsync, and FieldID (HS_IN, VS_IN, and FID) input terminals or based on SAV/EAV codes embedded in
the input video data.
GY[9:0]
BPb[9:0]
G/Y
RPr[9:0]
MPEG Decoder/
Graphics Processor/
Video Memory
B/Pb
R/Pr
THS8200
CLKIN
HS_OUT
HS
Drive TV or
Computer Monitor
VS_OUT
VS
FID
SCL
D1CLK
SDA
DO[9:0]
To an I2C
Master Device
To an NTSC/PAL
Encoder
Figure 8-3. Slave Operation Mode of THS8200
In master timing mode, the THS8200 generates two sets of output synchronization signals.
• HS_IN and VS_IN now become output signals to the video source (FID unused).
• HS_OUT and VS_OUT are still output signals to display device.
The intended purpose is that THS8200 requests video data from a source that requires external timing,
such as video memory.
88
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THS8200
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GY[9:0]
BPb[9:0]
G/Y
RPr[9:0]
MPEG Decoder/
Graphics Processor/
Video Memory
B/Pb
R/Pr
THS8200
CLKIN
HS
VS_OUT
VS
SCL
D1CLK
SDA
DO[9:0]
To an I2C
Master Device
Computer Monitor
HS_OUT
To an NTSC/PAL
Encoder
Figure 8-4. Master Operation Mode of THS8200
Application Information
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9 Device and Documentation Support
9.1
Device Support
9.1.1
Development Support
9.1.1.1
Getting Started and Next Steps
To get started with TI video and imaging product, see the Parametric Search on www.ti.com.
9.1.2
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
devices and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for example,
THS8200).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the final device's electrical
specifications and may not use production assembly flow.
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet
final electrical specifications.
null
Production version of the silicon die that is fully qualified.
X and P devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality
and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PFP) and the temperature range (for example, blank is the default commercial
temperature range).
For orderable part numbers of THS8200 devices in the PFP package types, see the Package Option
Addendum of this document, the TI website (www.ti.com), or contact your TI sales representative.
90
Device and Documentation Support
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Product Folder Links: THS8200
THS8200
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9.2
SLES032E – JUNE 2002 – REVISED SEPTEMBER 2014
Documentation Support
The following documents describe the THS8200 device. Copies of these documents are available on the
Internet at www.ti.com. Additional documents are available at www.ti.com/product/ths8200.
9.2.1
SLEA078
THS8200 PCB Layout Guidelines. Guidelines to help optimize device performance.
SPRA961
High Resolution Video Using the DM642 DSP and the THS8200 Driver. Gives a brief
discussion on the HDTV standards and demonstrates the hardware requirements and
implementation for interfacing the DM642 video port to a THS8200.
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster
innovation and growth of general knowledge about the hardware and software surrounding
these devices.
9.3
Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
9.4
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
9.5
Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2002–2014, Texas Instruments Incorporated
Mechanical, Packaging, and Orderable Information
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91
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
THS8200PFP
ACTIVE
HTQFP
PFP
80
96
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
THS8200
D
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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