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THVD1520
SLLSF67 – OCTOBER 2019
THVD1520 10 Mbps RS-485 Transceiver With ±8-kV IEC ESD Protection
1 Features
2 Applications
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
Meets or exceeds the requirements of the
TIA/EIA-485A standard
4.5-V to 5.5-V supply voltage
10 Mbps, Half-Duplex RS-422/RS-485
Bus I/O protection
– ± 16-kV HBM ESD
– ± 8-kV IEC 61000-4-2 contact discharge
– ± 8-kV IEC 61000-4-2 air gap discharge
– ± 4-kV IEC 61000-4-4 fast transient burst
Extended industrial temperature range: -40°C to
125°C
Large receiver hysteresis for noise rejection
Low power consumption
– Low standby supply current: < 1 µA
– Quiescent during operation: < 840 µA
Glitch-free power-up/down for hot plug-in
capability
Open, short and idle bus failsafe
1/8 unit load (up to 256 bus nodes)
Factory Automation & Control
Building Automation
HVAC Systems
Video Surveillance
Smart Meters
3 Description
THVD1520 is a robust half-duplex RS-485 transceiver
for industrial applications. The bus pins are immune
to high levels of IEC contact discharge ESD events
eliminating the need of additional system-level
protection components.
The device operates from a single 5-V supply. The
wide common-mode voltage range and low input
leakage on bus pins make THVD1520 suitable for
multi-point applications over long cable runs.
THVD1520 is available in industry standard 8-pin
SOIC package for drop-in compatibility. The device is
characterized for ambient temperatures from –40°C
to 125°C.
Device Information(1)
PART NUMBER
THVD1520
PACKAGE
SOIC (8)
BODY SIZE (NOM)
4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Spacer
Spacer
Simplified Schematic
R
RE
DE
D
1
2
7
3
6
B
A
4
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
THVD1520
SLLSF67 – OCTOBER 2019
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
5
5
6
7
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
ESD Ratings [IEC] ....................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Power Dissipation Characteristics ............................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 11
9
Application and Implementation ........................ 13
9.1 Application Information........................................ 13
9.2 Typical Application ................................................. 13
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
11.2 Layout Example .................................................... 19
12 Device and Documentation Support ................. 20
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Parameter Measurement Information .................. 9
Detailed Description ............................................ 11
Device Support......................................................
Third-Party Products Disclaimer ...........................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
20
20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
8.1 Overview ................................................................. 11
8.2 Functional Block Diagrams ..................................... 11
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
October 2019
*
Initial release.
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5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
R
1
8
VCC
RE
2
7
B
DE
3
6
A
D
4
5
GND
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
R
1
Digital output
Receive data output
RE
2
Digital input
Receiver enable, active low (internal 5-MΩ pull-up)
DE
3
Digital input
Driver enable, active high (internal 5-MΩ pull-down)
D
4
Digital input
Driver data input (internal 5-MΩ pull-up)
GND
5
Ground
A
6
Bus input/output
Bus I/O port, A (complementary to B)
B
7
Bus input/output
Bus I/O port, B (complementary to A)
VCC
8
Power
Device ground
5-V supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VCC
Supply voltage
–0.5
7
V
VL
Input voltage at any logic pin (D, DE or RE)
–0.3
5.7
V
VA, VB
Voltage at A or B inputs, as differential or common-mode with respect to GND
–18
18
V
IO
Receiver output current
–24
24
mA
TJ
Junction temperature
170
°C
TSTG
Storage temperature
150
°C
(1)
–65
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
VALUE
UNIT
Bus terminals and GND
±16,000
V
All other pins
±4,000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
(1)
(2)
±1,500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings [IEC]
VALUE
V(ESD)
4
Electrostatic discharge
IEC 61000-4-2 ESD (Contact Discharge), bus terminals and GND
±8,000
IEC 61000-4-2 ESD (Air-Gap Discharge), bus terminals and GND
±8,000
IEC 61000-4-4 EFT (Fast transient or burst), bus terminals and GND
±4,000
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UNIT
V
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6.4 Recommended Operating Conditions
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
V
VID
Differential input voltage
–12
12
V
VI
Input voltage at any bus terminal (1)
–7
12
V
VIH
High-level input voltage (driver, driver-enable, and receiver-enable inputs)
2
VCC
V
VIL
Low-level input voltage (driver, driver-enable, and receiver-enable inputs)
0
0.8
V
–60
60
–8
8
IO
Output current
RL
Differential load resistance
1/tUI
Signaling rate
TJ
Junction temperature
TA (2)
Operating ambient temperature
(1)
(2)
Driver
Receiver
54
UNIT
mA
60
Ω
10
Mbps
–40
150
°C
–40
125
°C
The algebraic convention in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
Operation is specified for internal (junction) temperatures upto 150°C. Self-heating due to internal power dissipation should be
considered for each application. Maximum junction temperature is internally limited by the thermal shutdown (TSD) circuit which disables
the device when the junction temperature reaches 170°C.
6.5 Thermal Information
THVD1520
THERMAL METRIC (1)
D (SOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
125.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
67.6
°C/W
RθJB
Junction-to-board thermal resistance
68.6
°C/W
ψJT
Junction-to-top characterization parameter
20.4
°C/W
ψJB
Junction-to-board characterization parameter
67.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
1.5
2.5
1.5
2.5
2
3
MAX
UNIT
Driver
Vtest from –7 to +12 V
Driver differential-output voltage
magnitude
│VOD│
RL = 54 Ω (RS-485), CL = 50 pF
RL = 100 Ω (RS-422), CL = 50 pF
Δ│VOD│
Change in magnitude of driver
differential-output voltage
VOC(SS)
Steady-state common-mode
output voltage
ΔVOC
Change in differential driver
common-mode output voltage
VOC(PP)
Peak-to-peak driver commonmode output voltage
│IOS│
Driver short-circuit output current
COD
Differential output capacitance
RL = 54 Ω or 100 Ω, CL = 50 pF
See Figure 7
See Figure 8
See Figure 8
–50
1
RL = 54 Ω or 100 Ω, CL = 50 pF
See Figure 8
VCC / 2
–50
V
50
mV
3
V
50
mV
220
DE = VCC, -7 V ≤ [VA or VB] ≤ 12 V, or A pin shorted to B
pin
mV
150
8
mA
pF
Receiver
VI = 12 V
75
110
II
Bus input current (driver disabled)
DE = 0 V, VCC = 0 V or 5.5 V
RA, RB
Bus input impedance
VA = -7 V, VB = 12 V and VA = 12
V, VB = -7 V
VIT+
Positive-going receiver
differential-input voltage threshold
VIT–
Negative-going receiver
differential-input voltage threshold
–200
–150
mV
VHYS (1)
Receiver differential-input voltage
threshold hysteresis (VIT+ – VIT– )
40
60
mV
VOH
Receiver high-level output voltage
IOH = –8 mA
4
VCC – 0.3
VOL
Receiver low-level output voltage
IOL = 8 mA
IOZ
Receiver high-impedance output
current
VO = 0 V or VCC, RE = VCC
IOSR
Receiver output short-circuit
current
RE = 0, DE = 0
VI = –7 V
See Figure 12
–90
–70
96
µA
kΩ
–90
0.2
–1
See Figure 13
–50
mV
V
0.4
V
1
µA
95
mA
2.5
µA
Logic
IIN
Input current (D, DE, RE)
–2.5
Supply
ICC
(1)
6
Driver and receiver enabled
DE = VCC, RE = 0,
no load
600
840
Driver enabled, receiver disabled
DE = VCC, RE =
VCC, no load
440
580
Driver disabled, receiver enabled
DE = 0, RE = 0, no
load
530
680
Driver and receiver disabled
DE = 0, RE = VCC,
no load
0.1
1
Supply current (quiescent)
µA
Under any specific conditions, VIT+ is specified to be at least VHYS higher than VIT–.
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6.7 Power Dissipation Characteristics
PARAMETER
PD
Power dissipation, driver and
receiver enabled, VCC = 5.5 V, TA =
125°C, 50% duty cycle square-wave
signal at maximum signaling rate
TEST CONDITIONS
VALUE
Unterminated
RL = 300 Ω, CL = 50 pF
100
RS-422 load
RL = 100 Ω, CL = 50 pF
135
RS-485 load
RL = 54 Ω, CL = 50 pF
190
UNIT
mW
6.8 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
10
UNIT
Driver
tr, tf
Driver differential output rise and fall times
See Figure 9
17
30
ns
tPHL, tPLH
Driver propagation delay
See Figure 9
20
35
ns
tSK(P)
Driver pulse skew, |tPHL – tPLH|
See Figure 9
0.8
4
ns
Driver disable time
See
Figure 10 and Figure 11
25
100
ns
Receiver enabled
See
Figure 10 and Figure 11
25
100
ns
Receiver disabled
See
Figure 10 and Figure 11
1.5
3
µs
tPHZ, tPLZ
tPHZ, tPLZ
Driver enable time
Receiver
tr, tf
Receiver output rise and fall times
See Figure 14
5
15
ns
tPHL, tPLH
Receiver propagation delay time
See Figure 14
50
95
ns
tSK(P)
Receiver pulse skew, |tPHL – tPLH|
See Figure 14
3
15
ns
tPHZ, tPLZ
Receiver disable time
See Figure 15
15
30
ns
Driver enabled
See Figure 15
25
170
ns
Driver disabled
See Figure 16
1
5
µs
tPZL(1),
tPZH(1)
tPZL(2),
tPZH(2)
Receiver enable time
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6.9 Typical Characteristics
4.8
4.5
4.2
3.9
3.6
3.3
3
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
VOL
VOH
Driver Differential Output Voltage (V)
Driver Output Voltage (V)
VCC = 5 V, TA = 250C (unless otherwise noted)
3.6
3
2.4
1.8
1.2
0.6
0
-0.6
0
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75
Driver Output Current (mA)
D_00
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75
Driver Output Current (mA)
D_00
Figure 2. Driver Differential Output Voltage vs Driver Output
Current
Figure 1. Driver Output Voltage vs Driver Output Current
21.5
65
60
55
50
45
40
35
30
25
20
15
10
5
0
21
Driver Rise and Fall Times (ns)
Driver Output Current (mA)
4.2
20.5
20
19.5
19
18.5
18
17.5
17
Rise time
Fall time
16.5
16
-40
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7
Supply Voltage (V)
D_00
-20
0
20
40
60
80
Temperature (0C)
100
120
140
D004
Figure 4. Driver Rise or Fall Time vs Temperature
Figure 3. Driver Output Current vs Supply Voltage
46.5
24
45.9
22
Supply Current (mA)
Driver Propagation Delay (ns)
46.2
23
21
20
19
18
45.6
45.3
45
44.7
44.4
44.1
17
TPLH
TPHL
16
-40
-20
0
20
40
60
80
Temperature (0C)
100
120
43.8
140
43.5
0
2000
D005
Figure 5. Driver Propagation Delay vs Temperature
50% duty
cycle squarewave
4000
6000
Signaling Rate (kbps)
RL = 54 Ω
CL = 50 pF
8000
10000
D006
DE = VCC, RE
= GND
Figure 6. Supply Current vs Signaling Rate
8
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7 Parameter Measurement Information
375 Ÿ
Vcc
DE
A
D
VOD
0V or Vcc
Vtest
RL
B
375 Ÿ
Figure 7. Measurement of Driver Differential Output Voltage With Common-Mode Load
A
0V or Vcc
A
D
RL/2
VA
B
VB
VOD
RL/2
B
CL
VOC(PP)
VOC
ûVOC(SS)
VOC
Figure 8. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
Vcc
Vcc
DE
A
D
Input
Generator
VI
50%
VI
VOD
50 Ÿ
0V
tPHL
tPLH
RL=
54 Ÿ
CL= 50 pF
90%
50%
10%
B
VOD
tr
tf
~2 V
~ ±2V
Figure 9. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
A
D
S1
Vcc
VO
50%
VI
B
DE
Input
Generator
VI
RL =
110 Ÿ
CL =
50 pF
50 Ÿ
0V
tPZH
90%
VO
VOH
50%
~
~ 0V
tPHZ
Figure 10. Measurement of Driver Enable and Disable Times With Active High Output and Pull-Down
Load
Vcc
Vcc
A
S1
B
D
DE
Input
Generator
RL= 110 Ÿ
CL=
50 pF
VO
50%
VI
0V
tPZL
tPLZ
§ Vcc
VO
50 %
VI
10%
VOL
50 Ÿ
Figure 11. Measurement of Driver Enable and Disable Times With Active Low Output and Pull-up Load
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Parameter Measurement Information (continued)
VCC
RE
VCC
DE
A
DI
B
VX
VA
=
Source meter to apply
VA/VB and measure IA/IB
IA
VB
IB
GND
R
Figure 12. Measurement of Bus Impedance
VCC
A
RE
VCC
DE
A
DI
B
R
GND
Figure 13. Measurement of Receiver Output Short Circuit Current
3V
A
Input
Generator
R VO
VI
50 Ÿ
1.5V
0V
50 %
VI
B
0V
tPLH
tPHL
VOH
90%
CL=15 pF
50%
RE
VOD
10 %
tr
VOL
tf
Figure 14. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
Vcc
Vcc
Vcc
VI
50 %
DE
0V or Vcc
0V
A
D
R
B
1 kŸ
VO
tPZH(1)
tPHZ
S1
VO
CL=15 pF
90 %
50 %
tPZL(1)
VI
D at Vcc
S1 to GND
§ 0V
RE
Input
Generator
VOH
50 Ÿ
tPLZ
VO
50 %
VCC D at 0V
S1 to Vcc
10 %
VOL
Figure 15. Measurement of Receiver Enable/Disable Times With Driver Enabled
Vcc
Vcc
VI
50%
0V
A
V or 1.5V
R
1.5 V or 0V
B
VO
RE
1 NŸ
tPZH(2)
S1
CL=15 pF
VOH
50%
VO
§ 0V
A at 1.5 V
B at 0 V
S1 to GND
tPZL(2)
Input
Generator
VI
50 Ÿ
VCC
VO
50%
VOL
A at 0V
B at 1.5V
S1 to VCC
Figure 16. Measurement of Receiver Enable Times With Driver Disabled
10
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8 Detailed Description
8.1 Overview
The THVD1520 is a low-power, half-duplex RS-485 transceiver suitable for data transmission up to 10 Mbps.
8.2 Functional Block Diagrams
VCC
R
RE
A
DE
B
D
GND
8.3 Feature Description
Internal ESD protection circuits protect the transceiver against Electrostatic Discharges (ESD) according to IEC
61000-4-2 of up to ±8 kV (contact discharge), ±8 kV (air gap discharge) and against electrical fast transients
(EFT) according to IEC 61000-4-4 of up to ±4 kV.
8.4 Device Functional Modes
When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input
D. A logic high at D causes A to turn high and B to turn low. In this case, the differential output voltage defined
as VOD = VA – VB is positive. When D is low, the output states reverse, B turns high, A becomes low, and VOD is
negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin
has an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance) by
default. The D pin has an internal pull-up resistor to VCC, thus, when left open while the driver is enabled, output
A turns high and B turns low.
Table 1. Driver Function Table
INPUT
ENABLE
OUTPUTS
D
DE
A
H
H
H
L
Actively drive bus high
L
H
L
H
Actively drive bus low
X
L
Z
Z
Driver disabled
X
OPEN
Z
Z
Driver disabled by default
OPEN
H
H
L
Actively drive bus high by default
FUNCTION
B
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is positive and higher than the positive input threshold, VIT+, the receiver output, R, turns
high. When VID is negative and lower than the negative input threshold, VIT-, the receiver output, R, turns low. If
VID is between VIT+ and VIT- the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven
(idle bus).
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Table 2. Receiver Function Table
12
DIFFERENTIAL INPUT
ENABLE
OUTPUT
VID = VA – VB
RE
R
VIT+ < VID
L
H
Receive valid bus high
VIT- < VID < VIT+
L
?
Indeterminate bus state
FUNCTION
VID < VIT-
L
L
Receive valid bus low
X
H
Z
Receiver disabled
X
OPEN
Z
Receiver disabled by default
Open-circuit bus
L
H
Fail-safe high output
Short-circuit bus
L
H
Fail-safe high output
Idle (terminated) bus
L
H
Fail-safe high output
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The THVD1520 is a half-duplex RS-485 transceiver commonly used for asynchronous data transmissions. The
driver and receiver enable pins allow for the configuration of different operating modes.
9.2 Typical Application
An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, allows for higher data rates over longer
cable length.
R
R
RE
B
DE
D
R
A
R
A
RT
RT
D
A
R
B
A
D
R RE DE D
R
RE
B
DE
D
B
D
D
R RE DE D
Figure 17. Typical RS-485 Network With Half-Duplex Transceivers
9.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
9.2.1.1 Data Rate and Bus Length
There is an inverse relationship between data rate and cable length, which means the higher the data rate, the
shorter the cable length; and conversely, the lower the data rate, the longer the cable length. While most RS-485
systems use data rates between 10 kbps and 100 kbps, some applications require data rates up to 250 kbps at
distances of 4000 feet and longer. Longer distances are possible by allowing for small signal jitter of up to 5 or
10%.
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Typical Application (continued)
9.2.1.2 Stub Length
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, should be as short as possible. Stubs present a non-terminated piece of bus line which can introduce
reflections as the length of the stub increases. As a general guideline, the electrical length, or round-trip delay, of
a stub should be less than one-tenth of the rise time of the driver, thus giving a maximum physical stub length as
shown in Equation 1.
L(STUB) ≤ 0.1 × tr × v × c
where
•
•
•
tr is the 10/90 rise time of the driver
c is the speed of light (3 × 108 m/s)
v is the signal velocity of the cable or trace as a factor of c
(1)
9.2.1.3 Bus Loading
The RS-485 standard specifies that a compliant driver must be able to driver 32 unit loads (UL), where 1 unit
load represents a load impedance of approximately 12 kΩ. Because the THVD1520 consists of 1/8 UL
transceivers, connecting up to 256 receivers to the bus is possible.
9.2.1.4 Receiver Failsafe
The differential receivers of the THVD1520 are failsafe to invalid bus states caused by the following:
• Open bus conditions, such as a disconnected connector
• Shorted bus conditions, such as cable damage shorting the twisted-pair together
• Idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver will output a failsafe logic high state so that the output of the
receiver is not indeterminate.
Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input indeterminate range
does not include zero volts differential. In order to comply with the RS-422 and RS-485 standards, the receiver
output must output a high when the differential input VID is more positive than 200 mV, and must output a low
when VID is more negative than –200 mV. The receiver parameters which determine the failsafe performance are
VIT+, VIT–, and VHYS (the separation between VIT+ and VIT–). As shown in the table, differential signals more
negative than –200 mV will always cause a low receiver output, and differential signals more positive than 200
mV will always cause a high receiver output.
When the differential input signal is close to zero, it is still above the VIT+ threshold, and the receiver output will
be high. Only when the differential input is more than VHYS below VIT+ will the receiver output transition to a low
state. Therefore, the noise immunity of the receiver inputs during a bus fault conditions includes the receiver
hysteresis value, VHYS, as well as the value of VIT+.
14
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Typical Application (continued)
9.2.1.5 Transient Protection
The bus pins of the THVD1520 transceiver family include on-chip ESD protection against ±16-kV HBM and ±8kV IEC 61000-4-2 contact discharge. The International Electrotechnical Commission (IEC) ESD test is far more
severe than the HBM ESD test. The 50% higher charge capacitance, C(S), and 78% lower discharge resistance,
R(D), of the IEC model produce significantly higher discharge currents than the HBM model.
R(C)
R(D)
High-Voltage
Pulse
Generator
330 Ω
(1.5 kΩ)
Device
Under
Test
150 pF
(100 pF)
C(S)
Current (A)
50 M
(1 M)
40
35
30 10-kV IEC
25
20
15
10
5
0
0
50
100
10-kV HBM
150
200
250
300
Time (ns)
Figure 18. HBM and IEC ESD Models and Currents in Comparison (HBM Values in Parenthesis)
The on-chip implementation of IEC ESD protection significantly increases the robustness of equipment. Common
discharge events occur because of human contact with connectors and cables. Designers may choose to
implement protection against longer duration transients, typically referred to as surge transients.
EFTs are generally caused by relay-contact bounce or the interruption of inductive loads. Surge transients often
result from lightning strikes (direct strike or an indirect strike which induce voltages and currents), or the
switching of power systems, including load changes and short circuit switching. These transients are often
encountered in industrial environments, such as factory automation and power-grid systems.
Figure 19 compares the pulse-power of the EFT and surge transients with the power caused by an IEC ESD
transient. The left hand diagram shows the relative pulse-power for a 0.5-kV surge transient and 4-kV EFT
transient, both of which dwarf the 10-kV ESD transient visible in the lower-left corner. 500-V surge transients are
representative of events that may occur in factory environments in industrial and process automation.
22
20
18
16
14
12
10
8
6
4
2
0
Pulse Power (MW)
Pulse Power (kW)
The right hand diagram shows the pulse-power of a 6-kV surge transient, relative to the same 0.5-kV surge
transient. 6-kV surge transients are most likely to occur in power generation and power-grid systems.
0.5-kV Surge
4-kV EFT
10-kV ESD
0
5
10
15
20
25
30
35
40
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
6-kV Surge
0.5-kV Surge
0
5
10
15
20
25
30
35
40
Time (µs)
Time (µs)
Figure 19. Power Comparison of ESD, EFT, and Surge Transients
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Typical Application (continued)
In the event of surge transients, high-energy content is characterized by long pulse duration and slow decaying
pulse power. The electrical energy of a transient that is dumped into the internal protection cells of a transceiver
is converted into thermal energy, which heats and destroys the protection cells, thus destroying the transceiver.
Figure 20 shows the large differences in transient energies for single ESD, EFT, surge transients, and an EFT
pulse train that is commonly applied during compliance testing.
1000
100
Surge
10
1
Pulse Energy (J)
EFT Pulse Train
0.1
0.01
EFT
10-3
10-4
ESD
10-5
10-6
0.5
1
2
4
6
8 10
15
Peak Pulse Voltage (kV)
Figure 20. Comparison of Transient Energies
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Typical Application (continued)
9.2.2 Detailed Design Procedure
In order to protect bus nodes against high-energy transients, the implementation of external transient protection
devices is necessary. Figure 21 suggests a protection circuit against 1 kV surge (IEC 61000-4-5) transients.
Table 3 shows the associated bill of materials.
5V
100nF
100nF
10k
VCC
R1
R
RxD
MCU/
UART
DIR
RE
A
DE
B
TVS
D
TxD
R2
10k
GND
Figure 21. Transient Protection Against Surge Transients for Half-Duplex Devices
Table 3. Bill of Materials
DEVICE
FUNCTION
ORDER NUMBER
MANUFACTURER
XCVR
RS-485 transceiver
THVD1520
TI
10-Ω, pulse-proof thick-film resistor
CRCW0603010RJNEAHP
Vishay
Bidirectional 400-W transient suppressor
CDSOT23-SM712
Bourns
R1
R2
TVS
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9.2.3 Application Curves
R
output
Bus
outputs
D
input
Figure 22. Waveforms at 10 Mbps Operation, PRBS7 Data Pattern
R
output
Bus
outputs
D
input
Figure 23. Waveforms at 10 Mbps Operation, Clock Data Pattern
10 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, each supply should be decoupled with a 100
nF ceramic capacitor located as close to the supply pins as possible. This helps to reduce supply voltage ripple
present on the outputs of switched-mode power supplies and also helps to compensate for the resistance and
inductance of the PCB power planes.
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11 Layout
11.1 Layout Guidelines
Robust and reliable bus node design often requires the use of external transient protection devices in order to
protect against surge transients that may occur in industrial environments. Since these transients have a wide
frequency bandwidth (from approximately 3 MHz to 300 MHz), high-frequency layout techniques should be
applied during PCB design.
1. Place the protection circuitry close to the bus connector to prevent noise transients from propagating across
the board.
2. Use VCC and ground planes to provide low inductance. Note that high-frequency currents tend to follow the
path of least impedance and not the path of least resistance.
3. Design the protection components into the direction of the signal path. Do not force the transient currents to
divert from the signal path to reach the protection device.
4. Apply 100-nF to 220-nF decoupling capacitors as close as possible to the VCC pins of transceiver, UART
and/or controller ICs on the board.
5. Use at least two vias for VCC and ground connections of decoupling capacitors and protection devices to
minimize effective via inductance.
6. Use 1-kΩ to 10-kΩ pull-up and pull-down resistors for enable lines to limit noise currents in theses lines
during transient events.
7. Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified
maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into the
transceiver and prevent it from latching up.
8. While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient
blocking units (TBUs) that limit transient current to less than 1 mA.
11.2 Layout Example
5
Via to ground
Via to VCC
4
6 R
1
R
MCU
R
7
5
R
6 R
THVD1520
JMP
C
R
TVS
5
Figure 24. Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.2 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document..
12.4 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
THVD1520DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1520
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
