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THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
ZHCSGQ1C – SEPTEMBER 2017 – REVISED DECEMBER 2018
具有 ±18kV IEC ESD 保护功能的 THVD15xx 5V RS-485 收发器
1 特性
•
•
•
1
•
•
•
•
•
•
•
•
•
符合或超过 TIA/EIA-485A 标准要求
4.5V 至 5.5V 电源电压
集成总线 I/O 保护
– ±30kV HBM ESD
– ±18kV IEC 61000-4-2 ESD 接触放电
– ±25kV IEC 61000-4-2 ESD 空气间隙放电
– ±4kV IEC 61000-4-4 电气快速瞬变
扩展级运行共模：± 15V
低 EMI 500kbps 和 50Mbps 数据速率
扩展温度范围：-40°C 至 125°C
用于噪声抑制的大接收器滞后
低功耗
– 低待机电源电流：小于 1µA
– 运行期间的电流：< 1mA
适用于热插拔功能的无干扰加电/断电
开路、短路和空闲总线失效防护
1/8 单位负载选项（多达 256 个总线节点）
小尺寸 VSSOP 封装（可节省布板空间）或 SOIC
封装（可实现快插兼容性）
每个器件由 5V 单电源供电。该系列中的器件具有扩展
共模电压范围，因此这些器件适用于长电缆上的 多点
应用。
THVD15xx 系列器件采用小型 VSSOP 封装，适用于
空间受限的 应用。这些器件在自然通风环境下的额定
温度范围为 –40°C 至 125°C。
器件信息(1)
器件型号
封装
THVD1510
THVD1550
3.00mm × 3.00mm
SOIC (8)
4.90mm × 3.91mm
THVD1551
VSSOP (8)
3.00mm × 3.00mm
THVD1512
VSSOP (10)
3.00mm × 3.00mm
VSSOP (10)
3.00mm × 3.00mm
SOIC (14)
8.65mm × 3.91mm
THVD1552
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
THVD1510 和 THVD1550 简化原理图
R
RE
DE
2 应用
•
•
•
•
•
•
•
•
电机驱动器
工厂自动化与控制
电网基础设施
楼宇自动化
HVAC 系统
视频监控
过程分析
电信基础设施
D
THVD15xx 是一系列抗噪 RS-485/RS-422 收发器，专
用于在恶劣的工业环境中运行。这些器件的总线引脚可
耐受高级别的 IEC 电气快速瞬变 (EFT) 和 IEC 静电放
电 (ESD) 事件，从而无需使用其他系统级保护组件。
1
2
7
3
6
B
A
4
THVD1551 简化原理图
R
D
2
8
A
7
B
3
6
Z
5
Y
THVD1512 和 THVD1552 简化原理图
R
3 说明
封装尺寸（标称值）
VSSOP (8)
RE
DE
D
2 (1)
3 (2)
(9 ) 12
A
(8 ) 11
B
4 (3)
5 (4)
(7 ) 10
Z
(6) 9
Y
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSEV1
THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
ZHCSGQ1C – SEPTEMBER 2017 – REVISED DECEMBER 2018
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性 ..........................................................................
应用 ..........................................................................
说明 ..........................................................................
修订历史记录 ...........................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8
9
1
1
1
2
3
3
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings ............................................................ 6
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 7
Power Dissipation ..................................................... 7
Electrical Characteristics........................................... 8
Switching Characteristics .......................................... 9
Switching Characteristics .......................................... 9
Typical Characteristics ............................................ 10
Parameter Measurement Information ................ 11
Detailed Description ............................................ 14
9.1 Overview ................................................................. 14
9.2 Functional Block Diagrams ..................................... 14
9.3 Feature Description................................................. 14
9.4 Device Functional Modes........................................ 15
10 Application and Implementation........................ 18
10.1 Application Information...................................... 18
10.2 Typical Application ............................................... 18
11 Power Supply Recommendations ..................... 24
12 Layout................................................................... 25
12.1 Layout Guidelines ................................................. 25
12.2 Layout Example .................................................... 25
13 器件和文档支持 ..................................................... 26
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
器件支持................................................................
第三方产品免责声明..............................................
相关链接................................................................
接收文档更新通知 .................................................
社区资源................................................................
商标 .......................................................................
静电放电警告.........................................................
术语表 ...................................................................
26
26
26
26
26
26
26
26
14 机械、封装和可订购信息 ....................................... 27
4 修订历史记录
Changes from Revision B (July 2018) to Revision C
•
Changed the Description of pins 13 and 14 in the Pin Functions table for THVD1512, THVD1552 D package ................... 5
Changes from Revision A (January 2018) to Revision B
•
Page
Page
Added TSD to the Electrical Characteristics table ................................................................................................................... 8
Changes from Original (September 2017) to Revision A
Page
•
Changed the Machine model (MM) value From: ±400 To: ±200 in the ESD Ratings............................................................ 6
•
Changed the VOH MIN value From: 2.4 V To: 4 V in the Electrical Characteristics table ..................................................... 8
2
Copyright © 2017–2018, Texas Instruments Incorporated
THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
www.ti.com.cn
ZHCSGQ1C – SEPTEMBER 2017 – REVISED DECEMBER 2018
5 Device Comparison Table
PART NUMBER
DUPLEX
ENABLES
THVD1512
Full
DE, RE
THVD1510
Half
DE, RE
THVD1552
Full
DE, RE
THVD1551
Full
None
THVD1550
Half
DE, RE
SIGNALING RATE
NODES
up to 500 kbps
256
up to 50 Mbps
196
6 Pin Configuration and Functions
THVD1510, THVD1550 Devices
8-Pin D Package (SOIC)
Top View
THVD1510, THVD1550 Devices
8-Pin DGK Package (VSSOP)
Top View
R
1
8
VCC
/RE
2
7
B
DE
3
6
A
D
4
5
GND
Not to scale
R
1
8
VCC
/RE
2
7
B
DE
3
6
A
D
4
5
GND
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
D
DGK
A
6
6
Bus input/output
Bus I/O port, A (complementary to B)
B
7
7
Bus input/output
Bus I/O port, B (complementary to A)
D
4
4
Digital input
Driver data input
DE
3
3
Digital input
Driver enable, active high (2 MΩ internal pull-down)
GND
5
5
Ground
R
1
1
Digital output
VCC
8
8
Power
RE
2
2
Digital input
Copyright © 2017–2018, Texas Instruments Incorporated
Device ground
Receive data output
5-V supply
Receiver enable, active low (2 MΩ internal pull-up)
3
THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
ZHCSGQ1C – SEPTEMBER 2017 – REVISED DECEMBER 2018
www.ti.com.cn
THVD1551 Device
8-Pin DGK Package (VSSOP)
Top View
VCC
1
8
A
R
2
7
B
D
3
6
Z
GND
4
5
Y
Not to scale
Pin Functions
PIN
NAME
DGK
I/O
DESCRIPTION
A
8
Bus input
Bus input, A (complementary to B)
B
7
Bus input
Bus input, B (complementary to A)
D
3
Digital input
GND
4
Ground
R
2
Digital output
VCC
1
Power
Y
5
Bus output
Bus output, Y (complementary to Z)
Z
6
Bus output
Bus output, Z (complementary to Y)
4
Driver data input
Device ground
Receive data output
5-V supply
Copyright © 2017–2018, Texas Instruments Incorporated
THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
www.ti.com.cn
ZHCSGQ1C – SEPTEMBER 2017 – REVISED DECEMBER 2018
THVD1552 Device
14-Pin D Package (SOIC)
Top View
THVD1512, THVD1552 Devices
10-Pin DGS Package (VSSOP)
Top View
NC
1
14
VCC
R
2
13
VCC
/RE
3
12
A
DE
4
11
B
D
5
10
Z
GND
6
9
Y
GND
7
8
NC
R
1
10
VCC
RE
2
9
A
DE
3
8
B
D
4
7
Z
GND
5
6
Y
Not to scale
Not to scale
Pin Functions
PIN
NAME
D
DGS
A
12
9
B
11
D
5
DE
I/O
DESCRIPTION
Bus input
Bus input, A (complementary to B)
8
Bus input
Bus input, B (complementary to A)
4
Digital input
Driver data input
4
3
Digital input
Driver enable, active high (2 MΩ internal pull-down)
6, 7 (1)
5
Ground
1, 8
—
—
2
1
Digital output
—
10
Power
5-V supply.
13, 14
—
Power
5-V supply. These pins are not connected together internally, so power must
be applied to both.
Y
9
6
Bus output
Bus output, Y (Complementary to Z)
Z
10
7
Bus output
Bus output, Z (Complementary to Y)
RE
3
2
Digital input
Receiver enable, active low (2 MΩ internal pull-up)
GND
NC
R
VCC
(1)
Device ground
Internally not connected
Receive data output
These pins are internally connected
Copyright © 2017–2018, Texas Instruments Incorporated
5
THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
ZHCSGQ1C – SEPTEMBER 2017 – REVISED DECEMBER 2018
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Supply voltage
VCC
–0.5
7
V
Bus voltage
Range at any bus pin (A, B, Y, or Z) as
differential or common-mode with respect to
GND
–18
18
V
Input voltage
Range at any logic pin (D, DE, or RE)
–0.3
5.7
V
Receiver output current
IO
–24
24
mA
–65
150
°C
Storage temperature, Tstg
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
Electrostatic discharge
Contact discharge, per IEC 61000-4-2
Bus terminals and GND
±18,000
Air-gap discharge, per IEC 61000-4-2
Bus terminals and GND
±25,000
Bus terminals and GND
±30,000
All pins except Bus
terminals and GND
±8,000
Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001 (1)
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
Machine model (MM), per JEDEC JESD22-A115-A
V(EFT)
(1)
(2)
6
Electrical fast transient
Per IEC 61000-4-4
Bus terminals
UNIT
V
±1,500
±200
±4,000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2017–2018, Texas Instruments Incorporated
THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
www.ti.com.cn
ZHCSGQ1C – SEPTEMBER 2017 – REVISED DECEMBER 2018
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5.5
V
VI
Input voltage at any bus terminal (1)
-15
15
V
VIH
High-level input voltage (driver, driver enable, and receiver enable
inputs)
2
VCC
V
VIL
Low-level input voltage (driver, driver enable, and receiver enable
inputs)
0
0.8
V
VID
Differential input voltage
-15
15
V
IO
Output current, driver
-60
60
mA
IOR
Output current, receiver
-8
8
mA
RL
Differential load resistance
54
Ω
THVD1510, THVD1512
500
kbps
1/tUI
Signaling rate
50
Mbps
TA
Operating ambient temperature
-40
125
°C
TJ
Junction temperature
-40
150
°C
(1)
THVD1550, THVD1551, THVD1552
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
7.4 Thermal Information
THERMAL METRIC
(1)
THVD1510
THVD1550
THVD1552
THVD1510
THVD1550
THVD1551
THVD1512
THVD1552
D (SOIC)
D (SOIC)
DGK (VSSOP)
DGS (VSSOP)
UNIT
8 PINS
14 PINS
8 PINS
10 PINS
RθJA
Junction-to-ambient thermal resistance
112.4
88.0
151.7
151.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
62.7
45.4
62.8
59.3
°C/W
RθJB
Junction-to-board thermal resistance
62.0
44.1
81.3
81.6
°C/W
ψJT
Junction-to-top characterization parameter
15.4
11.3
7.8
6.5
°C/W
ψJB
Junction-to-board characterization parameter
61.3
43.7
79.8
79.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Dissipation
PARAMETER
PD
Driver and receiver enabled,
VCC = 5.5 V, TA = 125 °C,
50% duty cycle square wave at
signaling rate
Copyright © 2017–2018, Texas Instruments Incorporated
TEST CONDITIONS
VALUE
Unterminated
RL = 300 Ω, CL = 50 pF (driver)
THVD151x 500 kbps
210
THVD155x 50 Mbps
350
RS-422 load
RL = 100 Ω, CL = 50 pF (driver)
THVD151x 500 kbps
220
THVD155x 50 Mbps
330
RS-485 load
RL = 54 Ω, CL = 50 pF (driver)
THVD151x 500 kbps
250
THVD155x 50 Mbps
340
UNIT
mW
mW
mW
7
THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
ZHCSGQ1C – SEPTEMBER 2017 – REVISED DECEMBER 2018
www.ti.com.cn
7.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.5
2.7
V
2
3
V
1.5
2.7
V
Driver
RL = 60 Ω, -15 V ≤ Vtest ≤ 15 V, (See 图 11)
|VOD|
Driver differential output
voltage magnitude
RL = 100 Ω (See 图 12)
RL = 54 Ω (See 图 12)
Δ|VOD|
Change in differential output
voltage
VOC
Common-mode output
voltage
ΔVOC(SS)
Change in steady-state
common-mode output
voltage
IOS
Short-circuit output current
–200
1
RL = 54 Ω (See 图 12)
DE = VCC, -15 V ≤ VO ≤ 15V
200
VCC/2
3
mV
V
–200
200
mV
–250
250
mA
Receiver
VI = 12 V
THVD151x
II
Bus input current
DE = 0 V, VCC = 0 V or 5.5 V
VI = 15 V
VI = -7 V
-100
VI = -15 V
-215
VI = 12 V
THVD155x
VI = 15 V
75
125
95
156
-40
-85
115
160
150
200
μA
VI = -7 V
-130
-75
VI = -15 V
-280
-180
See (1)
–85
–20
mV
–200
–135
See (1)
mV
Receiver
VTH+
Positive-going input
threshold voltage
VTH-
Negative-going input
threshold voltage
VHYS
Input hysteresis
VTH+
Positive-going input
threshold voltage
VTH-
Negative-going input
threshold voltage
VHYS
Input hysteresis
VOH
Output high voltage
IOH = -8 mA
VOL
Output low voltage
IOL = 8 mA
IOZ
Output high-impedance
current
VO = 0 V or VCC, RE = VCC
-1
Input current (D, DE, RE)
4.5 V ≤ VCC ≤ 5.5 V, 0 V ≤ VIN ≤ VCC
–5
Over common-mode range of - 7 V to +12 V
50
–85
–20
mV
–220
–135
See (1)
mV
4
VCC - 0.3
See
Over common-mode range of ± 15 V
mV
(1)
50
0.2
mV
V
0.4
V
1
µA
0
5
µA
Logic
IIN
Supply
ICC
TSD
(1)
8
Driver and receiver enabled
RE = 0 V, DE = VCC,
No load
700
1000
µA
Driver enabled, receiver disabled
RE = VCC, DE = VCC,
No load
400
620
µA
Driver disabled, receiver enabled
RE = 0 V, DE = 0 V,
No load
400
630
µA
Driver and receiver disabled
RE = VCC, DE = 0 V,
D = open, No load
0.1
1
µA
Supply current (quiescent)
Thermal shutdown temperature
170
°C
Under any specific conditions, VTH+ is specified to be at least VHYS higher than VTH–.
Copyright © 2017–2018, Texas Instruments Incorporated
THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
www.ti.com.cn
ZHCSGQ1C – SEPTEMBER 2017 – REVISED DECEMBER 2018
7.7 Switching Characteristics
500-kbps devices (THVD1510, THVD1512) over recommended operating conditions
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
300
400
600
ns
350
500
ns
15
ns
110
200
ns
100
500
ns
2
4
µs
15
25
ns
50
60
ns
10
ns
30
40
ns
Driver
tr, tf
Differential output rise/fall time
tPHL, tPLH
Propagation delay
tSK(P)
Pulse skew, |tPHL – tPLH|
tPHZ, tPLZ
Disable time (THVD1510,
THVD1512)
tPZH, tPZL
Enable time (THVD1510,
THVD1512)
RL = 54 Ω, CL = 50 pF
See 图 13
See 图 14 and 图 15
RE = 0 V
RE = VCC
Receiver
tr, tf
Differential output rise/fall time
tPHL, tPLH
Propagation delay
tSK(P)
Pulse skew, |tPHL – tPLH|
tPHZ, tPLZ
Disable time (THVD1510,
THVD1512)
tPZH(1),
tPZL(1),
tPZH(2),
tPZL(2)
Enable time (THVD1510,
THVD1512)
See 图 16
CL = 15 pF
DE = VCC
See 图 17
60
100
ns
DE = 0 V
See 图 18
3
8
μs
TYP
MAX
7.8 Switching Characteristics
50-Mbps devices (THVD1550, THVD1551, THVD1552) over recommended operating conditions
PARAMETER
TEST CONDITIONS
MIN
UNIT
Driver
tr, tf
Differential output rise/fall time
tPHL, tPLH
Propagation delay
tSK(P)
Pulse skew, |tPHL – tPLH|
tPHZ, tPLZ
Disable time (THVD1550,
THVD1552)
tPZH, tPZL
Enable time (THVD1550,
THVD1552)
RL = 54 Ω, CL = 50 pF
RE = 0 V
See 图 13
1
2
6
ns
5
10
16
ns
3.5
ns
10
22
ns
10
22
ns
2
4
μs
3
6
ns
30
45
ns
2
ns
8
18
ns
See 图 14 and 图 15
RE = VCC
Receiver
tr, tf
Differential output rise/fall time
tPHL, tPLH
Propagation delay
tSK(P)
Pulse skew, |tPHL – tPLH|
tPHZ, tPLZ
Disable time (THVD1550,
THVD1552)
tPZH(1),
tPZL(1),
tPZH(2),
tPZL(2)
Enable time (THVD1550,
THVD1552)
1
CL = 15 pF
See 图 16
DE = VCC
See 图 17
55
90
ns
DE = 0 V
See 图 18
3
8
μs
版权 © 2017–2018, Texas Instruments Incorporated
9
THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
ZHCSGQ1C – SEPTEMBER 2017 – REVISED DECEMBER 2018
www.ti.com.cn
7.9 Typical Characteristics
VOL
VOH
4.5
VO - Driver Output Voltage (V)
VO - Driver Differential Output Voltage (V)
5
4
3.5
3
2.5
2
1.5
1
0.5
0
10
20
30 40 50 60 70 80
IO - Driver Output Current (mA)
VCC = 5 V
90
3
2.5
2
1.5
1
0.5
0
10
20
D001
DE = VCC
D=0V
30 40 50 60 70 80
IO - Driver Output Current (mA)
VCC = 5 V
图 1. Driver Output Voltage vs Driver Output Current
90
100 110
D002
DE = VCC
D=0V
图 2. Driver Differential Output Voltage vs Driver Output
460
V0 - Driver Rise and Fall Time (ns)
IO - Driver Output Current (mA)
3.5
100 110
60
50
40
30
20
10
0
0
0.5
1
1.5
2
2.5 3 3.5 4 4.5
VCC - Supply Voltage (V)
TA = 25°C
DE = VCC
5
5.5
440
430
420
410
400
390
-20
0
D003
RL = 54 Ω
20
40
60
Temperature (qC)
80
100
120
D004
D = VCC
图 4. THVD1510 Driver Rise or Fall Time vs Temperature
3
VO - Driver Rise and Fall Time (ns)
395
390
385
380
375
370
365
360
355
350
345
340
335
330
-40
450
380
-40
6
图 3. Driver Output Current vs Supply Voltage
VO - Driver Propagation Delay (ns)
4
0
0
-20
0
20
40
60
80
Temperature (qC)
100
120
140
D005
图 5. THVD1510 Driver Propagation Delay vs Temperature
10
4.5
2.5
2
1.5
1
0.5
0
-40
-20
0
20
40
60
Temperature (qC)
80
100
120
D006
图 6. THVD1550 Driver Rise or Fall Time vs Temperature
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THVD1550, THVD1551, THVD1552
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ZHCSGQ1C – SEPTEMBER 2017 – REVISED DECEMBER 2018
14
80
12
70
ICC - Supply Current (mA)
VO - Driver Propagation Delay (ns)
Typical Characteristics (接
接下页)
10
8
6
4
60
50
40
30
20
2
10
0
-40
-20
0
20
40
60
Temperature (qC)
80
100
0
50
120
100
150
D007
200 250 300 350
Signaling Rate (Kbps)
400
450
500
D008
RL = 54 Ω
图 7. THVD1550 Driver Propagation Delay vs Temperature
图 8. THVD1510 Supply Current vs Signal Rate
7
90
VIT- ( 7 V) VIT+ ( 7 V)
VIT- (0 V) VIT+ (0 V)
VIT- (12 V) VIT+ (12 V)
6
70
Receiver Output (V)
ICC - Supply Current (mA)
80
60
50
40
30
5
4
3
2
20
1
10
0
0
5
10
15
20
25
30
35
Signaling Rate (Mbps)
40
45
0
-170 -160 -150 -140 -130 -120 -110 -100 -90
50
-80
-70
-60
Differential Input Voltage (mV)
D009
-50
D010
RL = 54 Ω
图 10. Receiver Output vs Input
图 9. THVD1550 Supply Current vs Signal Rate
8 Parameter Measurement Information
375 Ÿ
Vcc
DE
A
0V or Vcc
D
VOD
Vtest
RL
B
375 Ÿ
图 11. Measurement of Driver Differential Output Voltage With Common-Mode Load
A
0V or Vcc
D
A
RL/2
VOD
B
RL/2
VA
B
CL
VB
VOC(PP)
VOC
ûVOC(SS)
VOC
图 12. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
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Parameter Measurement Information (接
接下页)
Vcc
Vcc
DE
A
D
Input
Generator
VI
50%
VI
VOD
50 Ÿ
0V
tPHL
tPLH
RL=
54 Ÿ
CL= 50 pF
VOD
~2 V
90%
50%
10%
B
tr
~ ±2V
tf
图 13. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
A
S1
D
Vcc
VO
50%
VI
B
DE
Input
Generator
VI
RL =
110 Ÿ
CL =
50 pF
50 Ÿ
0V
tPZH
90%
VOH
50%
VO
~
~ 0V
tPHZ
图 14. Measurement of Driver Enable and Disable Times With Active High Output and Pull-Down Load
Vcc
Vcc
RL= 110 Ÿ
A
S1
DE
Input
Generator
0V
tPZL
VO
B
D
50%
VI
tPLZ
§ Vcc
VO
CL=
50 pF
10%
50 %
VI
VOL
50 Ÿ
图 15. Measurement of Driver Enable and Disable Times With Active Low Output and Pull-up Load
3V
A
Input
Generator
R VO
VI
50 Ÿ
1.5V
0V
50 %
VI
B
0V
tPLH
tPHL
VOH
90%
CL=15 pF
50%
RE
VOD
10 %
tr
VOL
tf
图 16. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
Vcc
Vcc
Vcc
VI
50 %
DE
0V or Vcc
0V
A
D
R
B
VO
1 kŸ
tPZH(1)
tPHZ
S1
CL=15 pF
VO
90 %
50 %
tPZL(1)
VI
50 Ÿ
D at Vcc
S1 to GND
§ 0V
RE
Input
Generator
VOH
VO
tPLZ
50 %
VCC D at 0V
S1 to Vcc
10 %
VOL
图 17. Measurement of Receiver Enable/Disable Times With Driver Enabled
12
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ZHCSGQ1C – SEPTEMBER 2017 – REVISED DECEMBER 2018
Parameter Measurement Information (接
接下页)
Vcc
Vcc
VI
50%
0V
A
V or 1.5V
R
1.5 V or 0V
B
RE
VO
1 NŸ
tPZH(2)
S1
CL=15 pF
VOH
50%
VO
§ 0V
A at 1.5 V
B at 0 V
S1 to GND
tPZL(2)
Input
Generator
VI
50 Ÿ
VCC
VO
50%
VOL
A at 0V
B at 1.5V
S1 to VCC
图 18. Measurement of Receiver Enable Times With Driver Disabled
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9 Detailed Description
9.1 Overview
THVD1510 and THVD1550 are low-power, half-duplex RS-485 transceivers available in two speed grades
suitable for data transmission up to 500 kbps and 50 Mbps respectively.
THVD1551 is fully enabled with no external enabling pins. THVD1512 and THVD1552 have active-high driver
enables and active-low receiver enables. A standby current of less than 1 µA can be achieved by disabling both
driver and receiver.
9.2 Functional Block Diagrams
VCC
R
RE
A
DE
B
D
GND
图 19. THVD1510 and THVD1550
VCC
A
R
R
B
VCC
D
Z
D
Y
GND
图 20. THVD1551
VCC
A
R
R
B
RE
DE
D
Z
D
Y
GND
图 21. THVD1512 and THVD1552
9.3 Feature Description
Internal ESD protection circuits of the THVD15xx protect the transceivers against electrostatic discharges (ESD)
according to IEC 61000-4-2 of up to ±18 kV and against electrical fast transients (EFT) according to IEC 610004-4 of up to ±4 kV. With careful system design, one could achieve ±4 kV EFT Criterion A (no data loss when
transient noise is present).
14
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Feature Description (接
接下页)
The THVD15xx device family provides internal biasing of the receiver input thresholds in combination with large
input-threshold hysteresis. The receiver output remains logic high under a bus-idle or bus-short conditions
without the need for external failsafe biasing resistors. Device operation is specified over a wide ambient
temperature range from –40°C to 125°C.
9.4 Device Functional Modes
9.4.1 Device Functional Modes for THVD1510 and THVD1550
When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input
D. A logic high at D causes A to turn high and B to turn low. In this case the differential output voltage defined as
VOD = VA – VB is positive. When D is low, the output states reverse: B turns high, A becomes low, and VOD is
negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin
has an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance) by
default. The D pin has an internal pull-up resistor to VCC, thus, when left open while the driver is enabled, output
A turns high and B turns low.
表 1. Driver Function Table for THVD1510 and THVD1550
INPUT
ENABLE
D
DE
A
OUTPUTS
B
H
H
H
L
Actively drive bus high
Actively drive bus low
FUNCTION
L
H
L
H
X
L
Z
Z
Driver disabled
X
OPEN
Z
Z
Driver disabled by default
OPEN
H
H
L
Actively drive bus high by default
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is higher than the positive input threshold, VTH+, the receiver output, R, turns high.
When VID is lower than the negative input threshold, VTH-, the receiver output, R, turns low. If VID is between VTH+
and VTH- the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not
actively driven (idle bus).
表 2. Receiver Function Table for THVD1510 and THVD1550
DIFFERENTIAL INPUT
ENABLE
OUTPUT
VID = VA – VB
RE
R
VTH+ < VID
L
H
Receive valid bus high
VTH- < VID < VTH+
L
?
Indeterminate bus state
VID < VTH-
L
L
Receive valid bus low
X
H
Z
Receiver disabled
FUNCTION
X
OPEN
Z
Receiver disabled by default
Open-circuit bus
L
H
Fail-safe high output
Short-circuit bus
L
H
Fail-safe high output
Idle (terminated) bus
L
H
Fail-safe high output
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9.4.2 Device Functional Modes for THVD1551
For this device, the driver and receiver are fully enabled, thus the differential outputs Y and Z follow the logic
states at data input D at all times. A logic high at D causes Y to turn high and Z to turn low. In this case, the
differential output voltage defined as VOD = VY – VZ is positive. When D is low, the output states reverse: Z turns
high, Y becomes low, and VOD is negative. The D pin has an internal pull-up resistor to VCC, thus, when left
open while the driver is enabled, output Y turns high and Z turns low.
表 3. Driver Function Table for THVD1551
INPUT
OUTPUTS
FUNCTIONS
D
Y
Z
H
H
L
L
L
H
Actively drive bus low
OPEN
H
L
Actively drive bus high by default
Actively drive bus high
When the differential input voltage defined as VID = VA – VB is higher than the positive input threshold, VTH+, the
receiver output, R, turns high. When VID is less than the negative input threshold, VTH–, the receiver output, R,
turns low. If VID is between VTH+ and VTH– the output is indeterminate. Internal biasing of the receiver inputs
causes the output to go failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus
lines are shorted to one another (short-circuit), or the bus is not actively driven (idle bus).
表 4. Receiver Function Table for THVD1551
DIFFERENTIAL INPUT
OUTPUT
VID = VA – VB
R
VTH+ < VID
H
Receive valid bus high
VTH- < VID < VTH+
?
Indeterminate bus state
FUNCTION
VID < VTH-
L
Receive valid bus low
Open-circuit bus
H
Fail-safe high output
Short-circuit bus
H
Fail-safe high output
Idle (terminated) bus
H
Fail-safe high output
9.4.3 Device Functional Modes for THVD1512 and THVD1552
When the driver enable pin, DE, is logic high, the differential outputs Y and Z follow the logic states at data input
D. A logic high at D causes Y to turn high and Z to turn low. In this case the differential output voltage defined as
VOD = VY – VZ is positive. When D is low, the output states reverse: Z turns high, Y becomes low, and VOD is
negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin
has an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance) by
default. The D pin has an internal pull-up resistor to VCC, thus, when left open while the driver is enabled, output
Y turns high and Z turns low.
表 5. Driver Function Table for THVD1512 and THVD1552
16
INPUT
ENABLE
D
DE
Y
OUTPUTS
Z
H
H
H
L
Actively drive bus high
Actively drive bus low
FUNCTION
L
H
L
H
X
L
Z
Z
Driver disabled
X
OPEN
Z
Z
Driver disabled by default
OPEN
H
H
L
Actively drive bus high by default
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THVD1550, THVD1551, THVD1552
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ZHCSGQ1C – SEPTEMBER 2017 – REVISED DECEMBER 2018
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is higher than the positive input threshold, VTH+, the receiver output, R, turns high.
When VID is lower than the negative input threshold, VTH-, the receiver output, R, turns low. If VID is between VTH+
and VTH- the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not
actively driven (idle bus).
表 6. Receiver Function Table for THVD1512 and THVD1552
DIFFERENTIAL INPUT
ENABLE
OUTPUT
VID = VA – VB
RE
R
VTH+ < VID
L
H
Receive valid bus high
VTH- < VID < VTH+
L
?
Indeterminate bus state
Receive valid bus low
FUNCTION
VID < VTH-
L
L
X
H
Z
Receiver disabled
X
OPEN
Z
Receiver disabled by default
Open-circuit bus
L
H
Fail-safe high output
Short-circuit bus
L
H
Fail-safe high output
Idle (terminated) bus
L
H
Fail-safe high output
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10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The THVD15xx family consists of half-duplex and full-duplex RS-485 transceivers commonly used for
asynchronous data transmissions. For half-duplex devices, the driver and receiver enable pins allow for the
configuration of different operating modes. Full-duplex implementation requires two signal pairs (four wires), and
allows each node to transmit data on one pair while simultaneously receiving data on the other pair.
10.2 Typical Application
An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, generally allows for higher data rates
over longer cable length.
R
R
R
A
RE
D
RT
B
DE
R
A
RT
D
A
R
B
A
R
D
R RE DE D
RE
B
DE
D
B
D
D
R RE DE D
图 22. Typical RS-485 Network With Half-Duplex Transceivers
Y
R
D
Z
A
RT
RT
B
R
R
DE
RE
Master
RE
D
Slave
B
R
A
DE
Z
RT
RT
A
B
Z
Y
D
D
Y
R Slave
D
R RE DE D
图 23. Typical RS-485 Network With Full-Duplex Transceivers
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Typical Application (接
接下页)
10.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
10.2.1.1 Data Rate and Bus Length
There is an inverse relationship between data rate and cable length, which means the higher the data rate, the
shorter the cable length; and conversely, the lower the data rate, the longer the cable length. While most RS-485
systems use data rates between 10 kbps and 100 kbps, some applications require data rates up to 250 kbps at
distances of 4000 feet and longer. Longer distances are possible by allowing for small signal jitter of up to 5 or
10%.
10000
Cable Length (ft)
5%, 10%, and 20% Jitter
1000
Conservative
Characteristics
100
10
100
1k
10 k
100 k
1M
10 M
100 M
Data Rate (bps)
图 24. Cable Length vs Data Rate Characteristic
Even higher data rates are achievable (that is, 50 Mbps for the THVD1550, THVD1551 and THVD1552) in cases
where the interconnect is short enough (or has suitably low attenuation at signal frequencies) to not degrade the
data.
10.2.1.2 Stub Length
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, should be as short as possible. Stubs present a non-terminated piece of bus line which can introduce
reflections of varying phase as the length of the stub increases. As a general guideline, the electrical length, or
round-trip delay, of a stub should be less than one-tenth of the rise time of the driver, thus giving a maximum
physical stub length as shown in 公式 1.
L(STUB) ≤ 0.1 × tr × v × c
where
•
•
•
tr is the 10/90 rise time of the driver
c is the speed of light (3 × 108 m/s)
v is the signal velocity of the cable or trace as a factor of c
(1)
10.2.1.3 Bus Loading
The RS-485 standard specifies that a compliant driver must be able to drive 32 unit loads (UL), where 1 unit load
represents a load impedance of approximately 12 kΩ. Because the THVD15xx family consists of 1/8 UL
transceivers, connecting up to 256 receivers to the bus is possible.
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Typical Application (接
接下页)
10.2.1.4 Receiver Failsafe
The differential receivers of the THVD15xx family are failsafe to invalid bus states caused by the following:
• Open bus conditions, such as a disconnected connector
• Shorted bus conditions, such as cable damage shorting the twisted-pair together
• Idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver will output a failsafe logic high state so that the output of the
receiver is not indeterminate.
Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input indeterminate range
does not include zero volts differential. In order to comply with the RS-422 and RS-485 standards, the receiver
output must output a high when the differential input VID is more positive than 200 mV, and must output a low
when VID is more negative than –200 mV. The receiver parameters which determine the failsafe performance are
VTH+, VTH–, and VHYS (the separation between VTH+ and VTH–). As shown in the Electrical Characteristics table,
differential signals more negative than –200 mV will always cause a low receiver output, and differential signals
more positive than 200 mV will always cause a high receiver output.
When the differential input signal is close to zero, it is still above the VTH+ threshold, and the receiver output will
be high. Only when the differential input is more than VHYS below VTH+ will the receiver output transition to a low
state. Therefore, the noise immunity of the receiver inputs during a bus fault conditions includes the receiver
hysteresis value, Vhys, as well as the value of VTH+.
20
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Typical Application (接
接下页)
10.2.1.5 Transient Protection
The bus pins of the THVD15xx transceiver family include on-chip ESD protection against ±30-kV HBM and ±18kV IEC 61000-4-2 contact discharge. The International Electrotechnical Commission (IEC) ESD test is far more
severe than the HBM ESD test. The 50% higher charge capacitance, C(S), and 78% lower discharge resistance,
R(D), of the IEC model produce significantly higher discharge currents than the HBM model. As stated in the IEC
61000-4-2 standard, contact discharge is the preferred transient protection test method.
R(C)
R(D)
High-Voltage
Pulse
Generator
330 Ω
(1.5 kΩ)
Device
Under
Test
150 pF
(100 pF)
C(S)
Current (A)
50 M
(1 M)
40
35
30 10-kV IEC
25
20
15
10
5
0
0
50
100
10-kV HBM
150
200
250
300
Time (ns)
图 25. HBM and IEC ESD Models and Currents in Comparison (HBM Values in Parenthesis)
The on-chip implementation of IEC ESD protection significantly increases the robustness of equipment. Common
discharge events occur because of human contact with connectors and cables. Designers may choose to
implement protection against longer duration transients, typically referred to as surge transients.
EFTs are generally caused by relay-contact bounce or the interruption of inductive loads. Surge transients often
result from lightning strikes (direct strike or an indirect strike which induce voltages and currents), or the
switching of power systems, including load changes and short circuit switching. These transients are often
encountered in industrial environments, such as factory automation and power-grid systems.
图 26 compares the pulse power of the EFT and surge transients with the power caused by an IEC ESD
transient. The left-hand diagram shows the relative pulse-power for a 0.5-kV surge transient and 4-kV EFT
transient, both of which dwarf the 10-kV ESD transient visible in the lower-left corner. 500-V surge transients are
representative of events that may occur in factory environments in industrial and process automation.
22
20
18
16
14
12
10
8
6
4
2
0
Pulse Power (MW)
Pulse Power (kW)
The right-hand diagram shows the pulse-power of a 6-kV surge transient, relative to the same 0.5-kV surge
transient. 6-kV surge transients are most likely to occur in power generation and power-grid systems.
0.5-kV Surge
4-kV EFT
10-kV ESD
0
5
10
15
20
25
Time (µs)
30
35
40
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
6-kV Surge
0.5-kV Surge
0
5
10
15
20
25
30
35
40
Time (µs)
图 26. Power Comparison of ESD, EFT, and Surge Transients
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Typical Application (接
接下页)
In the case of surge transients, high-energy content is characterized by long pulse duration and slow decaying
pulse power. The electrical energy of a transient that is dumped into the internal protection cells of a transceiver
is converted into thermal energy, which heats and destroys the protection cells, thus destroying the transceiver.
图 27 shows the large differences in transient energies for single ESD, EFT, surge transients, and an EFT pulse
train that is commonly applied during compliance testing.
1000
100
Surge
10
1
Pulse Energy (J)
EFT Pulse Train
0.1
0.01
EFT
10-3
10-4
ESD
10-5
10-6
0.5
1
2
4
6
8 10
15
Peak Pulse Voltage (kV)
图 27. Comparison of Transient Energies
10.2.2 Detailed Design Procedure
图 28 and 图 29 suggest a protection circuit against 1 kV surge (IEC 61000-4-5) transients. 表 7 shows the
associated bill of materials.
5V
100nF
100nF
10k
VCC
R1
R
RxD
MCU/
UART
DIR
RE
A
DE
B
TVS
D
TxD
R2
10k
GND
图 28. Transient Protection Against Surge Transients for Half-Duplex Devices
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Typical Application (接
接下页)
5V
100nF
R1
10k
VCC
A
TVS
R
RxD
B
RE
DIR
R2
R1
MCU/
UART
DE
DIR
Z
TVS
D
TxD
Y
GND
10k
R2
图 29. Transient Protection Against Surge Transients for Full-Duplex Devices
表 7. Bill of Materials
DEVICE
FUNCTION
ORDER NUMBER
MANUFACTURER
XCVR
5-V, RS-485 transceiver
THVD15xx
TI
10-Ω, pulse-proof thick-film resistor
CRCW0603010RJNEAHP
Vishay
Bidirectional 400-W transient suppressor
CDSOT23-SM712
Bourns
R1
R2
TVS
版权 © 2017–2018, Texas Instruments Incorporated
23
THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
ZHCSGQ1C – SEPTEMBER 2017 – REVISED DECEMBER 2018
www.ti.com.cn
10.2.3 Application Curves
500 kbps
图 30. THVD1510 Waveforms with 60-Ω Termination
50 Mbps
图 31. THVD1550 Waveforms with 60-Ω Termination
11 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, each supply should be decoupled with a 100
nF ceramic capacitor located as close to the supply pins as possible. This helps to reduce supply voltage ripple
present on the outputs of switched-mode power supplies and also helps to compensate for the resistance and
inductance of the PCB power planes.
24
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THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
www.ti.com.cn
ZHCSGQ1C – SEPTEMBER 2017 – REVISED DECEMBER 2018
12 Layout
12.1 Layout Guidelines
Robust and reliable bus node design often requires the use of external transient protection devices in order to
protect against surge transients that may occur in industrial environments. Since these transients have a wide
frequency bandwidth (from approximately 3 MHz to 300 MHz), high-frequency layout techniques should be
applied during PCB design.
1. Place the protection circuitry close to the bus connector to prevent noise transients from propagating across
the board.
2. Use VCC and ground planes to provide low inductance. Note that high-frequency currents tend to follow the
path of least impedance and not the path of least resistance.
3. Design the protection components into the direction of the signal path. Do not force the transient currents to
divert from the signal path to reach the protection device.
4. Apply 100-nF to 220-nF decoupling capacitors as close as possible to the VCC pins of transceiver, UART
and/or controller ICs on the board.
5. Use at least two vias for VCC and ground connections of decoupling capacitors and protection devices to
minimize effective via inductance.
6. Use 1-kΩ to 10-kΩ pullup and pulldown resistors for enable lines to limit noise currents in these lines during
transient events.
7. Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified
maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into the
transceiver and prevent it from latching up.
8. While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient
blocking units (TBUs) that limit transient current to less than 1 mA.
12.2 Layout Example
5
Via to ground
C
R
Via to VCC
R
1
JMP
6
4
R
MCU
5
6
R
THVD15x0
TVS
5
图 32. Half-Duplex Layout Example
版权 © 2017–2018, Texas Instruments Incorporated
25
THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
ZHCSGQ1C – SEPTEMBER 2017 – REVISED DECEMBER 2018
www.ti.com.cn
13 器件和文档支持
13.1 器件支持
13.2 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
13.3 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。
表 8. 相关链接
器件
产品文件夹
立即订购
技术文档
工具与软件
支持和社区
THVD1510
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
THVD1512
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
THVD1550
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
THVD1551
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
THVD1552
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
13.4 接收文档更新通知
要接收文档更新通知，请转至 TI.com.cn 上您的器件的产品文件夹。请在右上角单击通知我 按钮进行注册，即可收
到产品信息更改每周摘要（如有）。有关更改的详细信息，请查看任意已修订文档的修订历史记录。
13.5 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
13.6 商标
E2E is a trademark of Texas Instruments.
13.7 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
13.8 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
26
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THVD1510, THVD1512
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ZHCSGQ1C – SEPTEMBER 2017 – REVISED DECEMBER 2018
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查看左侧的导航栏。
版权 © 2017–2018, Texas Instruments Incorporated
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PACKAGE OUTLINE
D0008B
SOIC - 1.75 mm max height
SCALE 2.800
SOIC
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4
5
B
.150-.157
[3.81-3.98]
NOTE 4
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A
B
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
.004-.010
[ 0.11 -0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
.041
[1.04]
TYPICAL
4221445/B 04/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15], per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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THVD1510, THVD1512
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ZHCSGQ1C – SEPTEMBER 2017 – REVISED DECEMBER 2018
EXAMPLE BOARD LAYOUT
D0008B
SOIC - 1.75 mm max height
SOIC
8X (.061 )
[1.55]
SEE
DETAILS
SYMM
8X (.055)
[1.4]
SEE
DETAILS
SYMM
1
1
8
8X (.024)
[0.6]
8
SYMM
8X (.024)
[0.6]
5
4
6X (.050 )
[1.27]
SYMM
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
(.217)
[5.5]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
.0028 MAX
[0.07]
ALL AROUND
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221445/B 04/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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版权 © 2017–2018, Texas Instruments Incorporated
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ZHCSGQ1C – SEPTEMBER 2017 – REVISED DECEMBER 2018
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EXAMPLE STENCIL DESIGN
D0008B
SOIC - 1.75 mm max height
SOIC
8X (.061 )
[1.55]
8X (.055)
[1.4]
SYMM
SYMM
1
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
8
SYMM
8X (.024)
[0.6]
5
4
6X (.050 )
[1.27]
SYMM
5
4
(.217)
[5.5]
(.213)
[5.4]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:6X
4221445/B 04/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
30
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THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
www.ti.com.cn
版权 © 2017–2018, Texas Instruments Incorporated
ZHCSGQ1C – SEPTEMBER 2017 – REVISED DECEMBER 2018
31
THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
ZHCSGQ1C – SEPTEMBER 2017 – REVISED DECEMBER 2018
32
www.ti.com.cn
版权 © 2017–2018, Texas Instruments Incorporated
THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
www.ti.com.cn
版权 © 2017–2018, Texas Instruments Incorporated
ZHCSGQ1C – SEPTEMBER 2017 – REVISED DECEMBER 2018
33
THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
ZHCSGQ1C – SEPTEMBER 2017 – REVISED DECEMBER 2018
www.ti.com.cn
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
SCALE 3.200
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
10X
B
3.1
2.9
NOTE 4
SEE DETAIL A
0.27
0.17
0.1
C A
1.1 MAX
B
0.23
TYP
0.13
0.25
GAGE PLANE
0 -8
0.15
0.05
0.7
0.4
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
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版权 © 2017–2018, Texas Instruments Incorporated
THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
www.ti.com.cn
ZHCSGQ1C – SEPTEMBER 2017 – REVISED DECEMBER 2018
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
(R0.05)
TYP
SYMM
10X (0.3)
1
10
SYMM
6
5
8X (0.5)
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
版权 © 2017–2018, Texas Instruments Incorporated
35
THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
ZHCSGQ1C – SEPTEMBER 2017 – REVISED DECEMBER 2018
www.ti.com.cn
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
10X (0.3)
SYMM
(R0.05) TYP
1
10
SYMM
8X (0.5)
6
5
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
36
版权 © 2017–2018, Texas Instruments Incorporated
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
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束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
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Copyright © 2018 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
THVD1510D
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
VD1510
THVD1510DGK
ACTIVE
VSSOP
DGK
8
80
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1510
THVD1510DGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1510
THVD1510DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
VD1510
THVD1512DGS
ACTIVE
VSSOP
DGS
10
80
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1512
THVD1512DGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1512
THVD1550D
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
VD1550
THVD1550DGK
ACTIVE
VSSOP
DGK
8
80
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1550
THVD1550DGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1550
THVD1550DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
VD1550
THVD1551DGK
ACTIVE
VSSOP
DGK
8
80
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1551
THVD1551DGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1551
THVD1552D
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1552
THVD1552DGS
ACTIVE
VSSOP
DGS
10
80
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1552
THVD1552DGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1552
THVD1552DR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1552
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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