TIBPAL16L8-10C, TIBPAL16R4-10C, TIBPAL16R6-10C, TIBPAL16R8-10C
TIBPAL16L8-12M, TIBPAL16R4-12M, TIBPAL16R6-12M, TIBPAL16R8-12M
HIGH-PERFORMANCE IMPACT-X™ PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
TIBPAL16L8’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J PACKAGE
(TOP VIEW)
I
I
I
I
I
I
I
I
I
GND
Functionally Equivalent, but Faster than,
Existing 20-Pin PLDs
•
Preload Capability on Output Registers
Simplifies Testing
•
Power-Up Clear on Registered Devices (All
Register Outputs are Set Low, but Voltage
Levels at the Output Pins Go High)
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
•
Security Fuse Prevents Duplication
DEVICE
I
INPUTS
3-STATE
O OUTPUTS
REGISTERED
Q OUTPUTS
PAL16L8
10
2
0
6
PAL16R4
8
0
4 (3-state buffers)
4
PAL16R6
8
0
6 (3-state buffers)
2
PAL16R8
8
0
8 (3-state buffers)
0
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
TIBPAL16L8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
I
I
I
I
I
Dependable Texas Instruments Quality and
Reliability
I/O
PORT
S
1
I
I
I
VCC
O
•
High-Performance Operation:
fmax (w/o feedback)
TIBPAL16R’-10C Series . . . 62.5 MHz Min
TIBPAL16R’-12M Series . . . 56 MHz Min
fmax (with feedback)
TIBPAL16R’-10C Series . . . 55.5 MHz Min
TIBPAL16R’-12M Series . . . 48 MHz Min
Propagation Delay
TIBPAL16L’-10C Series . . . 10 ns Max
TIBPAL16L’-12M Series . . . 12 ns Max
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
I/O
I/O
I/O
I/O
I/O
I
GND
I
O
I/O
•
Pin assignments in operating mode
description
These programmable array logic devices feature high speed and functional equivalency when compared with
currently available devices. These IMPACT-X™ circuits combine the latest Advanced Low-Power Schottky
technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes for
conventional TTL logic. Their easy programmability allows for quick design of custom functions and typically
results in a more compact circuit board. In addition, chip carriers are available for futher reduction in board
space.
All of the register outputs are set to a low level during power up. Extra circuitry has been provided to allow loading
of each register asynchronously to either a high or low state. This feature simplifies testing because the registers
can be set to an initial state prior to executing the test sequence.
The TIBPAL16’ C series is characterized from 0°C to 75°C. The TIBPAL16’ M series is characterized for
operation over the full military temperature range of −55°C to 125°C.
IMPACT-X is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Advanced Micro Devices Inc.
Copyright © 2010, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TIBPAL16R4-10C, TIBPAL16R6-10C, TIBPAL16R8-10C
TIBPAL16R4-12M, TIBPAL16R6-12M, TIBPAL16R8-12M
HIGH-PERFORMANCE IMPACT-X™ PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
TIBPAL16R4’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
TIBPAL16R4’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J PACKAGE
(TOP VIEW)
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
I/O
I/O
Q
Q
Q
Q
I/O
I/O
OE
I
I
I
I
I
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
TIBPAL16R6’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
TIBPAL16R6’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J PACKAGE
(TOP VIEW)
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
I/O
Q
Q
Q
Q
Q
Q
I/O
OE
I
I
I
I
I
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
I
GND
1
I
I
CLK
VCC
I/O
(TOP VIEW)
CLK
I
I
I
I
I
I
I
I
GND
TIBPAL16R8’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J PACKAGE
(TOP VIEW)
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
I
I
CLK
VCC
Q
20
2
VCC
Q
Q
Q
Q
Q
Q
Q
Q
OE
I
I
I
I
I
Pin assignments in operating mode
2
POST OFFICE BOX 655303
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
I
GND
1
Q
Q
Q
Q
Q
TIBPAL16R8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
CLK
I
I
I
I
I
I
I
I
GND
I/O
Q
Q
Q
Q
OE
I/O
I/O
19
OE
I/O
Q
20
2
• DALLAS, TEXAS 75265
OE
Q
Q
1
I
GND
CLK
I
I
I
I
I
I
I
I
GND
I
I
CLK
VCC
I/O
(TOP VIEW)
Q
Q
Q
Q
Q
TIBPAL16L8-10C, TIBPAL16R4-10C
TIBPAL16L8-12M, TIBPAL16R4-12M
HIGH-PERFORMANCE IMPACT-X™ PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
functional block diagrams (positive logic)
TIBPAL16L8’
&
32 X 64
I
16 x
10
6
16
16
EN ≥ 1
7
O
7
O
7
I/O
7
I/O
7
I/O
7
I/O
7
I/O
7
I/O
6
TIBPAL16R4’
OE
CLK
EN 2
C1
&
32 X 64
I
16 x
8
I=0 2
≥1
8
Q
1D
8
Q
8
Q
8
Q
16
4
4
16
EN ≥ 1
7
I/O
7
I/O
7
I/O
7
I/O
4
4
denotes fused inputs
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TIBPAL16R6-10C, TIBPAL16R8-10C
TIBPAL16R6-12M, TIBPAL16R8-12M
HIGH-PERFORMANCE IMPACT-X™ PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
functional block diagrams (positive logic)
TIBPAL16R6’
OE
CLK
EN 2
C1
&
32 X 64
I
16 x
8
≥1
8
I=0 2
Q
1D
8
Q
8
Q
8
Q
8
Q
8
Q
16
6
2
16
EN ≥ 1
7
I/O
I/O
7
2
6
TIBPAL16R8’
OE
CLK
EN 2
C1
&
32 X 64
I
16 x
8
8
8
≥1
I=0 2
8
Q
8
Q
8
Q
8
Q
8
Q
8
Q
8
Q
16
16
8
denotes fused inputs
4
Q
1D
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TIBPAL16L8-10C
TIBPAL16L8-12M
HIGH-PERFORMANCE IMPACT-X™ PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
logic diagram (positive logic)
I
1
First
Fuse
Numbers
I
I
I
I
I
I
I
I
2
3
4
5
6
7
8
9
Increment
0
4
8
12
16
20
24
28
0
32
64
96
128
160
192
224
31
19
256
288
320
352
384
416
448
480
18
512
544
576
608
640
672
704
736
17
768
800
832
864
896
928
960
992
16
1024
1056
1088
1120
1152
1184
1216
1248
15
1280
1312
1344
1376
1408
1440
1472
1504
14
1536
1568
1600
1632
1664
1696
1728
1760
13
1792
1824
1856
1888
1920
1952
1984
2016
12
11
O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
Fuse number = First fuse number + Increment
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
TIBPAL16R4-10C
TIBPAL16R4-12M
HIGH-PERFORMANCE IMPACT-X™ PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
logic diagram (positive logic)
CLK
1
First
Fuse
Numbers
I
I
I
I
I
I
I
I
2
3
4
5
6
7
8
9
Increment
0
4
8
12
16
20
24
31
19
256
288
320
352
384
416
448
480
18
512
544
576
608
640
672
704
736
I=0
1D
768
800
832
864
896
928
960
992
I=0
1D
1024
1056
1088
1120
1152
1184
1216
1248
I=0
1D
1280
1312
1344
1376
1408
1440
1472
1504
I=0
1D
17
I/O
I/O
Q
C1
16
Q
C1
15
Q
C1
14
Q
C1
1536
1568
1600
1632
1664
1696
1728
1760
13
1792
1824
1856
1888
1920
1952
1984
2016
12
11
Fuse number = First fuse number + Increment
6
28
0
32
64
96
128
160
192
224
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
I/O
I/O
OE
TIBPAL16R6-10C
TIBPAL16R6-12M
HIGH-PERFORMANCE IMPACT-X™ PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
logic diagram (positive logic)
CLK
1
First
Fuse
Numbers
I
I
I
I
I
I
I
I
2
3
4
5
6
7
8
9
Increment
0
4
8
12
16
20
24
28
31
0
32
64
96
128
160
192
224
19
256
288
320
352
384
416
448
480
I=0
1D
512
544
576
608
640
672
704
736
I=0
1D
768
800
832
864
896
928
960
992
I=0
1D
1024
1056
1088
1120
1152
1184
1216
1248
I=0
1D
1280
1312
1344
1376
1408
1440
1472
1504
I=0
1D
1536
1568
1600
1632
1664
1696
1728
1760
I=0
1D
18
I/O
Q
C1
17
Q
C1
16
Q
C1
15
Q
C1
14
Q
C1
13
Q
C1
1792
1824
1856
1888
1920
1952
1984
2016
12
11
Fuse number = First fuse number + Increment
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
I/O
OE
7
TIBPAL16R8-10C
TIBPAL16R8-12M
HIGH-PERFORMANCE IMPACT-X™ PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
logic diagram (positive logic)
CLK
1
First
Fuse
Numbers
I
I
I
I
I
I
I
I
2
3
4
5
6
7
8
9
Increment
0
4
8
12
16
20
24
31
I=0
1D
256
288
320
352
384
416
448
480
I=0
1D
512
544
576
608
640
672
704
736
I=0
1D
768
800
832
864
896
928
960
992
I=0
1D
1024
1056
1088
1120
1152
1184
1216
1248
I=0
1D
1280
1312
1344
1376
1408
1440
1472
1504
I=0
1D
1536
1568
1600
1632
1664
1696
1728
1760
I=0
1D
1792
1824
1856
1888
1920
1952
1984
2016
I=0
1D
19
Q
C1
18
Q
C1
17
Q
C1
16
Q
C1
15
Q
C1
14
Q
C1
13
Q
C1
12
Q
C1
11
Fuse number = First fuse number + Increment
8
28
0
32
64
96
128
160
192
224
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
OE
TIBPAL16L8-10C, TIBPAL16R4-10C, TIBPAL16R6-10C, TIBPAL16R8-10C
HIGH-PERFORMANCE IMPACT-X™ PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
VCC
Supply voltage
VIH
High-level input voltage (see Note 2)
VIL
Low-level input voltage (see Note 2)
IOH
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
5.5
V
2
0.8
V
High-level output current
−3.2
mA
IOL
Low-level output current
24
mA
fclock
Clock frequency
62.5
MHz
0
High
8
Low
8
tw
Pulse duration, clock (see Note 2)
tsu
Setup time, input or feedback before clock↑
th
Hold time, input or feedback after clock↑
0
TA
Operating free-air temperature
0
ns
10
ns
ns
25
75
°C
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.
electrical characteristics over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
−0.8
−1.5
V
VIK
VCC = 4.75 V,
II = − 18 mA
VOH
VCC = 4.75 V,
IOH = − 3.2 mA
VOL
VCC = 4.75 V,
IOL = 24 mA
0.5
V
IOZH‡
VCC = 5.25 V,
VO = 2.4 V
100
μA
IOZL‡
VCC = 5.25 V,
VO = 0.4 V
−100
μA
II
VCC = 5.25 V,
VI = 5.5 V
0.2
mA
IIH‡
VCC = 5.25 V,
VI = 2.4 V
25
μA
‡
VCC = 5.25 V,
VI = 0.4 V
−0.08
−0.25
mA
IOS§
VCC = 5.25 V,
VO = 0
−70
−130
mA
ICC
VCC = 5.25 V,
VI = 0,
140
180
mA
Ci
f = 1 MHz,
VI = 2 V
5
pF
Co
f = 1 MHz,
VO = 2 V
6
pF
Ci/o
f = 1 MHz,
VI/O = 2 V
7.5
pF
Cclk
f = 1 MHz,
VCLK = 2 V
6
pF
IIL
2.4
3.2
0.3
−30
Outputs open
V
†
All typical values are at VCC = 5 V, TA = 25°C.
I/O leakage is the worst case of IOZL and IIL or IOZH and IIH respectively.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
‡
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
TIBPAL16L8-10C, TIBPAL16R4-10C, TIBPAL16R6-10C, TIBPAL16R8-10C
HIGH-PERFORMANCE IMPACT-X™ PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
FROM
(INPUT)
fmax
TO
(OUTPUT)
MIN
TYP†
With feedback
55.5
80
Without feedback
62.5
85
TEST CONDITION
tpd
I, I/O
O, I/O
R1 = 200 Ω,
3
7
tpd
CLK↑
Q
R2 = 390 Ω,
2
ten
OE↓
Q
See Figure 3
1
tdis
OE↑
Q
ten
I, I/O
tdis
I, I/O
UNIT
MHz
10
ns
5
8
ns
4
10
ns
1
4
10
ns
O, I/O
3
8
10
ns
O, I/O
3
8
10
ns
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
1
,
f max(with feedback) +
1
t su ) t
(CLK to Q) f max(without feedback) + t high ) t low
pd
w
w
10
MAX
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TIBPAL16L8-12M, TIBPAL16R4-12M, TIBPAL16R6-12M, TIBPAL16R8-12M
HIGH-PERFORMANCE IMPACT-X™ PAL® CIRCUITS
SRPS017D − D3023, MAY 1987 − REVISED DECEMBER 2010
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
UNIT
V
5.5
V
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
0.8
V
IOH
High-level output current
−2
mA
Low-level output current
12
mA
56
MHz
IOL
fclock
†
2
Clock frequency
0
tw
Pulse duration, clock (see Note 2)
tsu†
Setup time, input or feedback before clock↑
th
†
TA
High
9
Low
9
ns
11
Hold time, input or feedback after clock↑
ns
0
Operating free-air temperature
−55
ns
25
125
°C
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.
electrical characteristics over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
VIK
VCC = 4.5 V,
II = − 18 mA
VOH
VCC = 4.5 V,
IOH = − 2 mA
VOL
VCC = 4.5 V,
IOL = 12 mA
IOZH‡
VCC = 5.5 V,
IOZL‡
II
MIN
2.4
TYP†
MAX
UNIT
−0.8
−1.5
V
3.2
0.3
V
0.5
V
VO = 2.4 V
100
μA
VCC = 5.5 V,
VO = 0.4 V
−100
μA
VCC = 5.5 V,
VI = 5.5 V
0.2
mA
IIH‡
VCC = 5.5 V,
VI = 2.4 V
IIL‡
VCC = 5.5 V,
VI = 0.4 V
IOS§
VCC = 5.5 V,
VO = 0.5 V
ICC
VCC = 5.5 V,
VI = GND,
Ci
f = 1 MHz,
VI = 2 V
5
pF
Co
f = 1 MHz,
VO = 2 V
6
pF
Ci/o
f = 1 MHz,
VI/O = 2 V
7.5
pF
Cclk
f = 1 MHz,
VCLK = 2 V
6
pF
−30
Outputs open
25
μA
−0.08
−0.25
mA
−70
−250
mA
140
220
mA
†
All typical values are at VCC = 5 V, TA = 25°C.
I/O leakage is the worst case of IOZL and IIL or IOZH and IIH respectively.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. V is set at 0.5 V to
O
avoid test problems caused by test equipment ground degradation.
‡
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
TIBPAL16L8-12M, TIBPAL16R4-12M, TIBPAL16R6-12M, TIBPAL16R8-12M
HIGH-PERFORMANCE IMPACT-X™ PAL® CIRCUITS
SRPS017D − D3023, MAY 1987 − REVISED DECEMBER 2010
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
FROM
(INPUT)
fmax
TO
(OUTPUT)
MIN
TYP†
With feedback
48
80
Without feedback
56
85
TEST CONDITION
UNIT
MHz
tpd
I, I/O
O, I/O
R1 = 390 Ω,
3
7
12
ns
tpd
CLK↑
Q
R2 = 750 Ω,
2
5
10
ns
ten
OE↓
Q
See Figure 3
1
4
10
ns
tdis
OE↑
Q
1
4
10
ns
ten
I, I/O
O, I/O
3
8
14
ns
tdis
I, I/O
O, I/O
2
8
12
ns
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
1
,
f max(with feedback) +
1
t su ) t
(CLK to Q) f max(without feedback) + t high ) t low
pd
w
w
12
MAX
POST OFFICE BOX 655303
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TIBPAL16L8-10C, TIBPAL16R4-10C, TIBPAL16R6-10C, TIBPAL16R8-10C
TIBPAL16L8-12M, TIBPAL16R4-12M, TIBPAL16R6-12M, TIBPAL16R8-12M
HIGH-PERFORMANCE IMPACT-X™ PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
preload procedure for registered outputs (see Figure 1 and Note 3)
The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below.
Step 1.
Step 2.
Step 3.
Step 4.
With VCC at 5 volts and Pin 1 at VIL, raise Pin 11 to VIHH.
Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Pulse Pin 1, clocking in preload data.
Remove output voltage, then lower Pin 11 to VIL. Preload can be verified by observing the
voltage level at the output pin.
VIHH
Pin 11
td
tsu
tw
VIL
td
VIH
Pin 1
VIL
VIH
Registered I/O
Input
VOH
Output
VIL
VOL
Figure 1. Preload Waveforms
NOTE 3: td = tsu = th = 100 ns to 1000 ns VIHH = 10.25 V to 10.75 v
POST OFFICE BOX 655303
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13
TIBPAL16L8-10C, TIBPAL16R4-10C, TIBPAL16R6-10C, TIBPAL16R8-10C
TIBPAL16L8-12M, TIBPAL16R4-12M, TIBPAL16R6-12M, TIBPAL16R8-12M
HIGH-PERFORMANCE IMPACT-X™ PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER
power-up reset (see Figure 2)
Following power up, all registers are reset to zero. This feature provides extra flexibility to the system designer
and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is
important that the rise of VCC be monotonic. Following power-up reset, a low-to-high clock transition must not
occur until all applicable input and feedback setup times are met.
VCC
5V
4V
tpd†
(600 ns TYP, 1000 ns MAX)
VOH
Active Low
Registered Output
1.5 V
VOL
tsu‡
CLK
1.5 V
1.5 V
tw
†
‡
This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
This is the setup time for input or feedback.
Figure 2. Power-Up Reset Waveforms
14
POST OFFICE BOX 655303
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VIH
VIL
TIBPAL16L8-10C, TIBPAL16R4-10C, TIBPAL16R6-10C, TIBPAL16R8-10C
TIBPAL16L8-12M, TIBPAL16R4-12M, TIBPAL16R6-12M, TIBPAL16R8-12M
HIGH-PERFORMANCE IMPACT-X™ PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
PARAMETER MEASUREMENT INFORMATION
5V
S1
R1
From Output
Under Test
Test
Point
CL
(see Note A)
R2
LOAD CIRCUIT FOR
3-STATE OUTPUTS
1.5 V
1.5 V
(0.3 V) [0]
Data
Input
(3.5 V) [3 V]
1.5 V
1.5 V
(0.3 V) [0]
(3.5 V) [3 V]
VOH
1.5 V
VOL
tpd
tpd
1.5 V
VOH
1.5 V
VOL
(3.5 V) [3 V]
1.5 V
Waveform 1
S1 Closed
(see Note B)
tdis
1.5 V
tdis
ten
Waveform 2
S1 Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V
(0.3 V) [0]
ten
tpd
1.5 V
1.5 V
(0.3 V) [0]
Output
Control
(low-level
enabling)
(0.3 V) [0]
In-Phase
Output
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.5 V
tpd
(0.3 V) [0]
(3.5 V) [3 V]
Low-Level
Pulse
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Input
1.5 V
tw
th
tsu
Out-of-Phase
Output
(see Note D)
(3.5 V) [3 V]
High-Level
Pulse
(3.5 V) [3 V]
Timing
Input
≈ 3.3 V
VOL +0.5 V
VOL
VOH
1.5 V
VOH −0.5 V
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: For C suffix, use the voltage levels indicated in parentheses ( ), PRR ≤ 1 MHz,
tr = tf = 2 ns, duty cycle = 50%; For M suffix, use the voltage levels indicated in brackets [ ], PRR ≤ 10 MHz, tr and tf ≤ 2 ns, duty
cycle = 50%
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
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15
TIBPAL16R4-10C, TIBPAL16R6-10C, TIBPAL16R8-10C
HIGH-PERFORMANCE IMPACT-X™ PAL® CIRCUITS
SRPS017 − D3023, MAY 1987 − REVISED DECEMBER 2010
metastable characteristics of TIBPAL16R4-10C, TIBPAL16R6-10C, and TIBPAL16R8-10C
At some point a system designer is faced with the problem of synchronizing two digital signals operating at two
different frequencies. This problem is typically overcome by synchronizing one of the signals to the local clock
through use of a flip-flop. However, this solution presents an awkward dilemma since the setup and hold time
specifications associated with the flip-flop are sure to be violated. The metastable characteristics of the flip-flop
can influence overall system reliability.
Whenever the setup and hold times of a flip-flop are violated, its output response becomes uncertain and is said
to be in the metastable state if the output hangs up in the region between VIL and VIH. This metastable condition
lasts until the flip-flop falls into one of its two stable states, which takes longer than the specified maximum
propagation delay time (CLK to Q max).
From a system engineering standpoint, a designer cannot use the specified data sheet maximum for
propagation delay time when using the flip-flop as a data synchronizer − how long to wait after the specified data
sheet maximum must be known before using the data in order to guarantee reliable system operation.
The circuit shown in Figure 4 can be used to evaluate MTBF (Mean Time Between Failure) and Δt for a selected
flip-flop. Whenever the Q output of the DUT is between 0.8 V and 2 V, the comparators are in opposite states.
When the Q output of the DUT is higher than 2 V or lower than 0.8 V, the comparators are at the same logic level.
The outputs of the two comparators are sampled a selected time (Δt) after SCLK. The exclusive OR gate detects
the occurrence of a failure and increments the failure counter.
Noise
Generator
DATA IN
DUT
VIH
Comparator
1D
MTBF
Counter
1D
1D
C1
+
C1
VIL
Comparator
SCLK
C1
1D
C1
SCLK + Δ t
Figure 4. Metastable Evaluation Test Circuit
In order to maximize the possibility of forcing the DUT into a metastable state, the input data signal is applied
so that it always violates the setup and hold time. This condition is illustrated in the timing diagram in Figure 5.
Any other relationship of SCLK to data will provide less chance for the device to enter into the metastable state.
Data
SCLK
SCLK + Δ t
Time (sec)
MTBF +
# Failures
Δt
Δt
trec = Δ t − CLK to Q (max)
Figure 5. Timing Diagram
16
POST OFFICE BOX 655303
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TIBPAL16R4-10C, TIBPAL16R6-10C, TIBPAL16R8-10C
HIGH-PERFORMANCE IMPACT-X™ PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
By using the described test circuit, MTBF can be determined for several different values of Δt (see Figure 4).
Plotting this information on semilog scale demonstrates the metastable characteristics of the selected flip-flop.
Figure 6 shows the results for the TIBPAL16’-10C operating at 1 MHz.
10 9
10 yr
10 8
1 yr
MTBF (s)
10 7
10 6
1 mo
1 wk
10 5
1 day
10 4
1 hr
10 3
10 2
1 min
10 1
10 s
0
10
fclk = 1 MHz
fdata = 500 kHz
20
30
40
Δ t (ns)
50
60
70
Figure 6. Metastable Characteristics
From the data taken in the above experiment, an equation can be derived for the metastable characteristics at
other clock frequencies.
1
The metastable equation:
+ f
x f
x C1 e (*C2 x Dt)
data
SCLK
MTBF
The constants C1 and C2 describe the metastable characteristics of the device. From the experimental data,
these constants can be solved for: C1 = 9.15 X 10−7 and C2 = 0.959
Therefore
1
+ f
x f
x 9.15 x 10 *7 e (*0.959 x Dt)
data
SCLK
MTBF
definition of variables
DUT (Device Under Test): The DUT is a 10-ns registered PLD programmed with the equation Q : = D.
MTBF (Mean Time Between Failures): The average time (s) between metastable occurrences that cause a
violation of the device specifications.
fSCLK (system clock frequency): Actual clock frequency for the DUT.
fdata (data frequency): Actual data frequency for a specified input to the DUT.
C1: Calculated constant that defines the magnitude of the curve.
C2: Calculated constant that defines the slope of the curve.
trec (metastability recovery time): Minimum time required to guarantee recovery from metastability, at a given
MTBF failure rate. trec = Δt − tpd (CLK to Q, max)
Δt: The time difference (ns) from when the synchronizing flip-flop is clocked to when its output is sampled.
The test described above has shown the metastable characteristics of the TIBPAL16R4/R6/R8-10C series. For
additional information on metastable characteristics of Texas Instruments logic circuits, please refer to TI
Applications publication SDAA004, ”Metastable Characteristics, Design Considerations for ALS, AS, and LS
Circuits.’’
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
TIBPAL16L8-10C, TIBPAL16R4-10C, TIBPAL16R6-10C, TIBPAL16R8-10C
TIBPAL16L8-12M, TIBPAL16R4-12M, TIBPAL16R6-12M, TIBPAL16R8-12M
HIGH-PERFORMANCE IMPACT-X™ PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
vs
FREE - AIR TEMPERATURE
9
tPHL (I, I/O to O, I/O)
8
Propagation Delay Time − ns
Propagation Delay Time − ns
8
VCC = 5 V
CL = 50 pF
R1 = 200 Ω
R2 = 390 Ω
1 Output Switching
PROPAGATION DELAY TIME
vs
SUPPLY VOLTAGE
7
tPLH (I, I/O to O, I/O)
6
tPHL (CLK to Q)
5
4
3
−75
tPHL (I, I/O to O, I/O)
7
tPLH (I, I/O to O, I/O)
6
tPHL (CLK to Q)
5
4
tPLH (CLK to Q)
−50
TA = 25 °C
CL = 50 pF
R1 = 200 Ω
R2 = 390 Ω
75 100
−25
0
25
50
TA − Free - Air Temperature − ° C
tPLH (CLK to Q)
3
4.5
125
4.75
5
5.25
VCC − Supply Voltage − V
Figure 7
Figure 8
PROPAGATION DELAY TIME
vs
NUMBER OF OUTPUTS SWITCHING
Propagation Delay Time − ns
11
VCC = 5 V
TA = 25 ° C
10 CL = 50 pF
R1 = 200 Ω
R2 = 390 Ω
9
tPHL (I, I/O to O, I/O)
8
7
tPLH (I, I/O to O, I/O)
6
5
tPHL (CLK to Q)
4
3
tPLH (CLK to Q)
0
1
6
2
3
4
5
Number of Outputs Switching
7
Figure 9
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
8
5.5
TIBPAL16L8-10C, TIBPAL16R4-10C, TIBPAL16R6-10C, TIBPAL16R8-10C
TIBPAL16L8-12M, TIBPAL16R4-12M, TIBPAL16R6-12M, TIBPAL16R8-12M
HIGH-PERFORMANCE IMPACT-X™ PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS
POWER DISSIPATION
vs
FREQUENCY
8 - BIT COUNTER MODE
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
18
14
VCC = 5 V
P − Power Dissipation − mW
D
16
12
10
8
tPLH (CLK to Q)
tPHL (CLK to Q)
6
tPLH (I, I/O to O, I/O)
tPHL (I, I/O to O, I/O)
4
2
800
TA = 0 ° C
700
100
200
300
400
500
CL − Load Capacitance − pF
600
TA = 25 ° C
TA = 80 ° C
600
0
1
4
10
40
100
F − Frequency − MHz
Figure 11
Figure 10
SUPPLY CURRENT
vs
FREE - AIR TEMPERATURE
180
Unprogrammed Device
170
I CC − Supply Current − mA
Propagation Delay Time − ns
900
VCC = 5 V
TA = 25 ° C
R1 = 200 Ω
R2 = 390 Ω
1 Output Switching
VCC = 5.5 V
160
VCC = 5.25 V
150
140
130
120
VCC = 5 V
VCC = 4.75 V
110
100
−75
VCC = 4.5 V
−50
−25
0
25
50
75
100
TA − Free - Air Temperature − ° C
125
Figure 12
POST OFFICE BOX 655303
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19
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D0892
©1992 Texas Instruments Incorporated
SRPS017
PACKAGE OPTION ADDENDUM
www.ti.com
21-Mar-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
Samples
(Requires Login)
5962-85155132A
ACTIVE
LCCC
FK
20
1
TBD
Call TI
Call TI
5962-8515513RA
ACTIVE
CDIP
J
20
1
TBD
Call TI
Call TI
1
5962-8515513SA
ACTIVE
CFP
W
20
TBD
Call TI
Call TI
5962-85155142A
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
5962-8515514RA
OBSOLETE
CDIP
J
20
TBD
Call TI
Call TI
5962-8515514SA
OBSOLETE
CFP
W
20
TBD
Call TI
Call TI
5962-85155152A
ACTIVE
LCCC
FK
20
1
TBD
Call TI
Call TI
5962-8515515RA
ACTIVE
CDIP
J
20
1
TBD
Call TI
Call TI
5962-8515515SA
ACTIVE
CFP
W
20
1
TBD
Call TI
Call TI
5962-85155162A
ACTIVE
LCCC
FK
20
1
TBD
Call TI
Call TI
5962-8515516RA
ACTIVE
CDIP
J
20
1
TBD
Call TI
Call TI
5962-8515516SA
ACTIVE
CFP
W
20
1
TBD
Call TI
Call TI
TIBPAL16L8-10CFN
ACTIVE
PLCC
FN
20
46
Green (RoHS
& no Sb/Br)
TIBPAL16L8-10CN
ACTIVE
PDIP
N
20
20
Pb-Free (RoHS)
CU NIPDAU N / A for Pkg Type
TIBPAL16L8-12MFKB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE N / A for Pkg Type
TIBPAL16L8-12MJ
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
TIBPAL16L8-12MJB
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
TIBPAL16L8-12MWB
ACTIVE
CFP
W
20
1
TBD
Call TI
N / A for Pkg Type
TIBPAL16R4-10CFN
NRND
PLCC
FN
20
46
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-245C-168 HR
CU NIPDAU Level-3-245C-168 HR
TIBPAL16R4-10CN
NRND
PDIP
N
20
20
Pb-Free (RoHS)
CU NIPDAU N / A for Pkg Type
TIBPAL16R4-12MFKB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE N / A for Pkg Type
TIBPAL16R4-12MJ
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
TIBPAL16R4-12MJB
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
TIBPAL16R4-12MWB
ACTIVE
CFP
W
20
1
TBD
Call TI
N / A for Pkg Type
TIBPAL16R6-10CFN
NRND
PLCC
FN
20
46
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-245C-168 HR
TIBPAL16R6-10CN
NRND
PDIP
N
20
20
Pb-Free (RoHS)
CU NIPDAU N / A for Pkg Type
TIBPAL16R6-12MFKB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE N / A for Pkg Type
Addendum-Page 1
(3)
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
TIBPAL16R6-12MJB
21-Mar-2012
Status
(1)
ACTIVE
Package Type Package
Drawing
CDIP
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
J
20
1
TBD
A42
N / A for Pkg Type
1
TIBPAL16R6-12MWB
ACTIVE
CFP
W
20
TBD
Call TI
N / A for Pkg Type
TIBPAL16R8-10CFN
OBSOLETE
PLCC
FN
20
TBD
Call TI
Call TI
TIBPAL16R8-10CN
OBSOLETE
PDIP
N
20
TBD
Call TI
Call TI
TIBPAL16R8-12MFKB
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
TIBPAL16R8-12MJ
OBSOLETE
CDIP
J
20
TBD
Call TI
Call TI
TIBPAL16R8-12MJB
OBSOLETE
CDIP
J
20
TBD
Call TI
Call TI
TIBPAL16R8-12MWB
OBSOLETE
CFP
W
20
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPLC004A – OCTOBER 1994
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
E
18
D2 / E2
E1
D2 / E2
8
14
0.021 (0,53)
0.013 (0,33)
0.007 (0,18) M
0.050 (1,27)
9
13
0.008 (0,20) NOM
D/E
D2 / E2
D1 / E1
NO. OF
PINS
**
MIN
MAX
MIN
MAX
MIN
MAX
20
0.385 (9,78)
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.169 (4,29)
28
0.485 (12,32)
0.495 (12,57)
0.450 (11,43)
0.456 (11,58)
0.191 (4,85)
0.219 (5,56)
44
0.685 (17,40)
0.695 (17,65)
0.650 (16,51)
0.656 (16,66)
0.291 (7,39)
0.319 (8,10)
52
0.785 (19,94)
0.795 (20,19)
0.750 (19,05)
0.756 (19,20)
0.341 (8,66)
0.369 (9,37)
68
0.985 (25,02)
0.995 (25,27)
0.950 (24,13)
0.958 (24,33)
0.441 (11,20)
0.469 (11,91)
84
1.185 (30,10)
1.195 (30,35)
1.150 (29,21)
1.158 (29,41)
0.541 (13,74)
0.569 (14,45)
4040005 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
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