TIBPAL22V10-7CFN

TIBPAL22V10-7C HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS014E − D3520, AUGUST 1990 − REVISED DECEMBER 2010 • • • • • • CLK/I I I I I I I I I I I GND Increased Logic Power − Up to 22 Inputs and 10 Outputs Increased Product Terms − Average of 12 Per Output Variable Product Term Distribution Allows More Complex Functions to Be Implemented Each Output Is User Programmable for Registered or Combinational Operation, Polarity, and Output Enable Control TTL-Level Preload for Improved Testability Fast Programming, High Programming Yield, and Unsurpassed Reliability Ensured Using Ti-W Fuses • AC and DC Testing Done at the Factory Utilizing Special Designed-In Test Features • Package Options Include Both Plastic Chip Carrier and Plastic DIP description 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I FN PACKAGE (TOP VIEW) Power-Up Clear on Registered Outputs Extra Terms Provide Logical Synchronous Set and Asynchronous Reset Capability 1 I I I NC I I I 5 4 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 I/O/Q I/O/Q I/O/Q NC I/O/Q I/O/Q I/O/Q I I/O/Q I/O/Q • High-Performance Operation: fmax (External Feedback) . . . 80 MHz Propagation Delay . . . 7.5 ns Max I I CLK/I NC VCC I/O/Q I/O/Q • NT PACKAGE (TOP VIEW) Second-Generation PLD Architecture I I GND NC • • NC − No internal connection Pin assignments in operating mode The TIBPAL22V10-7C is a programmable array logic device featuring high speed and functional equivalency when compared to presently available devices. The TIBPAL22V10-7C is implemented with the familiar sum-of-products (AND-OR) logic structure featuring programmable output logic macrocells. This IMPACT-X™ circuit combines the latest Advanced Low-Power Schottky technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic. This device contains up to 22 inputs and 10 outputs. It incorporates the unique capability of defining and programming the architecture of each output on an individual basis. Outputs can be registered or nonregistered and inverting or noninverting as shown in the output logic macrocell diagram. The ten potential outputs are enabled through the use of individual product terms. IMPACT-X is a trademark of Texas Instruments Incorporated. Copyright © 2010, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TIBPAL22V10-7C HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS014E − D3520, AUGUST 1990 − REVISED DECEMBER 2010 description (continued) Further advantages can be seen in the introduction of variable product term distribution. This technique allocates from 8 to 16 logical product terms to each output for an average of 12 product terms per output. This variable allocation of terms allows far more complex functions to be implemented than in previously available devices. Circuit design is enhanced by the addition of a synchronous set and an asynchronous reset product term. These functions are common to all registers. When the synchronous set product term is a logic 1, the output registers are loaded with a logic 1 on the next low-to-high clock transition. When the asynchronous reset product term is a logic 1, the output registers are loaded with a logic 0. The output logic level after set or reset depends on the polarity selected during programming. Output registers can be preloaded to any desired state during testing. Preloading permits full logical verification during product testing. With features such as programmable output logic macrocells and variable product term distribution, the TIBPAL22V10’ offers quick design and development of custom LSI functions with complexities of 500 to 800 equivalent gates. Since each of the ten output pins may be individually configured as inputs on either a temporary or permanent basis, functions requiring up to 21 inputs and a single output or down to 12 inputs and 10 outputs are possible. A power-up clear function is supplied that forces all registered outputs to a predetermined state after power is applied to the device. Registered outputs selected as active-low power up with their outputs high. Registered outputs selected as active-high power up with their outputs low. A single security fuse is provided on each device to discourage unauthorized copying of fuse patterns. Once blown, the verification circuitry is disabled and all other fuses will appear to be open. The TIBPAL22V10-7C is characterized for operation from 0°C to 75°C. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TIBPAL22V10-7C HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS014E − D3520, AUGUST 1990 − REVISED DECEMBER 2010 functional block diagram (positive logic) C1 Set & 1S Reset 44 x 132 8 R 1 Output Logic Macrocell 10 22 CLK/I 12 10 I/O/Q EN I/O/Q EN 16 22 I/O/Q EN 16 11 I/O/Q EN 14 I I/O/Q EN I/O/Q EN 14 I/O/Q EN 12 I/O/Q EN 10 I/O/Q EN 8 I/O/Q EN 10 10 10 denotes fused inputs POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 I I I I 5 4 3 2 1 First Fuse Numbers CLK/I 2860 2156 2112 1496 1452 924 880 440 396 0 0 4 8 logic diagram (positive logic) 12 16 20 24 Increment 28 32 36 40 P = 5816 R = 5817 Macrocell P = 5814 R = 5815 Macrocell P = 5812 R = 5813 Macrocell P = 5810 R = 5811 Macrocell P = 5808 R = 5809 Macrocell 19 20 21 22 23 I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q Asynchronous Reset (to all registers) TIBPAL22V10-7C HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS014E − D3520, AUGUST 1990 − REVISED DECEMBER 2010 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 10 9 8 7 5764 5720 5368 5324 4884 4840 4312 4268 3652 3608 Fuse number = First fuse number + Increment Inside each MACROCELL the ”P” fuse is the polarity fuse and the ”R” fuse is the register fuse. I I I I I I 6 2904 P = 5826 R = 5827 Macrocell P = 5824 R = 5825 Macrocell P = 5822 R = 5823 Macrocell P = 5820 R = 5821 Macrocell P = 5818 R = 5819 Macrocell 13 14 15 16 17 18 I Synchronous Set (to all registers) I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q TIBPAL22V10-7C HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS014E − D3520, AUGUST 1990 − REVISED DECEMBER 2010 5 TIBPAL22V10-7C HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS014E − D3520, AUGUST 1990 − REVISED DECEMBER 2010 output logic macrocell diagram Output Logic Macrocell 2 AR R I=0 3 1D 0 C1 SS 1 1S 1 0 From Clock Buffer MUX S0 1 1 G1 S1 AR = asynchronous reset SS = synchronous set 6 MUX POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 G 0 3 TIBPAL22V10-7C HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS014E − D3520, AUGUST 1990 − REVISED DECEMBER 2010 R R 1D 1D C1 C1 1S 1S S1 = 0 S0 = 0 S1 = 0 S0 = 1 REGISTER FEEDBACK, REGISTERED, ACTIVE-LOW OUTPUT REGISTER FEEDBACK, REGISTERED, ACTIVE-HIGH OUTPUT S1 = 1 S1 = 1 S0 = 0 S0 = 1 I/O FEEDBACK, COMBINATIONAL, ACTIVE-LOW OUTPUT I/O FEEDBACK, COMBINATIONAL, ACTIVE-HIGH OUTPUT MACROCELL FEEDBACK AND OUTPUT FUNCTION TABLE FUSE SELECT S1 S0 FEEDBACK AND OUTPUT CONFIGURATION 0 0 Register feedback Registered Active low 0 1 Register feedback Registered Active high 1 0 I/O feedback Combinational Active low 1 1 I/O feedback Combinational Active high 0 = unblown fuse, 1 = blown fuse S1 and S0 are select-function fuses as shown in the output logic macrocell diagram. Figure 1. Resultant Macrocell Feedback and Output Logic After Programming POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TIBPAL22V10-7C HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS014E − D3520, AUGUST 1990 − REVISED DECEMBER 2010 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage range (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1.2 V to VCC +0.5 V Voltage range applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC +0.5 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle. recommended operating conditions VCC Supply voltage VIH High-level input voltage (see Note 2) VIL Low-level input voltage (see Note 2) IOH MIN NOM MAX UNIT 4.75 5 5.25 V 5.5 V 2 0.8 V High-level output current −3.2 mA IOL Low-level output current 16 mA tw Pulse duration tsu Setup time before clock↑ Clock high or low 4 Asynchronous reset high or low 6 Input 5.5 Feedback 5.5 Synchronous preset (active) 8 Synchronous preset (inactive) 8 Asynchronous reset (inactive) 6 th Hold time, input, set, or feedback after clock↑ 0 TA Operating free-air temperature 0 ns ns ns 75 °C NOTE 2: These are absolute voltage levels with respect to the ground terminal of the device and includes all overshoots due to system and/or tester noise. Testing these parameters should not be attempted without suitable equipment. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TIBPAL22V10-7C HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS014E − D3520, AUGUST 1990 − REVISED DECEMBER 2010 electrical characteristics over recommended operating free-air temperature range PARAMETER TEST CONDITIONS VIK VCC = 4.75 V, II = − 18 mA VOH VCC = 4.75 V, IOH = − 3.2 mA VOL VCC = 4.75 V, IOL = 16 mA ‡ VCC = 5.25 V, IOZL‡ VCC = 5.25 V, II VCC = 5.25 V, VI = 5.5 V VCC = 5.25 V, VI = 2.7 V IOZH IIH ‡ CLK MIN TYP† MAX UNIT −1.2 V 2.4 V 0.35 0.5 V VO = 2.7 V 0.1 mA VO = 0.4 V −0.1 mA 1 mA 25 μA −0.25 VCC = 5.25 V, VI = 0.4 V IOS§ VCC = 5.25 V, VO = 0.5 V ICC VCC = 5.25 V, VI = GND, Ci f = 1 MHz, VI = 2 V 6 pF Co f = 1 MHz, VO = 2 V 8 pF IIL All others −0.1 −30 Outputs open mA −130 mA 210 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ I/O leakage is the worst case of I OZL and IIL or IOZH and IIH, respectively. § Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. V is set at 0.5 V to O avoid test problems caused by test equipment ground degradation. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fmax¶ ¶ FROM (INPUT) TO (OUTPUT) TEST CONDITIONS TIBPAL22V10-7CFN MIN MAX TIBPAL22V10-7CNT MIN Without feedback 125 125 With internal feedback (counter configuration) 100 100 With external feedback 87 80 tpd I, I/O I/O R1 = 300 Ω, tpd I, I/O (reset) Q R2 = 300 Ω, tpd CLK Q See Figure 6 tpd# CLK Feedback ten I, I/O I/O, Q tdis I, I/O I/O, Q 3 7.5 3 MAX UNIT MHz 7.5 ns 12 ns 7 ns 4.5 ns 8 8 ns 7.5 7.5 ns 12 1.5 6 4.5 1.5 1 fmax (without feedback) = t w(low) ) t w(high) 1 fmax (with internal feedback) = t su ) t (CLK to feedback) pd 1 (CLK to Q) pd # This parameter is calculated from the measured f max with internal feedback in the counter configuration. fmax (with external feedback) = t su ) t POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TIBPAL22V10-7C HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS014E − D3520, AUGUST 1990 − REVISED DECEMBER 2010 preload procedure for registered outputs (see Notes 3 and 4) The output registers can be preloaded to any desired state during device testing. This permits any state to be tested without having to step through the entire state-machine sequence. Each register is preloaded individually by following the steps given below: Step 1. Step 2. Step 3. Step 4. With VCC at 5 V and pin 1 at VIL, raise pin 13 to VIHH. Apply either VIL or VIH to the output corresponding to the register to be preloaded. Pulse pin 1, clocking in preload data. Remove output voltage, then lower pin 13 to VIL. Preload can be verified by observing the voltage level at the output pin. VIHH Pin 13 td tsu tw VIL td VIH Pin 1 VIL VIH Registered I/O Input VOH Output VIL VOL Figure 2. Preload Waveforms NOTES: 3. Pin numbers shown are for the NT package only. If chip-carrier socket adapter is not used, pin numbers must be changed accordingly. 4. td = tsu = tw = 100 ns to 1000 ns. VIHH = 10.25 V to 10.75 V. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TIBPAL22V10-7C HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS014E − D3520, AUGUST 1990 − REVISED DECEMBER 2010 power-up reset Following power up, all registers are reset to zero. The output level depends on the polarity selected during programming. This feature provides extra flexibility to the system designer and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is important that the rise of VCC be monotonic. Following power-up reset, a low-to-high clock transition must not occur until all applicable input and feedback setup times are met. VCC 5V 4V tpd† (600 ns typ, 1000 ns MAX) Active High Registered Output State Unknown Active Low Registered Output State Unknown VOH 1.5 V VOL VOH 1.5 V VOL tsu‡ CLK 1.5 V 1.5 V tw † ‡ VIH VIL This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data. This is the setup time for input or feedback. Figure 3. Power-Up Reset Waveforms programming information Texas Instruments programmable logic devices can be programmed using widely available software and inexpensive device programmers. Complete programming specifications, algorithms, and the latest information on hardware, software, and firmware are available upon request. Information on programmers capable of programming Texas Instruments programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI distributor, or by calling Texas Instruments at (214) 997-5666. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TIBPAL22V10-7C HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS014E − D3520, AUGUST 1990 − REVISED DECEMBER 2010 THERMAL INFORMATION thermal management of the TIBPAL22V10-7C Thermal management of the TIBPAL22V10-7CNT and TIBPAL22V10-7CFN is necessary when operating at certain conditions of frequency, output loading, and outputs switching simultaneously. The device and system application will determine the appropriate level of management. Determining the level of thermal management is based on factors such as power dissipation (PD), ambient temperature (TA ), and transverse airflow (FPM). Figures 4 (a) and 4 (b) show the relationship between ambient temperature and transverse airflow at given power dissipation levels. The required transverse airflow can be determined at a particular ambient temperature and device power dissipation level in order to ensure the device specifications. Figure 5 illustrates how power dissipation varies as a function of frequency and the number of outputs switching simultaneously. It should be noted that all outputs are fully loaded (CL = 50 pF). Since the condition of ten fully loaded outputs represents the worst-case condition, each application must be evaluated accordingly. MINIMUM TRANSVERSE AIR FLOW vs AMBIENT TEMPERATURE MINIMUM TRANSVERSE AIR FLOW vs AMBIENT TEMPERATURE 600 Minimum Transverse Air Flow − ft/min Minimum Transverse Air Flow − ft/min 600 500 400 PD = 1.8 W PD = 1.6 W PD = 1.4 W PD = 1.2 W PD = 1 W 300 200 100 0 0 10 20 30 40 50 60 70 500 400 300 200 100 0 80 PD = 1.8 W PD = 1.6 W PD = 1.4 W PD = 1.2 W PD = 1 W 0 TA − Ambient Temperature − °C 20 30 40 50 60 TA − Ambient Temperature − °C (a) TIBPAL22V10-7CNT (b) TIBPAL22V10-7CFN Figure 4 12 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 70 80 TIBPAL22V10-7C HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS014E − D3520, AUGUST 1990 − REVISED DECEMBER 2010 THERMAL INFORMATION POWER DISSIPATION vs FREQUENCY 2000 P − Power Dissipation − mW D 1900 1800 VCC = 5 V R1 = 300 Ω R2 = 300 Ω TA = 25 °C CL = 50 pF 10 Outputs Switching 1700 1600 1500 1400 1300 1 Output Switching 1200 0.1 0.2 0.4 1 2 4 10 20 40 100 200 f − Frequency − MHz Figure 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TIBPAL22V10-7C HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS014E − D3520, AUGUST 1990 − REVISED DECEMBER 2010 PARAMETER MEASUREMENT INFORMATION 5V S1 R1 From Output Under Test Test Point CL (see Note A) R2 LOAD CIRCUIT FOR 3-STATE OUTPUTS 3V Timing Input 1.5 V 0 0 (see Note B) 1.5 V 3V 1.5 V tpd tpd 1.5 V VOH 1.5 V VOL tpd tpd 1.5 V 3V Low-Level Pulse 1.5 V 1.5 V VOLTAGE WAVEFORMS PULSE DURATIONS 0 Out-of-Phase Output (see Note D) 0 tw VOLTAGE WAVEFORMS SETUP AND HOLD TIMES In-Phase Output 1.5 V 3V 1.5 V 1.5 V Input 1.5 V th tsu Data Input 3V High-Level Pulse VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES Output Control (low-level enabling) 0 (see Note B) 3V 1.5 V ten 1.5 V tdis 1.5 V Waveform 1 S1 Closed (see Note C) tdis ten Waveform 2 S1 Open (see Note C) 0 (see Note B) ≈ 2.7 V VOL + 0.5 V VOL VOH 1.5 V VOH − 0.5 V ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis. B. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. When measuring propagation delay times of 3-state outputs, switch S1 is closed. E. Equivalent loads may be used for testing. Figure 6. Load Circuit and Voltage Waveforms 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TIBPAL22V10-7C HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS014E − D3520, AUGUST 1990 − REVISED DECEMBER 2010 TYPICAL CHARACTERISTICS PROPAGATION DELAY TIME vs SUPPLY VOLTAGE SUPPLY CURRENT vs FREE - AIR TEMPERATURE 7 210 tPLH (I, I/O to O, I/O) Propagation Delay Time − ns I CC − Supply Current − mA 6 200 VCC = 5.25 V 190 VCC = 5 V VCC = 4.75 V 180 tPLH (CLK to Q) 5 tPHL (I, I/O to O, I/O) 4 tPHL (CLK to Q) 3 2 TA = 25 ° C CL = 50 pF R1 = 300 Ω R2 = 300 Ω 10 Outputs Switching 1 170 0 25 50 TA − Free - Air Temperature − ° C 0 4.75 75 5 VCC − Supply Voltage − V Figure 7 Figure 8 PROPAGATION DELAY TIME vs FREE - AIR TEMPERATURE PROPAGATION DELAY TIME vs LOAD CAPACITANCE 16 7 tPLH (CLK to Q) 5 tPHL (I, I/O to O, I/O) 4 tPHL (CLK to Q) 3 2 VCC = 5 V CL = 50 pF R1 = 300 Ω R2 = 300 Ω 10 Outputs Switching 1 0 0 VCC = 5 V TA = 25 ° C R1 = 300 Ω R2 = 300 Ω 1 Output Switching 14 12 10 8 6 tpd (I, I/O to O, I/O) 4 tpd (CLK to Q) t Propagation Delay Time − ns pd − Propagation Delay Time − ns tPLH (I, I/O to O, I/O) 6 5.25 2 25 50 TA − Free - Air Temperature − ° C 75 0 0 Figure 9 100 500 200 300 400 CL − Load Capacitance − pF 600 Figure 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TIBPAL22V10-7C HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS014E − D3520, AUGUST 1990 − REVISED DECEMBER 2010 TYPICAL CHARACTERISTICS WORST-CASE PROPAGATION DELAY TIME vs NUMBER OF OUTPUTS SWITCHING NT PACKAGE 7 7 6 6 Propagation Delay Time − ns Propagation Delay Time − ns WORST-CASE PROPAGATION DELAY TIME vs NUMBER OF OUTPUTS SWITCHING FN PACKAGE 5 4 3 1 = tPLH (I, I/O to O, I/O) = tPHL (I, I/O to O, I/O) = tPLH (CLK to Q) = tPHL (CLK to Q) VCC = 5 V TA = 25 ° C CL = 50 pF R1 = 300 Ω R2 = 300 Ω 2 1 2 3 4 5 6 7 6 Number of Outputs Switching 7 5 4 3 VCC = 5 V TA = 25 ° C CL = 50 pF R1 = 300 Ω R2 = 300 Ω 2 1 10 1 2 6 7 6 3 4 5 Number of Outputs Switching Figure 11 Figure 12 POWER DISSIPATION vs FREQUENCY 10 - BIT COUNTER MODE 1200 P − Power Dissipation − mW D VCC = 5 V 1100 TA = 0 ° C 1000 TA = 25 ° C TA = 75 ° C 900 800 1 2 4 10 20 40 f − Frequency − MHz Figure 13 16 = tPLH (I, I/O to O, I/O) = tPHL (I, I/O to O, I/O) = tPLH (CLK to Q) = tPHL (CLK to Q) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 100 7 10 PACKAGE OPTION ADDENDUM www.ti.com 29-May-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) TIBPAL22V10-7CFN LIFEBUY PLCC FN 28 37 TBD CU SNPB Level-1-220C-UNLIM 0 to 75 22V10-7CFN TIBPAL22V10-7CNT LIFEBUY PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 75 TIBPAL22V10-7 CNT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 29-May-2015 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MPLC004A – OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58) 0.191 (4,85) 0.219 (5,56) 44 0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66) 0.291 (7,39) 0.319 (8,10) 52 0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20) 0.341 (8,66) 0.369 (9,37) 68 0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91) 84 1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45) 4040005 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. 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