TIOL112, TIOL1123, TIOL1125
SLLSFJ1D – FEBRUARY 2022 – REVISED MARCH 2023
TIOL112 and TIOL112x IO-Link Device Transceivers with Low Residual Voltage and
Integrated Surge Protection in Small Packages
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Field Transmitters and actuators
Factory automation
Process automation
IO-link PHY in remote IO
3 Description
The TIOL112(x) family of transceivers implements the
IO-Link interface for industrial bidirectional, point-topoint communication. When the device is connected
to an IO-Link master through a three-wire interface,
the master initiates communication and exchange
data with the remote node while the TIOL112(x) acts
as a complete physical layer for the communication.
– Configurable driver overcurrent limit:
50 mA to 350 mA
– Active reverse polarity protection of up to 65 V
on L+, CQ and L– Fault indicator for overcurrent, overtemperature
and UVLO faults
– Safe and fast demagnetization of inductive
loads
– Extended ambient temperature operation:
–40°C to 125°C
Integrated EMC protection on L+ and CQ
– ±8 kV IEC 61000-4-2 ESD contact discharge
– ±4 kV IEC 61000-4-4 electrical fast transient
– ±1.2 kV/500 Ω IEC 61000-4-5 surge
Large capacitive load driving capability
< 2-µA CQ leakage current
< 1.5-mA quiescent supply current
Integrated LDO options for up to 20 mA current
– TIOL1123: 3.3-V LDO
– TIOL1125: 5-V LDO
– TIOL1123L (YAH): Selectable 3.3-V/5-V Output
Remote wake-up indication and wake-up
generation
Small space-saving package options
– 3 mm x 3 mm 10-pin VSON package:
pin-compatible with TIOL111
– 2.45 mm x 1.7 mm DSBGA package
Sensor
Front-End
These devices are capable of withstanding up to
1.2 kV (500 Ω) of IEC 61000-4-5 surge and feature
integrated reverse polarity protection. A simple pinprogrammable interface allows easy interfacing with
the controller circuits. The output current limit can
be configured using an external resistor. TIOL112(x)
can be configured to generate wake-up pulse and be
used in IO-link master applications. Fault reporting
and internal protection functions are provided
for undervoltage, overcurrent and overtemperature
conditions.
Device Information
PACKAGE(1)
PART NUMBER
BODY SIZE (NOM)
TIOL112
TIOL1123
VSON (10)
3.00 mm x 3.00 mm
DSBGA (12)
2.45 mm x 1.70 mm
TIOL1125
TIOL112
TIOL1123
(1)
For all available devices, see the orderable addendum at the
end of the data sheet.
VCC_OUT
1 µF
10 V
VOLTAGE
REGULATOR
Rev.
Polarity
Protection
L+
0.1 µF
100 V
10 k
ESD and
Surge
Protection
RX
10 k
TX
Microcontroller
EN
WAKE
CONTRO
L LOGIC
•
7-V to 36-V supply voltage
PNP, NPN or IO-Link configurable output
– IEC 61131-9 COM1, COM2 and COM3 Data
Rate Support
Functional safety-capable
– Documentation available to aid in functional
safety system design
Pin-compatible with TIOL111(x) with improved
performance
– Low residual Voltage of 0.5 V (typical) at
200 mA
– Active driver current limiting capability
– Improved thermal performance of the package
– Slower driver slew rates to reduce overshoots:
maximum of 750 ns
Integrated protection features for robust systems
CQ
DIAGNOSTICS
& CONTROL
Rev. Polarity
Protection
ESD and
Surge
Protection
NFAULT
CUR_OK
TMP_OK
PWR_OK
L-
ILIM_ADJ
Typical Application Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
IO-Link Master
PHY
TIOL112, TIOL1123, TIOL1125
www.ti.com
SLLSFJ1D – FEBRUARY 2022 – REVISED MARCH 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 ESD Ratings - IEC Specifications............................... 5
6.4 Recommended Operating Conditions.........................5
6.5 Thermal Information....................................................6
6.6 Electrical Characteristics.............................................6
6.7 Switching Characteristics............................................8
6.8 Typical Characteristics................................................ 9
7 Parameter Measurement Information.......................... 10
8 Detailed Description......................................................12
8.1 Overview................................................................... 12
8.2 Functional Block Diagrams....................................... 12
8.3 Feature Description...................................................13
8.4 Device Functional Modes..........................................20
9 Application and Implementation.................................. 21
9.1 Application Information............................................. 21
9.2 Typical Application.................................................... 21
9.3 Power Supply Recommendations.............................24
9.4 Layout....................................................................... 25
10 Device and Documentation Support..........................26
10.1 Receiving Notification of Documentation Updates..26
10.2 Support Resources................................................. 26
10.3 Trademarks............................................................. 26
10.4 Electrostatic Discharge Caution..............................26
10.5 Glossary..................................................................26
11 Mechanical, Packaging, and Orderable
Information.................................................................... 26
4 Revision History
Changes from Revision C (January 2023) to Revision D (March 2023)
Page
• Added the package outline and land pattern images for the YAH (DSBGA) 12-pin package...........................26
Changes from Revision B (December 2022) to Revision C (January 2023)
Page
• Deleted the Advanced Information note from the DSBGA package in the Device Information table................. 1
Changes from Revision A (April 2022) to Revision B (December 2022)
Page
• Removed the conditional note 2 from the IEC Ratings - ESD Specifications table that specified 4.5kV when
EN=TX=HIGH .................................................................................................................................................... 5
• Changed the description of I(VCC_OUT) from: (TIOL112L only) to: TIOL1123(L), TIOL1125 only in the
Recommended Operating Conditions table........................................................................................................5
• Changed Figure 6-4 and Figure 6-6 .................................................................................................................. 9
• Added application curves Figure 9-6 and Figure 9-7 showing inductive load demagnetization....................... 24
Changes from Revision * (February 2022) to Revision A (April 2022)
Page
• Deleted the Advanced Information note from the TIOL112 and TIOL1125 for the VSON package in the Device
Information table................................................................................................................................................. 1
2
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SLLSFJ1D – FEBRUARY 2022 – REVISED MARCH 2023
5 Pin Configuration and Functions
VCC_IN
1
10 WAKE
NFAULT
2
9
L+
RX
3
8
TX
4
EN
5
Thermal Pad
VCC_OUT
1
10 WAKE
NFAULT
2
9
L+
CQ
RX
3
8
CQ
7
L–
TX
4
7
L–
6
ILIM_ADJ
EN
5
6
ILIM_ADJ
Figure 5-1. TIOL112
DRC (VSON), 10-Pin
(Top View)
Thermal Pad
Figure 5-2. TIOL1123, TIOL1125
DRC (VSON), 10-Pin
(Top View)
Table 5-1. Pin Functions (VSON Package)
PIN NAME
PIN NO
TIOL112
TIOL1123
TIOL1125
TYPE
DESCRIPTION
1
VCC_IN
VCC_OUT
P
VCC_IN (TIOL112): External 3.3-V or 5-V logic supply input pin. VCC_OUT (TIOL1123,
TIOL1125): 3.3-V or 5-V linear regulator output
2
NFAULT
NFAULT
O
Fault indicator output signal to the microcontroller. A low level indicates either an over- current, an
undervoltage supply or an overtemperature condition.
3
RX
RX
O
Receive data output to the local microcontroller
4
TX
TX
I
Transmit data input from the local microcontroller. No effect if EN is low. Logic high sets low-side
switch. Logic low sets high-side switch. Weak internal pull-up.
5
EN
EN
I
Driver enable input signal from the local microcontroller. Logic low sets the CQ output at Hi-Z.
Weak internal pull-down.
6
ILIM_ADJ
ILIM_ADJ
I
Input for current limit adjustment. Connect resistor RSET between ILIM_ADJ and L-.
7
L-
L-
GND
8
CQ
CQ
I/O
9
L+
L+
P
IO-Link supply voltage (24 V nominal)
10
WAKE
WAKE
O
Wake-up indicator to the local microcontroller. Open-drain output, connect this pin via pull-up
resistor to VCC_IN/OUT.
Thermal Pad
Thermal Pad
—
Connect to L- for optimal thermal and electrical performance
IO-Link ground potential
IO-Link data signal (bidirectional)
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1
2
3
1
2
3
A
L-
CQ
L+
A
L-
CQ
L+
B
ILIM
_ADJ
L-
VCC_
OUT
B
ILIM
_ADJ
L-
VCC_
IN
C
VSEL
WAKE
NFAU
LT
C
NC
WAKE
NFAU
LT
D
RX
TX
EN
D
RX
TX
EN
Figure 5-3. TIOL1123L
YAH (DSBGA), 12-Pin
(Top View)
Figure 5-4. TIOL112
YAH (DSBGA), 12-Pin
(Top View)
Table 5-2. Pin Functions (DSBGA)
PIN NO
PIN NAME
TYPE
DESCRIPTION
VCC_OUT
P
VCC_IN (TIOL112): External 3.3-V or 5-V logic supply input pin. VCC_OUT (TIOL1123): 3.3-V or
5-V linear regulator output
NFAULT
NFAULT
O
Fault indicator output signal to the microcontroller. A low level indicates either an over- current, an
undervoltage supply or an overtemperature condition.
D1
RX
RX
O
Receive data output to the local controller
D2
TX
TX
I
Transmit data input from the local controller. No effect if EN is low. Logic high sets low-side
switch. Logic low sets high-side switch. Weak internal pull-up.
D3
EN
EN
I
Driver enable input signal from the local controller. Logic low sets the CQ output at Hi-Z. Weak
internal pull-down.
Input for current limit adjustment. Connect resistor RSET between ILIM_ADJ and L-.
TIOL112
TIOL1123L
B3
VCC_IN
C3
B1
ILIM_ADJ
ILIM_ADJ
O
A1,
B2
L-
L-
GND
A2
CQ
CQ
I/O
A3
L+
L+
P
IO-Link supply voltage (24 V nominal)
C1
NC
VSEL
I
TIOL112 (NC): Leave floating. Do not connect.
TIOL1123 (VSEL): Connect to GND for 5V LDO output. Please leave this pin floating for 3.3V
LDO output. VSEL has an internal pull-up of 1 MΩ
C2
WAKE
WAKE
O
Wake-up indicator to the local controller. Open-drain output, connect this pin via pull-up resistor to
IO-Link ground potential
IO-Link data signal (bidirectional)
VCC_IN/OUT.
4
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Supply voltage
MIN
MAX
Steady state voltage for L+ and CQ
–65
65
UNIT
V
Transient pulse width < 100 µs for L+ and CQ
–70
70
V
65
V
Voltage difference
|V(L+) – V(CQ)|
Logic supply voltage (TIOL112)
VCC_IN
–0.3
6
V
Input logic voltage
TX, EN, VSEL
min(VCC_IN+
–0.3
0.3, 6)
V
Output current
RX, WAKE, NFAULT
Storage temperature, Tstg
(1)
–5
5
mA
-55
170
°C
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime. All voltages are with reference to the L- pin, unless otherwise specified.
6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
All pins
±4000
V
V(ESD)
Electrostatic discharge
Charged Device Model (CDM), per ANSI/ESDA/JEDEC
JS-002 (2)
All pins
±750
V
(1)
(2)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings - IEC Specifications
VALUE
V(ESD)
(1)
(1)
Electrostatic discharge
IEC 61000-4-2 ESD (Contact Discharge), L+, CQ and L-
Electrostatic discharge
IEC 61000-4-5, 1.2 µs/50 µs Surge with 500 Ω in series, L+, CQ and L- (1)
±1,200
Electrostatic discharge
IEC 61000-4-4 EFT (Fast transient or burst), L+, CQ and L- (1)
±4,000
UNIT
±8,000
V
Minimum 100-nF capacitor is required between L+ and L-. Minimum 1-µF capacitor is required between VCC_IN/VCC_OUT and L-.
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
V(L+)
MIN
NOM
MAX
7
24
36
V
3
3.3
3.6
V
4.5
5
5.5
V
Supply voltage
3.3 V configuration
V(VCC_IN)
Logic level input voltage (TIOL112 only)
RSET
External resistor for CQ current limit
1/tBIT
Data rate (Communication mode)
I(VCC_OUT)
LDO output current (TIOL1123(L), TIOL1125 only)
TA
Operating ambient temperature
TJ
Junction temperature
5 V configuration
0
–40
UNIT
110
kΩ
250
kbps
20
mA
125
°C
150
°C
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6.5 Thermal Information
THERMAL
METRIC(1)
TIOL112,
TIOL1123,
TIOL1125
TIOL112, TIOL1123L
DRC (10 Pins)
YAH (12 Pins)
UNIT
RθJA
Junction-to-ambient thermal resistance
45.9
79.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
45.9
0.3
°C/W
RθJB
Junction-to-board thermal resistance
17.9
19.5
°C/W
ψJT
Junction-to-top characterization parameter
0.7
0.1
°C/W
ψJB
Junction-to-board characterization parameter
17.8
19.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.7
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Electrical Characteristics
Over recommended operating conditions and recommended free-air temperature range (unless otherwise noted). Typical
values are at L+ = 24 V, VVCC_IN = 3.3 V, VVCC_OUT = 3.3 V and TA = 25 ℃ unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (L+)
I(L+)
Quiescent supply current
EN = LOW, no load
1
1.5
mA
EN = HIGH, no load
2
2.95
mA
0.8
V
LOGIC-LEVEL INPUTS (EN, TX, VSEL)
VIL
Input logic low voltage
VIH
Input logic high voltage
RPD
Pull-down (EN) resistance
RPU
Pull-up (TX) resistance
RPU
Pull-up (VSEL) resistance
2
V
100
kΩ
200
kΩ
1000
kΩ
CONTROL OUTPUTS (WAKE, NFAULT)
VOL
Output logic low voltage
IO = 4 mA
IOZ
Output high impedance leakage
Output in Hi-Z, VO = 0 V or VCC_IN/OUT
–1
0.5
V
1
µA
DRIVER OUTPUT (CQ)
RDS(ON)
High-side driver on-resistance
VDS(ON)
High-side driver residual voltage
RDS(ON)
Low-side driver on-resistance
2.5
4.5
Ω
I = 200 mA
0.5
0.9
V
I = 100 mA
0.25
0.5
V
2.5
4.5
Ω
I = 200 mA
0.5
0.9
V
I = 100 mA
0.25
0.5
V
–2
2
µA
5
15
mA
VDS(ON)
Low-side driver residual voltage
IOZ(CQ)
CQ leakage
EN = LOW, 0 ≤ V(CQ) ≤ (V(L+) - 0.1 V)
ILLM
CQ load discharge current
EN = LOW, RSET = 0 to 5 kΩ (2), V(CQ) >= 5 V
RSET = 110 kΩ; V(CQ)= (VL+ - 3) V or 3 V
IO(LIM)
Driver output current limit
35
50
70
mA
RSET = 10 kΩ
300
350
400
mA
RSET = 0 to 5 kΩ (2)
V(CQ)= (VL+ - 3) V or 3 V
TJ < T(SDN) or t < 200 µs (3)
500
(Fast-detect mode) RSET = OPEN(1)V(CQ)= (VL+ - 3) V or
3V
260
mA
330
400
mA
RECEIVER INPUT (CQ)
6
V(THH)
Input threshold “H”
10.5
13
V
V(THL)
Input threshold “L"
8
11.5
V
V(HYS)
Receiver Hysteresis
(V(THH) - V(THL))
V(THH)
Input threshold “H”
V(L+) > 18 V, EN= LOW
0.75
V(L+) < 18 V, EN= LOW
See Note (4)
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V
See Note (5)
V
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6.6 Electrical Characteristics (continued)
Over recommended operating conditions and recommended free-air temperature range (unless otherwise noted). Typical
values are at L+ = 24 V, VVCC_IN = 3.3 V, VVCC_OUT = 3.3 V and TA = 25 ℃ unless otherwise specified.
PARAMETER
TEST CONDITIONS
V(THL)
Input threshold “L"
V(HYS)
Receiver Hysteresis
(V(THH) - V(THL))
V(L+) < 18 V, EN= LOW
VOL
RX output low voltage
IOL = 4 mA
VOH
RX output high voltage
MIN
See Note
TYP
(6)
MAX
See Note
(7)
0.75
V
V
0.4
VCC_IN/
OUT–0.5
IOL = –4 mA
UNIT
V
V
PROTECTION CIRCUITS
L+ falling; NFAULT = Hi-Z
6
6.3
V
V(UVLO)
L+ under voltage lockout
V(UVLO,HYS)
L+ under voltage hysteresis
Rising to falling threshold
V(UVLO_IN)
VCC_IN under voltage lockout
(No LDO option)
VCC_IN falling; NFAULT = Hi-Z
2.3
V
VCC_IN rising; NFAULT = LOW
2.5
V
V(UVLO,HYS)
VCC_IN under voltage hysteresis
Rising to falling threshold
(No LDO option)
190
mV
T(WRN)
Thermal warning
T(SDN)
Thermal shutdown
T(HYS)
Thermal hysteresis for shutdown
T(WRN)
Thermal hysteresis for warning
Leakage current in reverse
polarity
IREV
L+ rising; NFAULT = LOW
6.5
6.8
200
125
Die temperature TJ
150
Die temperature TJ
V
mV
°C
160
°C
14
°C
14
°C
EN=LOW, TX=x; V(CQ) < V(L-) or V(CQ) > V(L+), up to |36
V|
60
µA
EN=LOW, TX=x; V(CQ) < V(L-) or V(CQ) > V(L+), up to |65
V|
110
µA
EN = HIGH, TX = LOW; V(CQ to L+) = 3 V
640
µA
EN = HIGH, TX = HIGH; V(CQ to L-) = -3 V
10
µA
LINEAR REGULATOR (LDO)
V(VCC_OUT)
Voltage regulator output
TIOL1125, TIOL1123L (5V)
4.75
5
5.25
V
TIOL1123, TIOL1123L (3.3V)
3.13
3.3
3.46
V
TIOL1125, TIOL1123L (5V)
0.75
1.9
V
TIOL1123, TIOL1123L
(3.3V)
0.75
2.3
V
mV/V
V(DROP)
Voltage regulator drop-out
voltage
(V(L+) – V(VCC_OUT))
ICC = 20 mA load current
REG
Line regulation (dV(VCC_OUT)/
dV(L+))
I(VCC_OUT) = 1 mA
1.7
LREG
Load regulation (dV(VCC_OUT)/
V(VCC_OUT))
V(L+) = 24 V, I(VCC_OUT) = 100 µA to 20 mA
1%
PSSR
Power Supply Rejection Ratio
100 kHz, I(VCC_OUT) = 20 mA
(1)
(2)
(3)
(4)
(5)
(6)
(7)
40
dB
Current fault indication will be active. Current fault auto recovery will be de-activated.
Current fault indication and current fault auto recovery will be de-activated.
If operating continuosly with this current limit, ensure that the current through the device does not cause the TJ to be greater than
T(SDN) for a given ambient temperature and thermal porperty of the system. For pulse durations t < 200 µs, the device can source or
sink current of at least 500 mA across the recommended operating conditions. For YAH (DSBGA) package, this parameter is specified
by design and characterization.
VTHH (min) = 5 V + (11/18) [V(L+) - 8 V]
VTHH (max) = 6.5 V + (13/18) [V(L+) - 8 V]
VTHL (min) = 4 V + (8/18) [V(L+) -8 V]
VTHL (max) = 6 V + (11/18) [V(L+) -8 V]
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6.7 Switching Characteristics
Over recommended operating conditions and recommended free-air temperature range (unless otherwise noted). Typical
values are at L+ = 24 V, VVCC_IN = 3.3 V, VVCC_OUT = 3.3 V and TA = 25 ℃ unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
600
1200
ns
DRIVER
tPLH, tPHL
Driver propagation delay
tP(skew)
Driver propagation delay skew.
|tPLH - tPHL |
tPZH, tPZL
Driver enable delay
tPHZ, tPLZ
Driver disable delay
tr, tf
Driver output rise, fall time
|tr – tf|
Difference in rise and fall time
tWU1
Wake-up recognition begin
tWU2
Wake-up recognition end
tpWAKE
Wake-up output delay
tSC
Current fault blanking time
tpSC
Current fault indication delay
tWUL
Wake output pulse duration on
wake detection in EN=L mode
tSCEN
Current fault driver re-enable
wait time
t(UVLO)
(1)
CQ re-enable delay after UVLO
See Figure 7-1
See Figure 7-2
See Figure 7-3
RL = 2 kΩ
CL = 5 nF
R(SET) = 10 kΩ
75
200
ns
4
µs
4
µs
700
ns
50
60
75
µs
85
100
145
µs
150
µs
See Figure 7-5
175
See Figure 7-6
ns
45
175
200
225
µs
280
µs
285
µs
15
V(UVLO) rising threshold crossing time to
CQ enable time
10
30
ms
50
ms
250
ns
300
ns
RECEIVER
tND
Noise suppression time (2)
tPLH, tPHL
Receiver propagation delay
(1)
(2)
8
See Figure 7-4 15-pF load on RX,
150
CQ output remains Hi-Z for this time
Noise suppression time is defined as the permissible duration of a receive signal above/below the detection threshold without detection
taking place.
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2.6
0.9
2.4
0.8
EN=L
EN=H
2.2
2
1.8
1.6
1.4
1.2
Driver Residual Voltage (V)
L+ Supply Current (mA)
6.8 Typical Characteristics
0.7
0.6
0.5
0.4
0.3
0.2
0.1
1
0
0.8
9
12
15
18 21 24 27 30
L+ Supply Voltage (V)
No Load
33
36
TX = Open
TA = 25°C
Figure 6-1. Supply Current vs Supply Voltage
0.9
TA = -40 C
TA = 25 C
TA = 125 C
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
25
50
75
100 125 150 175
Load Current (mA)
200
225
0
39
250
spacer
Figure 6-3. Residual Voltage vs Load Current:
Low Side
25
50
75
100 125 150 175
Load Current (mA)
200
225
250
spacer
Figure 6-2. Residual Voltage vs Load Current:
High Side
Driver Current Limit (mA), High-side and Low-side
6
Driver Residual Voltage (V)
TA = -40 C
TA = 25 C
TA = 125 C
800
Min
Typ
Max
700
600
For RSET below 5 k, TIOL112(x) can
generate wake-up pulse and
enables CQ load discharge current (I LLM)
500
400
300
200
100
0
0
10
20
30
40
50
60
RSET (k)
70
80
90
100 110
For RSET in the 0-5 kΩ range, TIOL112(x) can source/sink
500 mA required for wake-up pulse generation in IO-link
applications. For RSET in the 0-5 kΩ range, TIOL112(x) also
activates a pull-down current source (ILLM) when the driver
is disabled. Min and max curves specified by design and
characterization across temperature and process variation.
TA = 25°C (typ curve)
Figure 6-4. Current Limit vs RSET
14
VTHH
VTHL
13
Driver Current Limit (mA)
Receiver Threshold (V)
12
11
10
9
8
7
6
5
800
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
TIOL111
TIOL112
0
4
7
11
15
19
23
27
31
10
20
30
35
L+ (V)
40
50
60
RSET (k)
70
80
90
100 110
TA = 25°C
TA = 25°C
Figure 6-5. Receiver Threshold Boundaries
Figure 6-6. Current limit vs RSET:
TIOL112(x) vs TIOL111(x)
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7 Parameter Measurement Information
L+
RL
TX
CQ
RL
CL
EN
Copyright © 2016, Texas Instruments Incorporated
Figure 7-1. Test Circuit for Driver Switching
VOH
TX
VOH
80%
50%
tPHL
80%
CQ
tPLH
CQ
VOH
CQ
50%
20%
20%
VOL
VOL
VOL
tr
tf
Figure 7-2. Waveforms for Driver Output Switching Measurements
TX = LOW
TX = HIGH
EN
50%
EN
tPZL
tPLZ
50%
tPZH
tPHZ
V(L+) / 2
VOH
80%
CQ
50%
CQ
50%
20%
VOL
V(L+) / 2
Figure 7-3. Waveforms for Driver Enable or Disable Time Measurements
CQ
50%
tPLH
RX
tPHL
50%
Figure 7-4. Receiver Switching Measurements
10
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< tWU1
CQ
CQ
RX
CQ
tWU1 < t < tWU2
RX
high
WAKE
> tSC
RX
WAKE
high
WAKE
tpWAKE
NFAULT
high
NFAULT
NFAULT
tpSC
high
EN
high
EN
high
EN
low
a) Over-current due to transient
b) Valid Wake-up pulse
c) Over-current due to fault condition
Figure 7-5. Overcurrent and Wake Conditions for EN = H and ILIM_ADJ = 10 kΩ to 110 kΩ,
TX = H (Full Lines); and TX = L (Red Dotted Lines)
low
EN=L
75 s < t < 85 s
CQ
RX
tWUL
WAKE
tpWAKE
high
NFAULT
Figure 7-6. Wake Conditions for EN = L, RX = H (Full Lines); and RX = L (Red Dotted Lines)
< tWU1
CQ
RX
WAKE
tWU1 < t < tWU2
CQ
RX
high
> tSC
CQ
RX
WAKE
WAKE
high
tpWAKE
NFAULT
NFAULT
tpF1
tpF2
a) Over-current due to transient
NFAULT
tpF1
tpF2
b) Valid Wake-up pulse
tpF1
tpF2
c) Over-current due to fault condition
Figure 7-7. Overcurrent and Wake Conditions for EN = H and ILIM_ADJ is floating, TX = H (Full Lines);
and TX = L (Red Dotted Lines)
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8 Detailed Description
8.1 Overview
Figure 8-1 shows that the TIOL112 or TIOL112x driver output (CQ) can be used in either push-pull, high-side,
or low-side configuration using the enable (EN) and transmit data (TX) input pins. The internal receiver converts
the 24-V signal on the CQ line to standard logic levels on the receive data (RX) pin. A simple parallel interface is
used to receive/transmit data and status information between the device and the local controller.
These devices have integrated IEC 61000-4-4/5 EFT and surge protection. In addition, tolerance to ±70-V
transients enables flexibility to choose from a wider range of TVS diodes if an application requires higher levels
of protection. These integrated robustness features will simplify the system level design by reducing external
protection circuitry.
TIOL112 or TIOL112x transceivers implement protection features for overcurrent, overvoltage and overtemperature conditions. The devices also provide a current-limit setting of the driver output current using an
external resistor.
The devices derive the low-voltage supply from the IO-Link L+ voltage (24 V nominal) via an internal linear
regulator to provide power to the local controller and sensor circuitry.
8.2 Functional Block Diagrams
Rev.
Polarity
Protection
VCC_IN
ESD and
Surge
Protection
TX
WAKE
CONTRO
L LOGIC
RX
EN
L+
CQ
DIAGNOSTICS
& CONTROL
Rev. Polarity
Protection
ESD and
Surge
Protection
NFAULT
CUR_OK
TMP_OK
PWR_OK
L-
ILIM_ADJ
Figure 8-1. Block Diagram TIOL112
12
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VSEL (YAH package only)
VOLTAGE
REGULATOR
VCC_OUT
Rev.
Polarity
Protection
ESD and
Surge
Protection
TX
WAKE
CONTRO
L LOGIC
RX
EN
L+
CQ
DIAGNOSTICS
& CONTROL
Rev. Polarity
Protection
ESD and
Surge
Protection
NFAULT
CUR_OK
TMP_OK
PWR_OK
L-
ILIM_ADJ
Figure 8-2. Block Diagram TIOL1123(L), TIOL1125
8.3 Feature Description
8.3.1 Wake-Up Detection
The TIOL112(x) may be operated in IO-Link mode or Standard Input / Output (SIO) mode. If the device is
in SIO mode and the IO-link master node wants to initiate communication with the device node, the master
drives the CQ line to the opposite of its present state, and will either sink or source the current (≥ 500 mA) for
the wake-up duration (typically 80 μs) depending on the CQ logic level as per the IO-Link specification. The
TIOL112(x) detects this as a wake-up condition and communicates to the local microcontroller via the WAKE pin.
The IO-Link communication specification requires the device node to switch to receive mode within 500 μs after
receiving the wake-up signal.
For overcurrent conditions shorter or longer than a valid wake-up pulse, the WAKE pin remains in a highimpedance (inactive) state. This is illustrated in Figure 7-5.
If the driver of TIOL112(x) is disabled (EN = L), any change in CQ logic level for duration tWU1 < t < tWU2 is
detected as a wake-up event and WAKE asserts low for the duration of tWUL. This is illustrated in Figure 7-6.
Please refer to Table 8-4 for the summary of the conditions for Wake-Up detection.
8.3.2 Current Limit Configuration
The output current can be configured with an external resistor on ILIM_ADJ pin. The highest current limit setting
with an external resistor of 10 kΩ provides a minimum of 300 mA over the operating temperature and voltage
range.
Output disable due to current fault and current fault auto recovery features can be disabled by floating ILIM_ADJ
pin. However, the current fault indication is still active in this configuration. This feature is useful when driving
large capacitances.
When ILIM_ADJ pin is shorted to ground, the TIOL112(x) is configured to be in the IO-link master mode. In this
mode, the TIOL112(x) can source or sink minimum of 500 mA to generate a wake-up request. In addition, the
TIOL112(x) enables a small current sink of 5 mA (minimum). The current fault indication, output disable, and
auto recovery features are disabled in this mode.
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Table 8-1. Current Limit Configuration
ILIM_ADJ Pin Condition
CQ Current Limit
(Min.)
NFAULT Indication During
Current Fault
Output Disable and Auto
Recovery
RSET resistor to L(10 kΩ to 110 kΩ)
Variable
(35 mA to 300 mA)
Yes
Yes
Connected to L(RSET 0 to 5 kΩ)
500 mA
No
No
OPEN
260 mA
Yes
No
8.3.3 Current Fault Detection, Indication and Auto Recovery
If the output current at CQ exceeds the internally-set current limit IO(LIM) for a duration longer than tSC, the
NFAULT pin is driven logic low to indicate a fault condition. The output is turned off, but the LDO continues to
function. The output periodically retries to check if the output is still in the over current condition. In this mode,
the output is switched on for tSC in tSCEN intervals. Current fault auto recovery mode can be disabled by setting
ILIM_ADJ = OPEN. See Table 8-5. Toggling EN will clear NFAULT.
8.3.4 Thermal Warning, Thermal Shutdown
If the die temperature exceeds T(WRN), the NFAULT flag is held low indicating a potential over temperature
problem. When the TJ exceeds T(SDN), The output is disabled but the LDO remains operational. As soon as the
temperature drops below the temperature threshold (and after T(HYS)), the internal circuit re-enables the driver,
subject to the state of the EN and TX pins.
8.3.5 Fault Reporting (NFAULT)
NFAULT is driven low if either a current fault condition is detected, die temperature has exceeded T(WRN) or
supply has dropped below the UVLO threshold. NFAULT returns to high-impedance as soon as all three fault
conditions clear.
Receive
Only-Wake
CUR_OK = Z
WAKE = L for tWUL
Driver = OFF
LDO = ON
th
wid 2
U
lse
pu t < t W
CQ
<
1
t WU
Receive
Only
CUR_OK = Z
WAKE = Z
Driver = OFF
LDO = ON
EN
UL
t>t W
*
EN
Wake
WAKE = L
CUR_OK = Z
Driver = ON
LDO = ON
*
Receive and
Transmit
CUR_OK = Z
WAKE = Z
Driver = ON
LDO = ON
CQ @ ILIM
for tWU1 < t < tWU2
N
*
Thermal
Shutdown
CUR_OK = Z
TMP_OK = L
WAKE = Z
Driver = OFF
LDO = ON
@
ILIM
t>
tS
C
T > TWRN
T < TWRN
& Current Fault
Current
Fault
WAKE = Z
CUR_OK = L
Driver = OFF
LDO=ON
CQ NOT @ ILIM
T
for
N
&E
t = tSCEN
T < (TSD + THYS)
T<
N
WR
CQ @ ILIM
RN
EN
&
RN
TW
CQ
T<
T>
TW
T > TWRN
*
T > TSD
for t > tSC
EN
Thermal
Warning
CUR_OK = Z
TMP_OK = L
WAKE = Z
Driver = EN/EN*
LDO = ON
T WR
CQ @ ILIM
T>
Current
Fault Recovery
WAKE = Z
CUR_OK = L
Driver = ON for tsc
LDO=ON
Note: NFAULT = [CUR_OK && PWR_OK && TMP_OK]
Figure 8-3. Device State Diagram
14
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8.3.6 Transceiver Function Tables
Table 8-2. Driver Function
EN
TX
CQ
COMMENT
L / Open
X
Hi-Z
H
L
H
CQ is sourcing current (high-side drive)
H
H / Open
L
CQ is sinking current (low-side drive)
Device is in ready-to-receive state
Table 8-3. Receiver Function
CQ VOLTAGE
RX
COMMENT
V(CQ) < V(THL)
H
Normal receive mode, input low
V(THL) < V(CQ) < V(THH)
?
Indeterminate output, may be either high or low
V(THH) < V(CQ)
L
Normal receive mode, input high
Open
?
Indeterminate output, may be either high or low
Table 8-4. Wake-Up Function (tWU1 < t < tWU2)
EN
TX
CQ CURRENT
WAKE
COMMENT
L / Open
X
X
Asserts low for
tWUL
Device asserts low for tWUL if RX output changes highto-low or low-to-high for tWU1 < t < tWU2
H
H / Open
| I(CQ) | ≥ 500 mA
L
Device receives high-level wake-up request over the
IO-Link bus
H
L
| I(CQ) | ≥ 500 mA
L
Device receives low-level wake-up request over the
IO-Link bus
EN
TX
Table 8-5. Current Limit Indicator Function (t > tSC)
H
H / Open
H
L
L / Open
X
CQ CURRENT
NFAULT
| I(CQ) | > IO(LIM)
L
CQ current exceeds the set limit for over tSC
COMMENT
| I(CQ) | < IO(LIM)
Z
Normal operation
| I(CQ) | > IO(LIM)
L
CQ current exceeds the set limit for over tSC
| I(CQ) | < IO(LIM)
Z
Normal operation
X
Z
Driver is disabled, Current limit indicator is inactive
Note
Current limit indicator function is disabled when ILIM_ADJ is connected to GND (or RSET < 5 kΩ
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8.3.7 The Integrated Voltage Regulator (LDO)
The TIOL1123 and TIOL1125 each have an integrated linear voltage regulator (LDO) which can supply power to
external components. The voltage regulator is specified for L+ voltages in the range of 7 V to 36 V with respect
to L-. The LDO is capable of delivering up to 20 mA.
In the DSBGA (YAH) package, TIOL1123L offers pin-configurable LDO output via VSEL pin. When VSEL is
connected to GND, VCC_OUT is configured to provide a 5-V output. When VSEL is left floating, VCC_OUT
provides a 3.3-V output.
Table 8-6. LDO Output Configuration via VSEL pin (YAH Package)
VSEL pin connection
VCC_OUT
Connected to L-
5V
Floating
3.3 V
The LDO is designed to be stable with standard ceramic capacitors with values of 1 μF or larger at the
output. X5R- and X7R-type capacitors are best because they have minimal variation in value and ESR over
temperature. Maximum ESR should be less than 1 Ω. With tolerance and dc bias effects, the minimum
capacitance for stability is 1 μF.
The voltage regulator has an internal 35-mA current limit to protect against initial start-up inrush current due to
large decoupling capacitors and accidental short circuit conditions.
16
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8.3.8 Reverse Polarity Protection
Reverse polarity protection circuitry protects the devices against accidental reverse polarity connections to the
L+, CQ and L- pins. The maximum voltage between any of the pins may not exceed 65 V DC at any time.
Figure 8-4 and Figure 8-5 shows all the possible connection combinations.
L+
L+
DC
CQ
TIOL112(x)
DC
CQ
TIOL112(x)
RL
L-
L-
RL
Reverse Polarity Protected
Fault Condion
Correct
Conguraon
L+
L+
DC
CQ
DC
CQ
TIOL112(x)
TIOL112(x)
RL
L-
L-
Reverse Polarity Protected
Fault Condion
RL
Reverse Polarity Protected
Fault Condion
L+
L+
DC
CQ
TIOL112(x)
DC
CQ
TIOL112(x)
RL
L-
Reverse Polarity Protected
Fault Condion
L-
RL
Reverse Polarity Protected
Fault Condi on
Figure 8-4. High-Side Driver Configuration
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L+
L+
DC
CQ
TIOL112(x)
DC
CQ
TIOL112(x)
L-
RL
L-
RL
Reverse Polarity Protected
Fault Condion
Correct
Conguraon
L+
L+
DC
CQ
DC
CQ
TIOL112(x)
TIOL112(x)
L-
RL
L-
Reverse Polarity Protected
Fault Condion
RL
Reverse Polarity Protected
Fault Condion
L+
L+
DC
CQ
TIOL112(x)
DC
CQ
TIOL112(x)
L-
RL
Overcurrent Fault
Protecon Condion
L-
RL
Reverse Polarity Protected
Fault Condi on
Figure 8-5. Low-Side Driver Configuration
18
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8.3.9 Integrated Surge Protection and Transient Waveform Tolerance
The L+ and CQ pins of the device are capable of withstanding up to 1.2 kV of 1.2/50 – 8/20 μs IEC 61000-4-5
surge with a source impedance of 500 Ω. The surge testing should be performed with a minimum 100 nF supply
decoupling capacitor between L+ and L-, and 1 µF between VCC_IN/OUT and L-.
External TVS diodes may be required for higher transient protection levels. The system designer should make
sure the maximum clamping voltage of the external diodes is < 65 V at the desired current level. The device is
capable of withstanding up to ±70-V transient pulses < 100 µs.
Combination
R
wave
Generator
Protection
Equipment
Auxiliary
Equipment
EUT
L+
CQ
Decoupling
> 100 nF
Network
L-
1.2/50 – 8/20 µs CWG
R = 500 Ω
Figure 8-6. Surge Test Setup
8.3.10 Power Up Sequence (TIOL112)
VCC_IN and L+ domains can be powered up in any sequence. In the event of L+ is powered and VCC_IN is not,
the CQ pin will remain in high impedance.
8.3.11 Undervoltage Lock-Out (UVLO)
The device enters UVLO if the L+ voltage falls below V(UVLO). (For the device without the integrated LDO, the
device monitors VCC_IN in addition to L+. UVLO happens if either supply falls below the threshold.)
As soon as the supply falls below V(UVLO), NFAULT is pulled low, and the driver (CQ) is disabled (Hi-Z). Receiver
performance is not specified in this mode.
When the supply rises above V(UVLO), NFAULT returns to Hi-Z (given no other fault conditions present). The CQ
output is turned on after t(UVLO) delay.
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8.4 Device Functional Modes
These devices can operate in three different modes.
8.4.1 NPN Configuration (N-Switch SIO Mode)
Set TX pin high (or open) and use EN pin as control for realizing the function of an N-switch (low-side
configuration) on CQ.
8.4.2 PNP Configuration (P-Switch SIO Mode)
Set TX pin low and use EN pin as control for realizing the function of a P-switch (high-side configuration) on CQ.
8.4.3 Push-Pull, Communication Mode
Set EN pin high and toggle TX as control for realizing the function of a push-pull output on CQ. Table 8-7, Table
8-8 and Table 8-9 summarize the pin configurations to accomplish the functional modes.
Table 8-7. NPN Mode
EN
TX
CQ
L / Open
H / Open
Hi-Z
H
H / Open
N-Switch
Table 8-8. PNP Mode
EN
TX
CQ
L / Open
L
Hi-Z
H
L
P-Switch
Table 8-9. Push-Pull, Communication Mode
EN
20
TX
CQ
L / Open
X
Hi-Z
H
H
N-Switch
H
L
P-Switch
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
When TIOL112(x) is connected to an IO-Link master through a three-wire interface (Figure 9-1), the master can
initiate communication and exchange data with a remote node with the TIOL112(x) IO-Link transceiver acting as
a complete physical layer for the communication.
9.2 Typical Application
VCC_OUT
1 µF
10 V
VOLTAGE
REGULATOR
0.1 µF
100 V
10 k
ESD and
Surge
Protection
RX
TX
Microcontroller
EN
WAKE
CONTRO
L LOGIC
10 k
Sensor
Front-End
L+
Rev.
Polarity
Protection
CQ
DIAGNOSTICS
& CONTROL
IO-Link Master
PHY
Rev. Polarity
Protection
ESD and
Surge
Protection
NFAULT
CUR_OK
TMP_OK
PWR_OK
L-
ILIM_ADJ
Figure 9-1. Typical Application Schematic
9.2.1 Design Requirements
TIOL112 and TIOL112x IO-Link transceivers can be used to communicate using the IO-Link protocol, or
as standard digital outputs to either sense or drive a wide range of sensors and loads. Table 9-1 shows
recommended components for a typical system design.
Table 9-1. Design Parameters
PARAMETERS
Design Requirement
TIOL112(x) Specification
Input voltage range (L+)
24 V (typ), 30 V (max)
7 V to 36 V
Output current (CQ)
200 mA
Choose 250 mA limit with RSET =
27 kΩ
LDO Output voltage
5V
Choose TIOL1125; VCC_OUT =
5V
LDO output current
5 mA
I(VCC_OUT): Up to 20 mA
Pull-up resistors for NFAULT and
WAKE
10 kΩ
10 kΩ
L+ decoupling capacitor
0.1 µF / 100 V
0.1 µF / 100 V
LDO output capacitor
1 µF / 10 V
1 µF / 10 V
105 °C
TIOL112 can support up to TA of
125 °C if TJ < T(SDN)
Maximum Ambient Temperature,
TA
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9.2.2 Detailed Design Procedure
9.2.2.1 Maximum Junction Temperature Check
For a 200 mA current limit:
• Choose driver output current limit, IO(LIM) = 250 mA (allowing for current limit tolerance); RSET = 27 kΩ
• The maximum voltage drop across the high-side switch at 250 mA current is VDS(ON) = 1.1 V.
This causes a power consumption of:
PDOP = VDS ON × IO LIM = 1.1 V × 250 mA = 275 mW
(1)
PDLDO = VL + − VVCCOUT × IVCC_OUT = 30 − 5 V × 5 mA = 125 mW
(2)
PD = PDLDO + PDOP = 275 mW + 125 mW = 400 mW
(3)
∆ T = T J − TA = PD × θ JA = 400 mW × 45.9 ℃ W = 18.36 ℃
(4)
T J = TA + ∆ T = TA + PD × θ JA = 105 ℃ + 400 mW × 45.9 ℃ W = 105 ℃ + 18.36 ℃ = 123.36 ℃
(5)
For a 5 mA LDO current output,
Total power dissipation,
Multiply this value with the Junction-to-ambient thermal resistance of θJA = 45.9 °C/W (taken from the Thermal
Information table table) to receive the difference between junction temperature, TJ, and ambient temperature, TA:
Add this value to the maximum ambient temperature of TA = 105°C to receive the final junction temperature:
As long as TJ is below the recommended maximum value of 150°C, no thermal shutdown will occur. However,
the junction temperature is closer to TWRN and thermal warning may be generated if the junction temperature
rises above TWRN.
Note that the modeling of the complete system may be necessary to predict junction temperature in smaller
PCBs and/or enclosures without air flow.
9.2.2.2 Driving Capacitive Loads
These devices are capable of driving capacitive loads on the CQ output. Assuming a pure capacitive load
without series/parallel resistance, the maximum capacitance that can be charged without triggering current fault
can be calculated as:
CLOAD
[IO LIM x t SC ]
VL
(6)
To drive higher capacitive loads and avoid overcurrent condition disabling the driver, it is recommended leave
ILIM_ADJ pin floating. With ILIM_ADJ floating, TIOL112(x) indicates overcurrent fault without blanking time delay
(tSC) but does not disable the driver. Another approach is to drive high capacitive loads with a series resistor
between the CQ output and the load to avoid overcurrent condition. Capacitive loads can be connected to L- or
L+.
9.2.2.3 Driving Inductive Loads
The TIOL112(x) family is capable of magnetizing and demagnetizing large inductive loads. These devices
contain internal circuitry that enables fast and safe demagnetization when configured as either P-switch or
N-switch mode.
22
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In P-switch configuration, the load inductor L is magnetized when the CQ output is driven high. When the PNP
is turned off, there is a significant amount of negative inductive kick back at the CQ pin. This voltage is safely
clamped internally at about -15 V.
Similarly, in N-switch configuration, the load inductor L is magnetized when the CQ output is driven low. When
the NPN is turned off, there is a significant amount of positive inductive kick back at the CQ pin. This voltage is
safely clamped internally at about 15 V.
The equivalent protection circuits are shown in Figure 9-2 and Figure 9-3. The minimum value of the resistive
load R can be calculated as:
R
VL
IO( LIM )
(7)
Rev.
Polarity
Protection
ESD and
Surge
Protection
Rev. Polarity
Protection
Rev.
Polarity
Protection
L+
ESD and
Surge
Protection
CQ
L
ESD and
Surge
Protection
Rev. Polarity
Protection
R
L-
L+
R
CQ
L
ESD and
Surge
Protection
L-
Figure 9-2. P-Switch Mode
Figure 9-3. N-Switch Mode
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4 V/div
4 V/div
300 mA/div
300 mA/div
6 V/div
6 V/div
9.2.3 Application Curves
Time 10 ms/div
Time 10 ms/div
Figure 9-4. CQ in Current Fault Auto Recovery,
Low Side Mode
L+ = 36 V
L = 1.5 H RL =
360 Ω
RSET = 10 kΩ
TA = 25 °C
Figure 9-6. CQ Driving Inductive Load, Low Side
Mode (NPN mode)
Figure 9-5. CQ in Current Fault Auto Recovery,
High Side Mode
L+ = 36 V
L=1.5 H RL =
360 Ω
RSET = 10 kΩ
TA = 25 °C
Figure 9-7. CQ Driving Inductive Load, High Side
Mode (PNP mode)
NFAULT is indicated for the duration of charging and discharging of the capacitor but driver is not disabled when ILIM_ADJ is floating
L+ = 24 V
CL = 20 µF RL = 100 Ω
RSET = 1 MΩ (ILIM_ADJ Floating)
TA = 25 °C
Figure 9-8. CQ Driving Capacitive Load, Push-Pull Mode
9.3 Power Supply Recommendations
The TIOL112 and TIOL112x transceivers are designed to operate from a 24-V nominal supply at L+, which can
vary by +12 V and -17 V from the nominal value to remain within the device recommended supply voltage range
of 7 V to 36 V. This supply should be buffered with at least a 100-nF/100-V capacitor.
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9.4 Layout
9.4.1 Layout Guidelines
•
•
•
•
•
•
•
•
Use of a 4-layer board is recommended for good heat conduction. Use layer 1 (top layer) for control signals,
layer 2 as power ground layer for L-, layer 3 for the 24-V supply plane (L+), and layer 4 for the regulated
output supply (VCC_IN/OUT).
Connect the thermal pad to L- with maximum amount of thermal vias for best thermal performance.
Use entire planes for L+, VCC_IN/OUT and L- to assure minimum inductance.
The L+ terminal must be decoupled to ground with a low-ESR ceramic decoupling capacitor. The
recommended minimum capacitor value is 100 nF. The capacitor must have a voltage rating of 50 V minimum
(100 V depending on max sensor supply fault rating) and an X5R or X7R dielectric.
The optimum placement of the capacitor is closest to the transceiver’s L+ and L- terminals to reduce supply
drops during large supply current loads. See Figure 9-9 for a PCB layout example.
Connect all open-drain control outputs via 10 kΩ pull-up resistors to the VCC_IN/OUT plane to provide a
defined voltage potential to the system controller inputs when the outputs are high-impedance.
Connect the RSET resistor between ILIM_ADJ and L-.
Decouple the regulated output voltage at VCC_IN/OUT to ground with a low-ESR, ≥ 1-μF, ceramic decoupling
capacitor. The capacitor should have a voltage rating of 10 V minimum and an X5R or X7R dielectric.
9.4.2 Layout Example
VIA to Layer 2: Power Ground Plane (L-)
VIA to Layer 3: 24V Supply Plane (L+)
VIA to Layer 4: Regulated Supply Plane (VCC_IN/OUT)
WAKE
1uF/10V
N
_I
C
VC
100nF/
50V
U
/O
NFAULT
T
L+
RX
CQ
TX
L-
EN
ILIM_ADJ
L+
CQ
Exposed Thermal
Pad Area
RSET
L-
Use Multiple Vias
for L+ and L-
Figure 9-9. Layout Example
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10 Device and Documentation Support
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
YAH0012-C01
DSBGA - 0.4 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
C
0.4 MAX
SEATING PLANE
0.17
0.11
0.05 C
1 TYP
SYMM
D
C
SYMM
1.5
TYP
D: Max = 2.47 mm, Min = 2.43 mm
B
0.5
TYP
E: Max = 1.72 mm, Min = 1.68 mm
A
12X
0.015
0.25
0.21
C A B
1
2
3
0.5 TYP
4227086/A 09/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
YAH0012-C01
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
12X ( 0.23)
1
2
3
A
(0.5) TYP
B
SYMM
C
D
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 30X
0.05 MAX
0.05 MIN
METAL UNDER
SOLDER MASK
( 0.23)
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
( 0.23)
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4227086/A 09/2021
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
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EXAMPLE STENCIL DESIGN
YAH0012-C01
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
(R0.05) TYP
12X ( 0.25)
1
2
3
A
(0.5) TYP
B
SYMM
C
METAL
TYP
D
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.075 mm THICK STENCIL
SCALE: 30X
4227086/A 09/2021
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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PACKAGE OPTION ADDENDUM
www.ti.com
9-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TIOL1123DRCR
ACTIVE
VSON
DRC
10
5000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1123
Samples
TIOL1123LYAHR
ACTIVE
DSBGA
YAH
12
1500
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
T1123L
Samples
TIOL1125DRCR
ACTIVE
VSON
DRC
10
5000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1125
Samples
TIOL112DRCR
ACTIVE
VSON
DRC
10
5000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
112
Samples
TIOL112YAHR
ACTIVE
DSBGA
YAH
12
1500
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TL112
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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