TL061, TL061A, TL061B, TL062, TL062A, TL062B, TL064, TL064A, TL064B
SLOS078N – NOVEMBER 1978 – REVISED AUGUST 2023
TL06xx Low-Power JFET-Input Operational Amplifiers
1 Features
3 Description
•
•
•
The TL06x (TL061, TL062, and TL064) family of
industry-standard operational amplifiers (op amps)
mirror the TL07x and TL08x family of op amps with
lower power consumption. These devices provide
outstanding value for cost-sensitive applications,
featuring high input impedance, wide bandwidth,
high slew rate, and low input offset and input
bias currents. High ESD (1.5 kV, HBM), integrated
EMI and RF filters, and wide temperature operation
enable the TL06x devices to be used in rugged and
environmentally-demanding applications.
•
•
•
•
•
•
•
•
Very low power consumption
Typical supply current: 200 μA (per amplifier)
Wide common-mode and differential voltage
ranges
Low input bias and offset currents
Common-mode input voltage range
includes VCC+
Output short-circuit protection
High input impedance: JFET-input stage
Internal frequency compensation
Latch-up-free operation
High slew rate: 3.5 V/μs typical
On products compliant to MIL-PRF-38535,
all parameters are tested unless otherwise noted.
On all other products, production processing does
not necessarily include testing of all parameters.
Device Information
PART
NUMBER
CHANNEL
COUNT
PACKAGE(1)
PACKAGE SIZE(2)
D (SOIC, 8)
4.90 mm × 6.00 mm
P (PDIP, 8)
9.59 mm × 7.94 mm
2 Applications
PS (SO, 8)
6.20 mm × 7.80 mm
D (SOIC, 8)
4.90 mm × 6.00 mm
•
•
•
•
P (PDIP, 8)
9.59 mm × 7.94 mm
PS (SO, 8)
6.20 mm × 7.80 mm
JG (CDIP, 8)
9.58 mm × 7.62 mm
PW (TSSOP, 8)
3.00 mm × 6.40 mm
FK (LCCC, 20)
8.89 mm × 8.80 mm
D (SOIC, 14)
8.65 mm × 6.00 mm
J (CDIP, 14)
19.4 mm × 7.90 mm
N (PDIP, 14)
19.31 mm × 7.94 mm
NS (SO, 14)
10.20 mm × 7.80 mm
PW (TSSOP, 14)
5.00 mm × 6.40 mm
W (CFP, 14)
21.78 mm × 9.21 mm
FK (LCCC, 20)
8.89 mm × 8.80 mm
TL061x
Tablets
White goods
Personal electronics
Computers
Single
TL062x
Dual
TL064x
(1)
(2)
RG
Quad
For all available packages, see the orderable addendum at
the end of the data sheet.
The package size (length × width) is a nominal value and
includes pins, where applicable.
RF
R1
VOUT
VIN
C1
f-3 dB =
(
RF
VOUT
= 1+
RG
VIN
((
1
1 + sR1C1
1
2pR1C1
(
Single-Pole, Low-Pass Filter
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TL061, TL061A, TL061B, TL062, TL062A, TL062B, TL064, TL064A, TL064B
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SLOS078N – NOVEMBER 1978 – REVISED AUGUST 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information (TL061)...................................... 7
6.5 Thermal Information (TL062)...................................... 7
6.6 Thermal Information (TL064)...................................... 7
6.7 Electrical Characteristics for TL06xC and
TL06xxC........................................................................ 8
6.8 Electrical Characteristics for TL06xxC and TL06xI..... 9
6.9 Electrical Characteristics for TL06xM....................... 10
6.10 Operating Characteristics....................................... 10
Typical Characteristics.................................................... 11
7 Parameter Measurement Information.......................... 14
8 Detailed Description......................................................15
8.1 Overview................................................................... 15
8.2 Functional Block Diagram......................................... 15
8.3 Feature Description...................................................15
8.4 Device Functional Modes..........................................15
9 Applications and Implementation................................ 16
9.1 Application Information............................................. 16
9.2 Typical Applications.................................................. 16
9.3 System Examples..................................................... 17
9.4 Power Supply Recommendations.............................19
9.5 Layout....................................................................... 20
10 Device and Documentation Support..........................21
10.1 Documentation Support.......................................... 21
10.2 Support Resources................................................. 21
10.3 Trademarks............................................................. 21
10.4 Electrostatic Discharge Caution..............................21
10.5 Glossary..................................................................21
11 Mechanical, Packaging, and Orderable
Information.................................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision M (June 2023) to Revision N (August 2023)
Page
• Added typical specification for Unity-Gain Bandwidth in Electrical Characteristics for TL06xM ...................... 10
• Changed Equivalent Input Noise Voltage vs Frequency curve in Typical Characteristics section.................... 11
Changes from Revision L (May 2015) to Revision M (June 2023)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1
• Updated Device Information with package size and channel count, and reordered packages based on
channel count..................................................................................................................................................... 1
• Updated TL061 pinout diagram in Pin Configuration and Functions ................................................................. 4
• Changed Charged Device Model (CDM) ESD from 2 kV to 1.5 kV in ESD Ratings ..........................................6
• Added table note for input bias current and input offset current on Electrical Characteristics for TL06xC and
TL06xxC ............................................................................................................................................................ 8
• Added table note for input bias current and input offset current on Electrical Characteristics for TL06xxC and
TL06xI ................................................................................................................................................................9
• Changed name of Electrical Characteristics for TL06xM and TL064M to Electrical Characteristics for TL06xM
..........................................................................................................................................................................10
• Added table note for input bias current and input offset current on Electrical Characteristics for TL06xM ..... 10
• Changed typical input voltage noise density at 1 kHz from 42 nV/√Hz to 30 nV/√Hz ......................................10
• Updated description in Overview ..................................................................................................................... 15
• Updated image in Functional Block Diagram ...................................................................................................15
Changes from Revision K (January 2014) to Revision L (May 2015)
Page
• Added Applications ............................................................................................................................................1
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ............................................................................................................................................................... 1
2
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SLOS078N – NOVEMBER 1978 – REVISED AUGUST 2023
Changes from Revision J (September 2004) to Revision K (January 2014)
Page
• Updated document to new TI data sheet format - no specification changes......................................................1
• Deleted Ordering Information table.................................................................................................................... 1
• Updated Features with Military Disclaimer......................................................................................................... 1
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SLOS078N – NOVEMBER 1978 – REVISED AUGUST 2023
5 Pin Configuration and Functions
1OUT
1
8
VCC+
VCC+
1IN±
2
7
2OUT
6
OUT
1IN+
3
6
2IN±
5
NC
VCC±
4
5
2IN+
NC
1
8
NC
IN–
2
7
IN+
3
VCC–
4
Not to scale
Not to scale
Figure 5-1. TL061x D, P, and PS Package, 8-Pin
SOIC, PDIP, and SO (Top View)
12
4IN+
VCC+
4
11
VCC±
2IN+
5
10
2IN±
6
2OUT
7
NC
3
19
1IN+
VCC+
4IN±
20
13
NC
2
1
1IN±
1OUT
4OUT
2
14
NC
1
3
1OUT
Figure 5-2. TL062x D, JG, P, PS, and PW Package,
8-Pin SOIC, CDIP, PDIP, SO, and TSSOP (Top View)
5
17
2OUT
3IN+
NC
6
16
NC
9
3IN±
1IN+
7
15
2IN±
8
3OUT
NC
8
14
NC
13
1IN±
12
NC
11
18
10
4
9
NC
17
NC
VCC+
6
16
VCC±
NC
7
15
NC
2IN+
8
14
3IN+
3IN±
3OUT
NC
NC
2IN+
13
5
12
NC
11
4IN+
10
18
2OUT
NC
NC
4IN±
19
NC
1
4OUT
1OUT
2
20
1IN±
3
4
9
Not to scale
Figure 5-4. TL062 FK Package, 20-Pin LCCC (Top
View)
1IN+
2IN±
VCC±
Not to scale
Figure 5-3. TL064x D, J, N, NS, PW, and W
Package, 14-Pin SOIC, CDIP, PDIP, SO, TSSOP and
CFP (Top View)
Not to scale
Figure 5-5. TL064 FK Package, 20-Pin LCCC (Top View)
4
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SLOS078N – NOVEMBER 1978 – REVISED AUGUST 2023
Table 5-1. Pin Functions
PIN
TL061
NAME
TL062
D, P, PS
D, JG, P, PS,
PW
1IN–
—
1IN+
—
1OUT
—
2IN–
—
2IN+
2OUT
TL064
TYPE(1)
DESCRIPTION
FK
D, J, N, NS,
PW, W
FK
2
5
2
3
I
Negative input
3
7
3
4
I
Positive input
1
2
1
2
O
Output
6
15
6
9
I
Negative input
—
5
12
5
8
I
Positive input
—
7
17
7
10
O
Output
3IN–
—
—
—
9
13
I
Negative input
3IN+
—
—
—
10
14
I
Positive input
3OUT
—
—
—
8
12
O
Output
4IN–
—
—
—
13
19
I
Negative input
4IN+
—
—
—
12
18
I
Positive input
4OUT
—
—
—
14
20
O
Output
IN–
2
—
—
—
—
I
Negative input
IN+
3
—
—
—
—
I
Positive input
1
1
3
4
5
6
8
NC
8
—
9
11
7
—
—
Do not connect
11
13
14
15
16
18
17
19
OFFSET N1
1
—
—
—
—
—
Input offset adjustment
OFFSET N2
5
—
—
—
—
—
Input offset adjustment
OUT
6
—
—
—
—
O
Output
VCC–
4
4
10
11
16
—
Power supply
VCC+
7
8
20
4
6
—
Power supply
(1)
I = input, O = output
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SLOS078N – NOVEMBER 1978 – REVISED AUGUST 2023
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
VCC+
VI
Input
voltage(2) (4)
Duration of output short circuit(5)
TJ
(2)
(3)
(4)
(5)
±30
V
±15
V
Unlimited
Operating virtual junction temperature
Tstg
V
–18
Differential input voltage(3)
VID
UNIT
18
Supply voltage(2)
VCC–
(1)
MAX
150
°C
Case temperature for 60 seconds
FK package
260
°C
Lead temperature 1.6 mm (1/16 inch) from
case for 60 seconds
J, JG, U, or W package
300
°C
Lead temperature 1.6 mm (1/16 inch) from
case for 10 seconds
D, N, NS, P, PS, or PW package
260
°C
150
°C
Storage temperature
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC−.
Differential voltages are at IN+, with respect to IN−.
The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.
The output may be shorted to ground or to either supply. Temperature or supply voltages must be limited so that the dissipation rating
is not exceeded.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
2000
Charged-device model (CDM), per JEDEC specification JESD22C101(2)
1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
UNIT
VCC+
Supply voltage
5
15
V
VCC–
Supply voltage
–5
–15
V
VCM
Common-mode voltage
V
TA
Ambient temperature
VCC– + 4
VCC+ – 4
TL06xM
–55
125
TL06xQ
–40
125
TL06xI
–40
85
0
70
TL06xC
6
MAX
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SLOS078N – NOVEMBER 1978 – REVISED AUGUST 2023
6.4 Thermal Information (TL061)
TL061
THERMAL
METRIC(1)
D (SOIC)
P (PDIP)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance(2) (3)
97
85
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance(4) (5)
—
—
°C/W
(1)
(2)
(3)
(4)
(5)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/RθJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
The package thermal impedance is calculated in accordance with JESD 51-7.
Maximum power dissipation is a function of TJ(max), RθJC, and TC. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TC) / RθJC. Operating at the absolute maximum TJ of 150°C can affect reliability.
The package thermal impedance is calculated in accordance with MIL-STD-883.
6.5 Thermal Information (TL062)
TL062
THERMAL METRIC(1)
RθJA
Rθ
JC(top)
D (SOIC)
P (PDIP)
PS (SO)
PW
(TSSOP)
FK (LCCC) JG (CDIP)
UNIT
8 PINS
8 PINS
8 PINS
8 PINS
20 PINS
8 PINS
Junction-to-ambient thermal
resistance(2) (3)
97
85
95
149
—
—
°C/W
Junction-to-case (top) thermal
resistance(4) (5)
—
—
—
—
5.61
14.5
°C/W
UNIT
6.6 Thermal Information (TL064)
TL064
THERMAL METRIC(1)
RθJA
Rθ
JC(top)
(1)
(2)
(3)
D
(SOIC)
N (PDIP)
NS (SO)
PS (SO)
PW
(TSSOP)
FK
(LCCC)
J (CDIP)
W (CFP)
14 PINS
14 PINS
14 PINS
8 PINS
14 PINS
20 PINS
14 PINS
14 PINS
Junction-to-ambient thermal
resistance(2) (3)
86
80
76
95
113
—
—
—
°C/W
Junction-to-case (top) thermal
resistance(2) (3)
—
—
—
—
—
5.61
15.05
14.65
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Maximum power dissipation is a function of TJ(max), RθJC, and TC. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TC) / RθJC. Operating at the absolute maximum TJ of 150°C can affect reliability.
The package thermal impedance is calculated in accordance with MIL-STD-883.
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SLOS078N – NOVEMBER 1978 – REVISED AUGUST 2023
6.7 Electrical Characteristics for TL06xC and TL06xxC
VCC± = ±15 V, RL = 10 kΩ to (VCC+ + VCC–) / 2 (unless otherwise noted)
TEST CONDITIONS(1)
PARAMETER
MIN
Input offset voltage
VO = 0, RS = 50 Ω
αVIO
Temperature coefficient
of input offset voltage
VO = 0, RS = 50 Ω, TA = Full range
IIO (3)
Input offset current
VO = 0
IIB (3)
Input bias current(2)
VO = 0
TYP
MAX
3
15
TA = Full range
MIN
MAX
3
6
20
7.5
10
TA = 25°C
5
TA = Full range
10
200
5
5
TA = 25°C
30
TA = Full range
UNIT
TYP
400
30
10
nA
200
pA
7
nA
RL = 10 kΩ, TA = 25°C
±10
±13.5
RL ≥ 10 kΩ, TA = Full range
±10
AVD
Large-signal differential
voltage amplification
VO = ±10 V,
RL ≥ 2 kΩ
B1
Unity-gain bandwidth
RL = 10 kΩ, TA = 25°C
ri
Input resistance
TA = 25°C
CMRR
Common-mode
rejection ratio
VIC = VICRmin,
VO = 0, RS = 50 Ω, TA = 25°C
70
86
kSVR
Supply-voltage
rejection ratio
(ΔVCC±/ΔVIO)
VCC = ±9 V to ±15 V,
VO = 0, RS = 50 Ω, TA = 25°C
70
95
PD
Total power dissipation
(each amplifier)
VO = 0, No load, TA = 25°C
6
7.5
6
7.5
mW
ICC
Supply current
(each amplifier)
VO = 0, No load, TA = 25°C
200
250
200
250
µA
VO1/VO2
Crosstalk attenuation
AVD = 100, TA = 25°C
120
(2)
(3)
TA = 25°C
3
TA = Full range
3
±13.5
pA
3
Maximum peak output
voltage swing
VOM
±10
100
±11
Common-mode input
voltage range
±11
μV/°C
TA = 25°C
VICR
–12
to
15
mV
–12
to
15
(1)
8
TA = 25°C
VIO
TL061AC, TL062AC,
TL064AC
TL061C, TL062C, TL064C
V
V
±10
6
4
6
V/mV
4
1
1
1012
1012
Ω
80
86
dB
80
95
dB
120
MHz
dB
All characteristics are measured under open-loop conditions with zero common-mode input voltage unless otherwise specified. Full
range for TA is 0°C to 70°C for TL06xC, TL06xAC, and TL06xBC and –40°C to 85°C for TL06xI.
Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 6-12. Pulse techniques are used to maintain the junction temperature as close to the ambient temperature as
possible.
Specified by design and characterization; not production tested.
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SLOS078N – NOVEMBER 1978 – REVISED AUGUST 2023
6.8 Electrical Characteristics for TL06xxC and TL06xI
VCC± = ±15 V, RL = 10 kΩ to (VCC+ + VCC–) / 2 (unless otherwise noted)
TEST CONDITIONS(1)
PARAMETER
TL061BC, TL062BC,
TL064BC
MIN
TA = 25°C
VIO
Input offset voltage
VO = 0, RS = 50 Ω
αVIO
Temperature coefficient
of input offset voltage
VO = 0, RS = 50 Ω, TA = Full range
IIO (3)
Input offset current
VO = 0
IIB (3)
Input bias current(2)
VO = 0
TL061I, TL062I, TL064I
TYP
MAX
2
3
TA = Full range
MIN
MAX
3
6
5
9
10
TA = 25°C
5
TA = Full range
10
100
5
3
TA = 25°C
30
TA = Full range
UNIT
TYP
200
30
7
nA
200
pA
20
nA
Maximum peak output
voltage swing
RL = 10 kΩ, TA = 25°C
±10
±13.5
RL ≥ 10 kΩ, TA = Full range
±10
AVD
Large-signal differential
voltage amplification
VO = ±10 V,
RL ≥ 2 kΩ
B1
Unity-gain bandwidth
RL = 10 kΩ, TA = 25°C
ri
Input resistance
TA = 25°C
CMRR
Common-mode
rejection ratio
VIC = VICRmin,
VO = 0, RS = 50 Ω, TA = 25°C
80
86
kSVR
Supply-voltage
rejection ratio
(ΔVCC±/ΔVIO)
VCC = ±9 V to ±15 V,
VO = 0, RS = 50 Ω, TA = 25°C
80
95
PD
Total power dissipation
(each amplifier)
VO = 0, No load, TA = 25°C
6
7.5
6
7.5
mW
ICC
Supply current
(each amplifier)
VO = 0, No load, TA = 25°C
200
250
200
250
µA
VO1/VO2
Crosstalk attenuation
AVD = 100, TA = 25°C
120
(1)
(2)
(3)
TA = 25°C
4
TA = Full range
4
±13.5
pA
10
±11
VOM
±10
100
TA = 25°C
Common-mode input
voltage range
±11
μV/°C
–12
to
15
VICR
–12
to
15
mV
V
V
±10
6
4
6
V/mV
4
1
1
1012
1012
Ω
80
86
dB
80
95
dB
120
MHz
dB
All characteristics are measured under open-loop conditions with zero common-mode input voltage, unless otherwise specified. Full
range for TA is 0°C to 70°C for TL06xC, TL06xAC, and TL06xBC and –40°C to 85°C for TL06xI.
Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 6-12. Pulse techniques are used to maintain the junction temperature as close to the ambient temperature as
possible.
Assured by design and characterization; not production tested.
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SLOS078N – NOVEMBER 1978 – REVISED AUGUST 2023
6.9 Electrical Characteristics for TL06xM
VCC± = ±15 V, RL = 10 kΩ to (VCC+ + VCC–) / 2 (unless otherwise noted)
TEST CONDITIONS(2)
PARAMETER
TL061M, TL062M
MIN
MAX
3
6
TA = 25°C
VIO
Input offset voltage
VO = 0, RS = 50 Ω
αVIO
Temperature coefficient
of input offset voltage
VO = 0, RS = 50 Ω,
TA = –55°C to 125°C
IIO (4)
Input offset current
VO = 0
TA = –55°C to
125°C
VO = 0
TYP
MAX
3
9
15
10
5
10
100
5
20(1)
TA = 125°C
20
20
200
30
50(1)
50(1)
TA = 125°C
50
50
±11
–12
to
15
±11
–12
to
15
Maximum peak output
voltage swing
RL = 10 kΩ, TA = 25°C
±10
±13.5
±10
±13.5
RL ≥ 10 kΩ, TA = –55°C to 125°C
±10
AVD
Large-signal differential
voltage amplification
VO = ±10 V,
RL ≥ 2 kΩ
B1
Unity-gain bandwidth
RL = 10 kΩ, TA = 25°C
Common-mode input
voltage range
VOM
200
TA = –55°C
TA = 25°C
VICR
100
20(1)
30
TA = 25°C
4
TA = –55°C to
125°C
4
4
mV
pA
nA
pA
nA
V
V
±10
6
UNIT
μV/°C
TA = –55°C
TA = 25°C
Input bias current(3)
MIN
9
TA = 25°C
IIB (4)
TL064M
TYP
6
V/mV
4
1
1
1012
1012
MHz
Ω
ri
Input resistance
TA = 25°C
CMRR
Common-mode
rejection ratio
VIC = VICRmin,
VO = 0, RS = 50 Ω, TA = 25°C
80
86
80
86
dB
kSVR
Supply-voltage
rejection ratio
(ΔVCC±/ΔVIO)
VCC = ±9 V to ±15 V,
VO = 0, RS = 50 Ω, TA = 25°C
80
95
80
95
dB
PD
Total power dissipation
(each amplifier)
VO = 0, No load, TA = 25°C
6
7.5
6
7.5
mW
ICC
Supply current
(each amplifier)
VO = 0, No load, TA = 25°C
200
250
200
250
µA
VO1/VO2
Crosstalk attenuation
AVD = 100, TA = 25°C
120
(1)
(2)
(3)
(4)
120
dB
This parameter is not production tested.
All characteristics are measured under open-loop conditions, with zero common-mode voltage, unless otherwise specified.
Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 6-12. Pulse techniques are used to maintain the junction temperature as close to the ambient temperature as
possible.
Specified by design and characterization; not production tested.
6.10 Operating Characteristics
VCC± = ±15 V, TA= 25°C, RL = 10 kΩ to (VCC+ + VCC–) / 2
PARAMETER
TEST CONDITIONS
SR
Slew rate at unity gain(1)
VI = 10 V,
RL = 10 kΩ,
CL = 100 pF,
see Figure 7-1
tr
Rise-time
Overshoot factor
VI = 20 V,
RL = 10 kΩ,
CL = 100 pF,
see Figure 7-1
Equivalent input noise voltage
RS = 20 Ω
f = 1 kHz
Vn
(1)
10
MIN
TYP
MAX
UNIT
1.5
3.5
V/μs
0.2
μs
10%
30
nV/√ Hz
Slew rate at –55°C to 125°C is 0.7 V/μs min.
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Typical Characteristics
Data at high and low temperatures are applicable only within the specified operating free-air temperature ranges of the
various devices.
±15
VOM − Maximum Peak Output Voltage − V
RL = 10 kΩ
TA = 25°C
See Figure 2
±12.5
±12.5
±10
±7.5
±5
±2.5
±10
±7.5
±5
±2.5
0
2
0
4
6
8
10
12
14
0
−75
16
VCC± = ±15 V
RL = 10 kΩ
See Figure 2
−50
|VCC±| − Supply Voltage − V
Figure 6-1. Maximum Peak Output Voltage vs Supply Voltage
VOM − Maximum Peak Output Voltage − V
VOM − Maximum Peak Output Voltage − V
VCC± = ±15 V
TA = 25°C
See Figure 2
±10
±7.5
±5
±2.5
25
50
75
100
125
VCC± = ±15 V
RL = 10 kΩ
TA = 25°C
See Figure 2
±12.5
VCC± = ±12 V
±10
±7.5
±5
VCC± = ±5 V
±2.5
0
0
100
200
400
700 1 k
2k
4k
1k
7 k 10 k
10 k
100 k
Figure 6-3. Maximum Peak Output Voltage vs Load Resistance
100
AVD − Large-Signal Differential
Voltage Amplification − V/mV
VCC± = ±15 V
RL = 10 kΩ
4
2
1
−75
10 M
Figure 6-4. Maximum Peak Output Voltage vs Frequency
10
7
1M
f − Frequency − Hz
RL − Load Resistance − Ω
AVD − Differential Voltage Amplification − V/mV
0
Figure 6-2. Maximum Peak Output Voltage vs Free-Air
Temperature
±15
±12.5
−25
TA − Free-Air Temperature − °C
VCC± = ±15 V
Rext = 0
RL = 10 kΩ
TA = 25°C
10
Phase Shift
(right scale)
1
−25
0
25
50
75 100
TA − Free-Air Temperature − °C
125
Figure 6-5. Differential Voltage Amplification vs Free-Air
Temperature
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45°
90°
0.1
AVD
(left scale)
0.01
135°
0.001
−50
0°
1
10
100
1k
Phase Shift
VOM − Maximum Peak Output Voltage − V
±15
10 k
100 k
1M
180°
10 M
f − Frequency − Hz
Figure 6-6. Large-Signal Differential Voltage Amplification and
Phase Shift vs Frequency
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Typical Characteristics (continued)
Data at high and low temperatures are applicable only within the specified operating free-air temperature ranges of the
various devices.
250
TA = 25°C
No Signal
No Load
200
I CC±
ICC − Supply Current − µA
I CC±
ICC − Supply Current − µA
250
150
100
50
200
150
100
50
0
−75
0
0
2
4
6
8
10
12
14
VCC± = ±15 V
No Signal
No Load
16
TA − Free-Air Temperature − °C
|VCC±| − Supply Voltage − V
Figure 6-8. Supply Current vs Free-Air Temperature
Figure 6-7. Supply Current vs Supply Voltage
87
CMRR − Common-Mode Rejection Ratio − dB
P
PD
D − Total Power Dissipation − mW
30
25
TL064
VCC± = ±15 V
No Signal
No Load
20
15
TL062
10
TL061
5
0
−75
−50
−25
0
25
50
75
100
VCC± = ±15 V
RL = 10 kΩ
86
85
84
83
82
81
−75
125
1.01
1.1
Slew Rate
(left scale)
1
0.7
−75
1
0.99
0.9
0.8
VCC± = ±15 V
RL = 10 kΩ
f = B1 for Phase Shift
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
0.98
0.97
125
Figure 6-11. Normalized Unity-Gain Bandwidth, Slew Rate, and
Phase Shift vs Free-Air Temperature
12
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25
50
75
100
125
VCC± = ±15 V
1.02
Phase Shift
(right scale)
IIB
IIB − Input Bias Current − nA
Unity-Gain Bandwidth
(left scale)
0
100
40
1.2
−25
Figure 6-10. All Except TL06_C Common-Mode Rejection Ratio
vs Free-Air Temperature
1.03
Normalized Phase Shift
Normalized Unity-Gain Bandwidth and Slew Rate
Figure 6-9. Total Power Dissipation vs Free-Air Temperature
1.3
−50
TA − Free-Air Temperature − °C
TA − Free-Air Temperature − °C
10
4
1
0.4
0.1
0.04
0.01
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
125
Figure 6-12. Input Bias Current vs Free-Air Temperature
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Typical Characteristics (continued)
Data at high and low temperatures are applicable only within the specified operating free-air temperature ranges of the
various devices.
28
6
Input
24
Overshoot
VO − Output Voltage − mV
Input and Output Voltages − V
4
2
0
Output
−2
VCC± = ±15 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
−4
−6
20
16
12
8
4
10%
VCC± = ±15 V
RL = 10 kΩ
TA = 25°C
0
tr
−4
0
2
4
6
t − Time − µs
8
0
10
Input Voltage Noise Spectral Density (nV/rHz)
Figure 6-13. Voltage-Follower Large-Signal Pulse Response vs
Time
0.2
0.4
0.6
0.8
1
t − Elapsed Time − µs
1.2
1.4
Figure 6-14. Output Voltage vs Elapsed Time
120
110
100
90
80
70
60
50
40
30
20
10
0
10
100
1k
Frequency (Hz)
10k
100k
C017
Figure 6-15. Equivalent Input Noise Voltage vs Frequency
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7 Parameter Measurement Information
10 kΩ
−
−
OUT
OUT
+
+
VI
1 kΩ
VI
RL
RL = 2 kΩ
CL = 100 pF
CL = 100 pF
Figure 7-2. Gain-of-10 Inverting Amplifier
Figure 7-1. Unity-Gain Amplifier
−
IN−
TL061
N2
+
IN+
OUT
N1
100 kΩ
1.5 kΩ
VCC−
Figure 7-3. Input Offset-Voltage Null Circuit
14
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8 Detailed Description
8.1 Overview
The TL06x (TL061, TL062, and TL064) family of industry-standard operational amplifiers (op amps) mirror the
TL07x and TL08x family of op amps with lower power consumption. These devices provide outstanding value for
cost-sensitive applications, featuring high input impedance, wide bandwidth, high slew rate, and low input offset
and input bias currents. High ESD (1.5 kV, HBM), integrated EMI and RF filters, and wide temperature operation
enable the TL06x devices to be used in rugged and environmentally-demanding applications.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from −40°C to 85°C, and the M-suffix devices are characterized for operation over the full military
temperature range of −55°C to 125°C.
8.2 Functional Block Diagram
V+
V
V
IN–
IN+
V
BIAS1
Class AB
Control
Circuitry
V
O
V
BIAS2
Reference
Current
V–
(Ground)
8.3 Feature Description
8.3.1 Common-Mode Rejection Ratio
The common-mode rejection ratio (CMRR) of an amplifier is a measure of how well the device rejects unwanted
input signals common to both input leads. It is found by taking the ratio of the change in input offset voltage to
the change in the input voltage and converting to decibels. Ideally the CMRR is infinite, but in practice, amplifiers
are designed to have it as high as possible. The CMRR of this device is 86 dB.
8.3.2 Slew Rate
The slew rate is the rate at which an operational amplifier can change its output when there is a change on the
input. These devices have a 3.5-V/μs slew rate.
8.4 Device Functional Modes
These devices are powered on when the supply is connected. This device can be operated as a single supply
operational amplifier or dual supply amplifier depending on the application.
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9 Applications and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TL06x series of operational amplifiers can be used in countless applications. The few applications in this
section show principles used in all applications of these parts.
9.2 Typical Applications
9.2.1 Inverting Amplifier Application
A typical application for an operational amplifier in an inverting amplifier. This amplifier takes a positive voltage
on the input, and makes it a negative voltage of the same magnitude. In the same manner, it also makes
negative voltages positive.
RF
RI
Vsup+
VOUT
VIN
+
Vsup-
Figure 9-1. Schematic for Inverting Amplifier Application
9.2.1.1 Design Requirements
The supply voltage must be chosen such that it is larger than the input voltage range and output range. For
instance, this application will scale a signal of ±0.5 V to ±1.8 V. Setting the supply at ±12 V is sufficient to
accommodate this application.
9.2.1.2 Detailed Design Procedure
Determine the gain required by the inverting amplifier:
AV = VOUT
VIN
(1)
1.8
AV = −0.5
= − 3.6
(2)
AV = − RF
RI
(3)
Once the desired gain is determined, choose a value for RI or RF. Choose a value in the kΩ range to limit
currents in the amplifier circuit to the mA range. This example will choose 10 kΩ for RI which means 36 kΩ will
be used for RF. This was determined by Equation 3.
16
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9.2.1.3 Application Curve
2
VIN
1.5
VOUT
1
Volts
0.5
0
-0.5
-1
-1.5
-2
0
0.5
1
Time (ms)
1.5
2
Figure 9-2. Input and Output Voltages of the Inverting Amplifier
9.3 System Examples
9.3.1 General Applications
RF = 100 kΩ
VCC+
10 kΩ
0.1%
−
15 V
3.3 kΩ
+
VCC+
VCC−
Output
TL061
−
Output
TL064
100 kΩ
+
VCC+
VCC+
+
100 kΩ
Input A
−
10 kΩ
0.1%
TL064
CF = 3.3 µF
1 kΩ
−15 V
1 MΩ
VCC−
Input B
+
−
TL064
10 kΩ
0.1%
−
TL064
10 kΩ
0.1%
3.3 kΩ
100 kΩ
1
f=
2π ´ RF ´ CF
+
100 kΩ
VCC−
VCC−
Figure 9-4. 0.5-Hz Square-Wave Oscillator
Figure 9-3. Instrumentation Amplifier
VCC+
−
1 MΩ
−
Output
+
R2
1 µF
TL064
+
VCC−
Input
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100 µF
VCC+
100 kΩ
VCC+
TL064
Output C
+
Figure 9-5. High-Q Notch Filter
100 kΩ
−
C3
C1 = C2 =
= 110 pF
2
1
fO =
= 1 kHz
2π ´ R1´ C1
Output B
+
C1
R1 = R2 = 2 ´ R3 = 1.5 MΩ
VCC+
TL064
100 kΩ
R3
C2
Output A
−
C3
−
R1
TL064
VCC+
TL061
VCC+
+
Input
9.1 kΩ
Figure 9-6. Audio-Distribution Amplifier
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VCC+
15 V
10 kΩ
10 kΩ
0.1 µF
10 kΩ
10 kΩ
+
100 pF
Output
TL061
10 kΩ
1 MΩ
−
TIL601
10 kΩ
Output
TL061
50 Ω
−
+
10 kΩ
N2
10 kΩ
5 kΩ
0.1 µF
10 kΩ
N1
250 kΩ
−15 V
Figure 9-7. Low-Level Light Detector Preamplifier
Figure 9-8. AC Amplifier
10 kΩ
100 kΩ
1 kΩ
IN+
0.1 µF
0.06 µF
+
TL061
−
1.2 MΩ
47 kΩ
+
TL062
−
0.06 µF
1 µF
10 kΩ
0.002 µF
100 kΩ
50 kΩ
1 kΩ
1 kΩ
2.7 kΩ
100 kΩ
270 Ω
0.003 µF
+
0.001 µF
10 kΩ
100 kΩ
100 kΩ
50 kΩ
20 µF
0.02 µF
IN−
Figure 9-9. Microphone Preamplifier With Tone
Control
18
Output
100 kΩ
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−
TL062
+
Figure 9-10. Instrumentation Amplifier
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IC PREAMPLIFIER RESPONSE CHARACTERISTICS
25
Max Bass
20
15
Voltage Amplification − dB
Max
Treble
VCC± = ±15 V
TA = 25°C
10
5
0
−5
−10
−15
−20
Min
Treble
Min Bass
−25
20
40
100 200 400
1k 2k
4k
10 k 20 k
f − Frequency − Hz
220 kΩ
0.00375 µF
0.003 µF
10 kΩ
0.03 µF
0.01 µF
27 kΩ
MIN
100 kΩ
Bass
MAX
VCC+
100 Ω
1 µF
Input
100 Ω
+
TL062
−
10 kΩ
3.3 kΩ
MIN
100 kΩ
Treble
MAX
VCC+
+
TL062
0.03 µF
VCC−
VCC−
0.003 µF
10 kΩ
Balance
10 pF
75 µF
47 kΩ
+
50 pF
Output
−
10 pF
5 kΩ
Gain
+
68 kΩ
47 µF
Figure 9-11. IC Preamplifier
9.4 Power Supply Recommendations
CAUTION
Supply voltages larger than 36 V for a single supply, or outside the range of ±18 V for a dual supply
can permanently damage the device (see the Absolute Maximum Ratings).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
section.
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9.5 Layout
9.5.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
•
•
•
•
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to
Circuit Board Layout Techniques.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it
is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed
to in parallel with the noisy trace.
Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Layout Examples.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
9.5.2 Layout Examples
RIN
VIN
+
VOUT
RG
RF
Figure 9-12. Operational Amplifier Schematic for Noninverting Configuration
Place components close to
device and to each other to
reduce parasitic errors
Run the input traces as far
away from the supply lines
as possible
RF
NC
NC
IN1í
VCC+
IN1+
OUT
VCCí
NC
VS+
Use low-ESR, ceramic
bypass capacitor
RG
GND
VIN
RIN
GND
Only needed for
dual-supply
operation
GND
VS(or GND for single supply)
VOUT
Ground (GND) plane on another layer
Figure 9-13. Operational Amplifier Board Layout for Noninverting Configuration
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10 Device and Documentation Support
10.1 Documentation Support
10.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Circuit Board Layout Techniques chapter extracts
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
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PACKAGE OPTION ADDENDUM
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2-Dec-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
81023022A
LIFEBUY
LCCC
FK
20
55
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
81023022A
TL062MFKB
8102302PA
ACTIVE
CDIP
JG
8
50
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8102302PA
TL062M
Samples
81023032A
ACTIVE
LCCC
FK
20
55
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
81023032A
TL064MFKB
Samples
8102303CA
ACTIVE
CDIP
J
14
25
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8102303CA
TL064MJB
Samples
8102303DA
ACTIVE
CFP
W
14
25
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8102303DA
TL064MWB
Samples
TL061ACD
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
061AC
TL061ACDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
061AC
Samples
TL061ACP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL061ACP
Samples
TL061BCP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL061BCP
Samples
TL061BCPE4
ACTIVE
PDIP
P
8
50
TBD
Call TI
Call TI
0 to 70
Samples
TL061CD
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL061C
TL061CDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL061C
Samples
TL061CP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL061CP
Samples
TL061CPSR
LIFEBUY
SO
PS
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T061
TL061ID
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL061I
TL061IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL061I
TL061IDRG4
ACTIVE
SOIC
D
8
2500
TBD
Call TI
Call TI
-40 to 85
TL061IP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
TL061IPE4
ACTIVE
PDIP
P
8
50
TBD
Call TI
Call TI
-40 to 85
TL062ACD
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
Addendum-Page 1
Samples
Samples
TL061IP
Samples
Samples
062AC
PACKAGE OPTION ADDENDUM
www.ti.com
2-Dec-2023
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TL062ACDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
062AC
Samples
TL062ACDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
062AC
Samples
TL062ACP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL062ACP
Samples
TL062ACPSR
LIFEBUY
SO
PS
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T062A
TL062BCD
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
062BC
TL062BCDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
062BC
Samples
TL062BCP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL062BCP
Samples
TL062CD
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL062C
TL062CDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL062C
Samples
TL062CDRE4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL062C
Samples
TL062CDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL062C
Samples
TL062CP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL062CP
Samples
TL062CPE4
ACTIVE
PDIP
P
8
50
TBD
Call TI
Call TI
0 to 70
TL062CPS
LIFEBUY
SO
PS
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T062
TL062CPSR
LIFEBUY
SO
PS
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T062
TL062CPW
LIFEBUY
TSSOP
PW
8
150
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T062
TL062CPWR
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T062
TL062CPWRG4
LIFEBUY
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T062
Samples
Samples
TL062ID
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL062I
TL062IDG4
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL062I
TL062IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL062I
Samples
TL062IP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
TL062IP
Samples
TL062IPWR
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
Z062
Samples
TL062IPWRG4
ACTIVE
TSSOP
PW
8
2000
TBD
Call TI
Call TI
-40 to 85
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
2-Dec-2023
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TL062MFKB
LIFEBUY
LCCC
FK
20
55
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
81023022A
TL062MFKB
TL062MJG
ACTIVE
CDIP
JG
8
50
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
TL062MJG
Samples
TL062MJGB
ACTIVE
CDIP
JG
8
50
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8102302PA
TL062M
Samples
TL064ACD
LIFEBUY
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL064AC
TL064ACDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL064AC
Samples
TL064ACN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL064ACN
Samples
TL064BCD
LIFEBUY
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL064BC
TL064BCDG4
LIFEBUY
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL064BC
TL064BCDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL064BC
Samples
TL064BCN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL064BCN
Samples
TL064CD
LIFEBUY
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL064C
TL064CDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL064C
Samples
TL064CN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL064CN
Samples
TL064CNSR
LIFEBUY
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL064
TL064CPW
LIFEBUY
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T064
TL064CPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T064
TL064ID
LIFEBUY
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL064I
TL064IDG4
LIFEBUY
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL064I
TL064IDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
TL064I
TL064IDRG4
LIFEBUY
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL064I
TL064IN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
TL064IN
TL064INE4
ACTIVE
PDIP
N
14
25
TBD
Call TI
Call TI
-40 to 85
TL064INS
LIFEBUY
SO
NS
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL064I
TL064INSR
LIFEBUY
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL064I
Addendum-Page 3
Samples
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
2-Dec-2023
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TL064IPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
Z064
Samples
TL064MFKB
ACTIVE
LCCC
FK
20
55
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
81023032A
TL064MFKB
Samples
TL064MJ
ACTIVE
CDIP
J
14
25
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
TL064MJ
Samples
TL064MJB
ACTIVE
CDIP
J
14
25
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8102303CA
TL064MJB
Samples
TL064MWB
ACTIVE
CFP
W
14
25
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8102303DA
TL064MWB
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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