TL071, TL071A, TL071B, TL071H
TL072, TL072A, TL072B, TL072H, TL072M
TL074, TL074A, TL074B, TL074H, TL074M
SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
TL07xx Low-Noise FET-Input Operational Amplifiers
1 Features
•
•
•
•
•
•
•
•
•
•
High slew rate: 20 V/μs (TL07xH, typ)
Low offset voltage: 1 mV (TL07xH, typ)
Low offset voltage drift: 2 μV/°C
Low power consumption: 940 μA/ch (TL07xH, typ)
Wide common-mode and differential
voltage ranges
– Common-mode input voltage range
includes VCC+
Low input bias and offset currents
Low noise:
Vn = 18 nV/√Hz (typ) at f = 1 kHz
Output short-circuit protection
Low total harmonic distortion: 0.003% (typ)
Wide supply voltage:
±2.25 V to ±20 V, 4.5 V to 40 V
(1.5 kV, HBM), integrated EMI and RF filters, and
operation across the full –40°C to 125°C enable the
TL07xH devices to be used in the most rugged and
demanding applications.
Device Information
PART NUMBER(1)
TL071x
TL072x
2 Applications
•
•
•
•
•
•
Solar energy: string and central inverter
Motor drives: AC and servo drive control and
power stage modules
Single phase online UPS
Three phase UPS
Pro audio mixers
Battery test equipment
TL072M
TL074x
3 Description
The TL07xH (TL071H, TL072H, and TL074H) family
of devices are the next-generation versions of the
industry-standard TL07x (TL071, TL072, and TL074)
devices. These devices provide outstanding value for
cost-sensitive applications, with features including low
offset (1 mV, typical), high slew rate (20 V/μs), and
common-mode input to the positive supply. High ESD
TL074M
(1)
PACKAGE
BODY SIZE (NOM)
PDIP (8)
9.59 mm × 6.35 mm
SC70 (5)
2.00 mm × 1.25 mm
SO (8)
6.20 mm × 5.30 mm
SOIC (8)
4.90 mm × 3.90 mm
SOT-23 (5)
1.60 mm × 1.20 mm
PDIP (8)
9.59 mm × 6.35 mm
SO (8)
6.20 mm × 5.30 mm
SOIC (8)
4.90 mm × 3.90 mm
SOT-23 (8)
2.90 mm × 1.60 mm
TSSOP (8)
4.40 mm × 3.00 mm
CDIP (8)
9.59 mm × 6.67 mm
CFP (10)
6.12 mm × 3.56 mm
LCCC (20)
8.89 mm × 8.89 mm
PDIP (14)
19.30 mm × 6.35 mm
SO (14)
10.30 mm × 5.30 mm
SOIC (14)
8.65 mm × 3.91 mm
SOT-23 (14)
4.20 mm × 2.00 mm
SSOP (14)
6.20 mm × 5.30 mm
TSSOP (14)
5.00 mm × 4.40 mm
CDIP (14)
19.56 mm × 6.92 mm
CFP (14)
9.21 mm × 6.29 mm
LCCC (20)
8.89 mm × 8.89 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
TL071
TL072 (each amplifier)
TL074 (each amplifier)
OFFSET N1
IN+
+
IN+
+
IN−
−
OUT
IN−
OFFSET N2
OUT
−
Copyright © 2017, Texas Instruments Incorporated
Logic Symbols
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TL071, TL071A, TL071B, TL071H
TL072, TL072A, TL072B, TL072H, TL072M
TL074, TL074A, TL074B, TL074H, TL074M
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................5
6 Specifications................................................................ 12
6.1 Absolute Maximum Ratings: TL07xH .......................12
6.2 Absolute Maximum Ratings: All Devices Except
TL07xH........................................................................12
6.3 ESD Ratings: TL07xH ..............................................12
6.4 ESD Ratings: All Devices Except TL07xH................ 13
6.5 Recommended Operating Conditions: TL07xH ....... 13
6.6 Recommended Operating Conditions: All
Devices Except TL07xH.............................................. 13
6.7 Thermal Information for Single Channel: TL071H ... 13
6.8 Thermal Information: TL071x....................................14
6.9 Thermal Information for Dual Channel: TL072H ...... 14
6.10 Thermal Information: TL072x..................................14
6.11 Thermal Information: TL072x (cont.).......................15
6.12 Thermal Information for Quad Channel: TL074H ...15
6.13 Thermal Information: TL074x..................................15
6.14 Thermal Information: TL074x (cont)........................16
6.15 Thermal Information: TL074x (cont)........................16
6.16 Thermal Information................................................16
6.17 Electrical Characteristics: TL07xH ......................... 17
6.18 Electrical Characteristics: TL071C, TL072C,
TL074C........................................................................19
6.19 Electrical Characteristics: TL071AC, TL072AC,
TL074AC..................................................................... 20
6.20 Electrical Characteristics: TL071BC, TL072BC,
TL074BC..................................................................... 21
6.21 Electrical Characteristics: TL071I, TL072I,
TL074I......................................................................... 22
6.22 Electrical Characteristics: TL071M, TL072M.......... 23
6.23 Electrical Characteristics: TL074M......................... 24
6.24 Switching Characteristics: TL07xM.........................25
6.25 Switching Characteristics: TL07xC, TL07xAC,
TL07xBC, TL07xI........................................................ 25
6.26 Typical Characteristics: TL07xH............................. 26
6.27 Typical Characteristics: All Devices Except
TL07xH........................................................................33
7 Parameter Measurement Information.......................... 37
8 Detailed Description......................................................38
8.1 Overview................................................................... 38
8.2 Functional Block Diagram......................................... 38
8.3 Feature Description...................................................39
8.4 Device Functional Modes..........................................39
9 Application and Implementation.................................. 40
9.1 Application Information............................................. 40
9.2 Typical Application.................................................... 40
9.3 Unity Gain Buffer.......................................................41
9.4 System Examples..................................................... 42
10 Power Supply Recommendations..............................43
11 Layout........................................................................... 43
11.1 Layout Guidelines................................................... 43
11.2 Layout Example...................................................... 44
12 Device and Documentation Support..........................45
12.1 Receiving Notification of Documentation Updates..45
12.2 Support Resources................................................. 45
12.3 Trademarks............................................................. 45
12.4 Electrostatic Discharge Caution..............................45
12.5 Glossary..................................................................45
13 Mechanical, Packaging, and Orderable
Information.................................................................... 45
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision S (July 2021) to Revision T (December 2021)
Page
• Corrected DCK pinout diagram and table in Pin Configurations and Functions section.....................................5
Changes from Revision R (June 2021) to Revision S (July 2021)
Page
• Deleted preview note from TL071H SOIC (8), SOT-23 (5) and SC70 (5) packages throughout the data sheet 1
Changes from Revision Q (June 2021) to Revision R (June 2021)
Page
• Deleted preview note from TL072H SOIC (8), SOT-23 (8) and TSSOP (8) packages throughout the data
sheet................................................................................................................................................................... 1
• Added ESD information for TL072H................................................................................................................. 12
• Added IQ spec for TL072H................................................................................................................................17
Changes from Revision P (November 2020) to Revision Q (June 2021)
Page
• Deleted VSSOP (8) package from the Device Information section.................................................................... 1
2
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TL074, TL074A, TL074B, TL074H, TL074M
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•
•
•
•
•
•
•
•
SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
Added DBV, DCK, and D packages to TL071H in Pin Configuration and Functions section..............................5
Deleted DGK package from TL072x in Pin Configuration and Functions section.............................................. 5
Deleted tables with duplicate information from the Specifications section....................................................... 12
Added D, DCK, and DBV package thermal information in Thermal Information for Single Channel: TL071H
section.............................................................................................................................................................. 13
Added D, DDF, and PW package thermal information in Thermal Information for Dual Channel: TL072H
section.............................................................................................................................................................. 14
Added IB and IOS specification for single channel DCK and DBV package...................................................... 17
Added IQ spec for TL071H................................................................................................................................17
Deleted Related Links section from the Device and Documentation Support section......................................45
Changes from Revision O (October 2020) to Revision P (November 2020)
Page
• Added SOIC and TSSOP package thermal information in Thermal Information for Quad Channel: TL074H
section ........................................................................................................................................................... 15
• Added Typical Characteristics:TL07xH section in Specifications section......................................................... 26
Changes from Revision N (July 2017) to Revision O (October 2020)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Features of TL07xH added to the Features section........................................................................................... 1
• Added link to applications in the Applications section........................................................................................ 1
• Added TL07xH in the Description section...........................................................................................................1
• Added TL07xH device in the Device Information section................................................................................... 1
• Added SOT-23 (14), VSSOP (8), SOT-23 (8), SC70 (5), and SOT-23 (5) packages to the Device Information
section................................................................................................................................................................ 1
• Added TSSOP, VSSOP and DDF packages to TL072x in Pin Configuration and Functions section................. 5
• Added DYY package to TL074x in Pin Configuration and Functions section..................................................... 5
• Removed Table of Graphs from the Typical Characteistics section..................................................................33
• Deleted reference to obsolete documentation in Layout Guidelines section.................................................... 43
• Removed Related Documentation section....................................................................................................... 45
Changes from Revision M (February 2014) to Revision N (July 2017)
Page
• Updated data sheet text to latest documentation and translation standards...................................................... 1
• Added TL072M and TL074M devices to data sheet .......................................................................................... 1
• Rewrote text in Description section ................................................................................................................... 1
• Changed TL07x 8-pin PDIP package to 8-pin CDIP package in Device Information table ............................... 1
• Deleted 20-pin LCCC package from Device Information table .......................................................................... 1
• Added 2017 copyright statement to front page schematic..................................................................................1
• Deleted TL071x FK (LCCC) pinout drawing and pinout table in Pin Configurations and Functions section ..... 5
• Updated pinout diagrams and pinout tables in Pin Configurations and Functions section ................................ 5
• Deleted differential input voltage parameter from Absolute Maximum Ratings table ...................................... 12
• Deleted table notes from Absolute Maximum Ratings table ............................................................................ 12
• Added new table note to Absolute Maximum Ratings table ............................................................................ 12
• Changed minimum supply voltage value from –18 V to –0.3 V in Absolute Maximum Ratings table...............12
• Changed maximum supply voltage from 18 V to 36 V in Absolute Maximum Ratings table............................ 12
• Changed minimum input voltage value from –15 V to VCC– – 0.3 V in Absolute Maximum Ratings table....... 12
• Changed maximum input voltage from 15 V to VCC– + 36 V in Absolute Maximum Ratings table................... 12
• Added input clamp current parameter to Absolute Maximum Ratings table ....................................................12
• Changed common-mode voltage maximum value from VCC+ – 4 V to VCC+ in the Recommended Operating
Conditions table................................................................................................................................................ 13
• Changed devices in Recommended Operating Conditions table from TL07xA and TL07xB to TL07xAC and
TL07xBC ..........................................................................................................................................................13
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3
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TL074, TL074A, TL074B, TL074H, TL074M
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
•
•
•
•
•
•
Added TL07xI operating free-air temperature minimum value of –40°C to Recommended Operating
Conditions table ............................................................................................................................................... 13
Added U (CFP) package thermal values to Thermal Information: TL072x (cont.) table................................... 15
Added W (CFP) package thermal values to Thermal Information: TL074x (cont.) table.................................. 16
Added Figure 6-59 to Typical Characteristics section.......................................................................................33
Added second Typical Application section application curves .........................................................................41
Reformatted document references in Layout Guidelines section .................................................................... 43
Changes from Revision L (February 2014) to Revision M (February 2014)
Page
• Added Device Information table, Pin Configuration and Functions section, ESD Ratings table, Feature
Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section........................................................................................................ 1
Changes from Revision K (January 2014) to Revision L (February 2014)
Page
• Moved Tstg to Handling Ratings table .............................................................................................................. 13
4
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
5 Pin Configuration and Functions
OUT
1
V±
2
IN+
3
5
4
V+
IN±
IN+
1
V±
2
IN±
3
Not to scale
5
V+
4
OUT
Not to scale
Figure 5-1. TL071H DBV Package
5-Pin SOT-23
(Top View)
Figure 5-2. TL071H DCK Package
5-Pin SC70
(Top View)
NC
1
8
NC
IN–
2
7
VCC+
IN+
3
6
OUT
VCC–
4
5
NC
Not to scale
NC- no internal connection
Figure 5-3. TL071H D Package
8-Pin SOIC
(Top View)
Table 5-1. Pin Functions: TL071H
PIN
NAME
I/O
DESCRIPTION
DBV
DCK
D
IN–
4
3
2
I
Inverting input
IN+
3
1
3
I
Noninverting input
NC
—
—
8
—
Do not connect
NC
—
—
1
—
Do not connect
NC
—
—
5
—
Do not connect
OUT
1
4
6
O
Output
VCC–
2
2
4
—
Power supply
VCC+
5
5
7
—
Power supply
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
OFFSET N1
1
8
NC
IN±
2
7
VCC+
IN+
3
6
OUT
VCC±
4
5
OFFSET N2
Not to scale
NC- no internal connection
Figure 5-4. TL071x D, P, and PS Package
8-Pin SOIC, PDIP, and SO
(Top View)
Table 5-2. Pin Functions: TL071x
PIN
NAME
6
NO.
IN–
2
IN+
NC
I/O
DESCRIPTION
I
Inverting input
3
I
Noninverting input
8
—
Do not connect
OFFSET N1
1
—
Input offset adjustment
OFFSET N2
5
—
Input offset adjustment
OUT
6
O
Output
VCC–
4
—
Power supply
VCC+
7
—
Power supply
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
1OUT
1
8
VCC+
1IN±
2
7
2OUT
1IN+
3
6
2IN±
VCC±
4
5
2IN+
Not to scale
Figure 5-5. TL072x D, DDF, JG, P, PS, and PW Package
8-Pin SOIC, SOT-23 (8), CDIP, PDIP, SO, and TSSOP
(Top View)
Table 5-3. Pin Functions: TL072x
PIN
NAME
NO.
I/O
DESCRIPTION
1IN–
2
I
Inverting input
1IN+
3
I
Noninverting input
1OUT
1
O
Output
2IN–
6
I
Inverting input
2IN+
5
I
Noninverting input
2OUT
7
O
Output
VCC–
4
—
Power supply
VCC+
8
—
Power supply
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
NC
1
10
NC
1OUT
2
9
VCC+
1IN±
3
8
2OUT
1IN+
4
7
2IN±
VCC±
5
6
2IN+
Not to scale
NC- no internal connection
Figure 5-6. TL072x U Package
10-Pin CFP
(Top View)
Table 5-4. Pin Functions: TL072x
PIN
NAME
I/O
DESCRIPTION
1IN–
3
I
Inverting input
1IN+
4
I
Noninverting input
1OUT
2
O
Output
2IN–
7
I
Inverting input
2IN+
6
I
Noninverting input
2OUT
8
O
Output
NC
8
NO.
1, 10
—
Do not connect
VCC–
5
—
Power supply
VCC+
9
—
Power supply
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NC
19
NC
1
VCC+
1OUT
2
20
NC
3
SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
5
17
2OUT
NC
6
16
NC
1IN+
7
15
2IN±
NC
8
14
NC
NC
2IN+
NC
VCC±
NC
13
1IN±
12
NC
11
18
10
4
9
NC
Not to scale
NC- no internal connection
Figure 5-7. TL072 FK Package
20-Pin LCCC
(Top View)
Table 5-5. Pin Functions: TL072x
PIN
NAME
NO.
I/O
DESCRIPTION
1IN–
5
I
Inverting input
1IN+
7
I
Noninverting input
1OUT
2
O
Output
2IN–
15
I
Inverting input
2IN+
12
I
Noninverting input
2OUT
17
O
Output
1, 3, 4, 6, 8,
9, 11, 13, 14,
16, 18, 19
—
Do not connect
VCC–
10
—
Power supply
VCC+
20
—
Power supply
NC
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
1OUT
1
14
4OUT
1IN±
2
13
4IN±
1IN+
3
12
4IN+
VCC+
4
11
VCC±
2IN+
5
10
3IN+
2IN±
6
9
3IN±
2OUT
7
8
3OUT
Not to scale
Figure 5-8. TL074x D, N, NS, PW, J, DYY, and W Package
14-Pin SOIC, PDIP, SO, TSSOP, CDIP, SOT-23 (14), and CFP
(Top View)
Table 5-6. Pin Functions: TL074x
PIN
NAME
NO.
1IN–
2
1IN+
1OUT
I/O
DESCRIPTION
I
Inverting input
3
I
Noninverting input
1
O
Output
2IN–
6
I
Inverting input
2IN+
5
I
Noninverting input
2OUT
7
O
Output
3IN–
9
I
Inverting input
3IN+
10
I
Noninverting input
3OUT
8
O
Output
4IN–
13
I
Inverting input
4IN+
12
I
Noninverting input
4OUT
14
O
Output
VCC–
11
—
Power supply
VCC+
4
—
Power supply
10
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4IN±
19
NC
1
4OUT
1OUT
2
20
1IN±
3
SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
5
17
NC
VCC+
6
16
VCC±
NC
7
15
NC
2IN+
8
14
3IN+
3IN±
3OUT
NC
2OUT
2IN±
13
NC
12
4IN+
11
18
10
4
9
1IN+
Not to scale
NC- no internal connection
Figure 5-9. TL074 FK Package
20-Pin LCCC
(Top View)
Table 5-7. Pin Functions: TL074x
PIN
NAME
NO.
I/O
DESCRIPTION
1IN–
3
I
Inverting input
1IN+
4
I
Noninverting input
1OUT
2
O
Output
2IN–
9
I
Inverting input
2IN+
8
I
Noninverting input
2OUT
10
O
Output
3IN–
13
I
Inverting input
3IN+
14
I
Noninverting input
3OUT
12
O
Output
4IN–
19
I
Inverting input
4IN+
18
I
Noninverting input
4OUT
20
O
Output
1, 5, 7, 11, 15,
17
—
Do not connect
VCC–
16
—
Power supply
VCC+
6
—
Power supply
NC
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
6 Specifications
6.1 Absolute Maximum Ratings: TL07xH
over operating ambient temperature range (unless otherwise noted) (1)
MIN
MAX
0
42
V
(VCC–) – 0.5
(VCC+) + 0.5
V
Supply voltage, VS = (VCC+) – (VCC–)
Common-mode voltage
(3)
Differential voltage (3)
Signal input pins
VS + 0.2
Current (3)
–10
Output short-circuit (2)
–55
Junction temperature, TJ
Storage temperature, Tstg
(2)
(3)
V
10
mA
150
°C
150
°C
150
°C
Continuous
Operating ambient temperature, TA
(1)
UNIT
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
Short-circuit to ground, one amplifier per package.
Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
6.2 Absolute Maximum Ratings: All Devices Except TL07xH
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VCC+ - VCC–
Supply voltage
–0.3
36
V
VI
Input voltage (3)
VCC– – 0.3
VCC– + 36
V
IIK
Input clamp current
–50
mA
Operating virtual junction temperature
150
°C
Case temperature for 60 seconds - FK package
260
°C
300
°C
150
°C
Duration of output short circuit(2)
TJ
Unlimited
Lead temperature 1.8 mm (1/16 inch) from case for 10 seconds
Tstg
(1)
(2)
(3)
Storage temperature
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The output may be shorted to ground or to either supply. Temperature and supply voltages must be limited to ensure that the
dissipation rating is not exceeded.
Differential voltage only limited by input voltage.
6.3 ESD Ratings: TL07xH
VALUE
UNIT
TL074H
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±1500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
V
TL072H and TL071H
V(ESD)
(1)
(2)
12
Electrostatic discharge
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.4 ESD Ratings: All Devices Except TL07xH
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC
V(ESD)
(1)
(2)
Electrostatic discharge
JS-001(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101(2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.5 Recommended Operating Conditions: TL07xH
over operating ambient temperature range (unless otherwise noted)
VS
Supply voltage, (VCC+) – (VCC–)
VI
Input voltage range
TA
Specified temperature
MIN
MAX
4.5
40
UNIT
(VCC–) + 2
(VCC+) + 0.1
V
–40
125
°C
V
6.6 Recommended Operating Conditions: All Devices Except TL07xH
over operating free-air temperature range (unless otherwise noted)
VCC+
Supply voltage (1)
VCC–
Supply voltage
(1)
VCM
Common-mode voltage
TA
Operating free-air temperature
MAX
5
15
UNIT
V
–5
–15
V
VCC– + 4
VCC+
V
TL07xM
–55
125
TL08xQ
–40
125
TL07xI
–40
85
0
70
TL07xAC, TL07xBC, TL07xC
(1)
MIN
°C
VCC+ and VCC– are not required to be of equal magnitude, provided that the total VCC (VCC+ – VCC–) is between 10 V and 30 V.
6.7 Thermal Information for Single Channel: TL071H
TL071H
THERMAL METRIC (1)
D
(SOIC)
DCK
(SC70)
DBV
(SOT-23)
UNIT
8 PINS
5 PINS
5 PINS
RθJA
Junction-to-ambient thermal resistance
158.8
217.5
212.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
98.6
113.1
111.1
°C/W
RθJB
Junction-to-board thermal resistance
102.3
63.8
79.4
°C/W
ψJT
Junction-to-top characterization parameter
45.8
34.8
51.8
°C/W
ψJB
Junction-to-board characterization parameter
101.5
63.5
79.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.8 Thermal Information: TL071x
TL071x
THERMAL
METRIC(1)
D (SOIC)
P (PDIP)
PS (SO)
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
97
85
95
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
—
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.9 Thermal Information for Dual Channel: TL072H
TL072H
THERMAL METRIC
(1)
D
(SOIC)
DDF
(SOT-23)
PW
(TSSOP)
UNIT
8 PINS
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
147.8
181.5
200.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
88.2
112.5
89.4
°C/W
RθJB
Junction-to-board thermal resistance
91.4
98.2
131.0
°C/W
ψJT
Junction-to-top characterization parameter
36.8
17.2
22.2
°C/W
ψJB
Junction-to-board characterization parameter
90.6
97.6
129.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.10 Thermal Information: TL072x
TL072x
THERMAL
RθJA
METRIC(1)
Junction-to-ambient thermal resistance
RθJC(top) Junction-to-case (top) thermal resistance
(1)
14
D (SOIC)
JG (CDIP)
P (PDIP)
PS (SO)
8 PINS
8 PINS
8 PINS
8 PINS
UNIT
97
—
85
95
°C/W
—
15.05
—
—
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.11 Thermal Information: TL072x (cont.)
TL072x
THERMAL
METRIC(1)
PW (TSSOP)
U (CFP)
FK (LCCC)
8 PINS
10 PINS
20 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
150
169.8
—
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
—
62.1
5.61
°C/W
RθJB
Junction-to-board thermal resistance
—
176.2
—
°C/W
ψJT
Junction-to-top characterization parameter
—
48.4
—
°C/W
ψJB
Junction-to-board characterization parameter
—
144.1
—
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
5.4
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.12 Thermal Information for Quad Channel: TL074H
TL074H
THERMAL METRIC
(1)
D
(SOIC)
DYY (2)
(SOT-23)
PW
(TSSOP)
UNIT
14 PINS
14 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
114.2
TBD
134.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
70.3
TBD
62.6
°C/W
RθJB
Junction-to-board thermal resistance
70.2
TBD
77.6
°C/W
ψJT
Junction-to-top characterization parameter
28.8
TBD
13.0
°C/W
ψJB
Junction-to-board characterization parameter
69.8
TBD
77.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
TBD
N/A
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
This package option is preview for TL074H.
6.13 Thermal Information: TL074x
TL074x
THERMAL METRIC(1)
D (SOIC)
N (PDIP)
NS (SO)
UNIT
14 PINS
14 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
86
80
76
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
—
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.14 Thermal Information: TL074x (cont).
TL074x
THERMAL
METRIC(1)
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
ψJT
J (CDIP)
PW (TSSOP)
W (CFP)
14 PINS
14 PINS
14 PINS
UNIT
—
113
128.8
°C/W
14.5
—
56.1
°C/W
Junction-to-board thermal resistance
—
—
127.6
°C/W
Junction-to-top characterization parameter
—
—
29
°C/W
ψJB
Junction-to-board characterization parameter
—
—
106.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
0.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.15 Thermal Information: TL074x (cont).
TL074x
THERMAL
METRIC(1)
FK (LCCC)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
(1)
—
°C/W
5.61
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.16 Thermal Information
TL071/TL072/TL074
D (SOIC)
THERMAL METRIC(1)
8 PINS
FK
(LCCC)
J (CDIP)
14
20 PINS 8 PINS
PINS
N (PDIP)
14
PINS
8 PINS
14
PINS
NS (SO)
PW (TSSOP)
8
8 PINS 14 PINS
PINS
UNIT
14
PINS
RθJA
Junction-to-ambient
thermal resistance
97
86
—
—
—
85
80
95
76
150
113
°C/W
RθJC(top)
Junction-to-case (top)
thermal resistance
—
—
5.61
15.05
14.5
—
—
—
—
—
—
°C/W
(1)
16
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.17 Electrical Characteristics: TL07xH
For VS = (VCC+) – (VCC–) = 4.5 V to 40 V (±2.25 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VOUT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±1
±4
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
Input offset voltage drift
TA = –40°C to 125°C
±2
PSRR
Input offset voltage versus VS = 5 V to 40 V, VCM = VS /
power supply
2
TA = –40°C to 125°C
±1
Channel separation
TA = –40°C to 125°C
±5
f = 0 Hz
mV
µV/℃
±10
10
μV/V
µV/V
INPUT BIAS CURRENT
IB
Input bias current
DCK and DBV packages
±1
±120
pA
±1
±300
pA
±5
nA
±0.5
±120
pA
±0.5
±250
pA
±5
nA
TA = –40°C to 125°C (1)
IOS
Input offset current
DCK and DBV packages
TA = –40°C to 125°C (1)
NOISE
EN
Input voltage noise
eN
Input voltage noise density
iN
Input current noise
f = 0.1 Hz to 10 Hz
9.2
μVPP
1.4
µVRMS
f = 1 kHz
37
f = 10 kHz
21
f = 1 kHz
80
nV/√Hz
fA/√Hz
INPUT VOLTAGE RANGE
VCM
Common-mode voltage
range
CMRR
Common-mode rejection
ratio
CMRR
Common-mode rejection
ratio
CMRR
Common-mode rejection
ratio
CMRR
Common-mode rejection
ratio
(VCC–) + 1.5
VS = 40 V, (VCC–) + 2.5 V <
VCM < (VCC+) – 1.5 V
VS = 40 V, (VCC–) + 2.5 V <
VCM < (VCC+)
100
TA = –40°C to 125°C
105
95
90
TA = –40°C to 125°C
(VCC+)
V
dB
dB
105
80
dB
dB
INPUT CAPACITANCE
ZID
Differential
ZICM
Common-mode
100 || 2
MΩ || pF
6 || 1
TΩ || pF
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
VS = 40 V, VCM = VS / 2,
(VCC–) + 0.3 V < VO < (VCC+)
– 0.3 V
TA = –40°C to 125°C
118
125
dB
AOL
Open-loop voltage gain
VS = 40 V, VCM = VS / 2, RL =
2 kΩ, (VCC–) + 1.2 V < VO <
TA = –40°C to 125°C
(VCC+) – 1.2 V
115
120
dB
5.25
MHz
20
V/μs
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
tS
Settling time
VS = 40 V, G = +1, CL = 20 pF
To 0.1%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF
0.63
To 0.1%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF
0.56
To 0.01%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF
0.91
To 0.01%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF
0.48
Phase margin
G = +1, RL = 10kΩ, CL = 20 pF
Overload recovery time
VIN × gain > VS
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μs
56
°
300
ns
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6.17 Electrical Characteristics: TL07xH (continued)
For VS = (VCC+) – (VCC–) = 4.5 V to 40 V (±2.25 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VOUT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
THD+N
Total harmonic distortion +
VS = 40 V, VO = 6 VRMS, G = +1, f = 1 kHz
noise
EMIRR
EMI rejection ratio
f = 1 GHz
MIN
TYP
MAX
UNIT
0.00012
%
53
dB
OUTPUT
Positive rail headroom
Voltage output swing from
rail
Negative rail headroom
VS = 40 V, RL = 10 kΩ
115
210
VS = 40 V, RL = 2 kΩ
520
965
VS = 40 V, RL = 10 kΩ
105
215
VS = 40 V, RL = 2 kΩ
500
1030
mV
ISC
Short-circuit current
±26
mA
CLOAD
Capacitive load drive
300
pF
ZO
Open-loop output
impedance
125
Ω
f = 1 MHz, IO = 0 A
POWER SUPPLY
IO = 0 A
IQ
Quiescent current per
amplifier
IO = 0 A, (TL071H)
937.5
1125
960
1156
IO = 0 A
IO = 0 A, (TL072H)
1130
TA = –40°C to 125°C
IO = 0 A, (TL071H)
Turn-On Time
(1)
18
At TA = 25°C, VS = 40 V, VS ramp rate > 0.3 V/µs
µA
1143
1160
60
μs
Max IB and Ios data is specified based on characterization results.
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6.18 Electrical Characteristics: TL071C, TL072C, TL074C
VCC± = ±15 V (unless otherwise noted)
TEST CONDITIONS (1) (2)
PARAMETER
VIO
Input offset voltage
VO = 0
RS = 50 Ω
α
Temperature coefficient of
input offset voltage
VO = 0
RS = 50 Ω
IIO
Input offset current
VO = 0
IIB
Input bias current (3)
VICR
Common-mode input voltage
TA = 25°C
range
VOM
Maximum peak output
voltage swing
VO = 0
RL= 10 kΩ
RL≥ 10 kΩ
RL≥ 2 kΩ
MIN
TA = 25°C
TYP
MAX
3
10
TA = Full range
13
TA = Full range
18
TA = 25°C
TA = Full range
µV/°C
100
pA
10
nA
65
200
pA
7
nA
TA = Full range
TA = 25°C
mV
5
TA = Full range
TA = 25°C
UNIT
±11
–12 to 15
±12
±13.5
V
V
±12
±10
TA = 25°C
25
TA = Full range
15
200
AVD
Large-signal differential
voltage amplification
VO = ±10 V
RL≥ 2 kΩ
B1
Utility-gain bandwidth
TA = 25°C
3
rI
Input resistance
TA = 25°C
1012
Ω
CMRR
Common-mode rejection
ratio
VIC = VICR(min)
VO = 0
RS = 50 Ω
kSVR
V/mV
MHz
TA = 25°C
70
100
dB
V = ±9 V to ±15 V
Supply voltage rejection ratio CC
VO = 0
(ΔVCC±/ΔVIO)
RS = 50 Ω
TA = 25°C
70
100
dB
ICC
Supply current (each
amplifier)
VO = 0; no load
TA = 25°C
1.4
VO1 / VO2
Crosstalk attenuation
AVD = 100
TA = 25°C
120
(1)
(2)
(3)
2.5
mA
dB
All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified.
Full range is TA = 0°C to 70°C.
Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 6-40. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as
possible.
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6.19 Electrical Characteristics: TL071AC, TL072AC, TL074AC
VCC± = ±15 V (unless otherwise noted)
TEST CONDITIONS (1) (2)
PARAMETER
VIO
Input offset voltage
VO = 0
RS = 50 Ω
α
Temperature coefficient of
input offset voltage
VO = 0
RS = 50 Ω
IIO
Input offset current
VO = 0
IIB
Input bias current (3)
VICR
Common-mode input voltage
TA = 25°C
range
VOM
Maximum peak output
voltage swing
VO = 0
RL= 10 kΩ
RL≥ 10 kΩ
RL≥ 2 kΩ
MIN
TA = 25°C
TYP
MAX
3
TA = Full range
TA = Full range
18
TA = 25°C
TA = 25°C
µV/°C
100
pA
2
nA
65
200
pA
7
nA
TA = Full range
TA = Full range
mV
5
TA = Full range
TA = 25°C
6
7.5
UNIT
±11
–12 to 15
±12
±13.5
V
V
±12
±10
TA = 25°C
50
TA = Full range
25
200
AVD
Large-signal differential
voltage amplification
VO = ±10 V
RL≥ 2 kΩ
B1
Utility-gain bandwidth
TA = 25°C
3
rI
Input resistance
TA = 25°C
1012
Ω
CMRR
VIC = VICR(min)
Common-mode rejection ratio VO = 0
RS = 50 Ω
TA = 25°C
75
100
dB
kSVR
V = ±9 V to ±15 V
Supply-voltage rejection ratio CC
VO = 0
(ΔVCC± / ΔVIO)
RS = 50 Ω
TA = 25°C
80
100
dB
ICC
Supply current
(each amplifier)
VO = 0; no load
TA = 25°C
1.4
AVD = 100
TA = 25°C
120
VO1 / VO2 Crosstalk attenuation
(1)
(2)
(3)
20
V/mV
MHz
2.5
mA
dB
All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified.
Full range is TA = 0°C to 70°C.
Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 6-40. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as
possible.
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6.20 Electrical Characteristics: TL071BC, TL072BC, TL074BC
VCC± = ±15 V (unless otherwise noted)
TEST CONDITIONS (1) (2)
PARAMETER
VIO
Input offset voltage
VO = 0
RS = 50 Ω
α
Temperature coefficient of
input offset voltage
VO = 0
RS = 50 Ω
IIO
Input offset current
VO = 0
IIB
Input bias current (3)
VO = 0
VICR
Common-mode input
voltage range
TA = 25°C
VOM
Maximum peak output
voltage swing
RL= 10 kΩ
RL≥ 10 kΩ
RL≥ 2 kΩ
MIN
TA = 25°C
TYP
2
TA = Full range
18
TA = 25°C
TA = 25°C
mV
µV/°C
5
100
pA
2
nA
65
200
pA
7
nA
TA = Full range
TA = Full range
TA = Full range
3
5
TA = Full range
TA = 25°C
MAX UNIT
±11
–12 to 15
±12
±13.5
V
V
±12
±10
TA = 25°C
50
TA = Full range
25
200
AVD
Large-signal differential
voltage amplification
VO = ±10 V
RL ≥ 2 kΩ
B1
Utility-gain bandwidth
TA = 25°C
3
rI
Input resistance
TA = 25°C
1012
Ω
CMRR
Common-mode rejection
ratio
VIC = VICR(min)
VO = 0
RS = 50 Ω
TA = 25°C
75
100
dB
kSVR
Supply-voltage rejection
ratio (ΔVCC±/ΔVIO)
VCC = ±9 V to ±15 V
VO = 0
RS = 50 Ω
TA = 25°C
80
100
dB
ICC
Supply current (each
amplifier)
VO = 0; no load
TA = 25°C
1.4
VO1 / VO2
Crosstalk attenuation
AVD = 100
TA = 25°C
120
(1)
(2)
(3)
V/mV
MHz
2.5
mA
dB
All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified.
Full range is TA = 0°C to 70°C.
Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 6-40. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as
possible.
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
6.21 Electrical Characteristics: TL071I, TL072I, TL074I
VCC± = ±15 V (unless otherwise noted)
TEST CONDITIONS (1) (2)
PARAMETER
VIO
Input offset voltage
VO = 0
RS = 50 Ω
α
Temperature coefficient of
input offset voltage
VO = 0
RS = 50 Ω
IIO
Input offset current
VO = 0
IIB
Input bias current (3)
VICR
Common-mode input voltage
TA = 25°C
range
VOM
Maximum peak output
voltage swing
VO = 0
RL= 10 kΩ
RL ≥ 10 kΩ
RL ≥ 2 kΩ
MIN
TA = 25°C
TYP
MAX
3
6
TA = Full range
8
TA = Full range
18
TA = 25°C
TA = Full range
µV/°C
100
pA
2
nA
65
200
pA
7
nA
TA = Full range
TA = 25°C
mV
5
TA = Full range
TA = 25°C
UNIT
±11
–12 to 15
±12
±13.5
V
V
±12
±10
TA = 25°C
50
TA = Full range
25
200
AVD
Large-signal differential
voltage amplification
VO = ±10 V
RL ≥ 2 kΩ
B1
Utility-gain bandwidth
TA = 25°C
3
rI
Input resistance
TA = 25°C
1012
Ω
CMRR
Common-mode rejection
ratio
VIC = VICR(min)
VO = 0
RS = 50 Ω
TA = 25°C
75
100
dB
kSVR
Supply-voltage rejection
ratio (ΔVCC±/ΔVIO)
VCC = ±9 V to ±15 V
VO = 0
RS = 50 Ω
TA = 25°C
80
100
dB
ICC
Supply current (each
amplifier)
VO = 0; no load
TA = 25°C
1.4
VO1 / VO2
Crosstalk attenuation
AVD = 100
TA = 25°C
120
(1)
(2)
(3)
22
V/mV
MHz
2.5
mA
dB
All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified.
TA = –40°C to 85°C.
Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 6-40. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as
possible.
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
6.22 Electrical Characteristics: TL071M, TL072M
VCC± = ±15 V (unless otherwise noted)
TEST CONDITIONS (1) (2)
PARAMETER
VIO
Input offset voltage
VO = 0
RS = 50 Ω
αVIO
Temperature coefficient
of input offset voltage
VO = 0
RS = 50 Ω
IIO
Input offset current
VO = 0
IIB
Input bias current
VO = 0
VICR
Common-mode input
voltage range
TA = 25°C
VOM
Maximum peak output
voltage swing
RL = 10 kΩ
RL ≥ 10 kΩ
RL ≥ 2 kΩ
AVD
Large-signal differential
voltage amplification
B1
Unity-gain bandwidth
ri
Input resistance
CMRR
V = VICR(min),
Common-mode rejection IC
VO = 0
ratio
RS = 50 Ω
kSVR
Supply-voltage rejection
ratio (ΔVCC±/ΔVIO)
ICC
VO1 / VO2
(1)
(2)
VO = ±10 V
RL ≥ 2 kΩ
MIN
TA = 25°C
TYP
MAX
3
6
TA = Full range
9
TA = Full range
18
TA = 25°C
5
100
pA
20
nA
65
200
pA
50
nA
TA = Full range
±11 –12 to 15
TA = 25°C
TA = Full range
±12
mV
μV/°C
TA = Full range
TA = 25°C
UNIT
V
±13.5
V
±12
±10
TA = 25°C
35
TA = Full range
15
200
V/mV
3
MHz
1012
Ω
TA = 25°C
80
86
dB
VCC = ±9 V to ±15 V
VO = 0
RS = 50 Ω
TA = 25°C
80
86
dB
Supply current
(each amplifier)
VO = 0; no load
TA = 25°C
1.4
Crosstalk attenuation
AVD = 100
TA = 25°C
120
2.5
mA
dB
Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 6-40. Pulse techniques that maintain the junction temperature as close to the ambient temperature as possible must
be used.
All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is
TA = –55°C to +125°C.
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
6.23 Electrical Characteristics: TL074M
VCC± = ±15 V (unless otherwise noted)
TEST CONDITIONS (1) (2)
PARAMETER
VO = 0
RS = 50 Ω
VIO
Input offset voltage
αVIO
Temperature coefficient of
VO = 0, RS = 50 Ω
input offset voltage
IIO
Input offset current
VO = 0
IIB
Input bias current
VO = 0
VICR
Common-mode input
voltage range
TA = 25°C
VOM
Maximum peak output
voltage swing
RL = 10 kΩ
RL ≥ 10 kΩ
RL ≥ 2 kΩ
TA = 25°C
TYP
3
TA = Full range
18
TA = 25°C
TA = 25°C
μV/°C
pA
20
nA
65
200
pA
20
nA
±11
–12 to 15
±12
±13.5
V
V
±12
±10
TA = 25°C
35
TA = Full range
15
200
B1
Unity-gain bandwidth
ri
Input resistance
CMRR
Common-mode rejection
ratio
VIC = VICR(min)
VO = 0
RS = 50 Ω
TA = 25°C
kSVR
Supply-voltage rejection
ratio (ΔVCC±/ΔVIO)
VCC = ±9 V to ±15 V
VO = 0
RS = 50 Ω
TA = 25°C
ICC
Supply current
(each amplifier)
VO = 0; no load
TA = 25°C
1.4
VO1 / VO2
Crosstalk attenuation
AVD = 100
TA = 25°C
120
24
mV
100
TA = Full range
TA = Full range
UNIT
5
TA = Full range
TA = 25°C
9
15
Large-signal differential
voltage amplification
(2)
MAX
TA = Full range
AVD
(1)
VO = ±10 V
RL ≥ 2 kΩ
MIN
V/mV
3
MHz
1012
Ω
80
86
dB
80
86
dB
2.5
mA
dB
Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 6-40. Pulse techniques that maintain the junction temperature as close to the ambient temperature as possible must
be used .
All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is
TA = –55°C to +125°C.
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
6.24 Switching Characteristics: TL07xM
VCC± = ±15 V, TA = 25°C
PARAMETER
TEST CONDITIONS
SR
Slew rate at unity gain
VI = 10 V
CL = 100 pF
RL = 2 kΩ
See Figure 7-1
tr
Rise-time overshoot factor
VI = 20 V
CL = 100 pF
RL = 2 kΩ
See Figure 7-1
Vn
Equivalent input noise voltage RS = 20 Ω
In
Equivalent input noise current RS = 20 Ω
THD
Total harmonic distortion
VIrms = 6 V
RL ≥ 2 kΩ
f = 1 kHz
MIN
TYP
MAX
UNIT
5
13
V/μs
0.1
μs
20%
f = 1 kHz
18
f = 10 Hz to 10 kHz
nV/√Hz
4
f = 1 kHz
μV
0.01
AVD = 1
RS ≤ 1 kΩ
pA/√Hz
0.003%
6.25 Switching Characteristics: TL07xC, TL07xAC, TL07xBC, TL07xI
VCC± = ±15 V, TA = 25°C
PARAMETER
TEST CONDITIONS
SR
Slew rate at unity gain
VI = 10 V
CL = 100 pF
tr
Rise-time overshoot factor
VI = 20 V
CL = 100 pF
Vn
Equivalent input noise voltage RS = 20 Ω
In
Equivalent input noise current RS = 20 Ω
THD
Total harmonic distortion
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VIrms = 6 V
RL ≥ 2 kΩ
f = 1 kHz
RL = 2 kΩ
See Figure 7-1
RL = 2 kΩ
See Figure 7-1
f = 1 kHz
f = 10 Hz to 10 kHz
f = 1 kHz
AVD = 1
RS ≤ 1 kΩ
MIN
TYP
MAX
UNIT
8
13
V/μs
0.1
μs
20%
18
4
0.01
nV/√Hz
μV
pA/√Hz
0.003%
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
6.26 Typical Characteristics: TL07xH
at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 20 pF (unless otherwise noted)
TA = 25°C
Figure 6-1. Offset Voltage Production Distribution
VCM = VS / 2
Figure 6-3. Offset Voltage vs Temperature
TA = 125°C
Figure 6-5. Offset Voltage vs Common-Mode Voltage
26
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Figure 6-2. Offset Voltage Drift Distribution
TA = 25°C
Figure 6-4. Offset Voltage vs Common-Mode Voltage
TA = –40°C
Figure 6-6. Offset Voltage vs Common-Mode Voltage
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
6.26 Typical Characteristics: TL07xH (continued)
at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 20 pF (unless otherwise noted)
Figure 6-7. Offset Voltage vs Power Supply
Figure 6-8. Open-Loop Gain and Phase vs Frequency
Figure 6-9. Closed-Loop Gain vs Frequency
Figure 6-10. Input Bias Current vs Common-Mode Voltage
Figure 6-11. Input Bias Current vs Temperature
Figure 6-12. Output Voltage Swing vs Output Current (Sourcing)
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
6.26 Typical Characteristics: TL07xH (continued)
at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 20 pF (unless otherwise noted)
Figure 6-13. Output Voltage Swing vs Output Current (Sinking)
f = 0 Hz
Figure 6-15. CMRR vs Temperature (dB)
Figure 6-17. 0.1-Hz to 10-Hz Noise
28
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Figure 6-14. CMRR and PSRR vs Frequency
f = 0 Hz
Figure 6-16. PSRR vs Temperature (dB)
Figure 6-18. Input Voltage Noise Spectral Density vs Frequency
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
6.26 Typical Characteristics: TL07xH (continued)
at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 20 pF (unless otherwise noted)
BW = 80 kHz, VOUT = 1 VRMS
Figure 6-19. THD+N Ratio vs Frequency
BW = 80 kHz, f = 1 kHz
Figure 6-20. THD+N vs Output Amplitude
VCM = VS / 2
Figure 6-21. Quiescent Current vs Supply Voltage
Figure 6-23. Open-Loop Voltage Gain vs Temperature (dB)
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Figure 6-22. Quiescent Current vs Temperature
Figure 6-24. Open-Loop Output Impedance vs Frequency
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
6.26 Typical Characteristics: TL07xH (continued)
at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 20 pF (unless otherwise noted)
G = –1, 25-mV output step
Figure 6-25. Small-Signal Overshoot vs Capacitive Load
G = 1, 10-mV output step
Figure 6-26. Small-Signal Overshoot vs Capacitive Load
VS = ±10 V, VIN = VOUT
Figure 6-27. Phase Margin vs Capacitive Load
G = –10
Figure 6-29. Positive Overload Recovery
30
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Figure 6-28. No Phase Reversal
G = –10
Figure 6-30. Negative Overload Recovery
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
6.26 Typical Characteristics: TL07xH (continued)
at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 20 pF (unless otherwise noted)
CL = 20 pF, G = 1, 10-mV step response
Figure 6-31. Small-Signal Step Response, Rising
CL = 20 pF, G = 1
Figure 6-33. Large-Signal Step Response (Rising)
CL = 20 pF, G = 1, 10-mV step response
Figure 6-32. Small-Signal Step Response, Falling
CL = 20 pF, G = 1
Figure 6-34. Large-Signal Step Response (Falling)
CL = 20 pF, G = 1
Figure 6-35. Large-Signal Step Response
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Figure 6-36. Short-Circuit Current vs Temperature
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
6.26 Typical Characteristics: TL07xH (continued)
at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 20 pF (unless otherwise noted)
Figure 6-37. Maximum Output Voltage vs Frequency
Figure 6-38. Channel Separation vs Frequency
Figure 6-39. EMIRR (Electromagnetic Interference Rejection Ratio) vs Frequency
32
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
6.27 Typical Characteristics: All Devices Except TL07xH
±15
100
VCC± = ±15 V
VOM
VOM − Maximum Peak Output Voltage − V
IIIB−
IB Input Bias Current − nA
VCC± = ±15 V
10
1
0.1
0.01
−75
−50
−25
0
25
50
75
100
±12.5
±10
VCC± = ±10 V
±7.5
VCC± = ±5 V
±5
±2.5
0
100
125
1k
TA − Free-Air Temperature − °C
Figure 6-40. Input Bias Current vs Free-Air Temperature
RL = 10 kΩ
TA = 25°C
See Figure 2
10 k
100 k
f − Frequency − Hz
1M
10 M
Figure 6-41. Maximum Peak Output Voltage vs Frequency
VOM
VOM − Maximum Peak Output Voltage − V
±15
RL = 2 kΩ
TA = 25°C
See Figure 2
VCC± = ±15 V
±12.5
±10
VCC± = ±10 V
±7.5
±5
VCC± = ±5 V
±2.5
8
0
100
1k
10 k
100 k
f − Frequency − Hz
1M
10 M
Figure 6-42. Maximum Peak Output Voltage vs Frequency
Figure 6-43. Maximum Peak Output Voltage vs Frequency
±15
RL = 10 kΩ
VOM − Maximum Peak Output Voltage − V
VOM
V
VOM
OM − Maximum Peak Output Voltage − V
±15
±12.5
RL = 2 kΩ
±10
±7.5
±5
±2.5
VCC± = ±15 V
8
See Figure 2
0
−75
−50
−25
0
25
50
75
100
125
TA − Free-Air Temperature − °C
Figure 6-44. Maximum Peak Output Voltage vs Free-Air
Temperature
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±12.5
VCC± = ±15 V
TA = 25°C
See Figure 2
±10
±7.5
±5
±2.5
8
0
0.1
0.2
0.4
0.7 1
2
4
7 10
RL − Load Resistance − kΩ
Figure 6-45. Maximum Peak Output Voltage vs Load Resistance
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
6.27 Typical Characteristics: All Devices Except TL07xH (continued)
1000
RL = 10 kΩ
TA = 25°C
400
±10
±7.5
±5
±2.5
200
100
40
20
10
4
VCC± = ±15 V
VO = ±10 V
RL = 2 kΩ
2
1
−75
0
0
2
4
6
8
10
12
14
16
|VCC±| − Supply Voltage − V
Figure 6-46. Maximum Peak Output Voltage vs Supply Voltage
−50
−25
0
25
50
75
Normalized Unity-Gain Bandwidth
1.03
1.01
1.1
Phase Shift
1
1
0.99
0.9
VCC± = ±15 V
RL = 2 kΩ
f = B1 for Phase Shift
0.8
−50
0.98
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
0.97
125
Figure 6-49. Normalized Unity-Gain Bandwidth and Phase Shift
vs Free-Air Temperature
89
2
VCC± = ±15 V
ICC − Supply Current Per Amplifier − mA
I CC±
CMRR − Common-Mode Rejection Ratio − dB
1.02
Unity-Gain Bandwidth
1.2
0.7
−75
RL = 10 kΩ
88
87
86
85
84
83
−75
−50
−25
0
25
50
75
100
125
TA − Free-Air Temperature − °C
Figure 6-50. Common-Mode Rejection Ratio vs Free-Air
Temperature
34
125
TA − Free-Air Temperature − °C
Figure 6-47. Large-Signal Differential Voltage Amplification vs
Free-Air Temperature
1.3
Figure 6-48. Large-Signal Differential Voltage Amplification and
Phase Shift vs Frequency
100
Normalized Phase Shift
±12.5
AAVD
VD − Large-Signal Differential
Voltage Amplification − V/mV
VOM
VOM − Maximum Peak Output Voltage − V
±15
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TA = 25°C
No Signal
No Load
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
2
4
6
8
10
12
14
16
|VCC±| − Supply Voltage − V
Figure 6-51. Supply Current Per Amplifier vs Supply Voltage
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
6.27 Typical Characteristics: All Devices Except TL07xH (continued)
250
VCC± = ±15 V
No Signal
No Load
1.8
1.6
PD − Total Power Dissipation − mW
ICC − Supply Current Per Amplifier − mA
I CC±
2
1.4
1.2
1
0.8
0.6
0.4
200
175
TL074
150
125
100
0.2
0
−75
VCC± =±15 V
No Signal
No Load
225
TL072
75
TL071
50
25
−50
−25
0
25
50
75
100
0
−75
125
−50
Figure 6-54. Normalized Slew Rate vs Free-Air Temperature
0.04
0.01
0.004
1k
4 k 10 k
f − Frequency − Hz
40 k 100 k
Figure 6-56. Total Harmonic Distortion vs Frequency
Copyright © 2021 Texas Instruments Incorporated
75
100
125
VCC± = ±15 V
AVD = 10
RS = 20 Ω
TA = 25°C
40
30
20
10
10
40 100
400 1 k
4 k 10 k
f − Frequency − Hz
40 k 100 k
Figure 6-55. Equivalent Input Noise Voltage vs Frequency
VI and VO − Input and Output Voltages − V
THD − Total Harmonic Distortion − %
0.1
400
50
6
VCC± = ±15 V
AVD = 1
VI(RMS) = 6 V
TA = 25°C
0.001
100
25
50
0
0.4
0
Figure 6-53. Total Power Dissipation vs Free-Air Temperature
V n − Equivalent Input Noise Voltage − nV/Hz
nV/ Hz
Figure 6-52. Supply Current Per Amplifier vs Free-Air
Temperature
1
−25
TA − Free-Air Temperature −C
°
TA − Free-Air Temperature − °C
VCC± = ±15 V
RL = 2 kΩ
CL = 100 pF
TA = 25°C
4
Output
2
0
−2
Input
−4
−6
0
0.5
1
1.5
t − Time − µs
2
2.5
3
3.5
Figure 6-57. Voltage-Follower Large-Signal Pulse Response
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
6.27 Typical Characteristics: All Devices Except TL07xH (continued)
10
8
VCCr = r15 V
6
VIO (mV)
4
2
0
-2
-4
-6
-8
-10
-13 -11 -9
-7
-5
-3
-1
1
3
5
7
9
11
VCM (V)
Figure 6-58. Output Voltage vs Elapsed Time
36
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13 15
17
D003
Figure 6-59. VIO vs VCM
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
7 Parameter Measurement Information
−
OUT
+
VI
CL = 100 pF
RL = 2 kΩ
Figure 7-1. Unity-Gain Amplifier
10 kΩ
1 kΩ
−
VI
OUT
+
RL
CL = 100 pF
Figure 7-2. Gain-of-10 Inverting Amplifier
Figure 7-3. Input Offset-Voltage Null Circuit
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37
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8 Detailed Description
8.1 Overview
The TL07xH (TL071H, TL072H, and TL074H) family of devices are the next-generation versions of the industrystandard TL07x (TL071, TL072, and TL074) devices. These devices provide outstanding value for cost-sensitive
applications, with features including low offset (1 mV, typ), high slew rate (25 V/μs, typ), and common-mode
input to the positive supply. High ESD (1.5 kV, HBM), integrated EMI and RF filters, and operation across the full
–40°C to 125°C enable the TL07xH devices to be used in the most rugged and demanding applications.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from −40°C to +85°C. The M-suffix devices are characterized for operation over the full military
temperature range of −55°C to +125°C.
8.2 Functional Block Diagram
VCC+
IN+
IN−
64 Ω
128 Ω
OUT
64 Ω
C1
18 pF
1080 Ω
1080 Ω
VCC−
OFFSET
N1
OFFSET
N2
TL071 Only
All component values shown are nominal.
COMPONENT COUNT†
COMPONENT
TYPE
Resistors
Transistors
JFET
Diodes
Capacitors
epi-FET
†
38
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TL071
TL072
TL074
11
14
2
1
1
1
22
28
4
2
2
2
44
56
6
4
4
4
Includes bias and trim circuitry
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
8.3 Feature Description
The TL07xH family of devices improve many specifications as compared to the industry-standard TL07x family.
Several comparisons of key specifications between these families are included below to show the advantages of
the TL07xH family.
8.3.1 Total Harmonic Distortion
Harmonic distortions to an audio signal are created by electronic components in a circuit. Total harmonic
distortion (THD) is a measure of harmonic distortions accumulated by a signal in an audio system. These
devices have a very low THD of 0.003% meaning that the TL07x device adds little harmonic distortion when
used in audio signal applications.
8.3.2 Slew Rate
The slew rate is the rate at which an operational amplifier can change the output when there is a change on the
input. These devices have a 13-V/μs slew rate.
8.4 Device Functional Modes
These devices are powered on when the supply is connected. These devices can be operated as a single-supply
operational amplifier or dual-supply amplifier depending on the application.
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39
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
A typical application for an operational amplifier is an inverting amplifier. This amplifier takes a positive voltage
on the input, and makes the voltage a negative voltage. In the same manner, the amplifier makes negative
voltages positive.
9.2 Typical Application
RF
RI
Vsup+
VOUT
+
VIN
Vsup-
Figure 9-1. Inverting Amplifier
9.2.1 Design Requirements
The supply voltage must be selected so the supply voltage is larger than the input voltage range and output
range. For instance, this application scales a signal of ±0.5 V to ±1.8 V. Setting the supply at ±12 V is sufficient
to accommodate this application.
9.2.2 Detailed Design Procedure
Vo = Vi + Vio * 1 + 1MΩ
1kΩ
(1)
Determine the gain required by the inverting amplifier:
AV =
VOUT
VIN
(2)
AV =
1.8
= -3.6
-0.5
(3)
Once the desired gain is determined, select a value for RI or RF. Selecting a value in the kilohm range is
desirable because the amplifier circuit uses currents in the milliamp range. This ensures the part does not draw
too much current. This example uses 10 kΩ for RI which means 36 kΩ is used for RF. This is determined by
Equation 4.
AV = -
40
RF
RI
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(4)
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
9.2.3 Application Curve
2
VIN
1.5
VOUT
1
Volts
0.5
0
-0.5
-1
-1.5
-2
0
0.5
1
Time (ms)
1.5
2
Figure 9-2. Input and Output Voltages of the Inverting Amplifier
9.3 Unity Gain Buffer
± U1 TL072
VIN
+
+
VOUT
10 k
+
12
Copyright © 2017, Texas Instruments Incorporated
Figure 9-3. Single-Supply Unity Gain Amplifier
9.3.1 Design Requirements
•
•
•
VCC must be within valid range per Section 6.6. This example uses a value of 12 V for VCC.
Input voltage must be within the recommended common-mode range, as shown in Section 6.6. The valid
common-mode range is 4 V to 12 V (VCC– + 4 V to VCC+).
Output is limited by output range, which is typically 1.5 V to 10.5 V, or VCC– + 1.5 V to VCC+ – 1.5 V.
9.3.2 Detailed Design Procedure
•
•
Avoid input voltage values below 1 V to prevent phase reversal where output goes high.
Avoid input values below 4 V to prevent degraded VIO that results in an apparent gain greater than 1. This
may cause instability in some second-order filter designs.
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12
1.5
10
1
8
0.5
Gain (V/V)
VOUT (V)
9.3.3 Application Curves
6
0
4
-0.5
2
-1
-1.5
0
0
2
4
6
VIN (V)
8
10
0
12
D001
2
4
6
VIN (V)
8
10
12
D002
Figure 9-5. Gain vs Input Voltage
Figure 9-4. Output Voltage vs Input Voltage
9.4 System Examples
VCC+
–
R1
R2
+
Input
Output
VCC–
C3
R1 = R2 = 2R3 = 1.5 MW
C1
R3
C1
C1 = C2 =
fo =
Figure 9-6. 0.5-Hz Square-Wave Oscillator
C3
= 110 pF
2
1
= 1kHz
2p R1 C1
Figure 9-7. High-Q Notch Filter
Figure 9-8. 100-kHz Quadrature Oscillator
Figure 9-9. AC Amplifier
42
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TL074, TL074A, TL074B, TL074H, TL074M
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
10 Power Supply Recommendations
CAUTION
Supply voltages larger than 36 V for a single-supply or outside the range of ±18 V for a dual-supply
can permanently damage the device (see Section 6.2).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or
high-impedance power supplies. For more detailed information on bypass capacitor placement, see Section 11.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
•
•
•
•
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from VCC+ to ground is applicable for singlesupply applications.
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Take care to physically separate digital
and analog grounds, paying attention to the flow of the ground current.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it
is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed
to in parallel with the noisy trace.
Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Section 11.2.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
11.2 Layout Example
Place components close to
device and to each other to
reduce parasitic errors
Run the input traces as far
away from the supply lines
as possible
RF
NC
NC
IN1í
VCC+
IN1+
OUT
VCCí
NC
VS+
Use low-ESR, ceramic
bypass capacitor
RG
GND
VIN
RIN
GND
Only needed for
dual-supply
operation
GND
VS(or GND for single supply)
VOUT
Ground (GND) plane on another layer
Figure 11-1. Operational Amplifier Board Layout for Noninverting Configuration
RIN
VIN
+
VOUT
RG
RF
Figure 11-2. Operational Amplifier Schematic for Noninverting Configuration
44
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SLOS080T – SEPTEMBER 1978 – REVISED DECEMBER 2021
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
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45
PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
81023052A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
81023052A
TL072MFKB
Samples
8102305HA
ACTIVE
CFP
U
10
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8102305HA
TL072M
Samples
8102305PA
ACTIVE
CDIP
JG
8
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8102305PA
TL072M
Samples
81023062A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
81023062A
TL074MFKB
Samples
8102306CA
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8102306CA
TL074MJB
Samples
8102306DA
ACTIVE
CFP
W
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8102306DA
TL074MWB
Samples
JM38510/11905BPA
ACTIVE
CDIP
JG
8
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510
/11905BPA
Samples
M38510/11905BPA
ACTIVE
CDIP
JG
8
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510
/11905BPA
Samples
TL071ACD
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
071AC
TL071ACDG4
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
071AC
TL071ACDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
071AC
Samples
TL071ACP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL071ACP
Samples
TL071BCD
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
071BC
TL071BCDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
071BC
Samples
TL071BCP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL071BCP
Samples
TL071CD
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL071C
TL071CDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL071C
Samples
TL071CDRE4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL071C
Samples
TL071CDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL071C
Samples
TL071CP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL071CP
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TL071CPE4
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL071CP
Samples
TL071CPSR
ACTIVE
SO
PS
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T071
Samples
TL071HIDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T71V
Samples
TL071HIDCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
1IO
Samples
TL071HIDR
ACTIVE
SOIC
D
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TL071D
Samples
TL071ID
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL071I
TL071IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL071I
Samples
TL071IDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL071I
Samples
TL071IP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
TL071IP
Samples
TL072ACD
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
072AC
TL072ACDE4
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
072AC
TL072ACDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
072AC
Samples
TL072ACDRE4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
072AC
Samples
TL072ACDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
072AC
Samples
TL072ACP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL072ACP
Samples
TL072ACPE4
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL072ACP
Samples
TL072BCD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
072BC
Samples
TL072BCDE4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
072BC
Samples
TL072BCDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
072BC
Samples
TL072BCDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
072BC
Samples
TL072BCP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL072BCP
Samples
TL072CD
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL072C
TL072CDE4
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL072C
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TL072CDG4
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL072C
TL072CDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL072C
Samples
TL072CDRE4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL072C
Samples
TL072CDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL072C
Samples
TL072CP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL072CP
Samples
TL072CPE4
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL072CP
Samples
TL072CPS
ACTIVE
SO
PS
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T072
Samples
TL072CPSR
ACTIVE
SO
PS
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T072
Samples
TL072CPSRG4
ACTIVE
SO
PS
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T072
Samples
TL072CPWR
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T072
Samples
TL072CPWRE4
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T072
Samples
TL072CPWRG4
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T072
Samples
TL072HIDDFR
ACTIVE
SOT-23-THIN
DDF
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
O72F
Samples
TL072HIDR
ACTIVE
SOIC
D
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TL072D
Samples
TL072HIPWR
ACTIVE
TSSOP
PW
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
072HPW
Samples
TL072ID
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL072I
TL072IDE4
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL072I
TL072IDG4
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL072I
TL072IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL072I
Samples
TL072IDRE4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL072I
Samples
TL072IDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL072I
Samples
TL072IP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
TL072IP
Samples
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TL072IPE4
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
TL072IP
Samples
TL072MFKB
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
81023052A
TL072MFKB
Samples
TL072MJG
ACTIVE
CDIP
JG
8
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
TL072MJG
Samples
TL072MJGB
ACTIVE
CDIP
JG
8
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8102305PA
TL072M
Samples
TL072MUB
ACTIVE
CFP
U
10
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8102305HA
TL072M
Samples
TL074ACD
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074AC
Samples
TL074ACDE4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074AC
Samples
TL074ACDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074AC
Samples
TL074ACDRE4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074AC
Samples
TL074ACN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL074ACN
Samples
TL074ACNE4
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL074ACN
Samples
TL074ACNSR
ACTIVE
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074A
Samples
TL074BCD
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074BC
Samples
TL074BCDE4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074BC
Samples
TL074BCDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074BC
Samples
TL074BCDRE4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074BC
Samples
TL074BCDRG4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074BC
Samples
TL074BCN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL074BCN
Samples
TL074BCNE4
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL074BCN
Samples
TL074CD
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074C
Samples
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TL074CDBR
ACTIVE
SSOP
DB
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T074
Samples
TL074CDG4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074C
Samples
TL074CDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
0 to 70
TL074C
Samples
TL074CDRG4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074C
Samples
TL074CN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL074CN
Samples
TL074CNE4
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL074CN
Samples
TL074CNSR
ACTIVE
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL074
Samples
TL074CPW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T074
Samples
TL074CPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T074
Samples
TL074CPWRE4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T074
Samples
TL074CPWRG4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T074
Samples
TL074HIDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TL074HID
Samples
TL074HIDYYR
ACTIVE
SOT-23-THIN
DYY
14
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T074HDYY
Samples
TL074HIPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TL074PW
Samples
TL074ID
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL074I
Samples
TL074IDE4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL074I
Samples
TL074IDG4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL074I
Samples
TL074IDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL074I
Samples
TL074IDRE4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL074I
Samples
TL074IDRG4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL074I
Samples
TL074IN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
TL074IN
Samples
Addendum-Page 5
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TL074MFK
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
TL074MFK
Samples
TL074MFKB
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
81023062A
TL074MFKB
Samples
TL074MJ
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
TL074MJ
Samples
TL074MJB
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8102306CA
TL074MJB
Samples
TL074MWB
ACTIVE
CFP
W
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8102306DA
TL074MWB
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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