TL081, TL081A, TL081B, TL081H
TL082, TL082A, TL082B, TL082H
TL084, TL084A, TL084B, TL084H
SLOS081M – FEBRUARY 1977 – REVISED DECEMBER 2021
TL08xx FET-Input Operational Amplifiers
1 Features
3 Description
•
•
•
•
•
The TL08xH (TL081H, TL082H, and TL084H) family
of devices are the next-generation versions of the
industry-standard TL08x (TL081, TL082, and TL084)
devices. These devices provide outstanding value for
cost-sensitive applications, with features including low
offset (1 mV, typical), high slew rate (20 V/μs), and
common-mode input to the positive supply. High ESD
(1.5 kV, HBM), integrated EMI and RF filters, and
operation across the full –40°C to 125°C enable the
TL08xH devices to be used in the most rugged and
demanding applications.
•
•
•
•
•
High slew rate: 20 V/μs (TL08xH, typ)
Low offset voltage: 1 mV (TL08xH, typ)
Low offset voltage drift: 2 μV/°C
Low power consumption: 940 μA/ch (TL08xH, typ)
Wide common-mode and differential
voltage ranges
– Common-mode input voltage range
includes VCC+
Low input bias and offset currents
Low noise:
Vn = 18 nV/√Hz (typ) at f = 1 kHz
Output short-circuit protection
Low total harmonic distortion: 0.003% (typ)
Wide supply voltage:
±2.25 V to ±20 V, 4.5 V to 40 V
2 Applications
•
•
•
•
•
•
Device Information
PART NUMBER(1)
TL081x
Solar energy: string and central inverter
Motor drives: AC and servo drive control and
power stage modules
Single phase online UPS
Three phase UPS
Pro audio mixers
Battery test equipment
TL082x
TL082M
TL084x
TL084M
(1)
PACKAGE
BODY SIZE (NOM)
PDIP (8)
9.59 mm × 6.35 mm
SC70 (5)
2.00 mm × 1.25 mm
SO (8)
6.20 mm × 5.30 mm
SOIC (8)
4.90 mm × 3.90 mm
SOT-23 (5)
1.60 mm × 1.20 mm
PDIP (8)
9.59 mm × 6.35 mm
SO (8)
6.20 mm × 5.30 mm
SOIC (8)
4.90 mm × 3.90 mm
SOT-23 (8)
2.90 mm × 1.60 mm
TSSOP (8)
4.40 mm × 3.00 mm
CDIP (8)
9.59 mm × 6.67 mm
LCCC (20)
8.89 mm × 8.89 mm
PDIP (14)
19.30 mm × 6.35 mm
SO (14)
10.30 mm × 5.30 mm
SOIC (14)
8.65 mm × 3.91 mm
SOT-23 (14)
4.20 mm × 2.00 mm
TSSOP (14)
5.00 mm × 4.40 mm
CDIP (14)
19.56 mm × 6.92 mm
LCCC (20)
8.89 mm × 8.89 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
TL081
TL082 (EACH AMPLIFIER)
TL084 (EACH AMPLIFIER)
OFFSET N1
IN +
+
IN −
−
OUT
IN +
+
IN −
−
OUT
OFFSET N2
Logic Symbols
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TL081, TL081A, TL081B, TL081H
TL082, TL082A, TL082B, TL082H
TL084, TL084A, TL084B, TL084H
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SLOS081M – FEBRUARY 1977 – REVISED DECEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications................................................................ 10
6.1 Absolute Maximum Ratings: TL08xH .......................10
6.2 Absolute Maximum Ratings: All Other Devices........ 10
6.3 ESD Ratings: TL08xH ..............................................10
6.4 ESD Ratings: All Other Devices................................11
6.5 Recommended Operating Conditions: TL08xH ....... 11
6.6 Recommended Operating Conditions: All Other
Devices........................................................................11
6.7 Thermal Information for Single Channel: TL081H ....11
6.8 Thermal Information for Dual Channel: TL082H ...... 11
6.9 Thermal Information for Quad Channel: TL084H .....12
6.10 Thermal Information: All Other Devices.................. 12
6.11 Electrical Characteristics: TL08xH ......................... 13
6.12 Electrical Characteristics for TL08xC, TL08xxC,
and TL08xI.................................................................. 15
6.13 Electrical Characteristics for TL08xM and
TL084x........................................................................ 16
6.14 Switching Characteristics........................................17
6.15 Dissipation Rating Table......................................... 17
6.16 Typical Characteristics: TL08xH............................. 18
6.17 Typical Characteristics: All Other Devices.............. 25
7 Parameter Measurement Information.......................... 28
8 Detailed Description......................................................29
8.1 Overview................................................................... 29
8.2 Functional Block Diagram......................................... 29
8.3 Feature Description...................................................29
8.4 Device Functional Modes..........................................30
9 Applications and Implementation................................ 31
9.1 Application Information............................................. 31
9.2 Typical Applications.................................................. 31
9.3 System Examples..................................................... 32
10 Power Supply Recommendations..............................34
11 Layout........................................................................... 35
11.1 Layout Guidelines................................................... 35
11.2 Layout Examples.....................................................35
12 Device and Documentation Support..........................36
12.1 Receiving Notification of Documentation Updates..36
12.2 Support Resources................................................. 36
12.3 Trademarks............................................................. 36
12.4 Electrostatic Discharge Caution..............................36
12.5 Glossary..................................................................36
13 Mechanical, Packaging, and Orderable
Information.................................................................... 36
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision L (July 2021) to Revision M (December 2021)
Page
• Corrected DCK pinout diagram and table in Pin Configurations and Functions section.....................................4
Changes from Revision K (June 2021) to Revision L (July 2021)
Page
• Deleted preview note from TL081H SOIC (8), SOT-23 (5), and SC70 (5) packages throughout the data sheet
............................................................................................................................................................................1
Changes from Revision J (November 2020) to Revision K (June 2021)
Page
• Deleted VSSOP (8) package references throughout data sheet........................................................................ 1
• Deleted preview note from TL082H SOIC (8), SOT-23 (8), and TSSOP (8) packages throughout the data
sheet................................................................................................................................................................... 1
• Added DBV, DCK, and D packages to TL081H in Pin Configuration and Functions section..............................4
• Added ESD information for TL082H................................................................................................................. 10
• Added D, DCK, and DBV package thermal information in Thermal Information for Single Channel: TL081H
section...............................................................................................................................................................11
• Added D, DDF, and PW package thermal information in Thermal Information for Dual Channel: TL082H
section ..............................................................................................................................................................11
• Added IB and IOS specification for single channel DCK and DBV package...................................................... 13
• Added IQ spec for TL081H and TL082H........................................................................................................... 13
• Removed Related Links section from Device and Documentation Support section.........................................36
2
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SLOS081M – FEBRUARY 1977 – REVISED DECEMBER 2021
Changes from Revision I (May 2015) to Revision J (November 2020)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Added TL08xH devices throughout the data sheet.............................................................................................1
• Added features for TL08xH to the Features section........................................................................................... 1
• Added link to applications in the Applications section........................................................................................ 1
• Added TL08xH in the Description section...........................................................................................................1
• Added TL08xH in the Device Information table.................................................................................................. 1
• Updated pinout diagrams and pinout tables in Pin Configurations and Functions section ................................ 4
• Added TSSOP, VSSOP and DDF packages to TL082x in Pin Configuration and Functions section................. 4
• Added DYY package to TL084x in Pin Configuration and Functions section..................................................... 4
• Added Typical Characteristics:TL08xH section in Specifications section......................................................... 18
• Removed Table of Graphs in Typical Characteristics: All Other Devices section............................................. 25
• Removed references to obsolete documentation............................................................................................. 35
Changes from Revision H (January 2014) to Revision I (May 2015)
Page
• Added Applications section, Device Information table, Pin Functions table, Thermal Information table, Feature
Description section, Device Functional Modes section, Application and Implementation section, Power Supply
Recommendations section, ESD information, Layout section, Device and Documentation Support section,
and Mechanical, Packaging, and Orderable Information section....................................................................... 1
• Added Applications ............................................................................................................................................ 1
• Moved Typical Characteristics into Specifications section. ..............................................................................25
Changes from Revision G (September 2004) to Revision H (January 2014)
Page
• Deleted Ordering Information table.....................................................................................................................1
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SLOS081M – FEBRUARY 1977 – REVISED DECEMBER 2021
5 Pin Configuration and Functions
OUT
1
V±
2
IN+
3
5
4
V+
IN±
IN+
1
V±
2
IN±
3
Not to scale
5
V+
4
OUT
Not to scale
Figure 5-1. TL081H DBV Package
5-Pin SOT-23
(Top View)
Figure 5-2. TL081H DCK Package
5-Pin SC70
(Top View)
NC
1
8
NC
IN–
2
7
VCC+
IN+
3
6
OUT
VCC–
4
5
NC
Not to scale
NC- no internal connection
Figure 5-3. TL081H D Package
8-Pin SOIC
(Top View)
Table 5-1. Pin Functions: TL081H
PIN
NAME
4
I/O
DESCRIPTION
DBV
DCK
D
IN–
4
3
2
I
Inverting input
IN+
3
1
3
I
Noninverting input
NC
—
—
8
—
Do not connect
NC
—
—
1
—
Do not connect
NC
—
—
5
—
Do not connect
OUT
1
4
6
O
Output
VCC–
2
2
4
—
Power supply
VCC+
5
5
7
—
Power supply
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SLOS081M – FEBRUARY 1977 – REVISED DECEMBER 2021
OFFSET N1
1
8
NC
IN±
2
7
VCC+
IN+
3
6
OUT
VCC±
4
5
OFFSET N2
Not to scale
NC- no internal connection
Figure 5-4. TL081x D, P, and PS Package
8-Pin SOIC, PDIP, and SO
(Top View)
Table 5-2. Pin Functions: TL081x
PIN
NAME
NO.
IN–
2
IN+
NC
I/O
DESCRIPTION
I
Inverting input
3
I
Noninverting input
8
—
Do not connect
OFFSET N1
1
—
Input offset adjustment
OFFSET N2
5
—
Input offset adjustment
OUT
6
O
Output
VCC–
4
—
Power supply
VCC+
7
—
Power supply
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SLOS081M – FEBRUARY 1977 – REVISED DECEMBER 2021
1OUT
1
8
VCC+
1IN±
2
7
2OUT
1IN+
3
6
2IN±
VCC±
4
5
2IN+
Not to scale
Figure 5-5. TL082x D, DDF, DGK, JG, P, PS, and PW Package
8-Pin SOIC, SOT-23 (8), VSSOP, CDIP, PDIP, SO, and TSSOP
(Top View)
Table 5-3. Pin Functions: TL082x
PIN
NAME
6
NO.
I/O
DESCRIPTION
1IN–
2
I
Inverting input
1IN+
3
I
Noninverting input
1OUT
1
O
Output
2IN–
6
I
Inverting input
2IN+
5
I
Noninverting input
2OUT
7
O
Output
VCC–
4
—
Power supply
VCC+
8
—
Power supply
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NC
19
NC
1
VCC+
1OUT
2
20
NC
3
SLOS081M – FEBRUARY 1977 – REVISED DECEMBER 2021
5
17
2OUT
NC
6
16
NC
1IN+
7
15
2IN±
NC
8
14
NC
NC
2IN+
NC
VCC±
NC
13
1IN±
12
NC
11
18
10
4
9
NC
Not to scale
NC- no internal connection
Figure 5-6. TL082 FK Package
20-Pin LCCC
(Top View)
Table 5-4. Pin Functions: TL082x
PIN
NAME
NO.
I/O
DESCRIPTION
1IN–
5
I
Inverting input
1IN+
7
I
Noninverting input
1OUT
2
O
Output
2IN–
15
I
Inverting input
2IN+
12
I
Noninverting input
2OUT
17
O
Output
1, 3, 4, 6, 8,
9, 11, 13, 14,
16, 18, 19
—
Do not connect
VCC–
10
—
Power supply
VCC+
20
—
Power supply
NC
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SLOS081M – FEBRUARY 1977 – REVISED DECEMBER 2021
1OUT
1
14
4OUT
1IN±
2
13
4IN±
1IN+
3
12
4IN+
VCC+
4
11
VCC±
2IN+
5
10
3IN+
2IN±
6
9
3IN±
2OUT
7
8
3OUT
Not to scale
Figure 5-7. TL084x D, N, NS, PW, J, and DYY Package
14-Pin SOIC, PDIP, SO, TSSOP, CDIP, and SOT-23 (14)
(Top View)
Table 5-5. Pin Functions: TL084x
PIN
NAME
8
NO.
1IN–
2
1IN+
1OUT
I/O
DESCRIPTION
I
Inverting input
3
I
Noninverting input
1
O
Output
2IN–
6
I
Inverting input
2IN+
5
I
Noninverting input
2OUT
7
O
Output
3IN–
9
I
Inverting input
3IN+
10
I
Noninverting input
3OUT
8
O
Output
4IN–
13
I
Inverting input
4IN+
12
I
Noninverting input
4OUT
14
O
Output
VCC–
11
—
Power supply
VCC+
4
—
Power supply
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4IN±
19
NC
1
4OUT
1OUT
2
20
1IN±
3
SLOS081M – FEBRUARY 1977 – REVISED DECEMBER 2021
5
17
NC
VCC+
6
16
VCC±
NC
7
15
NC
2IN+
8
14
3IN+
3IN±
3OUT
NC
2OUT
2IN±
13
NC
12
4IN+
11
18
10
4
9
1IN+
Not to scale
NC- no internal connection
Figure 5-8. TL084 FK Package
20-Pin LCCC
(Top View)
Table 5-6. Pin Functions: TL084x
PIN
NAME
NO.
I/O
DESCRIPTION
1IN–
3
I
Inverting input
1IN+
4
I
Noninverting input
1OUT
2
O
Output
2IN–
9
I
Inverting input
2IN+
8
I
Noninverting input
2OUT
10
O
Output
3IN–
13
I
Inverting input
3IN+
14
I
Noninverting input
3OUT
12
O
Output
4IN–
19
I
Inverting input
4IN+
18
I
Noninverting input
4OUT
20
O
Output
1, 5, 7, 11, 15,
17
—
Do not connect
VCC–
16
—
Power supply
VCC+
6
—
Power supply
NC
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SLOS081M – FEBRUARY 1977 – REVISED DECEMBER 2021
6 Specifications
6.1 Absolute Maximum Ratings: TL08xH
over operating ambient temperature range (unless otherwise noted) (1)
MIN
MAX
0
42
V
(VCC–) – 0.5
(VCC+) + 0.5
V
Supply voltage, VS = (VCC+) – (VCC–)
Common-mode voltage
Signal input pins
(3)
Differential voltage (3)
VS + 0.2
Current (3)
–10
Output short-circuit (2)
–55
Junction temperature, TJ
Storage temperature, Tstg
(2)
(3)
V
10
mA
150
°C
150
°C
150
°C
Continuous
Operating ambient temperature, TA
(1)
UNIT
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
Short-circuit to ground, one amplifier per package.
Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
6.2 Absolute Maximum Ratings: All Other Devices
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Supply voltage(2)
-18
18
V
VID
Differential input voltage(3)
-30
+30
V
VI
Input voltage(2) (4)
-15
+15
V
VCC+ VCC-
Duration of output short circuit(5)
Unlimited
Continuous total power dissipation
Tstg
(1)
(2)
(3)
(4)
(5)
See Section 6.15
Storage temperature
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC−.
Differential voltages are at IN+, with respect to IN−.
The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.
The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the
dissipation rating is not exceeded.
6.3 ESD Ratings: TL08xH
VALUE
UNIT
TL084H
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101
±1500
(2)
±1000
V
TL082H and TL081H
V(ESD)
(1)
(2)
10
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SLOS081M – FEBRUARY 1977 – REVISED DECEMBER 2021
6.4 ESD Ratings: All Other Devices
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC
V(ESD)
(1)
(2)
Electrostatic discharge
JS-001(1)
UNIT
±1000
Charged-device model (CDM), per JEDEC specification JESD22C101(2)
V
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.5 Recommended Operating Conditions: TL08xH
over operating ambient temperature range (unless otherwise noted)
VS
Supply voltage, (VCC+) – (VCC–)
VI
Input voltage range
TA
Specified temperature
MIN
MAX
4.5
40
UNIT
(VCC–) + 2
(VCC+) + 0.1
V
–40
125
°C
V
6.6 Recommended Operating Conditions: All Other Devices
over operating free-air temperature range (unless otherwise noted)
VCC+
Supply voltage
VCC–
Supply voltage
VCM
Common-mode voltage
TA
Ambient temperature
MIN
MAX
5
15
UNIT
V
–5
–15
V
VCC– + 4
VCC+ – 4
V
TL08xM
–55
125
TL08xQ
–40
125
TL08xI
–40
85
0
70
TL08xC
°C
6.7 Thermal Information for Single Channel: TL081H
TL081H
THERMAL METRIC (1)
D
(SOIC)
DCK
(SC70)
DBV
(SOT-23)
UNIT
8 PINS
5 PINS
5 PINS
RθJA
Junction-to-ambient thermal resistance
158.8
217.5
212.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
98.6
113.1
111.1
°C/W
RθJB
Junction-to-board thermal resistance
102.3
63.8
79.4
°C/W
ψJT
Junction-to-top characterization parameter
45.8
34.8
51.8
°C/W
ψJB
Junction-to-board characterization parameter
101.5
63.5
79.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.8 Thermal Information for Dual Channel: TL082H
TL082H
THERMAL METRIC (1)
D
(SOIC)
DDF
(SOT-23)
PW
(TSSOP)
UNIT
8 PINS
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
147.8
181.5
200.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
88.2
112.5
89.4
°C/W
RθJB
Junction-to-board thermal resistance
91.4
98.2
131.0
°C/W
ψJT
Junction-to-top characterization parameter
36.8
17.2
22.0
°C/W
ψJB
Junction-to-board characterization parameter
90.6
97.6
129.3
°C/W
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6.8 Thermal Information for Dual Channel: TL082H (continued)
TL082H
THERMAL METRIC (1)
RθJC(bot)
(1)
Junction-to-case (bottom) thermal resistance
D
(SOIC)
DDF
(SOT-23)
PW
(TSSOP)
8 PINS
8 PINS
8 PINS
N/A
N/A
N/A
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.9 Thermal Information for Quad Channel: TL084H
TL084H
THERMAL METRIC (1)
D
(SOIC)
DYY (2)
(SOT-23)
PW
(TSSOP)
UNIT
14 PINS
14 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
114.2
TBD
134.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
70.3
TBD
62.6
°C/W
RθJB
Junction-to-board thermal resistance
70.2
TBD
77.6
°C/W
ψJT
Junction-to-top characterization parameter
28.8
TBD
13.0
°C/W
ψJB
Junction-to-board characterization parameter
69.8
TBD
77.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
TBD
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
This package option is preview for TL084H.
(2)
6.10 Thermal Information: All Other Devices
TL08xxx
THERMAL METRIC(1)
RθJA
Junction-toambient thermal
resistance
RθJC(top)
Junction-tocase (top)
thermal
resistance
(1)
12
D (SOIC)
8 PIN
14 PIN
97
86
FK
(LCCC)
20 PIN
J (CDIP)
8 PIN
14 PIN
N (PDIP)
NS (SO)
PW (TSSOP)
8 PIN
14 PIN
8 PIN
14 PIN
8 PIN
14 PIN
85
80
95
76
150
113
UNIT
°C/W
5.61
15.05
14.5
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.11 Electrical Characteristics: TL08xH
For VS = (VCC+) – (VCC–) = 4.5 V to 40 V (±2.25 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VO UT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±1
±4
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
Input offset voltage drift
TA = –40°C to 125°C
±2
PSRR
Input offset voltage versus VS = 5 V to 40 V, VCM = VS /
power supply
2
TA = –40°C to 125°C
±1
Channel separation
TA = –40°C to 125°C
±5
f = 0 Hz
mV
µV/℃
±10
10
μV/V
µV/V
INPUT BIAS CURRENT
IB
Input bias current
DCK and DBV packages
±1
±120
pA
±1
±300
pA
±5
nA
±0.5
±120
pA
±0.5
±250
pA
±5
nA
TA = –40°C to 125°C (1)
IOS
Input offset current
DCK and DBV packages
TA = –40°C to 125°C (1)
NOISE
EN
Input voltage noise
eN
Input voltage noise density
iN
Input current noise
f = 0.1 Hz to 10 Hz
9.2
μVPP
1.4
µVRMS
f = 1 kHz
37
f = 10 kHz
21
f = 1 kHz
80
nV/√Hz
fA/√Hz
INPUT VOLTAGE RANGE
VCM
Common-mode voltage
range
CMRR
Common-mode rejection
ratio
CMRR
Common-mode rejection
ratio
CMRR
Common-mode rejection
ratio
CMRR
Common-mode rejection
ratio
(VCC–) + 1.5
VS = 40 V, (VCC–) + 2.5 V <
VCM < (VCC+) – 1.5 V
VS = 40 V, (VCC–) + 2.5 V <
VCM < (VCC+)
100
TA = –40°C to 125°C
105
95
90
TA = –40°C to 125°C
(VCC+)
V
dB
dB
105
80
dB
dB
INPUT CAPACITANCE
ZID
Differential
ZICM
Common-mode
100 || 2
MΩ || pF
6 || 1
TΩ || pF
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
VS = 40 V, VCM = VS / 2,
(VCC–) + 0.3 V < VO < (VCC+)
– 0.3 V
TA = –40°C to 125°C
118
125
dB
AOL
Open-loop voltage gain
VS = 40 V, VCM = VS / 2, RL =
2 kΩ, (VCC–) + 1.2 V < VO <
TA = –40°C to 125°C
(VCC+) – 1.2 V
115
120
dB
5.25
MHz
20
V/μs
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
tS
Settling time
VS = 40 V, G = +1, CL = 20 pF
To 0.1%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF
0.63
To 0.1%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF
0.56
To 0.01%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF
0.91
To 0.01%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF
0.48
Phase margin
G = +1, RL = 10kΩ, CL = 20 pF
Overload recovery time
VIN × gain > VS
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μs
56
°
300
ns
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6.11 Electrical Characteristics: TL08xH (continued)
For VS = (VCC+) – (VCC–) = 4.5 V to 40 V (±2.25 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VO UT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
THD+N
Total harmonic distortion +
VS = 40 V, VO = 6 VRMS, G = +1, f = 1 kHz
noise
EMIRR
EMI rejection ratio
f = 1 GHz
MIN
TYP
MAX
UNIT
0.00012
%
53
dB
OUTPUT
Positive rail headroom
Voltage output swing from
rail
Negative rail headroom
VS = 40 V, RL = 10 kΩ
115
210
VS = 40 V, RL = 2 kΩ
520
965
VS = 40 V, RL = 10 kΩ
105
215
VS = 40 V, RL = 2 kΩ
500
1030
mV
ISC
Short-circuit current
±26
mA
CLOAD
Capacitive load drive
300
pF
ZO
Open-loop output
impedance
125
Ω
f = 1 MHz, IO = 0 A
POWER SUPPLY
IO = 0 A
IQ
Quiescent current per
amplifier
IO = 0 A, (TL081H)
937.5
1125
960
1156
IO = 0 A
IO = 0 A, (TL082H)
1130
TA = –40°C to 125°C
IO = 0 A, (TL081H)
Turn-On Time
(1)
14
At TA = 25°C, VS = 40 V, VS ramp rate > 0.3 V/µs
µA
1143
1160
60
μs
Max IB and Ios data is specified based on characterization results.
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6.12 Electrical Characteristics for TL08xC, TL08xxC, and TL08xI
VCC± = ±15 V (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
VIO
Input offset
voltage
VO = 0,
RS = 50 Ω
αVIO
Temperature
coefficient of
VO = 0,
input
RS = 50 Ω
offset
voltage
IIO
Input offset
current(2)
VO = 0
IIB
Input bias
current(2)
VO = 0
VICR
Commonmode
input voltage
range
VOM
Maximum
peak
output
voltage
swing
TA (1)
TL081C, TL082C,
TL084C
MIN
25°C
RL ≥ 10 kΩ
RL ≥ 2 kΩ
TYP
MAX
3
15
Full
range
MIN
Full
range
18
25°C
5
Full
range
MAX
3
6
30
MIN
TYP
MAX
2
3
7.5
200
5
30
10
100
5
200
30
7
–12
to
15
±11
–12
to
15
±11
–12
to
15
25°C
±12
±13.5
±12
±13.5
±12
±13.5
±12
MAX
3
6
9
18
100
5
200
30
7
±11
UNIT
TYP
2
25°C
±12
MIN
18
2
400
TL081I, TL082I,
TL084I
5
18
2
Full
range
TL081BC, TL082BC,
TL084BC
TYP
20
25°C
RL = 10 kΩ
TL081AC, TL082AC,
TL084AC
±11
mV
μV/°C
100
pA
10
nA
200
pA
20
nA
–12
to
15
V
±12 ±13.5
±12
±12
V
Full
range
±10
±12
±10
±12
±10
±12
±10
±12
25°C
25
200
50
200
50
200
50
200
Full
range
15
AVD
Large-signal
differential
VO = ±10 V,
voltage
RL ≥ 2 kΩ
amplification
B1
Unity-gain
bandwidth
25°C
3
3
3
3
ri
Input
resistance
25°C
1012
1012
1012
1012
Ω
CMRR
Commonmode
rejection
ratio
VIC = VICRmin,
VO = 0,
RS = 50 Ω
25°C
70
86
75
86
75
86
75
86
dB
kSVR
Supplyvoltage
rejection
ratio
(ΔVCC±/
ΔVIO)
VCC = ±15 V to
±9 V,
VO = 0,
RS = 50 Ω
25°C
70
86
80
86
80
86
80
86
dB
ICC
Supply
current
(each
amplifier)
VO = 0,
No load
25°C
1.4
VO1/VO2
Crosstalk
attenuation
AVD = 100
25°C
120
(1)
(2)
15
2.8
25
1.4
120
2.8
V/mV
25
1.4
120
2.8
1.4
120
MHz
2.8
mA
dB
All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range
for TA is 0°C to 70°C for TL08_C, TL08_AC, TL08_BC and –40°C to 85°C for TL08_I.
Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 6-52. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as
possible.
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SLOS081M – FEBRUARY 1977 – REVISED DECEMBER 2021
6.13 Electrical Characteristics for TL08xM and TL084x
VCC± = ±15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS(1)
VIO
Input offset voltage
VO = 0, RS = 50 Ω
αVIO
Temperature
coefficient of input
offset voltage
VO = 0, RS = 50 Ω
IIO
Input offset current(2)
VO = 0
Input bias current(2)
IIB
VO = 0
TA
TL081M, TL082M
MIN
25°C
TYP
TL084Q, TL084M
MAX
3
Full range
MIN
6
TYP
3
9
Full range
18
25°C
5
125°C
30
125°C
18
100
5
200
30
50
25°C
±11
–12
to
15
25°C
±12
±13.5
9
15
20
25°C
UNIT
MAX
±11
–12
to
15
±12
±13.5
mV
μV/°C
100
pA
20
nA
200
pA
50
nA
VICR
Common-mode
input voltage range
VOM
Maximum peak
output voltage swing
AVD
Large-signal differential
voltage amplification
B1
Unity-gain bandwidth
25°C
3
3
ri
Input resistance
25°C
1012
1012
Ω
CMRR
Common-mode
rejection ratio
VIC = VICRmin,
VO = 0, RS = 50 Ω
25°C
80
86
80
86
dB
kSVR
Supply-voltage
rejection ratio
(ΔVCC±/ΔVIO)
VCC = ±15 V to ±9 V,
VO = 0, RS = 50 Ω
25°C
80
86
80
86
dB
ICC
Supply current
(each amplifier)
VO = 0, No load
25°C
1.4
VO1/VO2
Crosstalk attenuation
AVD = 100
25°C
120
RL = 10 kΩ
RL ≥ 10 kΩ
RL ≥ 2 kΩ
(1)
(2)
16
VO = ±10 V, RL ≥ 2 kΩ
Full range
±12
V
V
±12
±10
±12
±10
±12
25°C
25
200
25
200
Full range
15
V/mV
15
2.8
1.4
120
MHz
2.8
mA
dB
All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise specified.
Input bias currents of a FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 6-52. Pulse techniques must be used that maintain the junction temperatures as close to the ambient temperature as
possible.
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6.14 Switching Characteristics
VCC± = ±15 V, TA= 25°C (unless otherwise noted)
PARAMETER
SR
Slew rate at unity gain
tr
Rise-time
TEST CONDITIONS
MIN
TYP
VI = 10 V, RL = 2 kΩ, CL = 100 pF,
see Figure 7-1
8(1)
13
VI = 10 V, RL = 2 kΩ, CL = 100 pF,
TA = −55°C to 125°C,
see Figure 7-1
5(1)
UNIT
V/μs
0.05
overshoot factor
VI = 20 V, RL = 2 kΩ, CL = 100 pF,
see Figure 7-1
Vn
Equivalent input noise
voltage
RS = 20 Ω
In
Equivalent input noise
current
RS = 20 Ω
THD
Total harmonic distortion
VIrms = 6 V, AVD = 1, RS ≤ 1 kΩ, RL ≥ 2 kΩ,
f = 1 kHz
(1)
MAX
μs
20%
f = 1 kHz
18
nV/√ Hz
4
μV
f = 10 Hz to 10 kHz
f = 1 kHz
0.01
pA/√Hz
0.003%
On products compliant to MIL-PRF-38535, this parameter is not production tested.
6.15 Dissipation Rating Table
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING
FACTOR
DERATE
ABOVE TA
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D (14 pin)
680 mW
7.6 mW/°C
60°C
604 m/W
490 mW
186 mW
FK
680 mW
11.0 mW/°C
88°C
680 m/W
680 mW
273 mW
J
680 mW
11.0 mW/°C
88°C
680 m/W
680 mW
273 mW
JG
680 mW
8.4 mW/°C
69°C
672 m/W
546 mW
210 mW
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6.16 Typical Characteristics: TL08xH
at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 20 pF (unless
otherwise noted)
TA = 25°C
Figure 6-1. Offset Voltage Production Distribution
VCM = VS / 2
Figure 6-3. Offset Voltage vs Temperature
TA = 125°C
Figure 6-5. Offset Voltage vs Common-Mode
Voltage
18
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Figure 6-2. Offset Voltage Drift Distribution
TA = 25°C
Figure 6-4. Offset Voltage vs Common-Mode
Voltage
TA = –40°C
Figure 6-6. Offset Voltage vs Common-Mode
Voltage
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Figure 6-7. Offset Voltage vs Power Supply
Figure 6-8. Open-Loop Gain and Phase vs
Frequency
Figure 6-9. Closed-Loop Gain vs Frequency
Figure 6-10. Input Bias Current vs Common-Mode
Voltage
Figure 6-11. Input Bias Current vs Temperature
Figure 6-12. Output Voltage Swing vs Output
Current (Sourcing)
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Figure 6-13. Output Voltage Swing vs Output
Current (Sinking)
f = 0 Hz
20
Figure 6-14. CMRR and PSRR vs Frequency
f = 0 Hz
Figure 6-15. CMRR vs Temperature (dB)
Figure 6-16. PSRR vs Temperature (dB)
Figure 6-17. 0.1-Hz to 10-Hz Noise
Figure 6-18. Input Voltage Noise Spectral Density
vs Frequency
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BW = 80 kHz, VOUT = 1 VRMS
Figure 6-19. THD+N Ratio vs Frequency
BW = 80 kHz, f = 1 kHz
Figure 6-20. THD+N vs Output Amplitude
VCM = VS / 2
Figure 6-21. Quiescent Current vs Supply Voltage
Figure 6-22. Quiescent Current vs Temperature
Figure 6-23. Open-Loop Voltage Gain vs
Temperature (dB)
Figure 6-24. Open-Loop Output Impedance vs
Frequency
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G = –1, 25-mV output step
Figure 6-25. Small-Signal Overshoot vs Capacitive
Load
G = 1, 10-mV output step
Figure 6-26. Small-Signal Overshoot vs Capacitive
Load
VS = ±10 V, VIN = VOUT
Figure 6-27. Phase Margin vs Capacitive Load
G = –10
Figure 6-29. Positive Overload Recovery
22
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Figure 6-28. No Phase Reversal
G = –10
Figure 6-30. Negative Overload Recovery
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CL = 20 pF, G = 1, 10-mV step response
Figure 6-31. Small-Signal Step Response, Rising
CL = 20 pF, G = 1
Figure 6-33. Large-Signal Step Response (Rising)
CL = 20 pF, G = 1, 10-mV step response
Figure 6-32. Small-Signal Step Response, Falling
CL = 20 pF, G = 1
Figure 6-34. Large-Signal Step Response (Falling)
CL = 20 pF, G = 1
Figure 6-35. Large-Signal Step Response
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Figure 6-36. Short-Circuit Current vs Temperature
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Figure 6-37. Maximum Output Voltage vs
Frequency
Figure 6-38. Channel Separation vs Frequency
Figure 6-39. EMIRR (Electromagnetic Interference Rejection Ratio) vs Frequency
24
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6.17 Typical Characteristics: All Other Devices
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various
devices. The Figure numbers referenced in the following graphs are located in Section 7.
±15
VOM
VOM − Maximum Peak Output Voltage − V
RL = 10 kΩ
TA = 25°C
See Figure 2
±12.5
±10
VCC± = ±10 V
±7.5
VCC± = ±5 V
±5
±2.5
0
100
1k
10 k
100 k
f − Frequency − Hz
1M
VOM
VOM − Maximum Peak Output Voltage − V
±15
VCC± = ±15 V
±12.5
Figure 6-40. Maximum Peak Output Voltage vs Frequency
±5
VCC± = ±5 V
±2.5
1k
10 k
100 k
f − Frequency − Hz
±15
VCC± = ±15 V
RL = 2 kΩ
See Figure 2
TA = 25°C
±12.5
V
VOM
OM − Maximum Peak Output Voltage − V
VOM
VOM − Maximum Peak Output Voltage − V
VCC± = ±10 V
±7.5
±10
TA = −55°C
±7.5
TA = 125°C
±5
±2.5
1M
10 M
Figure 6-41. Maximum Peak Output Voltage vs Frequency
±15
RL = 10 kΩ
±12.5
RL = 2 kΩ
±10
±7.5
±5
±2.5
VCC± = ±15 V
See Figure 2
0
10 k
40 k 100 k
400 k 1 M
f − Frequency − Hz
4M
0
−75
10 M
0
25
50
75
100
125
±15
VOM
VOM − Maximum Peak Output Voltage − V
VCC± = ±15 V
TA = 25°C
See Figure 2
±10
±7.5
±5
±2.5
8
0
0.1
−25
Figure 6-43. Maximum Peak Output Voltage vs Free-Air
Temperature
±15
±12.5
−50
TA − Free-Air Temperature − °C
Figure 6-42. Maximum Peak Output Voltage vs Frequency
VOM − Maximum Peak Output Voltage − V
VOM
±10
0
100
10 M
RL = 2 kΩ
TA = 25°C
See Figure 2
VCC± = ±15 V
RL = 10 kΩ
TA = 25°C
±12.5
±10
±7.5
±5
±2.5
8
0
0.2
0.4
0.7 1
2
4
7 10
RL − Load Resistance − kΩ
Figure 6-44. Maximum Peak Output Voltage vs Load Resistance
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0
2
4
6
8
10
12
14
16
|VCC±| − Supply Voltage − V
Figure 6-45. Maximum Peak Output Voltage vs Supply Voltage
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6.17 Typical Characteristics: All Other Devices (continued)
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various
devices. The Figure numbers referenced in the following graphs are located in Section 7.
106
AAVD – Large-Signal Differential
Voltage Amplification
AAVD − Large-Signal Differential
Voltage Amplification − V/mV
400
200
100
40
20
10
4
2
1
−75
VCC± = ±15 V
VO = ±10 V
RL = 2 kΩ
VCC± = ±5 V to ±15 V
RL = 2 kΩ
TA = 25°C
105
104
103
102
90°
Phase Shift
101
−25
0
25
50
75
125
100
1
10
TA − Free-Air Temperature − °C
100
1k
10 k 100 k
f − Frequency − Hz
180°
10 M
1M
250
VCC± =±15 V
C2 = 3 pF
TA = 25°C
See Figure 3
105
104
103
102
10
VCC± =±15 V
No Signal
No Load
225
PD − Total Power Dissipation − mW
AVD − Differential Voltage Amplification − V/mV
135°
Figure 6-47. Large-Signal Differential Voltage Amplification and
Phase Shift vs Frequency
106
200
175
TL084, TL085
150
125
100
TL082, TL083
75
TL081
50
25
1
100
1k
10 k
100 k
1M
0
−75
10 M
−50
Figure 6-48. Differential Voltage Amplification vs Frequency
with Feed-Forward Compensation
0
25
50
75
100
125
Figure 6-49. Total Power Dissipation vs Free-Air Temperature
2
2
1.6
ICC − Supply Current Per Amplifier − mA
I CC±
VCC± = ±15 V
No Signal
No Load
1.8
1.4
1.2
1
0.8
0.6
0.4
0.2
0
−75
−25
TA − Free-Air Temperature °−C
f − Frequency With Feed-Forward Compensation − Hz
ICC − Supply Current Per Amplifier − mA
I CC±
45°
1
−50
Figure 6-46. Large-Signal Differential Voltage Amplification vs
Free-Air Temperature
TA = 25°C
No Signal
No Load
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
−50
−25
0
25
50
75
100
125
TA − Free-Air Temperature − °C
Figure 6-50. Supply Current per Amplifier vs Free-Air
Temperature
26
0°
Differential
Voltage
Amplification
Phase Shift
1000
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0
2
4
6
8
10
12
14
16
|VCC±| − Supply Voltage − V
Figure 6-51. Supply Current per Amplifier vs Supply Voltage
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6.17 Typical Characteristics: All Other Devices (continued)
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various
devices. The Figure numbers referenced in the following graphs are located in Section 7.
6
100
VI and VO − Input and Output Voltages − V
I IB − Input Bias Current − nA
V CC± =±15 V
10
1
0.1
0.01
− 50
0
25
50
75
100
Output
2
0
−2
Input
−4
0
125
TA − Free-Air Temperature − °C
Figure 6-52. Input Bias Current vs Free-Air Temperature
CMRR − Common-Mode Rejection Ratio − dB
20
16
VCC± =±15 V
RL = 2 kΩ
CL = 100 pF
TA = 25°C
See Figure 1
12
8
4
0
−4
0
2.5
3
3.5
0.2
0.4
0.6
0.8
1.0
VCC± =±15 V
RL = 10 kΩ
88
87
86
85
84
83
− 75
1.2
t − Elapsed Time – µs
VCC± = ±15 V
AVD = 10
RS = 20 Ω
TA = 25°C
40
30
20
10
10
40 100
400 1 k
4 k 10 k
f − Frequency − Hz
40 k 100 k
Figure 6-56. Equivalent Input Noise Voltage vs Frequency
Copyright © 2021 Texas Instruments Incorporated
− 25
0
25
50
75
100
125
Figure 6-55. Common-Mode Rejection Ratio vs Free-Air
Temperature
1
THD − Total Harmonic Distortion − %
50
− 50
TA − Free-Air Temperature −C
°
Figure 6-54. Output Voltage vs Elapsed Time
V n − Equivalent Input Noise Voltage − nV/Hz
nV/ Hz
2
89
24
0
0.5
1
1.5
t − Time − µs
Figure 6-53. Voltage-Follower Large-Signal Pulse Response
28
VO − Output Voltage − mV
4
−6
− 25
VCC± = ±15 V
RL = 2 kΩ
CL = 100 pF
TA = 25°C
0.4
VCC± = ±15 V
AVD = 1
VI(RMS) = 6 V
TA = 25°C
0.1
0.04
0.01
0.004
0.001
100
400
1k
4 k 10 k
f − Frequency − Hz
40 k 100 k
Figure 6-57. Total Harmonic Distortion vs Frequency
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7 Parameter Measurement Information
10 kΩ
1 kΩ
−
−
VI
OUT
OUT
+
+
VI
RL
CL = 100 pF
CL = 100 pF
RL = 2 kΩ
Figure 7-2. Test Figure 2
Figure 7-1. Test Figure 1
100 kΩ
TL081
−
IN −
C2
OUT
C1 500 pF
−
IN −
N2
+
IN +
N1
100 kΩ
N1
OUT
1.5 kΩ
+
VCC −
Figure 7-3. Test Figure 3
28
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Figure 7-4. Test Figure 4
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8 Detailed Description
8.1 Overview
The TL08xH family (TL081H, TL082H, and TL084H) is the next-generation family of the industry standard TL08x
(TL081, TL082, and TL084) high-voltage general purpose amplifiers. These devices provide outstanding value
for cost-sensitive applications requiring high slew rate with high voltage signals, such as motor drive and inverter
systems.
A robust MUX-friendly input stage enhances flexibility in design, with common-mode voltage range extending to
the positive rail as well as improved settling time in multi-channel applications. Low offset voltage (1 mV, typ) and
low offset voltage drift (2 µV/°C) allows the TL08xH family to be used in rugged applications requiring precision
current and voltage sensing. High voltage operation (up to 40 V) and high slew rate (20 V/µs) make the TL08xH
family a premier choice for high-voltage applications with fast transients.
8.2 Functional Block Diagram
VCC +
IN +
64Ω
IN −
OUT
128Ω
64Ω
C1
1080Ω
1080Ω
VCC −
OFFSET N1
OFFSET N2
TL081 Only
8.3 Feature Description
8.3.1 Total Harmonic Distortion
Harmonic distortions to an audio signal are created by electronic components in a circuit. Total harmonic
distortion (THD) is a measure of harmonic distortions accumulated by a signal in an audio system. These
devices have a very low THD of 0.003% meaning that the TL08x devices will add little harmonic distortion when
used in audio signal applications.
8.3.2 Slew Rate
The slew rate is the rate at which an operational amplifier can change its output when there is a change on the
input. These devices have a 13-V/μs slew rate.
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8.4 Device Functional Modes
These devices are powered on when the supply is connected. This device can be operated as a single-supply
operational amplifier or dual-supply amplifier depending on the application.
30
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TL082, TL082A, TL082B, TL082H
TL084, TL084A, TL084B, TL084H
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SLOS081M – FEBRUARY 1977 – REVISED DECEMBER 2021
9 Applications and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TL08x series of operational amplifiers can be used in countless applications. The few applications in this
section show principles used in all applications of these parts.
9.2 Typical Applications
9.2.1 Inverting Amplifier Application
A typical application for an operational amplifier in an inverting amplifier. This amplifier takes a positive voltage
on the input, and makes it a negative voltage of the same magnitude. In the same manner, it also makes
negative voltages positive.
RF
RI
Vsup+
VOUT
VIN
+
Vsup-
Figure 9-1. Schematic for Inverting Amplifier Application
9.2.1.1 Design Requirements
The supply voltage must be chosen such that it is larger than the input voltage range and output range. For
instance, this application will scale a signal of ±0.5 V to ±1.8 V. Setting the supply at ±12 V is sufficient to
accommodate this application.
9.2.1.2 Detailed Design Procedure
Determine the gain required by the inverting amplifier:
AV
VOUT
VIN
AV
1.8
0.5
(1)
3.6
(2)
Once the desired gain is determined, choose a value for RI or RF. Choosing a value in the kΩ range is desirable
because the amplifier circuit will use currents in the milliamp range. This ensures the part will not draw too much
current. This example will choose 10 kΩ for RI which means 36 kΩ will be used for RF. This was determined by
Equation 3.
AV
RF
RI
(3)
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9.2.1.3 Application Curve
2
VIN
1.5
VOUT
1
Volts
0.5
0
-0.5
-1
-1.5
-2
0
0.5
1
Time (ms)
1.5
2
Figure 9-2. Input and Output Voltages of the Inverting Amplifier
9.3 System Examples
9.3.1 General Applications
RF = 100 kΩ
VCC +
−
Output
−
3.3 kΩ
R1
Input
TL081
R2
+
15 V
C3
VCC −
TL081
+
CF = 3.3 µF
Output
1 kΩ
R1 = R2 = 2(R3) = 1.5 MΩ
R3
−15 V
C1
C2
C1 = C2 = C3 = 110 pF
2
1
fo =
= 1 kHz
2π R1 C1
3.3 kΩ
9.1 kΩ
Figure 9-4. High-Q Notch Filter
Figure 9-3. 0.5-Hz Square-Wave Oscillator
− 15 V
18 pF
−
TL084
VCC +
18 pF
Output A
+
+
VCC +
88.4 kΩ
−
100 kΩ
VCC −
VCC −
A.
VCC +
−
TL084
6 cos ωt
1 kΩ
15 V
1N4148
88.4 kΩ
VCC +
100 kΩ
VCC+
Output B
+
100 kΩ
100 µF
18 kΩ
(see Note A)
1/2
TL082
18 pF
TL084
100 kΩ
88.4 kΩ
+
Input
1/2
TL082
TL084
−
1 kΩ
VCC +
−
1 µF
1N4148
6 sin ωt
VCC +
1 MΩ
+
1
2π RF CF
−
f=
Output C
18 kΩ
(see Note A)
These resistor values may be adjusted for a symmetrical
output.
Figure 9-6. 100-kHz Quadrature Oscillator
+
Figure 9-5. Audio-Distribution Amplifier
32
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16 kΩ
16 kΩ
220 pF
220 pF
VCC +
43 kΩ
43 kΩ
1/4
TL084
VCC +
VCC +
43 kΩ
1/4
TL084
1/4
TL084
+
+
+
1.5 kΩ
+
−
1/4
TL084
220 pF
VCC +
−
Input
220 pF
30 kΩ
−
43 kΩ
43 kΩ
30 kΩ
1.5 kΩ
VCC −
−
43 kΩ
VCC −
VCC −
Output
B
VCC −
Output A
Output A
Output B
2 kHz/div
Second-Order Bandpass Filter
fo = 100 kHz, Q = 30, GAIN = 4
2 kHz/div
Cascaded Bandpass Filter
fo = 100 kHz, Q = 69, GAIN = 16
Figure 9-7. Positive-Feedback Bandpass Filter
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10 Power Supply Recommendations
CAUTION
Supply voltages larger than 36 V for a single-supply or outside the range of ±18 V for a dual-supply
can permanently damage the device (see Section 6.2).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement, refer to Section 11.
34
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11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
•
•
•
•
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it
is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed
to in parallel with the noisy trace.
Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Section 11.2.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
11.2 Layout Examples
Place components close to
device and to each other to
reduce parasitic errors
Run the input traces as far
away from the supply lines
as possible
RF
NC
NC
IN1í
VCC+
IN1+
OUT
VCCí
NC
VS+
Use low-ESR, ceramic
bypass capacitor
RG
GND
VIN
RIN
GND
Only needed for
dual-supply
operation
GND
VS(or GND for single supply)
VOUT
Ground (GND) plane on another layer
Figure 11-1. Operational Amplifier Board Layout for Noninverting Configuration
RIN
VIN
+
VOUT
RG
RF
Figure 11-2. Operational Amplifier Schematic for Noninverting Configuration
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
36
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-9851501Q2A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629851501Q2A
TL082MFKB
5962-9851501QPA
ACTIVE
CDIP
JG
8
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
9851501QPA
TL082M
5962-9851503Q2A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629851503Q2A
TL084
MFKB
5962-9851503QCA
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9851503QC
A
TL084MJB
Samples
Samples
Samples
Samples
TL081ACD
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
081AC
TL081ACDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
081AC
Samples
TL081ACP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL081ACP
Samples
TL081BCD
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
081BC
TL081BCDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
081BC
Samples
TL081BCP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL081BCP
Samples
TL081CD
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL081C
TL081CDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL081C
Samples
TL081CP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL081CP
Samples
TL081CPE4
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL081CP
Samples
TL081CPSR
ACTIVE
SO
PS
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T081
Samples
TL081HIDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T81V
Samples
TL081HIDCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
1IP
Samples
TL081HIDR
ACTIVE
SOIC
D
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TL081D
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TL081ID
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL081I
TL081IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL081I
Samples
TL081IP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
TL081IP
Samples
TL082ACD
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
082AC
TL082ACDE4
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
082AC
TL082ACDG4
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
082AC
TL082ACDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
082AC
Samples
TL082ACDRE4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
082AC
Samples
TL082ACDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
082AC
Samples
TL082ACP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL082ACP
Samples
TL082ACPSR
ACTIVE
SO
PS
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T082A
Samples
TL082BCD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
082BC
Samples
TL082BCDE4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
082BC
Samples
TL082BCDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
082BC
Samples
TL082BCP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL082BCP
Samples
TL082BCPE4
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL082BCP
Samples
TL082CD
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL082C
TL082CDE4
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL082C
TL082CDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL082C
Samples
TL082CDRE4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL082C
Samples
TL082CDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL082C
Samples
TL082CP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL082CP
Samples
TL082CPSR
ACTIVE
SO
PS
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T082
Samples
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T082
(3)
Samples
(4/5)
(6)
TL082CPSRG4
ACTIVE
SO
PS
8
Samples
TL082CPW
LIFEBUY
TSSOP
PW
8
150
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T082
TL082CPWR
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T082
Samples
TL082CPWRG4
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T082
Samples
TL082HIDDFR
ACTIVE
SOT-23-THIN
DDF
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
082F
Samples
TL082HIDR
ACTIVE
SOIC
D
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TL082D
Samples
TL082HIPWR
ACTIVE
TSSOP
PW
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
082HPW
Samples
TL082ID
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL082I
TL082IDG4
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL082I
TL082IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL082I
Samples
TL082IDRE4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL082I
Samples
TL082IDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL082I
Samples
TL082IP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
TL082IP
Samples
TL082IPE4
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
TL082IP
Samples
TL082IPWR
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
Z082
Samples
TL082MFKB
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629851501Q2A
TL082MFKB
TL082MJG
ACTIVE
CDIP
JG
8
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
TL082MJG
Samples
TL082MJGB
ACTIVE
CDIP
JG
8
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
9851501QPA
TL082M
Samples
TL084ACD
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL084AC
Samples
TL084ACDE4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL084AC
Samples
TL084ACDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL084AC
Samples
Addendum-Page 3
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TL084ACDRE4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL084AC
Samples
TL084ACDRG4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL084AC
Samples
TL084ACN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL084ACN
Samples
TL084ACNSR
ACTIVE
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL084A
Samples
TL084BCD
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL084BC
Samples
TL084BCDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL084BC
Samples
TL084BCDRG4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL084BC
Samples
TL084BCN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL084BCN
Samples
TL084BCNE4
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL084BCN
Samples
TL084CD
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL084C
Samples
TL084CDE4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL084C
Samples
TL084CDG4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL084C
Samples
TL084CDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL084C
Samples
TL084CDRG4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL084C
Samples
TL084CN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL084CN
Samples
TL084CNE4
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL084CN
Samples
TL084CNSR
ACTIVE
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL084
Samples
TL084CPW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T084
Samples
TL084CPWE4
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T084
Samples
TL084CPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
T084
Samples
TL084HIDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TL084HID
Samples
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TL084HIDYYR
ACTIVE
SOT-23-THIN
DYY
14
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T084HDYY
Samples
TL084HIPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TL084PW
Samples
TL084ID
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL084I
Samples
TL084IDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL084I
Samples
TL084IDRE4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL084I
Samples
TL084IDRG4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL084I
Samples
TL084IN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
TL084IN
Samples
TL084INE4
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
TL084IN
Samples
TL084MFK
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
TL084MFK
Samples
TL084MFKB
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629851503Q2A
TL084
MFKB
TL084MJ
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
TL084MJ
TL084MJB
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9851503QC
A
TL084MJB
TL084QD
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TL084Q
Samples
TL084QDG4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TL084Q
Samples
TL084QDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TL084Q
Samples
TL084QDRG4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TL084Q
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
Addendum-Page 5
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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