SLLS185D − DECEMBER 1994 − REVISED JULY 2001
D Meets or Exceeds the Requirements of
D
D
D
D
D
DW OR N PACKAGE
(TOP VIEW)
ANSI TIA/EIA-232-F and ITU V.28
Designed to Support Data Rates up to
120 kbit/s Over 3-m Cable
ESD Protection Exceeds 5 kV on All Pins
Flow-Through Design
Wide-Driver Supply Voltage . . . ±7.5 V to
±15 V
Functionally Interchangeable With Motorola
MC145406 and Texas Instruments
SN75C1406
VDD
1RA
1DY
2RA
2DY
3RA
3DY
VSS
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
1RY
1DA
2RY
2DA
3RY
3DA
GND
description
The TL145406 is a bipolar device containing three independent drivers and receivers that are used to interface
data terminal equipment (DTE) with data circuit-terminating equipment (DCE). The drivers and receivers of the
TL145406 are similar to those of the SN75188 quadruple driver and SN75189A quadruple receiver,
respectively. The pinout matches the flow-through design of the SN75C1406 to reduce the board space required
and to allow easy interconnection. The bipolar circuits and processing of the TL145406 provide a rugged
low-cost solution for this function at the expense of quiescent power and external passive components relative
to the SN75C1406.
The TL145406 complies with the requirements of TIA/EIA-232-F and ITU (formerly CCITT) V.28 standards.
These standards are for data interchange between a host computer and peripheral at signaling rates up to
20 kbit/s. The switching speeds of the TL145406 are fast enough to support rates up to 120 kbit/s with lower
capacitive loads (shorter cables). Interoperability at the higher signaling rates cannot be assured unless the
designer has design control of the cable and of the interface circuits at both ends. For interoperability at signaling
rates to 120 kbit/s, use of TIA/EIA-423-B (ITU V.10) and TIA/EIA-422-B (ITU V.11) standards is recommended.
The TL145406 is characterized for operation from 0°C to 70°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
PLASTIC
DIP
(N)
PLASTIC
SMALL OUTLINE
(DW)
0°C to 70°C
TL145406N
TL145406DW
The DW package also is available taped and reeled. Add
the suffix R to the device type (e.g., TL145406DWR).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
! "#$ ! %#&'" ($)
(#"! " !%$""! %$ *$ $! $+! !#$!
!(( ,-)
(#" %"$!!. ($! $"$!!'- "'#($
$!. '' %$$!)
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1
SLLS185D − DECEMBER 1994 − REVISED JULY 2001
logic symbol†
1RA
2RA
3RA
1DY
2DY
3DY
2
15
4
13
6
11
3
14
5
12
7
10
1RY
2RY
3RY
1DA
2DA
3DA
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
Typical of Each Receiver
RA
2, 4, 6
15, 13, 11
RY
Typical of Each Driver
14, 12, 10
3, 5, 7
DA
DY
schematic (each driver)
To Other Drivers
VDD
ESD
11.6 kΩ
Input
DAx
9.4 kΩ
ESD
75.8 Ω
320 Ω
4.2 kΩ
GND
To Other
Drivers
10.4 kΩ
VSS
3.3 kΩ
68.5 Ω
ESD
To Other Drivers
Resistor values shown are nominal.
2
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ESD
DYx
Output
SLLS185D − DECEMBER 1994 − REVISED JULY 2001
schematic (each receiver)
To Other Receivers
ESD
9 kΩ
5 kΩ
VCC
1.66 kΩ
ESD
RYx
Output
2 kΩ
Input
RAx
ESD
3.8 kΩ
10 kΩ
GND
To Other Receivers
Resistor values shown are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage (see Note 1): VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 V
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −15 V
Input voltage range: Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −15 V to 7 V
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30 V to 30 V
Driver output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −15 V to 15 V
Receiver low-level output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to the network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
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3
SLLS185D − DECEMBER 1994 − REVISED JULY 2001
recommended operating conditions
MIN
NOM
MAX
UNIT
VDD
VSS
Supply voltage
7.5
9
15
V
Supply voltage
−7.5
−9
−15
V
VCC
VIH
Supply voltage
4.5
5
5.5
V
High-level input voltage (driver only)
1.9
VIL
Low-level input voltage (driver only)
IOH
High-level output current
IOL
Low-level output current
TA
Operating free-air temperature
V
0.8
Driver
V
−6
Receiver
−0.5
Driver
mA
6
Receiver
16
0
70
mA
°C
supply currents
PARAMETER
TEST CONDITIONS
All inputs at 1.9 V,
IDD
Supply current from VDD
All inputs at 0.8 V,
All inputs at 1.9 V,
ISS
4
No load
No load
Supply current from VSS
All inputs at 0.8 V,
ICC
No load
Supply current from VCC
All inputs at 5 V,
TYP
MAX
VSS = −9 V
VSS = −12 V
15
VDD = 15 V,
VDD = 9 V,
VSS = −15 V
VSS = −9 V
25
VDD = 12 V,
VDD = 15 V,
VSS = −12 V
VSS = −15 V
5.5
VDD = 9 V,
VDD = 12 V,
VDD = 15 V,
VSS = −9 V
VSS = −12 V
−15
VSS = −15 V
VSS = −9 V
−25
No load
VDD = 9 V,
VDD = 12 V,
No load,
VDD = 15 V,
VCC = 5 V
POST OFFICE BOX 655303
MIN
VDD = 9 V,
VDD = 12 V,
• DALLAS, TEXAS 75265
UNIT
19
4.5
mA
9
−19
−3.2
VSS = −12 V
VSS = −15 V
mA
−3.2
−3.2
13.2
20
mA
SLLS185D − DECEMBER 1994 − REVISED JULY 2001
DRIVER SECTION
electrical characteristics over recommended operating free-air temperture range, VDD = 9 V,
VSS = −9 V, VCC = 5 V (unless otherwise noted)
PARAMETER
VOH
VOL
High-level output voltage
IIH
IIL
High-level input current
IOS(H)
IOS(L)
rO
TEST CONDITIONS
MIN
MAX
RL = 3 kΩ,
See Figure 1
RL = 3 kΩ,
See Figure 1
VI = 5 V,
VI = 0,
See Figure 2
10
µA
Low-level input current
See Figure 2
−1.6
mA
High-level short-circuit output current
(see Note 4)
VIL = 0.8 V,
VO = 0 or VSS,
Low-level short-circuit output current
Output resistance (see Note 5)
7.5
UNIT
VIL = 0.8 V,
VIH = 1.9 V,
Low-level output voltage (see Note 3)
6
TYP
−7.5
V
−6
V
See Figure 1
−4.5
−10
−19.5
mA
VIH = 2 V,
VO = 0 or VDD,
See Figure 1
VCC = VDD = VSS = 0, VO = −2 V to 2 V
4.5
10
19.5
mA
Ω
300
NOTES: 3. The algebraic convention, where the more positive (less negative) limit is designated as maximum, is used in this data sheet for logic
levels only (e.g., if −10 V is maximum, the typical value is a more negative voltage).
4. Output short-circuit conditions must maintain the total power dissipation below absolute maximum ratings.
5. Test conditions are those specified by TIA/EIA-232-F and as listed above.
switching characteristics, VCC = 5 V, VDD = 12 V, VSS = −12 V, TA = 25°C
PARAMETER
tPLH
tPHL
tTLH
tTHL
TYP
MAX
UNIT
Propagation delay time, low- to high-level output
RL = 3 kΩ to 7 kΩ, CL = 15 pF, See Figure 3
315
500
ns
Propagation delay time, high- to low-level output
RL = 3 kΩ to 7 kΩ, CL = 15 pF, See Figure 3
75
175
ns
RL = 3 kΩ to 7 kΩ, CL = 15 pF, See Figure 3
60
100
ns
RL = 3 kΩ to 7 kΩ, CL = 2500 pF,
See Figure 3 and Note 6
1.7
2.5
µs
RL = 3 kΩ to 7 kΩ, CL = 15 pF, See Figure 3
40
75
ns
RL = 3 kΩ to 7 kΩ, CL = 2500 pF,
See Figure 3 and Note 7
1.5
2.5
µs
Transition time, low- to high-level output
Transition time, high- to low-level output
TEST CONDITIONS
MIN
NOTES: 6. Measured between −3-V and 3-V points of the output waveform (TIA/EIA-232-F conditions). All unused inputs are tied.
7. Measured between 3-V and −3-V points of the output waveform (TIA/EIA-232-F conditions). All unused inputs are tied.
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5
SLLS185D − DECEMBER 1994 − REVISED JULY 2001
RECEIVER SECTION
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
See Figure 5
TA = 25°C
TA = 0°C to 70°C
MIN
TYPĔ
MAX
1.75
1.9
2.3
VIT+
Positive-going threshold voltage
VIT−
Vhys
Negative-going threshold voltage
VOH
High-level output voltage
IOH = −0.5 mA
VIH = 0.75 V
Inputs open
VOL
Low-level output voltage
IOL = 10 mA,
VI = 25 V,
VI = 3 V
See Figure 5
3.6
VI = 3 V,
VI = −25 V,
See Figure 5
0.43
See Figure 5
−3.6
VI = −3 V,
See Figure 5
−0.43
0.75
Input hysteresis (VIT+ − VIT−)
IIH
High-level input current
IIL
Low-level input current
1.55
2.3
0.97
1.25
0.5
2.6
V
V
V
4
5
V
2.6
0.2
IOS
Short-circuit output current
† All typical values are at TA = 25°C, VCC = 5, VDD = 9 V, and VSS = −9 V.
UNIT
0.45
V
8.3
mA
−8.3
mA
−3.4
−12
mA
TYP
MAX
UNIT
switching characteristics, VCC = 5 V, VDD = 12 V, VSS = −12 V, TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
tPLH
tPHL
Propagation delay time, low- to high-level output
CL = 50 pF,
RL = 5 kΩ,
See Figure 6
107
425
ns
Propagation delay time, high- to low-level output
CL = 50 pF,
RL = 5 kΩ,
See Figure 6
42
150
ns
tTLH
tTHL
Transition time, low- to high-level output
CL = 50 pF,
RL = 5 kΩ,
See Figure 6
175
400
ns
Transition time, high- to low-level output
CL = 50 pF,
RL = 5 kΩ,
See Figure 6
16
60
ns
PARAMETER MEASUREMENT INFORMATION
IOS(L)
VDD
VCC
VDD or GND
VDD
VCC
−IOS(H)
IIH
VSS or GND
VI
VI
VO
−IIL
RL = 3 kΩ
VI
VSS
Figure 1. Driver Test Circuit
for VOH, VOL, IOS(H), and IOS(L)
6
POST OFFICE BOX 655303
VSS
Figure 2. Driver Test Circuit for IIH and IIL
• DALLAS, TEXAS 75265
SLLS185D − DECEMBER 1994 − REVISED JULY 2001
PARAMETER MEASUREMENT INFORMATION
3V
Input
Input
1.5 V
1.5 V
VDD
VCC
Pulse
Generator
(see Note B)
0
tPHL
CL
(see Note A)
RL
90%
tPLH
50%
10%
Output
VSS
90%
50%
10%
VOL
tTHL
TEST CIRCUIT
VOH
tTLH
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: tw = 25 µs, PRR = 20 kHz, ZO = 50 Ω, tr = tf < 50 ns.
Figure 3. Driver Test Circuit and Voltage Waveforms
VDD
VCC
VDD
VCC
VIT,
VI
−IOS
−IOH
VOH
VOL
VI
IOL
VSS
VSS
Figure 5. Receiver Test Circuit
for VIT, VOH, and VOL
Figure 4. Receiver Test Circuit for IOS
4V
Input
Input
50%
50%
VDD
VCC
Pulse
Generator
(see Note B)
0
tPHL
CL
(see Note A)
RL
90%
50%
10%
Output
VSS
tPLH
50%
10%
tTHL
90%
VOH
VOL
tTLH
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: tw = 25 µs, PRR = 20 kHz, ZO = 50 Ω, tr = tf < 50 ns.
Figure 6. Receiver Propagation and Transition Times
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7
SLLS185D − DECEMBER 1994 − REVISED JULY 2001
TYPICAL CHARACTERISTICS
DRIVER
OUTPUT CURRENT
vs
OUTPUT VOLTAGE
DRIVER
VOLTAGE TRANSFER CHARACTERISTICS
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
12
20
VDD = 12 V, VSS = −12 V
9
VDD = 9 V, VSS = −9 V
12
IO − Output Current − mA
6
VO − Output Voltage − V
16
VDD = 6 V, VSS = −6 V
3
0
−3
−6
−9
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
8
0
0.2
0.4 0.6
VDD = 9 V
VSS = −9 V
TA = 25°C
0
−8
1.2
1.4 1.6
1.8
VOH (VI = 0.8 V)
−20
−16
2
−12
−8
−4
DRIVER
SHORT-CIRCUIT OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
8
12
16
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
DRIVER
SLEW RATE
vs
LOAD CAPACITANCE
1000
IOS(L) (VI = 1.9 V)
9
6
SR − Slew Rate − V/µs
I OS − Short-Circuit Output Current − mA
4
Figure 8
Figure 7
ÎÎÎÎÎ
ÎÎÎÎÎ
3
VDD = 9 V
VSS = −9 V
VO = 0
0
−3
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
−6
IOS(H) (VI = 0.8 V)
−9
−12
0
10
20
30
40
50
60
70
TA − Free-Air Temperature − °C
100
10
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
1
10
VDD = 9 V
VSS = −9 V
RL = 3 kΩ
TA = 25°C
100
Figure 10
POST OFFICE BOX 655303
1000
CL − Load Capacitance − pF
Figure 9
8
0
VO − Output Voltage − V
VI − Input Voltage − V
12
3-kΩ
Load Line
ÎÎÎÎÎ
−16
1
ÎÎÎÎ
ÎÎÎÎ
−4
−12
0.8
VOL (VI = 1.9 V)
4
RL = 3 kΩ
TA = 25°C
−12
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎ
• DALLAS, TEXAS 75265
10000
SLLS185D − DECEMBER 1994 − REVISED JULY 2001
TYPICAL CHARACTERISTICS
RECEIVER
INPUT THRESHOLD VOLTAGE
vs
SUPPLY VOLTAGE
RECEIVER
INPUT THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE
2.4
2
1.6
VIT+
V IT − Input Threshold Voltage − V
V IT − Input Threshold Voltage − V
VIT+
1.8
2.2
1.8
1.6
1.4
1.2
1
VIT−
0.8
0.6
0.4
ÎÎÎ
2
1.4
ÎÎ
ÎÎ
1.2
VIT−
1
0.8
0.6
0.4
0.2
0
0
10
20
30
40
50
60
2
70
3
TA − Free-Air Temperature − °C
4
Figure 11
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Amplitude − V
4
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
VCC = 5 V
TA = 25°C
See Note A
16
CC = 300 pF
14
CC = 500 pF
3
CC = 12 pF
2
CC = 100 pF
1
0
0
40
100
400
7
8
9
10
RECEIVER
MAXIMUM SUPPLY VOLTAGE
vs
FREE-AIR TEMPERATURE
1000
4000 10000
tw − Pulse Duration − ns
NOTE A: This figure shows the maximum amplitude of a
positive-going pulse that, starting from 0, does not cause a
change of the output level.
VCC − Supply Voltage − V
5
6
Figure 12
RECEIVER
NOISE REJECTION
6
5
VCC − Supply Voltage − V
12
10
8
6
4
ÎÎÎÎÎÎÎÎÎÎÎ
2
RL ≥ 3 kΩ (from each output to GND)
0
0
10
20
30
40
50
60
70
TA − Free-Air Temperature − °C
Figure 13
Figure 14
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9
SLLS185D − DECEMBER 1994 − REVISED JULY 2001
APPLICATION INFORMATION
Diodes placed in series with the VDD and VSS leads protect the TL145406 during the fault condition in which the device
outputs are shorted to ±15 V and the power supplies are at low. Diodes also provide low-impedance paths to ground
(see Figure 15).
VDD
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
TL145406
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
VDD
Output
±15 V
TL145406
VSS
VSS
Figure 15. Power-Supply Protection to Meet Power-Off Fault Conditions of ANSI TIA/EIA-232-F
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
10-May-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TL145406DW
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL145406DWE4
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL145406DWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL145406DWR
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL145406DWRE4
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL145406DWRG4
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL145406N
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TL145406NE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TL145406DWR
Package Package Pins
Type Drawing
SOIC
DW
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
10.75
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.7
2.7
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TL145406DWR
SOIC
DW
16
2000
367.0
367.0
38.0
Pack Materials-Page 2
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