TL16C2550-Q1
SLWS232 – DECEMBER 2011
www.ti.com
1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS
Check for Samples: TL16C2550-Q1
FEATURES
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Qualified for Automotive Applications
Programmable Auto-RTS and Auto-CTS
In Auto-CTS Mode, CTS Controls Transmitter
In Auto-RTS Mode, RCV FIFO Contents, and
Threshold Control RTS
Serial and Modem Control Outputs Drive a
RJ11 Cable Directly When Equipment Is on the
Same Power Drop
Capable of Running With All Existing
TL16C450 Software
After Reset, All Registers Are Identical to the
TL16C450 Register Set
Up to 24-MHz Clock Rate for up to 1.5-Mbaud
Operation With VCC = 5 V
Up to 20-MHz Clock Rate for up to 1.25-Mbaud
Operation With VCC = 3.3 V
Up to 16-MHz Clock Rate for up to 1-Mbaud
Operation With VCC = 2.5 V
Up to 10-MHz Clock Rate for up to 625-kbaud
Operation With VCC = 1.8 V
In the TL16C450 Mode, Hold and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and Serial
Data
Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1 to
(2 16 -1) and Generates an Internal 16 × Clock
Standard Asynchronous Communication Bits
(Start, Stop, and Parity) Added to or Deleted
From the Serial Data Stream
5-V, 3.3-V, 2.5-V, and 1.8-V Operation
Independent Receiver Clock Input
Transmit, Receive, Line Status, and Data Set
Interrupts Independently Controlled
Fully Programmable Serial Interface
Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation
and Detection
– 1-, 1 1/2-, or 2-Stop Bit Generation
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– Baud Generation (DC to 1 Mbit/s)
False-Start Bit Detection
Complete Status Reporting Capabilities
3-State Output TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus
Line Break Generation and Detection Internal
Diagnostic Capabilities:
– Loopback Controls for Communications
Link Fault Isolation
– Break, Parity, Overrun, and Framing Error
Simulation
Fully Prioritized Interrupt System Controls
Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
Available in 48-Pin TQFP (PFB) Package
Pin Compatible with TL16C752B (48-Pin
Package PFB)
APPLICATIONS
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Automotive Applications
Point-of-Sale Terminals
Gaming Terminals
Portable Applications
Router Control
Cellular Data
Factory Automation
DESCRIPTION
The TL16C2550 is a dual universal asynchronous
receiver and transmitter (UART). It incorporates the
functionality of two TL16C550D UARTs, each UART
having its own register set and FIFOs. The two
UARTs share only the data bus interface and clock
source, otherwise they operate independently.
Another name for the uart function is Asynchronous
Communications Element (ACE), and these terms will
be used interchangeably. The bulk of this document
describes the behavior of each ACE, with the
understanding that two such devices are incorporated
into the TL16C2550.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
TL16C2550-Q1
SLWS232 – DECEMBER 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
Each ACE is a speed and voltage range upgrade of the TL16C550C, which in turn is a functional upgrade of the
TL16C450. Functionally equivalent to the TL16C450 on power up or reset (single character or TL16C450 mode),
each ACE can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead by
buffering received and to be transmitted characters. Each receiver and transmitter store up to 16 bytes in their
respective FIFOs, with the receive FIFO including three additional bits per byte for error status. In the FIFO
mode, a selectable autoflow control feature can significantly reduce software overload and increase system
efficiency by automatically controlling serial data flow using handshakes between the RTS output and CTS input,
thus eliminating overruns in the receive FIFO.
Each ACE performs serial-to-parallel conversions on data received from a peripheral device or modem and
stores the parallel data in its receive buffer or FIFO, and each ACE performs parallel-to-serial conversions on
data sent from its CPU after storing the parallel data in its transmit buffer or FIFO. The CPU can read the status
of either ACE at any time. Each ACE includes complete modem control capability and a processor interrupt
system that can be tailored to the application.
Each ACE includes a programmable baud rate generator capable of dividing a reference clock with divisors from
1 to 65535, thus producing a 16× internal reference clock for the transmitter and receiver logic. Each ACE
accommodates up to a 1.5-Mbaud serial data rate (24-MHz input clock). As a reference point, that speed would
generate a 667-ns bit time and a 6.7-µs character time (for 8,N,1 serial data), with the internal clock running at
24 MHz.
Each ACE has a TXRDY and RXRDY output that can be used to interface to a DMA controller.
D4
D3
D2
D1
D0
TXRDYA
VCC
RIA
CDA
DSRA
CTSA
NC
PFB PACKAGE
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
D5
D6
D7
RXB
RXA
TXRDYB
TXA
TXB
OPB
CSA
CSB
NC
1
36
2
35
3
34
4
33
5
32
6
7
TL16C2550PFB
31
30
8
29
9
28
10
27
11
26
12
25
RESET
DTRB
DTRA
RTSA
OPA
RXRDYA
INTA
INTB
A0
A1
A2
NC
XTAL1
XTAL2
IOW
CDB
GND
RXRDYB
IOR
DSRB
RIB
RTSB
CTSB
NC
13 14 15 16 17 18 19 20 21 22 23 24
NC - No internal connection
2
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TL16C2550 Block Diagram
UART Channel A
TXA
A2 − A0
16 Byte Tx FIFO
D7 − D0
Tx
CSA
CTSA
OPA, DTRA
UART Regs
CSB
BAUD
Rate
Gen
IOR
IOW
DSRA, RIA, CDA
RTSA
16 Byte Rx FIFO
Rx
RXA
INTA
Data Bus
Interface
INTB
UART Channel B
TXRDYA
TXB
TXRDYB
16 Byte Tx FIFO
Tx
RXRDYA
CTSB
OPB, DTRB
RXRDYB
UART Regs
BAUD
Rate
Gen
RESET
RTSB
16 Byte Rx FIFO
Crystal
OSC
Buffer
XTAL1
XTAL2
DSRB, RIB, CDB
Rx
RXB
VCC
GND
DEVICE INFORMATION
PIN FUNCTIONS
PIN
NAME
PFB NO.
I/O
DESCRIPTION
A0
28
I
Address 0 select bit. Internal registers address selection
A1
27
I
Address 1 select bit. Internal registers address selection
A2
26
I
Address 2 select bit. Internal registers address selection
CDA, CDB
40, 16
I
Carrier detect (active low). These inputs are associated with individual UART channels A and B. A low
on these pins indicates that a carrier has been detected by the modem for that channel. The state of
these inputs is reflected in the modem status register (MSR).
CSA, CSB
10, 11
I
Chip select A and B (active low). These pins enable data transfers between the user CPU and the
TL16C2550 for the channel(s) addressed. Individual UART sections (A, B) are addressed by providing
a low on the respective CSA and CSB pins.
Clear to send (active low). These inputs are associated with individual UART channels A and B. A
logic low on the CTS pins indicates the modem or data set is ready to accept transmit data from the
2550. Status can be tested by reading MSR bit 4. These pins only affect the transmit and receive
operations when auto CTS function is enabled through the enhanced feature register (EFR) bit 7, for
hardware flow control operation.
CTSA, CTSB
38, 23
I
D0-D4
D5-D7
44 -48
1 -3
I/O
Data bus (bidirectional). These pins are the eight bit, 3-state data bus for transferring information to or
from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive
serial data stream.
DSRA, DSRB
39, 20
I
Data set ready (active low). These inputs are associated with individual UART channels A and B. A
logic low on these pins indicates the modem or data set is powered on and is ready for data exchange
with the UART. The state of these inputs is reflected in the modem status register (MSR).
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PIN FUNCTIONS (continued)
PIN
NAME
PFB NO.
DTRA, DTRB
GND
34, 35
I/O
DESCRIPTION
O
Data terminal ready (active low). These outputs are associated with individual UART channels A and
B. A logic low on these pins indicates that theTLl16C2550 is powered on and ready. These pins can
be controlled through the modem control register. Writing a 1 to MCR bit 0 sets the DTR output to low,
enabling the modem. The output of these pins is high after writing a 0 to MCR bit 0, or after a reset.
17
Signal and power ground.
30, 29
O
Interrupt A and B (active high). These pins provide individual channel interrupts, INT A and B. INT A
and B are enabled when MCR bit 3 is set to a logic 1, interrupt sources are enabled in the interrupt
enable register (IER). Interrupt conditions include: receiver errors, available receiver buffer data,
available transmit buffer space or when a modem status flag is detected. INTA-B are in the
high-impedance state after reset.
IOR
19
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Read input (active low strobe). A high to low transition on IOR will load the contents of an internal
register defined by address bits A0-A2 onto the TL16C2550 data bus (D0-D7) for access by an
external CPU.
IOW
15
I
Write input (active low strobe). A low to high transition on IOW will transfer the contents of the data
bus (D0-D7) from the external CPU to an internal register that is defined by address bits A0-A2 and
CSA and CSB
NC
12, 24, 25,
37
INTA, INTB
No internal connection
32, 9
O
User defined outputs. This function is associated with individual channels A and B. The state of these
pins is defined by the user through the software settings of the MCR register, bit 3. INTA-B are set to
active mode and OP to a logic 0 when the MCR-3 is set to a logic 1. INTA-B are set to the 3-state
mode and OP to a logic 1 when MCR-3 is set to a logic 0. See bit 3, modem control register (MCR bit
3). The output of these two pins is high after reset.
RESET
36
I
Reset. RESET will reset the internal registers and all the outputs. The UART transmitter output and
the receiver input will be disabled during reset time. See TL16C2550 external reset conditions for
initialization details. RESET is an active-high input.
RIA, RIB
41, 21
I
Ring indicator (active low). These inputs are associated with individual UART channels A and B. A
logic low on these pins indicates the modem has received a ringing signal from the telephone line. A
low to high transition on these input pins generates a modem status interrupt, if enabled. The state of
these inputs is reflected in the modem status register (MSR)
33, 22
O
Request to send (active low). These outputs are associated with individual UART channels A and B. A
low on the RTS pin indicates the transmitter has data ready and waiting to send. Writing a 1 in the
modem control register (MCR bit 1) sets these pins to low, indicating data is available. After a reset,
these pins are set to high. These pins only affects the transmit and receive operation when auto RTS
function is enabled through the enhanced feature register (EFR) bit 6, for hardware flow control
operation.
RXA, RXB
5, 4
I
Receive data input. These inputs are associated with individual serial channel data to the 2550. During
the local loopback mode, these RX input pins are disabled and TX data is internally connected to the
UART RX input internally.
RXRDYA,
RXRDYB
31, 18
O
Receive ready (active low). RXRDY A and B goes low when the trigger level has been reached or a
timeout interrupt occurs. They go high when the RX FIFO is empty or there is an error in RX FIFO.
TXA, TXB
7, 8
O
Transmit data. These outputs are associated with individual serial transmit channel data from the
2550. During the local loopback mode, the TX input pin is disabled and TX data is internally connected
to the UART RX input.
TXRDYA,
TXRDYB
43, 6
O
Transmit ready (active low). TXRDY A and B go low when there are at least a trigger level numbers of
spaces available. They go high when the TX buffer is full.
VCC
42
I
Power supply inputs.
XTAL1
13
I
Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock input. A
crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see
Figure 14). Alternatively, an external clock can be connected to XTAL1 to provide custom data rates.
XTAL2
14
O
Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a crystal oscillator
output or buffered a clock output.
OPA, OPB
RTSA, RTSB
4
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DETAILED DESCRIPTION
Autoflow Control (see Figure 1)
Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input must be active before
the transmitter FIFO can emit data. With auto-RTS, RTS becomes active when the receiver needs more data and
notifies the sending serial device. When RTS is connected to CTS, data transmission does not occur unless the
receiver FIFO has space for the data; thus, overrun errors are eliminated using ACE1 and ACE2 from a
TLC16C2550 with the autoflow control enabled. If not, overrun errors occur when the transmit data rate exceeds
the receiver FIFO read latency.
ACE1
ACE2
Serial to
Parallel
RX
TX
Parallel
to Serial
RCV
FIFO
XMT
FIFO
Flow
Control
RTS
CTS
Flow
Control
D7 −D0
D7 −D0
Parallel
to Serial
TX
RX
Serial to
Parallel
XMT
FIFO
RCV
FIFO
Flow
Control
CTS
RTS
Flow
Control
Figure 1. Autoflow Control (Auto-RTS and Auto-CTS) Example
Auto-CTS (See Figure 2)
The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the next
byte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the last
stop bit that is currently being sent (see Figure 1). The auto-CTS function reduces interrupts to the host system.
When flow control is enabled, CTS level changes do not trigger host interrupts because the device automatically
controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the transmit FIFO and a
receiver overrun error may result.
Auto-RTS (See Figure 3 and Figure 4)
Auto-RTS data flow control originates in the receiver timing and control block (see functional block diagram) and
is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level of
1, 4, or 8 (see Figure 2), RTS is deasserted. With trigger levels of 1, 4, and 8, the sending ACE may send an
additional byte after the trigger level is reached (assuming the sending ACE has another byte to send) because it
may not recognize the deassertion of RTS until after it has begun sending the additional byte. RTS is
automatically reasserted once the RCV FIFO is emptied by reading the receiver buffer register.
When the trigger level is 14 (see Figure 3), RTS is deasserted after the first data bit of the 16th character is
present on the RX line. RTS is reasserted when the RCV FIFO has at least one available byte space.
Enabling Autoflow Control and Auto-CTS
Autoflow control is enabled by setting modem control register bits 5 (autoflow enable or AFE) and 1 (RTS) to a 1.
Autoflow incorporates both auto-RTS and auto-CTS. When only auto-CTS is desired, bit 1 in the modem control
register should be cleared (this assumes that a control signal is driving CTS).
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Auto-CTS and Auto-RTS Functional Timing
Start
SOUT
Bits 0−7
Start
Stop
Bits 0−7 Stop
Start
Bits 0−7 Stop
CTS
Figure 2. CTS Functional Timing Waveforms
SIN
Start
Byte N
Stop
Start
Byte N+1
Start
Stop
Byte
Stop
RTS
RD
(RD RBR)
1
2
N
N+1
Figure 3. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 1, 4, or 8 Bytes
SIN
RTS
Byte 14
Byte 15
Start
Byte 16
Stop
Start
Byte 18 Stop
RTS Released After the
First Data Bit of Byte 16
RD
(RD RBR)
Figure 4. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 14 Bytes
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Internal
Data Bus
3 −1
48−44
D(7 −0)
XTAL1
XTAL2
A0
A1
A2
13
14
8
S
e
l
e
c
t
Data
Bus
Buffer
Crystal
OSC
Buffer
Receiver
FIFO
8
Receiver
Shift
Register
Receiver
Buffer
Register
Receiver
Timing and
Control
Line
Control
Register
CSB
RESET
IOR
IOW
TXRDYA
RXRDYA
TXRDYB
RXRDYB
27
Divisor
Latch (LS)
26
10
11
36
19
Transmitter
Timing and
Control
Line
Status
Register
Select
and
Control
Logic
Transmitter
FIFO
Transmitter
Holding
Register
15
43
31
8
Modem
Control
Register
6
S
e
l
e
c
t
8
Transmitter
Shift
Register
Autoflow
Control
(AFE)
7, 8
38, 23
18
34, 35
8
Modem
Control
Logic
39, 20
40, 16
41, 21
32, 9
INTA, B
42
17
Power
Supply
Interrupt
Enable
Register
Interrupt
Identification
Register
TXA, B
8
30, 29
GND
33, 22
RTSA, B
Baud
Generator
Modem
Status
Register
VCC
RXA, B
28
Divisor
Latch (MS)
CSA
5,4
8
CTSA, B
DTRA, B
DSRA, b
CDA,B
RIA, B
OPA, B
Interrupt
Control
Logic
8
FIFO
Control
Register
A.
Pin numbers shows are for 48-pin TQFP PFB package.
Figure 5. Functional Block Diagram
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ORDERING INFORMATION
TA
–40°C to 85°C
PACKAGE
TQFP - PFB
ORDERABLE PART NAME
TOP-SIDE MARKING
TL16C2550IPFBRQ1
TL2550RQ
Reel of 1000
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
UNIT
(2)
–0.5 V to 7 V
VCC
Supply voltage range,
VI
Input voltage range at any input
–0.5 V to 7 V
VO
Output voltage range
–0.5 V to 7 V
TA
Operating free-air temperature, TL16C2550
0°C to 70°C
TA
Operating free-air temperature, TL16C2550I
–40°C to 85°C
Tstg
Storage temperature range
–65°C to 150°C
ESD
(1)
(2)
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260°C
Human Body Model (HBM)
2000 V
Charged Device Model (CDM)
1000 V
Machine Model (MM)
150 V
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to VSS.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM MAX
UNIT
1.8 V ±10%
VCC
Supply voltage
VI
Input voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VO
Output voltage
IOH
High-level output current (all outputs)
IOL
Low-level output current (all outputs)
1.62
1.8
1.98
V
0
VCC
V
1.4
1.98
V
–0.3
0.4
V
0
VCC
V
0.5
mA
1
mA
10
MHz
Oscillator/clock speed
2.5 V ±10%
VCC
Supply voltage
VI
Input voltage
2.25
2.75
V
0
VCC
V
VIH
VIL
High-level input voltage
1.8
2.75
V
Low-level input voltage
–0.3
0.6
VO
Output voltage
V
0
VCC
V
IOH
High-level output current (all outputs)
1
IOL
Low-level output current (all outputs)
2
mA
16
MHz
Oscillator/clock speed
8
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2.5
mA
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RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
NOM MAX
UNIT
3.3 V ±10%
VCC
Supply voltage
3
VI
Input voltage
0
VIH
High-level input voltage
VIL
Low-level input voltage
VO
Output voltage
IOH
IOL
2.5
2.75
V
VCC
V
0.7VCC
V
0.3V
V
CC
0
VCC
V
High-level output current (all outputs)
1.8
mA
Low-level output current (all outputs)
3.2
mA
Oscillator/clock speed
20
MHz
5.5
V
VCC
V
5 V ±10%
VCC
Supply voltage
VI
Input voltage
VIH
4.5
5
0
All except XTAL1, XTAL2
High-level input voltage
2
XTAL1, XTAL2
V
0.7VCC
All except XTAL1, XTAL2
0.8
V
VIL
Low-level input voltage
VO
Output voltage
IOH
High-level output current (all outputs)
4
mA
IOL
Low-level output current (all outputs)
4
mA
24
MHz
MAX
UNIT
0.3V
XTAL1, XTAL2
CC
0
VCC
Oscillator/clock speed
V
ELECTRICAL CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
MIN TYP (1)
TEST CONDITIONS
1.8 V NOMINAL
VOH
High-level output
voltage (1)
VOL
Low-level output voltage (2) IOL = 1 mA
IOH = –0.5 mA
(3)
1.3
V
0.5
V
II
Input current
VCC = 1.98 V, VSS = 0, VI = 0 to 1.98 V, All other terminals floating
10
µA
IOZ
High-impedance-state
output current (3)
VCC = 1.98 V, VSS = 0, VI = 0 to 1.98 V, Chip slected in write mode
or chip deselcted
±20
µA
ICC
Supply current (3)
VCC = 1.98 V, TA = 0°C, RXA, RXB, DSRA, DSRB, CDA, CDB,
CTSA, CTSB, RIA, and RIB at 1.4 V, All other inputs at 0.4 V,
XTAL1 at 10 MHz, No load on outputs
1.5
mA
Ci(CLK)
Clock input impedance (3)
15
20
pF
20
30
pF
6
10
pF
10
20
pF
CO(CLK)
Clock output impedance
CI
Input impedance (3)
CO
Output impedance (3)
(1)
(2)
(3)
(3)
VCC = 0, VSS = 0, f = 1 MHz, TA = 25°C, All other terminals
grounded
All typical values are at VCC = 1.8 V and TA = 25°C.
These parameters apply for all outputs except XTAL2.
Not production tested.
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ELECTRICAL CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
MIN TYP (1)
TEST CONDITIONS
MAX
UNIT
2.5 V NOMINAL
VOH
High-level output
voltage (2) (3)
IOH = –1 mA
VOL
Low-level output
voltage (2) (3)
IOL = 2 mA
0.5
V
II
Input current
VCC = 5.5 V, VSS = 0, VI = 0 to 2.75 V, All other terminals floating
10
µA
IOZ
High-impedance-state
output current
VCC = 2.75 V, VSS = 0, VI = 0 to 2.75 V, Chip slected in write mode
or chip deselcted
±20
µA
ICC
Supply current (3)
VCC = 2.75 V, TA = 0°C, RXA, RXB, DSRA, DSRB, CDA, CDB,
CTSA, CTSB, RIA, and RIB at 1.8 V, All other inputs at 0.6 V,
XTAL1 at 16 MHz, No load on outputs
2.5
mA
Ci(CLK)
Clock input impedance (3)
15
20
pF
CO(CLK)
20
30
pF
CI
Clock output impedance (3) VCC = 0, VSS = 0, f = 1 MHz, TA = 25°C, All other terminals
grounded
Input impedance (3)
6
10
pF
CO
Output impedance (3)
10
20
pF
MIN TYP (1)
MAX
(1)
(2)
(3)
1.8
V
All typical values are at VCC = 2.5 V and TA = 25°C.
These parameters apply for all outputs except XTAL2.
Not production tested.
ELECTRICAL CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
UNIT
3.3 V NOMINAL
High-level output
voltage (2)
VOH
IOH = –1.8 mA
(2)
2.4
V
VOL
Low-level output voltage
IOL = 3.2 mA
0.5
V
II
Input current
VCC = 3.6 V, VSS = 0, VI = 0 to 3.6 V, All other terminals floating
10
µA
IOZ
High-impedance-state
output current
VCC = 3.6 V, VSS = 0, VI = 0 to 3.6 V, Chip slected in write mode or
chip deselcted
±20
µA
ICC
Supply current (3)
VCC = 3.6 V, TA = 0°C, RXA, RXB, DSRA, DSRB, CDA, CDB,
CTSA, CTSB, RIA, and RIB at 2 V, All other inputs at 0.8 V,
XTAL1 at 20 MHz, No load on outputs
4
mA
Ci(CLK)
Clock input impedance (3)
15
20
pF
CO(CLK)
20
30
pF
CI
Clock output impedance (3) VCC = 0, VSS = 0, f = 1 MHz, TA = 25°C, All other terminals
grounded
Input impedance (3)
6
10
pF
CO
Output impedance (3)
10
20
pF
(1)
(2)
(3)
10
All typical values are at VCC = 3.3 V and TA = 25°C.
These parameters apply for all outputs except XTAL2.
Not production tested.
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ELECTRICAL CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
MIN TYP (1)
TEST CONDITIONS
MAX
UNIT
5 V NOMINAL
VOH
High-level output
voltage (2)
VOL
Low-level output voltage (2) IOL = 4 mA
0.4
V
II
Input current
VCC = 5.5 V, VSS = 0, VI = 0 to 5.5 V, All other terminals floating
10
µA
IOZ
High-impedance-state
output current
VCC = 5.5 V, VSS = 0, VI = 0 to 5.5 V, Chip slected in write mode
or chip deselcted
±20
µA
ICC
Supply current
VCC = 5.5 V, TA = 0°C, RXA, RXB, DSRA, DSRB, CDA, CDB,
CTSA, CTSB, RIA, and RIB at 2 V, All other inputs at 0.8 V,
XTAL1 at 24 MHz, No load on outputs
7.5
mA
Ci(CLK)
Clock input impedance (3)
15
20
pF
20
30
pF
6
10
pF
10
20
pF
CO(CLK)
Clock output impedance
CI
Input impedance (3)
CO
Output impedance (3)
(1)
(2)
(3)
IOH = –4 mA
(3)
4
V
VCC = 0, VSS = 0, f = 1 MHz, TA = 25°C, All other terminals
grounded
All typical values are at VCC = 5 V and TA = 25°C.
These parameters apply for all outputs except XTAL2.
Not production tested.
TIMING REQUIREMENTS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ALT.
SYMBOL
FIGURE
TEST
CONDITIONS
1.8 V
2.5 V
3.3 V
5V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
tw8
Pulse duration, RESET
1
1
1
1
µs
tw1
Pulse duration, clock high
tXH
6
40
25
20
18
ns
tw2
Pulse duration, clock low
tXL
8
115
80
62
57
ns
tcR
Cycle time, read (tw7 + td8 + th7)
RC
8
115
80
62
57
ns
tcW
Cycle time, write (tw6 + td5 + th4)
WC
7
115
80
62
57
ns
tw6
Pulse duration, IOW
tIOW
7
80
55
45
40
ns
tw7
Pulse duration, IOR
tIOR
8
80
55
45
40
ns
tSU3
Setup time, data valid before IOW↑
tDS
7
25
20
15
15
ns
th3
Hold time, CS valid after IOW↑
tWCS
7
0
0
0
0
ns
th4
Hold time, address valid after IOW↑
tWA
7
20
15
10
10
ns
th5
Hold time, data valid after IOW↑
tDH
7
15
10
5
5
ns
th6
Hold time, chip select valid after IOR↑
tRCS
8
0
0
0
0
ns
th7
Hold time, address valid after IOR↑
tRA
8
20
15
10
10
ns
td4
Delay time, CS valid before IOW↓
tCSW
7
0
0
0
0
ns
td5
Delay time, address valid before IOW↓
tAW
7
15
10
7
7
ns
td7
Delay time, CS valid to IOR↓
tCSR
8
0
0
0
0
ns
td8
Delay time, address valid to IOR↓
tAR
8
15
10
7
7
td10
Delay time, IOR↓ to data valid
tRVD
8
CL = 30 pF
55
35
25
20
ns
td11
Delay time, IOR↓ to floating data
tHZ
8
CL = 30 pF
40
30
20
20
ns
tRESET
ns
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RECEIVER SWITCHING CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)
LIMITS
ALT.
SYMBOL
PARAMETER
FIGURE
TEST
CONDITIONS
1.8 V
MIN
td12
Delay time, RCLK to sample
td13
Delay time, stop to set INT or read RBR to
LSI interrupt or stop to RXRDY↓
tSCD
9
tSINT
8, 9, 10,
11, 12
tRINT
8, 9, 10,
11, 12
CL = 30 pF
td14
Delay time, read RBR/LSR to reset INT
td26
Delay time, RCV threshold byte to RTS↑
19
td27
Delay time, read of last byte in receive FIFO
to RTS↓
td28
td29
(1)
(2)
2.5 V
MAX
MIN
3.3 V
MAX
20
MIN
5V
MAX
15
MIN
10
1
1
1
100
90
80
UNIT
MAX
10
ns
RCLK
cycle
1
70
ns
CL = 30 pF
2
baudout
cycles
19
CL = 30 pF
2
baudout
cycles
Delay time, first data bit of 16th character to
RTS↑
20
CL = 30 pF
2
baudout
cycles
Delay time, RBRRD low to RTS↓
20
CL = 30 pF
2
baudout
cycles
In the FIFO mode, the read cycle (RC) = 1 baudclock (min) between reads of the receive FIFO and the status registers (interrupt
identification register or line status register)
Not production tested.
TRANSMITTER SWITCHING CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)
LIMITS
ALT.
SYMBOL
PARAMETER
FIGURE
TEST
CONDITIONS
1.8 V
2.5 V
3.3 V
5V
MAX
MIN
MAX
MIN
MAX
MIN
MAX
8
24
baudout
cycles
10
baudout
cycles
td15
Delay time, initial write to transmit start
tIRS
14
8
24
8
24
8
24
td16
Delay time, start to INT
tSTI
14
8
10
8
10
8
10
td17
Delay time, IOW (WR THR) to reset INT
tHR
14
(3)
UNIT
MIN
CL = 30 pF
70
tIR
14
CL = 30 pF
70
50
35
35
td20
Delay time, write to TXRDY inactive
tWXI
15, 16
CL = 30 pF
60
45
35
35
ns
9
baudout
cycles
24
baudout
cycles
tSU4
Setup time, CTS↑ before midpoint of stop bit
18
td25
Delay time, CTS low to TX↓
18
(1)
(2)
(3)
30
CL = 30 pF
9
20
9
10
24
16
ns
Delay time, read IOR↑ to reset INT
(THRE (3))
9
34
34
td19
CL = 30 pF
16
ns
baudout
cycles
14
15, 16
34
50
tSI
tSXA
16
8
Delay time, initial write to INT (THRE )
Delay time, start to TXRDY active
34
50
td18
td21
16
60
10
24
24
ns
In the FIFO mode, the read cycle (RC) = 1 baudclock (min) between reads of the receive FIFO and the status registers (interrupt
identification register or line status register)
Not production tested.
THRE = Transmitter Holding Register Empty; IIR = Interrupt Identification Register.
MODEM CONTROL SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
(1)
LIMITS
PARAMETER
ALT.
SYMBOL
FIGURE
TEST
CONDITIONS
1.8 V
MIN
2.5 V
MAX
MIN
3.3 V
MAX
MIN
UNIT (2)
5V
MAX
MIN
MAX
td22
Delay time, WR MCR to output
tMDO
17
CL = 30 pF
90
70
60
50
ns
td23
Delay time, modem interrupt to set INT
tSIM
17
CL = 30 pF
60
50
40
35
ns
td24
Delay time, RD MSR to reset INT
tRIM
17
CL = 30 pF
80
60
50
40
ns
(1)
(2)
12
Not production tested.
A baudout cycle is equal to the period of the input clock divided by the programmed divider in DLL, DLM.
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SPACER
TYPICAL CHARACTERISTICS
0.5
VCC = 2.5 V
TA = 22°C
1.0
Divisor = 1
0.9
Divisor = 2
0.3
Divisor = 3
Divisor = 10
Divisor = 255
0.2
ICC − Supply Current − mA
0.4
ICC − Supply Current − mA
Divisor = 1
1.1
VCC = 1.8 V
TA = 22°C
0.1
Divisor = 2
0.8
Divisor = 3
0.7
Divisor = 10
Divisor = 255
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
1
2
3
4
5
6
7
8
9
0.0
10
0
2
4
f − Frequency − MHz
6
G001
12
14
16
Figure 7.
2.0
4.0
Divisor = 1
VCC = 3.3 V
TA = 22°C
Divisor = 1
VCC = 5 V
TA = 22°C
3.6
1.6
3.2
Divisor = 2
1.4
Divisor = 3
1.2
Divisor = 10
Divisor = 255
1.0
0.8
0.6
ICC − Supply Current − mA
ICC − Supply Current − mA
10
G002
Figure 6.
1.8
8
f − Frequency − MHz
Divisor = 3
2.4
Divisor = 10
Divisor = 255
2.0
1.6
1.2
0.4
0.8
0.2
0.4
0.0
Divisor = 2
2.8
0.0
0
2
4
6
8
10
12
14
16
18
20
0
4
f − Frequency − MHz
G003
Figure 8.
8
12
16
20
24
f − Frequency − MHz
G004
Figure 9.
tw2
tw1
XTALI
Figure 10. Clock Input
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TYPICAL CHARACTERISTICS (continued)
A2 −A0
50%
Valid
50%
td5
CSA, CSB
th4
50%
50%
th3
td4
IOW
50%
50%
tw6
tsu3
th5
Valid Data
D7 −D0
Figure 11. Write Cycle Timing Waveforms
A2 −A0
50%
Valid
50%
th7
td8
CSA, CSB
50%
50%
th6
td7
tw7
IOR
50%
50%
td10
td11
D7 −D0
Valid Data
Figure 12. Read Cycle Timing Waveforms
14
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TYPICAL CHARACTERISTICS (continued)
RCLK
(Internal)
td12
8 CLKs
Sample Clock
(Internal)
TL16C450 Mode:
RXA, RXB
Start
Data Bits 5−8
Parity
Stop
Sample Clock
INT
(data ready)
50%
td13
INT
(RCV error)
50%
td14
50%
50%
IOR
(read RBR)
50%
IOR
(read LSR)
50%
Active
Active
td14
Figure 13. Receiver Timing Waveforms
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TYPICAL CHARACTERISTICS (continued)
RXA, RXB
Data Bits 5−8
Stop
Sample Clock
(Internal)
Trigger Level
INT
(FCR6, 7 = 0, 0)
50%
50%
(FIFO at or above
trigger level)
(FIFO below
trigger level)
td13
(see Note A)
INT
Line Status
Interrupt (LSI)
td14
50%
50%
td14
IOR
(RD LSR)
Active
50%
IOR
(RD RBR)
50%
Active
Figure 14. Receive First Byte (Sets DR Bit) Waveforms
RXA, RXB
Stop
Sample Clock
(Internal)
Time-Out or
Trigger Level
Interrupt
50%
50%
(FIFO at or above
trigger level)
(FIFO below
trigger level)
td13
td14
(see Note A)
50%
Line Status
Interrupt (LSI)
td13
50%
Top Byte of FIFO
td14
IOP
(RD LSR)
50%
IOR
(RD RBR)
Active
50%
50%
Active
Previous Byte
Read From FIFO
Figure 15. Receive FIFO Bytes Other than the First Byte (DR Internal BIt already set) Waveforms
16
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TYPICAL CHARACTERISTICS (continued)
IOR
(RD RBR)
50%
Active
See Note A
RXA, RXB
(first byte)
Stop
Sample Clock
(Internal)
td13
(see Note B)
td14
50%
50%
RXRDYA, RXRDYB
Figure 16. Receiver Ready (RXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)
IOR
(RD RBR)
Active
50%
See Note A
RXA, RXB
(first byte that reaches
the trigger level)
Sample Clock
(Internal)
td13
(see Note B)
td14
50%
RXRDYA, RXRDYB
50%
Figure 17. Receiver Ready (RXRDY) Waveforms, FCR0 = 0 and FCR3 = 1 (Mode 1)
Start
50%
TXA, TXB
Data Bits
Parity
td15
INT
(THRE)
50%
Stop
Start
50%
td16
50%
50%
50%
50%
td18
td17
td17
IOW 50%
(WR THR)
50%
50%
td19
IOR
50%
Figure 18. Transmitter Timing Waveforms
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TYPICAL CHARACTERISTICS (continued)
Byte 1
IOW
(WR THR)
50%
Data
TXA, TXB
Parity
Stop
Start
50%
td21
td20
TXRDYA, TXRDYB
50%
50%
Figure 19. Tranceiver Ready (TXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)
Byte 16
IOW
(WR THR)
50%
Data
TXA, TXB
Parity
td21
td20
TXRDYA, TXRDYB
Start
50%
Stop
50%
50%
FIFO Full
Figure 20. Tranceiver Ready (TXRDY) Waveforms, FCR0 = 0 and FCR3 = 1 (Mode 1)
IOW
(WR MCR)
50%
50%
td22
td22
RTSA, RTSB, DTRA,
DTRB, OPA, OPB
50%
50%
50%
CTSA, CTSB, DSRA,
DSRB, CDA, CDB
td23
INT
(modem)
50%
50%
50%
td24
IOR
(RD MSR)
50%
td23
RI
50%
Figure 21. Modem Control Timing Waveforms
18
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TYPICAL CHARACTERISTICS (continued)
tsu4
CTSA, CTSB
50%
50%
td25
TXA, TXB
50%
Midpoint of Stop Bit
Figure 22. CTS and TX Autoflow Control Timing (Start and Stop) Waveforms
Midpoint of Stop Bit
RXA, RXB
td26
td27
50%
50%
RTSA,
RTSB
50%
IOR
Figure 23. Auto-RTS Timing for RCV Threshold of 1, 4, or 8 Waveforms
Midpoint of Data Bit 0
RXA,
RXB
15th Character
16th Character
td28
td29
50%
50%
RTSA,
RTSB
50%
IOR
Figure 24. Auto-RTS Timing for RCV Threshold of 14 Waveforms
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APPLICATION INFORMATION
TXA, B
D7 −D0
D7 −D0
MEMR or I/OR
MEMW or I/OW
INTR
C
P
U
B
u
s
RESET
A0
A1
A2
RXA, B
IOR
RTSA, B
IOW
DTRA, B
INTA, B
DSRA, B
RESET
EIA-232-D
Drivers
and Receivers
CDA, B
A0
CTSA, B
A1
RIA, B
A2
TL16C2550
XTAL1
CS
CSA, B
3.072 MHz
33 pF
XTAL2
(Optional)
33 pF
Figure 25. Basic TL16C2550 Configuration
20
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TL16C2550
XTAL1
14
33 pF
A0 −A23
A0 −A2
XTAL2
15
(Optional)
10
Address
Decoder
11
33 pF
CSA
CSB
CPU
DTRA, B
RTSA, B
36
RSI/ABT
34, 35
33, 22
20
1
RESET
D0 −D7
Buffer
(Optional)
D0 −D15
D0 −D7
41, 21
RIA, B
40, 16
PHI1
CDA, B
PHI2
39, 20
DSRA, B
CTSA, B
PHI1
RSTO
RD
PHI2
19
TCU
15
WR
IOR
38, 23
6
5
7, 8
TXA, B
2
IOW
5, 4
RXA, B
30, 29
8
3
INTA, B
7
1
GND
(VSS)
17
42
EIA-232-D
Connector
VCC
Figure 26. Typical TL16C2550 Connection
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PRINCIPLES OF OPERATION
REGISTER SELECTION
Table 1. Register Selection
DLAB
(1)
(1)
A2
A1
A0
0
L
L
L
Receiver buffer (read), transmitter holding register (write)
REGISTER
0
L
L
H
Interrupt enable register
X
L
H
L
Interrupt identification register (read only)
X
L
H
L
FIFO control register (write)
X
L
H
H
Line control register
X
H
L
L
Modem control register
X
H
L
H
Line status register
X
H
H
L
Modem status register
X
H
H
H
Scratch register
1
L
L
L
Divisor latch (LSB)
1
L
L
H
Divisor latch (MSB)
The divisor latch access bit (DLAB) is the most significant bit of the line control register. The DLAB signal is controlled by writing to this
bit location (see Table 2).
Table 2. ACE Reset Functions
REGISTER/SIGNAL
RESET CONTROL
RESET STATE
Interrupt enable register
Master reset
All bits cleared (0–3 forced and 4–7
permanent)
Interrupt identification register
Master reset
Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared,
and bits 4–5 are permanently cleared
FIFO control register
Master reset
All bits cleared
Line control register
Master reset
All bits cleared
Modem control register
Master reset
All bits cleared (6 -7 permanent)
Line status register
Master reset
Bits 5 and 6 are set; all other bits are cleared
Modem status register
Master reset
Bits 0–3 are cleared; bits 4–7 are input
signals
TX
Master reset
High
INT
Master reset, MCR3
Output buffer tristated
Interrupt condition (receiver error flag)
Read LSR/MR
Low
Interrupt condition (received data available)
Read RBR/MR
Low
Read IIR/write THR/MR
Low
Interrupt condition (transmitter holding
register empty)
Interrupt condition (modem status changes)
Read MSR/MR
Low
OP
Master reset
High
RTS
Master reset
High
DTR
Master reset
High
Scratch register
Master reset
No effect
Divisor latch (LSB and MSB) registers
Master reset
No effect
Receiver buffer register
Master reset
No effect
Transmitter holding register
Master reset
No effect
RCVR FIFO
MR/FCR1 – FCR0/DFCR0
All bits cleared
XMIT FIFO
MR/FCR2 – FCR0/DFCR0
All bits cleared
22
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Accessible Registers
The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 2. These registers control ACE operations, receive data, and transmit data. Descriptions of
these registers follow Table 3.
Table 3. Summary of Accessible Registers
REGISTER ADDRESS
DLAB = 0
BIT
NO.
0
0
0
Receiver
Buffer
Register
(Read Only)
Transmitter
Holding
Register
(Write
Only)
RBR
Data Bit 0 (1)
DLAB = 1
1
2
2
3
4
5
6
7
0
1
Interrupt
Enable
Register
Interrupt
Ident
Register
(Read
Only)
FIFO
Control
Register
(WriteOnl
y)
Line
Control
Register
Modem
Control
Register
Line
Status
Register
Modem Status
Register
Scratch
Register
Divisor
Latch
(LSB)
Divisor
Latch
(MSB)
THR
IER
IIR
FCR
LCR
MCR
LSR
MSR
SCR
DLL
DLM
Data Bit 0
Enable
Received Data
Available
Interrupt (ERBI)
0 if
Interrupt
Pending
FIFO
Enable
Word
Length
Select Bit 0
(WLS0)
Data Terminal
Ready (DTR)
Data
Ready
(DR)
Delta Clear to
Send (ΔCTS)
Bit 0
Bit 0
Bit 8
Interrupt
ID Bit 1
Receiver
FIFO
Reset
Word
Length
Select Bit 1
(WLS1)
Request to
Send (RTS)
Overrun
Error (OE)
Delta Data Set
Ready (ΔDSR)
Bit 1
Bit 1
Bit 9
1
Data Bit 1
Data Bit 1
Enable
Transmitter
Holding
Register Empty
Interrupt
(ETBEI)
2
Data Bit 2
Data Bit 2
Enable
Receiver Line
Status Interrupt
(ELSI)
Interrupt
ID Bit 2
Transmitte
r FIFO
Reset
Number of
Stop Bits
(STB)
OUT1
Parity
Error (PE)
Trailing Edge
Ring Indicator
(TERI)
Bit 2
Bit 2
Bit 10
3
Data Bit 3
Data Bit 3
Enable Modem
Status Interrupt
(EDSSI)
Interrupt
ID Bit 3 (2)
DMA
Mode
Select
Parity
Enable
(PEN)
OUT2,
OPcontrol, INT
Enable
Framing
Error (FE)
Delta Data Carrier
Detect (ΔDCD)
Bit 3
Bit 3
Bit 11
4
Data Bit 4
Data Bit 4
0
0
Reserved
Even Parity
Select
(EPS)
Loop
Break
Interrupt
(BI)
Clear to Send
(CTS)
Bit 4
Bit 4
Bit 12
5
Data Bit 5
Data Bit 5
0
0
Reserved
Stick Parity
Autoflow
Control Enable
(AFE)
Transmitte
r Holding
Register
(THRE)
Data Set Ready
(DSR)
Bit 5
Bit 5
Bit 13
6
Data Bit 6
Data Bit 6
0
FIFOs
Enabled (2)
Receiver
Trigger
(LSB)
Break
Control
0
Transmitte
r Empty
(TEMT)
Ring Indicator
(RI)
Bit 6
Bit 6
Bit 14
7
Data Bit 7
Data Bit 7
0
FIFOs
Enabled (2)
Receiver
Trigger
(MSB)
Divisor
Latch
Access Bit
(DLAB)
0
Error in
RCVR
FIFO(2)
Data Carrier
Detect (DCD)
Bit 7
Bit 7
Bit 15
(1)
(2)
Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
These bits are always 0 in the TL16C450 mode.
FIFO Control Register (FCR)
The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables
and clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signalling.
• Bit 0: This bit, when set, enables the transmitter and receiver FIFOs. Bit 0 must be set when other FCR bits
are written to or they are not programmed. Changing this bit clears the FIFOs.
• Bit 1: This bit, when set, clears all bytes in the receiver FIFO and clears its counter. The shift register is not
cleared. The 1 that is written to this bit position is self-clearing.
• Bit 2: This bit, when set, clears all bytes in the transmit FIFO and clears its counter. The shift register is not
cleared. The 1 that is written to this bit position is self-clearing.
• Bit 3: When FCR0 is set, setting FCR3 causes RXRDY and TXRDY to change from level 0 to level 1.
• Bits 4 and 5: These two bits are reserved for future use.
• Bits 6 and 7: These two bits set the trigger level for the receiver FIFO interrupt (see Table 4).
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Table 4. Receiver FIFO Trigger Level
BIT 7
BIT 6
RECEIVER FIFO TRIGGER LEVEL (BYTES)
0
0
01
0
1
04
1
0
08
1
1
14
FIFO Interrupt Mode Operation
When the receiver FIFO and receiver interrupts are enabled (FCR0 = 1, IER0 = 1, IER2 = 1), a receiver interrupt
occurs as follows:
1. The received data available interrupt is issued to the microprocessor when the FIFO has reached its
programmed trigger level. It is cleared when the FIFO drops below its programmed trigger level.
2. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and like the
interrupt, it is cleared when the FIFO drops below the trigger level.
3. The receiver line status interrupt (IIR = 06) has higher priority than the received data available (IIR = 04)
interrupt.
4. The data ready bit (LSR0) is set when a character is transferred from the shift register to the receiver FIFO. It
is cleared when the FIFO is empty.
When the receiver FIFO and receiver interrupts are enabled:
1. FIFO time-out interrupt occurs if the following conditions exist:
(a) At least one character is in the FIFO.
(b) The most recent serial character was received more than four continuous character times ago (if two
stop bits are programmed, the second one is included in this time delay).
(c) The most recent microprocessor read of the FIFO has occurred more than four continuous character
times before. This causes a maximum character received command to interrupt an issued delay of 160
ms at a 300-baud rate with a 12-bit character.
2. Character times are calculated by using the RCLK input for a clock signal (makes the delay proportional to
the baud rate).
3. When a time-out interrupt has occurred, it is cleared and the timer is cleared when the microprocessor reads
one character from the receiver FIFO.
4. When a time-out interrupt has not occurred, the time-out timer is cleared after a new character is received or
after the microprocessor reads the receiver FIFO.
When the transmitter FIFO and THRE interrupt are enabled (FCR0 = 1, IER1 = 1), transmit interrupts occur as
follows:
1. The transmitter holding register empty interrupt [IIR (3 -0) = 2] occurs when the transmit FIFO is empty. It is
cleared [IIR (3 -0) = 1] when the THR is written to (1 to 16 characters may be written to the transmit FIFO
while servicing this interrupt) or the IIR is read.
2. The transmitter holding register empty interrupt is delayed one character time minus the last stop bit time
when there have not been at least two bytes in the transmitter FIFO at the same time since the last time that
the FIFO was empty. The first transmitter interrupt after changing FCR0 is immediate if it is enabled.
24
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FIFO Polled Mode Operation
With FCR0 = 1 (transmitter and receiver FIFOs enabled), clearing IER0, IER1, IER2, IER3, or all four to 0 puts
the ACE in the FIFO polled mode of operation. Because the receiver and transmitter are controlled separately,
either one or both can be in the polled mode of operation.
In this mode, the user program checks receiver and transmitter status using the LSR. As stated previously:
• LSR0 is set as long as one byte is in the receiver FIFO.
• LSR1 -LSR 4 specify which error(s) have occurred. Character error status is handled the same way as when
in the interrupt mode; the IIR is not affected since IER2 = 0.
• LSR5 indicates when the THR is empty.
• LSR6 indicates that both the THR and TSR are empty.
• LSR7 indicates whether any errors are in the receiver FIFO.
There is no trigger level reached or time-out condition indicated in the FIFO polled mode. However, the
receiver and transmitter FIFOs are still fully capable of holding characters.
Interrupt Enable Register (IER)
The IER enables each of the five types of interrupts (see Table 5) and enables INTRPT in response to an
interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The contents of
this register are summarized in Table 3 and are described in the following bullets.
• Bit 0: When set, this bit enables the received data available interrupt.
• Bit 1: When set, this bit enables the THRE interrupt.
• Bit 2: When set, this bit enables the receiver line status interrupt.
• Bit 3: When set, this bit enables the modem status interrupt.
• Bits 4 through 7: These bits are not used (always cleared).
Interrupt Identification Register (IIR)
The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with the
most popular microprocessors.
The ACE provides four prioritized levels of interrupts:
• Priority 1 -Receiver line status (highest priority)
• Priority 2 -Receiver data ready or receiver character time-out
• Priority 3 -Transmitter holding register empty
– Priority 4 -Modem status (lowest priority)
– When an interrupt is generated, the IIR indicates that an interrupt is pending and encodes the type of
interrupt in its three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in
Table 3 and described in Table 5. Detail on each bit is as follows:
• Bit 0: This bit is used either in a hardwire prioritized or polled interrupt system. When bit 0 is cleared, an
interrupt is pending. If bit 0 is set, no interrupt is pending.
• Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in Table 3.
• Bit 3: This bit is always cleared in TL16C450 mode. In FIFO mode, bit 3 is set with bit 2 to indicate that a
time-out interrupt is pending.
• Bits 4 and 5: These two bits are not used (always cleared).
• Bits 6 and 7: These bits are always cleared in TL16C450 mode. They are set when bit 0 of the FIFO control
register is set.
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Table 5. Interrupt Control Functions
INTERRUPT
IDENTIFICATION
REGISTER
PRIORITY
LEVEL
BIT
3
BIT
2
BIT 1
BIT 0
0
0
0
1
None
0
1
1
0
0
1
0
0
1
1
0
0
INTERRUPT
TYPE
INTERRUPT SOURCE
INTERRUPT RESET METHOD
None
None
None
1
Receiver line
status
Overrun error, parity error, framing
error, or break interrupt
Read the line status register
2
Received data
available
Receiver data available in the
TL16C450 mode or trigger level
reached in the FIFO mode
Read the receiver buffer register
2
Character
time-out
indication
No characters have been removed
from or input to the receiver FIFO
during the last four character times,
and there is at least one character
in it during this time
Read the receiver buffer register
Transmitter holding register empty
Read the interrupt identification
register (if source of interrupt) or
writing into the transmitter holding
register
Clear to send, data set ready, ring
indicator, or data carrier detect
Read the modem status register
0
0
1
0
3
Transmitter
holding register
empty
0
0
0
0
4
Modem status
Line Control Register (LCR)
The system programmer controls the format of the asynchronous data communication exchange through the
LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates
the need for separate storage of the line characteristics in system memory. The contents of this register are
summarized in Table 3 and described in the following bulleted list.
• Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character. These
bits are encoded as shown in Table 6.
Table 6. Serial Character Word Length
•
BIT 1
BIT 0
WORD LENGTH
0
0
5 bits
0
1
6 bits
1
0
7 bits
1
1
8 bits
Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When bit
2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated is
dependent on the word length selected with bits 0 and 1. The receiver clocks only the first stop bit regardless
of the number of stop bits selected. The number of stop bits generated in relation to word length and bit 2 are
shown in Table 7.
Table 7. Number of Stop Bits Generated
26
BIT 2
Word Length Selectedby Bits 1 and 2
Number of Stop Bits Generated
0
Any word length
1
1
5 bits
1 1/2
1
6 bits
2
1
7 bits
2
1
8 bits
2
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•
•
•
•
•
Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in transmitted data between
the last data word bit and the first stop bit. In received data, if bit 3 is set, parity is checked. When bit 3 is
cleared, no parity is generated or checked.
Bit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set, even parity (an
even number of logic 1s in the data and parity bits) is selected. When parity is enabled and bit 4 is cleared,
odd parity (an odd number of logic 1s) is selected.
Bit 5: This bit is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked as
cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set. If bit 5
is cleared, stick parity is disabled.
Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition; i.e., a condition where TX is
forced to the spacing (cleared) state. When bit 6 is cleared, the break condition is disabled and has no effect
on the transmitter logic; it only effects TX.
Bit 7: This bit is the divisor latch access bit (DLAB). Bit 7 must be set to access the divisor latches of the baud
generator during a read or write. Bit 7 must be cleared during a read or write to access the receiver buffer,
the THR, or the IER.
NOTE
The line status register is intended for read operations only; writing to this register is not
recommended outside of a factory testing environment.
The LSR provides information to the CPU concerning the status of data transfers. The contents of this register
are summarized in Table 3 and described in the following bulleted list.
• Bit 0: This bit is the data ready (DR) indicator for the receiver. DR is set whenever a complete incoming
character has been received and transferred into the RBR or the FIFO. DR is cleared by reading all of the
data in the RBR or the FIFO.
NOTE
Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.
•
•
•
•
•
Bit 1: This bit is the overrun error (OE) indicator. When OE is set, it indicates that before the character in the
RBR was read, it was overwritten by the next character transferred into the register. OE is cleared every time
the CPU reads the contents of the LSR. If the FIFO mode data continues to fill the FIFO beyond the trigger
level, an overrun error occurs only after the FIFO is full, and the next character has been completely received
in the shift register. An overrun error is indicated to the CPU as soon as it happens. The character in the shift
register is overwritten, but it is not transferred to the FIFO.
Bit 2: This bit is the parity error (PE) indicator. When PE is set, it indicates that the parity of the received data
character does not match the parity selected in the LCR (bit 4). PE is cleared every time the CPU reads the
contents of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to
which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO.
Bit 3: This bit is the framing error (FE) indicator. When FE is set, it indicates that the received character did
not have a valid (set) stop bit. FE is cleared every time the CPU reads the contents of the LSR. In the FIFO
mode, this error is associated with the particular character in the FIFO to which it applies. This error is
revealed to the CPU when its associated character is at the top of the FIFO. The ACE tries to resynchronize
after a framing error. To accomplish this, it is assumed that the framing error is due to the next start bit. The
ACE samples this start bit twice and then accepts the input data.
Bit 4: This bit is the break interrupt (BI) indicator. When BI is set, it indicates that the received data input was
held low for longer than a full-word transmission time. A full-word transmission time is defined as the total
time to transmit the start, data, parity, and stop bits. BI is cleared every time the CPU reads the contents of
the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it
applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. When a
break occurs, only one 0 character is loaded into the FIFO. The next character transfer is enabled after RX
goes to the marking state for at least two RCLK samples and then receives the next valid start bit.
Bit 5: This bit is the THRE indicator. THRE is set when the THR is empty, indicating that the ACE is ready to
accept a new character. If the THRE interrupt is enabled when THRE is set, an interrupt is generated. THRE
is set when the contents of the THR are transferred to the TSR. THRE is cleared concurrent with the loading
of the THR by the CPU. In the FIFO mode, THRE is set when the transmit FIFO is empty; it is cleared when
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at least one byte is written to the transmit FIFO.
Bit 6: This bit is the transmitter empty (TEMT) indicator. TEMT bit is set when the THR and the TSR are both
empty. When either the THR or the TSR contains a data character, TEMT is cleared. In the FIFO mode,
TEMT is set when the transmitter FIFO and shift register are both empty.
Bit 7: In the TL16C450 mode, this bit is always cleared. In the FIFO mode, LSR7 is set when there is at least
one parity, framing, or break error in the FIFO. It is cleared when the microprocessor reads the LSR and there
are no subsequent errors in the FIFO.
Modem Control Register (MCR)
The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is
emulating a modem. The contents of this register are summarized in Table 3 and are described in the following
bulleted list.
• Bit 0: This bit (DTR) controls the DTR output.
• Bit 1: This bit (RTS) controls the RTS output.
• Bit 2: This bit (OUT1) is reserved for output and can also be used for loopback mode.
• Bit 3: This bit (OUT2) controls the high-impedance state output buffer for the INT signal and the OP output.
When low, the INT signal is in a high-impedance state and OP is high. When high, the INT signal is enabled
and OP is low.
• Bit 4: This bit (LOOP) provides a local loop back feature for diagnostic testing of the ACE. When LOOP is set,
the following occurs:
– The transmitter TX is set high.
– The receiver RX is disconnected.
– The output of the TSR is looped back into the receiver shift register input.
– The four modem control inputs (CTS, DSR, CD, and RI) are disconnected.
– The four modem control outputs (DTR, RTS, OUT1, and OUT2) are internally connected to the four
modem control inputs.
– The four modem control outputs are forced to the inactive (high) levels.
• Bit 5: This bit (AFE) is the autoflow control enable. When set, the autoflow control as described in the detailed
description is enabled. In the diagnostic mode, data that is transmitted is immediately received. This allows
the processor to verify the transmit and receive data paths to the ACE. The receiver and transmitter interrupts
are fully operational. The modem control interrupts are also operational, but the modem control interrupt's
sources are now the lower four bits of the MCR instead of the four modem control inputs. All interrupts are
still controlled by the IER.
The ACE flow can be configured by programming bits 1 and 5 of the MCR as shown in Table 8.
Table 8. ACE Flow Configuration
28
MCR BIT 5 (AFE)
MCR BIT 1 (RTS)
ACE FLOW CONFIGURATION
1
1
Auto-RTS and auto-CTS enabled (autoflow control enabled)
1
0
Auto-CTS only enabled
0
X
Auto-RTS and auto-CTS disabled
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Modem Status Register (MSR)
The MSR is an 8-bit register that provides information about the current state of the control lines from the
modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide change
information; when a control input from the modem changes state, the appropriate bit is set. All four bits are
cleared when the CPU reads the MSR. The contents of this register are summarized in Table 3 and are
described in the following bulleted list.
• Bit 0: This bit is the change in clear-to-send (ΔCTS) indicator. ΔCTS indicates that the CTS input has
changed state since the last time it was read by the CPU. When ΔCTS is set (autoflow control is not enabled
and the modem status interrupt is enabled), a modem status interrupt is generated. When autoflow control is
enabled (ΔCTS is cleared), no interrupt is generated.
• Bit 1: This bit is the change in data set ready (ΔDSR) indicator. ΔDSR indicates that the DSR input has
changed state since the last time it was read by the CPU. When ΔDSR is set and the modem status interrupt
is enabled, a modem status interrupt is generated.
• Bit 2: This bit is the trailing edge of the ring indicator (TERI) detector. TERI indicates that the RI input to the
chip has changed from a low to a high level. When TERI is set and the modem status interrupt is enabled, a
modem status interrupt is generated.
• Bit 3: This bit is the change in data carrier detect (ΔDCD) indicator. ΔDCD indicates that the DCD input to the
chip has changed state since the last time it was read by the CPU. When ΔDCD is set and the modem status
interrupt is enabled, a modem status interrupt is generated.
• Bit 4: This bit is the complement of the clear-to-send (CTS) input. When the ACE is in the diagnostic test
mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 1 (RTS).
• Bit 5: This bit is the complement of the data set ready (DSR) input. When the ACE is in the diagnostic test
mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 0 (DTR).
• Bit 6: This bit is the complement of the ring indicator (RI) input. When the ACE is in the diagnostic test mode
(LOOP [MCR4] = 1), this bit is equal to the MCR bit 2 (OUT1).
• Bit 7: This bit is the complement of the data carrier detect (DCD) input. When the ACE is in the diagnostic test
mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 3 (OUT2).
Programmable Baud Generator
The ACE contains a programmable baud generator that takes a clock input in the range between dc and 16 MHz
and divides it by a divisor in the range between 1 and (216 -1). The output frequency of the baud generator is
sixteen times (16 ×) the baud rate. The formula for the divisor is:
divisor = XIN frequency input P (desired baud rate × 16)
Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must
be loaded during initialization of the ACE in order to ensure desired operation of the baud generator. When either
of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.
Table 9 and Table 10 illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz and 3.072
MHz respectively. For baud rates of 38.4 kbits/s and below, the error obtained is small. The accuracy of the
selected baud rate is dependent on the selected crystal frequency (see Figure 27 for examples of typical clock
circuits).
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Table 9. Baud Rates Using a 1.8432-MHz Crystal
PERCENT ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL
DESIRED BAUD RATE
DIVISOR USED TO GENERATE
16× CLOCK
50
2304
75
1536
110
1047
0.026
134.5
857
0.058
150
768
300
384
600
192
1200
96
1800
64
2000
58
2400
48
3600
32
4800
24
7200
16
9600
12
19200
6
38400
3
56000
2
0.69
2.86
Table 10. Baud Rates Using a 3.072-MHz Crystal
30
DESIRED BAUD RATE
DIVISOR USED TO GENERATE
16× CLOCK
50
3840
75
2560
PERCENT ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL
110
1745
0.026
134.5
1428
0.034
150
1280
300
640
600
320
1200
160
1800
107
2000
96
2400
80
3600
53
4800
40
7200
27
9600
20
19200
10
38400
5
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0.312
0.628
1.23
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Figure 27. Typical Clock Circuits
Table 11. Typical Crystal Oscillator Network
Crystal
RP
RX2 (Optional)
C1
C2
3.072 MHz
1 MΩ
1.5 kΩ
10–30 pF
40–60 pF
1.8432 MHz
1 MΩ
1.5 kΩ
10–30 pF
40–60 pF
16 MHz
1 MΩ
0 kΩ
33 pF
33 pF
Receiver Buffer Register (RBR)
The ACE receiver section consists of a receiver shift register (RSR) and a RBR. The RBR is actually a 16-byte
FIFO. Timing is derived from the input clock divided by the programmed devisor. Receiver section control is a
function of the ACE line control register.
The ACE RSR receives serial data from RX. The RSR then concatenates the data and moves it into the RBR
FIFO. In the TL16C450 mode, when a character is placed in the RBR and the received data available interrupt is
enabled (IER0 = 1), an interrupt is generated. This interrupt is cleared when the data is read out of the RBR. In
the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register.
Scratch Register
The scratch register is an 8-bit register that is intended for the programmer's use as a scratchpad in the sense
that it temporarily holds the programmer's data without affecting any other ACE operation.
Transmitter Holding Register (THR)
The ACE transmitter section consists of a THR and a transmitter shift register (TSR). The THR is actually a
16-byte FIFO. Timing is derived from the input clock divided by the programmed devisor. Transmitter section
control is a function of the ACE line control register.
The ACE THR receives data off the internal data bus and when the shift register is idle, moves it into the TSR.
The TSR serializes the data and outputs it at TX. In the TL16C450 mode, if the THR is empty and the transmitter
holding register empty (THRE) interrupt is enabled (IER1 = 1), an interrupt is generated. This interrupt is cleared
when a character is loaded into the register. In the FIFO mode, the interrupts are generated based on the control
setup in the FIFO control register.
Table 12. Typical Package Thermal Resistance Data
PACKAGE
48-Pin TQFP PFB
WEIGHT IN GRAMS
θJA = 50.1°C/W
θJC = 21.1°C/W
0.2
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TL16C2550-Q1
SLWS232 – DECEMBER 2011
32
www.ti.com
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Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s) :TL16C2550-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TL16C2550IPFBRQ1
ACTIVE
TQFP
PFB
48
1000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TL2550RQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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