TL16C2752
www.ti.com ................................................................................................................................................ SLWS188A – JUNE 2006 – REVISED SEPTEMBER 2008
1.8-V to 5-V DUAL UART WITH 64-BYTE FIFOS
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Larger FIFOs Reduce CPU Overhead
Programmable Auto-RTS and Auto-CTS
In Auto-CTS Mode, CTS Controls the
Transmitter
In Auto-RTS Mode, RCV FIFO Contents, and
Threshold Control RTS
Serial and Modem Control Outputs Drive a
RJ11 Cable Directly When Equipment is on the
Same Power Drop
Capable of Running With All Existing
TL16C450 Software
After Reset, All Registers Are Identical to the
TL16C450 Register Set
Up to 48-MHz Clock Rate for up to 3-Mbps
(Standard 16× Sampling) Operation, or up to
6-Mbps (Optional 8× Sampling) Operation With
VCC = 5 V Nominal
Up to 32-MHz Clock Rate for up to 2-Mbps
(Standard 16× Sampling) Operation, or up to
4-Mbps (Optional 8× Sampling) Operation With
VCC = 3.3 V Nominal
Up to 24-MHz Clock Rate for up to 1.5-Mbps
(Standard 16× Sampling) Operation, or up to
3-Mbps (Optional 8× Sampling) Operation With
VCC = 2.5 V Nominal
Up to 16-MHz Clock Rate for up to 1-Mbps
(Standard 16× Sampling) Operation, or up to
2-Mbps (Optional 8× Sampling) Operation With
VCC = 1.8 V Nominal
In TL16C450 Mode, Hold and Shift Registers
Eliminate the Need for Precise
Synchronization Between the CPU and Serial
Data
Programmable Baud-Rate Generator Allows
Division of Any Input Reference Clock by 1 to
(216 – 1) and Generates an Internal 16× Clock
Standard Asynchronous Communication Bits
(Start, Stop, and Parity) Added to or Deleted
From the Serial Data Stream
5-V, 3.3-V, 2.5-V, and 1.8-V Operation
Independent Receiver Clock Input
Transmit, Receive, Line Status, and Data Set
Interrupts Independently Controlled
•
•
•
•
•
•
•
•
•
•
•
Fully Programmable Serial Interface
Characteristics
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation
and Detection
– 1-, 1 ＝-, or 2-Stop Bit Generation
– Baud Generation (DC to 1 Mbit/s)
False-Start Bit Detection
Complete Status Reporting Capabilities
3-State Output TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus
Line Break Generation and Detection
Internal Diagnostic Capabilities
– Loopback Controls for Communications
Link Fault Isolation
– Break, Parity, Overrun, and Framing Error
Simulation
Fully Prioritized Interrupt System Controls
Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
Available in 44-Pin PLCC (FN) or 32-Pin QFN
(RHB) Packages
Each UART's Internal Register Set May Be
Written Concurrently to Save Setup Time
Multifunction (MF) Output Allows Users to
Select Among Several Functions, Saving
Package Pins
APPLICATIONS
•
•
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•
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•
Point-of-Sale Terminals
Gaming Terminals
Portable Applications
Router Control
Cellular Data
Factory Automation
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2008, Texas Instruments Incorporated
TL16C2752
SLWS188A – JUNE 2006 – REVISED SEPTEMBER 2008 ................................................................................................................................................ www.ti.com
DESCRIPTION
The TL16C2752 is a speed and functional upgrade of the TL16C2552. Since they are pinout and software
compatible, designs can easily migrate from the TL16C2552 to the TL16C2752 if needed. The additional
functionality within the TL16C2752 is accessed via an extended register set. Some of the key new features are
larger receive and transmit FIFOs, embedded IrDA encoders and decoders, RS-485 transceiver controls,
software flow control (Xon/Xoff) modes, programmable transmit FIFO thresholds, extended receive and transmit
threshold levels for interrupts, and extended receive threshold levels for flow control halt/resume operation.
The TL16C2752 is a dual universal asynchronous receiver and transmitter (UART). It incorporates the
functionality of two independent UARTs: each UART having its own register set and transmit and receive FIFOs.
The two UARTs share only the data bus interface and clock source, otherwise they operate independently.
Another name for the UART function is asynchronous communications element (ACE), and these terms will be
used interchangeably. The bulk of this document describes the behavior of each ACE, with the understanding
that two such devices are incorporated into the TL16C2752.
Functionally equivalent to the TL16C450 on power up or reset (single character or TL16C450 mode), each ACE
can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead by buffering
received and to-be-transmitted characters. Each receiver and transmitter store up to 64 bytes in their respective
FIFOs, with the receive FIFO including three additional bits per byte for error status. In the FIFO mode,
selectable hardware or software autoflow control features can significantly reduce program overload and
increase system efficiency by automatically controlling serial data flow.
Each ACE performs serial-to-parallel conversions on data received from a peripheral device or modem and
stores the parallel data in its receive buffer or FIFO, and each ACE performs parallel-to-serial conversions on
data sent from its CPU after storing the parallel data in its transmit buffer or FIFO. The CPU can read the status
of either ACE at any time. Each ACE includes complete modem control capability and a processor interrupt
system that can be tailored to the application.
Each ACE includes a programmable baud rate generator capable of dividing a reference clock with divisors of
from 1 to 65535, thus producing a 16× or 8× internal reference clock for the transmitter and receiver logic. Each
ACE accommodates up to a 3-Mbaud serial data rate (48-MHz input clock). As a reference point, that speed
would generate a 333-ns bit time and a 3.33-＝s character time (for 8,N,1 serial data), with the internal clock
running at 48 MHz and 16× sampling.
Each ACE has a TXRDY and RXRDY (via MF) output that can be used to interface to a DMA controller.
2
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TL16C2752 Block Diagram
UART Channel A
A2−A0
64-Byte TX FIFO
D7−D0
Tx
IR ENC
CS
TXA
CTSA
DTRA
UART Registers
CHSEL
BaudRate
Gen
IOR
IOW
DSRA, RIA, CDA
RTSA
64-Byte RX FIFO
Rx
IR DEC
RXA
INTA
INTB
Data Bus
Interface
UART Channel B
TXRDYA
TXRDYB
64-Byte TX FIFO
Tx
IR ENC
MFA
UART Registers
BaudRate
Gen
RESET
XTAL2
CTSB
DTRB
MFB
XTAL1
TXB
DSRB, RIB, CDB
RTSB
64-Byte RX FIFO
Crystal
OSC
Buffer
Rx
IR DEC
RXB
VCC
GND
A.
MF output allows selection of OP, BAUDOUT, or RXRDY per channel.
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TL16C2752
SLWS188A – JUNE 2006 – REVISED SEPTEMBER 2008 ................................................................................................................................................ www.ti.com
TERMINAL FUNCTIONS
TERMINAL
NAME
I/O
DESCRIPTION
FN NO.
RHB NO.
A0
10
3
I
Address 0 select bit. Internal registers address selection.
A1
14
6
I
Address 1 select bit. Internal registers address selection.
A2
15
7
I
Address 2 select bit. Internal registers address selection.
CDA,
CDB
42,
30
–
I
Carrier detect (active low). These inputs are associated with individual UART channels A and
B. A low on these pins indicates that a carrier has been detected by the modem for that
channel. The state of these inputs is reflected in the modem status register (MSR). These
inputs should be pulled high if unused.
CHSEL
16
8
I
Channel select. UART channel A or B is selected by the state of this pin when CS is a logic 0.
A logic 0 on the CHSEL selects the UART channel B, while a logic 1 selects UART channel A.
CHSEL could just be an address line from the user CPU such as A3. Bit 0 of the alternate
function register (AFR) can temporarily override CHSEL function, allowing the user to write to
both channel register simultaneously with one write cycle when CS is low. It is especially
useful during the initialization routine.
CS
18
10
I
UART chip select (active low). This pin selects channel A or B in accordance with the state of
the CHSEL pin. This allows data to be transferred between the user CPU and the TL16C2752.
I
Clear to send (active low). These inputs are associated with individual UART channels A and
B. A logic low on the CTS pins indicates the modem or data set is ready to accept transmit
data from the TL16C2752. Status can be tested by reading MSR bit 4. These pins only affect
the transmit and receive operations when auto CTS function is enabled through the enhanced
feature register (EFR) bit 7, for hardware flow control operation. These inputs should be pulled
high if unused.
I/O
Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring information
to or from the controlling CPU. D0 is the least significant bit (LSB) and the first data bit in a
transmit or receive serial data stream.
I
Data set ready (active low). These inputs are associated with individual UART channels A and
B. A logic low on these pins indicates the modem or data set is powered on and is ready for
data exchange with the UART. The state of these inputs is reflected in the modem status
register (MSR). These inputs should be pulled high if unused.
O
Data terminal ready (active low). These outputs are associated with individual UART channels
A and B. A logic low on these pins indicates that the TL16C2752 is powered on and ready.
These pins can be controlled through the modem control register. Writing a 1 to MCR bit 0
sets the DTR output to low, enabling the modem. The output of these pins is high after writing
a 0 to MCR bit 0, or after a reset.
CTSA,
CTSB
40,
28
25,
17
D0–D4
2–6
27–31
D5–D7
7–9
DSRA,
DSRB
41,
29
DTRA,
DTRB
32, 1, 2
–
37,
27
–
GND
12, 22
20
Signal and power ground
INTA,
INTB
34,
17
21,
9
O
Interrupt A and B (active high). These pins provide individual channel interrupts, INTA and
INTB. INTA and INTB are enabled when MCR bit 3 is set to a logic 1, interrupt sources are
enabled in the interrupt enable register (IER). Interrupt conditions include receiver errors,
available receiver buffer data, available transmit buffer space, or when a modem status flag is
detected. INTA and INTB are in the high-impedance state after reset.
IOR
24
14
I
Read input (active-low strobe). A high-to-low transition on IOR loads the contents of an
internal register defined by address bits A0–A2 onto the TL16C2752 data bus (D0–D7) for
access by an external CPU.
IOW
20
11
I
Write input (active-low strobe). A low-to-high transition on IOW transfers the contents of the
data bus (D0–D7) from the external CPU to an internal register that is defined by address bits
A0–A2 and CSA and CSB.
NC
–
18, 19
MFA,
MFB
4
35,
19
–
No internal connection
O
Multifunction. This output pin can function as the OP, BAUDOUT, or RXRDY pin. One of these
output signal functions can be selected by the user-programmable bits 1–2 of the alternate
function register (AFR). These signal functions are described as follows:
1. OP–When OP (active low) is selected, the MF pin is a logic 0 when MCR bit 3 is set to a
logic 1 (see MCR bit 3). MCR bit 3 defaults to a logic 1 condition after a reset or
powerup.
2. BAUDOUT–When BAUDOUT function is selected, the 16× baud rate clock output is
available at this pin.
3. RXRDY–RXRDY (active low) is intended for monitoring DMA data transfers.
If it is not used, leave it unconnected.
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TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
FN NO.
RHB NO.
RESET
21
12
RIA,
RIB
43,
31
–
I/O
DESCRIPTION
I
Reset. RESET will reset the internal registers and all the outputs. The UART transmitter
output and the receiver input are disabled during reset time. See TL16C2752 external reset
conditions for initialization details. RESET is an active-high input.
I
Ring indicator (active low). These inputs are associated with individual UART channels A and
B. A logic low on these pins indicates the modem has received a ringing signal from the
telephone line. A low-to-high transition on these input pins generates a modem status
interrupt, if enabled. The state of these inputs is reflected in the modem status register (MSR).
These inputs should be pulled high if unused.
RTSA,
RTSB
36,
23
22,
13
O
Request to send (active low). These outputs are associated with individual UART channels A
and B. A low on the RTS pin indicates the transmitter has data ready and waiting to send.
Writing a 1 in the modem control register (MCR bit 1) sets these pins to low, indicating data is
available. After a reset, these pins are set to high. These pins only affects the transmit and
receive operation when auto RTS function is enabled through the enhanced feature register
(EFR) bit 6, for hardware flow control operation.
RXA,
RXB
39,
25
24,
15
I
Receive data input. These inputs are associated with individual serial channel data to the
TL16C2752. During the local loopback mode, these RX input pins are disabled and TX data is
internally connected to the UART RX input internally.
TXA,
TXB
38,
26
23,
16
O
Transmit data. These outputs are associated with individual serial transmit channel data from
the TL16C2752. During the local loopback mode, the TX input pin is disabled and TX data is
internally connected to the UART RX input.
TXRDYA,
TXRDYB
1,
32
–
O
Transmit ready (active low). TXRDY A and B go low when there are at least a trigger-level
number of spaces available. They go high when the TX buffer is full.
33, 44
26
I
Power-supply inputs
VCC
XTAL1
11
4
I
Crystal or external clock. XTAL1 functions as a crystal input or as an external clock input. A
crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see
Figure 4). Alternatively, an external clock can be connected to XTAL1 to provide custom data
rates.
XTAL2
13
5
O
Crystal oscillator or buffered clock (see also XTAL1). XTAL2 is used as a crystal oscillator
output or buffered a clock output.
Detailed Description
Hardware Autoflow Control (see Figure 1)
Hardware autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input must be
active before the transmitter FIFO can emit data. With auto-RTS, RTS becomes active when the receiver needs
more data and notifies the sending serial device. When RTS is connected to CTS, data transmission does not
occur unless the receiver FIFO has space for the data; thus, overrun errors are eliminated using ACE1 and
ACE2 from a TLC16C2752 with the autoflow control enabled. If not, overrun errors can occur when the transmit
data rate exceeds the receiver FIFO read latency.
ACE1
RCV
FIFO
ACE2
Serial to
Parallel
Flow
Control
RX
RTS
TX
CTS
Parallel
to Serial
XMT
FIFO
Flow
Control
D7 −D0
D7 −D0
XMT
FIFO
Parallel
to Serial
Flow
Control
TX
CTS
RX
RTS
Serial to
Parallel
RCV
FIFO
Flow
Control
Figure 1. Autoflow Control (Auto-RTS and Auto-CTS) Example
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TL16C2752
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Auto-RTS
Auto-RTS data flow control originates in the receiver timing and control block (see Figure 4) and is linked to the
programmed receiver FIFO trigger level. When the receiver FIFO level reaches the defined halt trigger level 8
(see Figure 3), RTS is deasserted. The sending ACE may send an additional byte after the trigger level is
reached (assuming the sending ACE has another byte to send) because it may not recognize the deassertion of
RTS until after it has begun sending the additional byte. RTS is automatically reasserted once the defined
resume trigger level is reached.
Auto-CTS
The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the next
byte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the last
stop bit that is currently being sent (see Figure 2). The auto-CTS function reduces interrupts to the host system.
When flow control is enabled, CTS level changes do not trigger host interrupts because the device automatically
controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the transmit FIFO and a
receiver overrun error may result.
Auto-RTS and Auto-CTS Functional Timing
SIN
Start
Byte N
Stop
Start
Byte N+1
Start
Stop
Byte
Stop
RTS
RD
(RD RBR)
1
2
N
N+1
Figure 2. RTS Functional Timing Waveforms
SOUT
Start
Bits 0 −7
Stop
Start
Bits 0 −7 Stop
Start
Bits 0 −7 Stop
CTS
Figure 3. CTS Functional Timing Waveforms
A.
Pin numbers shown are for 44-pin PLCC FN package.
Figure 4. Functional Block Diagram
6
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range (2)
–0.5
7
V
VI
Input voltage range at any input
–0.5
7
V
VO
Output voltage range
V
TA
Operating free-air temperature range
Tstg
Storage temperature range
–0.5
7
TL16C2752
0
70
TL16C2752I
–40
85
–65
150
°C
260
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 s
(1)
(2)
UNIT
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to VSS.
RECOMMENDED OPERATING CONDITIONS
1.8 V ＝10%
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
1.62
1.8
1.98
V
0
VCC
V
High-level input voltage
1.4
1.98
V
VIL
Low-level input voltage
–0.3
0.4
V
VO
Output voltage
0
VCC
V
IOH
High-level output current (all outputs)
0.5
mA
IOL
Low-level output current (all outputs)
VCC
Supply voltage
VI
Input voltage
VIH
Oscillator/clock speed
1
mA
10
MHz
RECOMMENDED OPERATING CONDITIONS
2.5 V ＝10%
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
2.25
2.5
2.75
V
0
VCC
V
High-level input voltage
1.8
2.75
V
Low-level input voltage
–0.3
0.6
V
0
VCC
VCC
Supply voltage
VI
Input voltage
VIH
VIL
VO
Output voltage
IOH
High-level output current (all outputs)
IOL
Low-level output current (all outputs)
1
Oscillator/clock speed
2
mA
16
MHz
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V
mA
7
TL16C2752
SLWS188A – JUNE 2006 – REVISED SEPTEMBER 2008 ................................................................................................................................................ www.ti.com
RECOMMENDED OPERATING CONDITIONS
3.3 V ＝10%
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
VCC
Supply voltage
3
3.3
3.6
V
VI
Input voltage
0
VCC
V
VIH
High-level input voltage
VIL
Low-level input voltage
VO
Output voltage
IOH
IOL
0.7 × VCC
UNIT
V
0.3 × VCC
0
V
VCC
V
High-level output current (all outputs)
1.8
mA
Low-level output current (all outputs)
3.2
mA
Oscillator/clock speed
20
MHz
RECOMMENDED OPERATING CONDITIONS
5 V ＝10%
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
4.5
5
5.5
UNIT
V
VCC
V
VCC
Supply voltage
VI
Input voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VO
Output voltage
IOH
High-level output current (all outputs)
4
mA
IOL
Low-level output current (all outputs)
4
mA
24
MHz
0
All except XTAL1, XTAL2
2
XTAL1, XTAL2
V
0.7 × VCC
All except XTAL1, XTAL2
0.8
XTAL1, XTAL2
V
0.3 × VCC
0
VCC
Oscillator/clock speed
V
ELECTRICAL CHARACTERISTICS
1.8 V Nominal
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
MIN TYP (1) MAX
TEST CONDITIONS
(2)
VOH
High-level output voltage
VOL
Low-level output voltage (2)
IOL = 1 mA
0.5
V
II
Input current
VCC = 1.98 V, VSS = 0, VI = 0 to 1.98 V,
All other terminals floating
10
＝A
IOZ
High-impedance-state
output current
VCC = 1.98 V, VSS = 0, VI = 0 to 1.98 V,
Chip selected in write mode or chip deselected
±20
＝A
ICC
Supply current
VCC = 1.98 V, TA = 0°C, RXA, RXB, DSRA, DSRB, CDA,
CDB, CTSA, CTSB, RIA, and RIB at 1.4 V, All other inputs at
0.4 V, XTAL1 at 16 MHz, No load on outputs
Ci(CLK)
Clock input impedance
CO(CLK)
Clock output impedance
CI
Input impedance
CO
Output impedance
(1)
(2)
8
IOH = –0.5 mA
VCC = 0, VSS = 0, f = 1 MHz,
TA = 25°C, All other terminals grounded
1.3
UNIT
V
mA
15
20
pF
20
30
pF
6
10
pF
10
20
pF
All typical values are at VCC = 1.8 V and TA = 25°C.
These parameters apply for all outputs except XTAL2.
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ELECTRICAL CHARACTERISTICS
2.5 V Nominal
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
MIN TYP (1) MAX
TEST CONDITIONS
(2)
High-level output voltage
VOL
Low-level output voltage (2)
IOL = 2 mA
0.5
V
II
Input current
VCC = 2.75 V, VSS = 0, VI = 0 to 2.75 V,
All other terminals floating
10
＝A
IOZ
High-impedance-state
output current
VCC = 2.75 V, VSS = 0, VI = 0 to 2.75 V,
Chip selected in write mode or chip deselected
±20
＝A
ICC
Supply current
VCC = 2.75 V, TA = 0°C, RXA, RXB, DSRA, DSRB, CDA,
CDB, CTSA, CTSB, RIA, and RIB at 1.8 V, All other
inputs at 0.6 V, XTAL1 at 24 MHz, No load on outputs
Ci(CLK)
Clock input impedance
CO(CLK)
Clock output impedance
CI
Input impedance
CO
Output impedance
(1)
(2)
IOH = –1 mA
1.8
UNIT
VOH
V
mA
VCC = 0, VSS = 0, f = 1 MHz,
TA = 25°C, All other terminals grounded
15
20
pF
20
30
pF
6
10
pF
10
20
pF
All typical values are at VCC = 2.5 V and TA = 25°C.
These parameters apply for all outputs except XTAL2.
ELECTRICAL CHARACTERISTICS
3.3 V Nominal
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(2)
MIN
MAX
High-level output voltage
VOL
Low-level output voltage (2)
IOL = 3.2 mA
0.5
V
II
Input current
VCC = 3.6 V, VSS = 0, VI = 0 to 3.6 V,
All other terminals floating
10
＝A
IOZ
High-impedance-state
output current
VCC = 3.6 V, VSS = 0, VI = 0 to 3.6 V,
Chip selected in write mode or chip deselected
±20
＝A
ICC
Supply current
VCC = 3.6 V, TA = 0°C, RXA, RXB, DSRA, DSRB, CDA,
CDB, CTSA, CTSB, RIA, and RIB at 2 V, All other inputs
at 0.8 V, XTAL1 at 32 MHz, No load on outputs
Ci(CLK)
Clock input impedance
CO(CLK)
Clock output impedance
CI
Input impedance
CO
Output impedance
VCC = 0, VSS = 0, f = 1 MHz,
TA = 25°C, All other terminals grounded
2.4
UNIT
VOH
(1)
(2)
IOH = –1.8 mA
TYP (1)
V
mA
15
20
pF
20
30
pF
6
10
pF
10
20
pF
All typical values are at VCC = 3.3 V and TA = 25°C.
These parameters apply for all outputs except XTAL2.
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ELECTRICAL CHARACTERISTICS
5 V Nominal
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(2)
TYP (1)
MIN
VOL
Low-level output voltage (2)
IOL = 4 mA
0.4
V
II
Input current
VCC = 5.5 V, VSS = 0, VI = 0 to 5.5 V,
All other terminals floating
10
＝A
IOZ
High-impedance-state
output current
VCC = 3.6 V, VSS = 0, VI = 0 to 3.6 V,
Chip selected in write mode or chip deselected
＝20
＝A
ICC
Supply current
VCC = 5.5 V, TA = 0°C, RXA, RXB, DSRA, DSRB, CDA,
CDB, CTSA, CTSB, RIA, and RIB at 2 V,
All other inputs at 0.8 V, XTAL1 at 32 MHz,
No load on outputs
Ci(CLK)
Clock input impedance
Clock output impedance
CI
Input impedance
CO
Output impedance
(1)
(2)
4
UNIT
High-level output voltage
CO(CLK)
IOH = –4 mA
MAX
VOH
V
mA
VCC = 0, VSS = 0, f = 1 MHz,
TA = 25°C, All other terminals grounded
15
20
pF
20
30
pF
6
10
pF
10
20
pF
All typical values are at VCC = 3.3 V and TA = 25°C.
These parameters apply for all outputs except XTAL2.
TIMING REQUIREMENTS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
LIMITS
PARAMETER
ALT.
SYMBOL
FIGURE
TEST
CONDITIONS
1.8 V
MIN
2.5 V
MAX
MIN
3.3 V
MAX
MIN
5V
MAX
MIN
UNIT
MAX
1
1
1
1
＝s
6
25
16
12
8
ns
RC
8
115
80
62
57
ns
WC
7
115
80
62
57
ns
tIOW
7
80
55
45
40
ns
Pulse duration, IOR or CS
tIOR
8
80
55
45
40
ns
tSU3
Setup time, data valid before IOW↑
or CS↑
tDS
7
25
20
15
15
ns
th4
Hold time, address valid after IOW↑
or CS↑
tWA
7
20
15
10
10
ns
th5
Hold time, data valid after IOW↑ or
CS↑
tDH
7
15
10
5
5
ns
th7
Hold time, data valid after IOR↑ or
CS↑
tRA
8
20
15
10
10
ns
td5
Delay time, address valid before
IOW↓ or CS↓
tAW
7
15
10
7
7
ns
td8
Delay time, address valid to IOR↓ or
CS↓
tAR
8
15
10
7
7
ns
td10
Delay time, IOR↓ or CS↓ to data
valid
tRVD
8
CL = 30 pF
55
35
25
20
ns
td11
Delay time, IOR↑ or CS↑ to floating
data
tHZ
8
CL = 30 pF
40
30
20
20
ns
td12
Write cycle to write cycle delay
7
100
75
60
50
ns
td13
Read cycle to read cycle delay
8
100
75
60
50
ns
tw8
Pulse duration, RESET
tw1
Pulse duration, clock high
tXH
tw2
Pulse duration, clock low
tXL
tcR
Cycle time, read (tw7 + td8 + th7)
tcW
Cycle time, write (tw6 + td5 + th4)
tw6
Pulse duration, IOW or CS
tw7
10
tRESET
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BAUD GENERATOR SWITCHING CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature, CL = 30 pF (for FN package only)
PARAMETER
ALT.
SYMBOL
FIGURE
TEST
CONDITION
S
LIMITS
1.8 V
MIN
2.5 V
MAX
MIN
3.3 V
MAX
MIN
5V
MAX
MIN
UNIT
MAX
tw3
Pulse duration, BAUDOUT low
tLW
6
CLK ÷ 2
50
35
27
16
tw4
Pulse duration, BAUDOUT high
tHW
6
CLK ÷ 2
50
35
27
16
ns
td1
Delay time, XIN↑ to BAUDOUT↑
tBLD
6
35
25
20
15
ns
td2
Delay time, XIN↑↓ to BAUDOUT↓
tBHD
6
35
25
20
15
ns
ns
RECEIVER SWITCHING CHARACTERISTICS (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
LIMITS
PARAMETER
ALT.
SYMBOL
FIGURE
TEST
CONDITIONS
1.8 V
2.5 V
MIN
MAX
MIN
3.3 V
MAX
MIN
5V
MAX
td12
Delay time, RCLK to sample
tSCD
9
20
15
10
td13
Delay time, stop to set INT or
read RBR to LSI interrupt or stop
to RXRDY↓
tSINT
8, 9, 10,
11, 12
1
1
1
td14
Delay time, read RBR/LSR to
reset INT
tRINT
8, 9, 10,
11, 12
CL = 30 pF
100
90
80
td26
Delay time, RCV threshold byte
to RTS↑
19
td27
Delay time, read of last byte in
receive FIFO to RTS↓
td28
Delay time, first data bit of 16th
character to RTS↑
td29
(1)
(2)
Delay time, RBRRD low to RTS↓
MIN
UNIT
MAX
10
ns
RCLK
cycle
1
70
ns
CL = 30 pF
2
baudout
cycles (2)
19
CL = 30 pF
2
baudout
cycles
20
CL = 30 pF
2
baudout
cycles
20
CL = 30 pF
2
baudout
cycles
In the FIFO mode, the read cycle (RC) = 1 baud clock (min) between reads of the receive FIFO and the status registers (interrupt
identification register or line status register).
A baudout cycle is equal to the period of the input clock divided by the programmed divider in DLL, DLM.
TRANSMITTER SWITCHING CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
LIMITS
PARAMETER
ALT.
SYMBOL
FIGURE
TEST
CONDITIONS
1.8 V
2.5 V
3.3 V
5V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
td15
Delay time, initial write to transmit
start
tIRS
14
8
24
8
24
8
24
8
24
baudout
cycles
td16
Delay time, start to INT
tSTI
14
8
10
8
10
8
10
8
10
baudout
cycles
td17
Delay time, IOW (WR THR) to
reset INT
tHR
14
50
ns
td18
Delay time, initial write to INT
(THRE (1))
tSI
14
34
baudout
cycles
td19
Delay time, read IOR↑ to reset INT
(THRE (1))
tIR
14
CL = 30 pF
70
50
35
35
ns
td20
Delay time, write to TXRDY
inactive
tWXI
15, 16
CL = 30 pF
60
45
35
35
ns
td21
Delay time, start to TXRDY active
tSXA
15, 16
CL = 30 pF
9
9
9
9
baudout
cycles
tSU4
Setup time, CTS↑ before midpoint
of stop bit
18
td25
Delay time, CTS low to TX↓
18
(1)
CL = 30 pF
70
16
34
30
CL = 30 pF
60
16
34
20
24
50
16
34
10
24
16
10
24
ns
24
baudout
cycles
THRE = Transmitter holding register empty; IIR = interrupt identification register
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MODEM CONTROL SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
LIMITS
ALT.
SYMBOL
PARAMETER
FIGURE
TEST
CONDITIONS
1.8 V
MIN
2.5 V
MAX
MIN
3.3 V
MAX
MIN
5V
MAX
MIN
UNIT
MAX
td22
Delay time, WR MCR to output
tMDO
17
CL = 30 pF
90
70
60
50
ns
td23
Delay time, modem interrupt to
set INT
tSIM
17
CL = 30 pF
60
50
40
35
ns
td24
Delay time, RD MSR to reset
INT
tRIM
17
CL = 30 pF
80
60
50
40
ns
N
tw1
tw2
XTAL
td2
td1
MFA,B
(1/1)
td1
td2
MFA,B
(1/2)
tw3
tw4
MFA,B
(1/3)
MFA,B
(1/N)
(N > 3)
2 XIN Cycles
(N −2) XIN Cycles
Figure 5. Input Clock and Baud Generator Timing Waveforms
(for FN Package Only) (When AFR2:1 = 01)
12
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CHSEL,
A2 −A0
Valid Address
Valid Address
td5
td5
th4
th4
tw6
tw6
CS
td12
tw6
tw6
IOW
tsu3
tsu3
th5
D7 −D0
th5
Valid Data
Valid Data
Figure 6. Write Cycle Timing Waveforms
CHSEL,
A2 −A0
Valid Address
Valid Address
td8
td8
th7
th7
tw7
tw7
CS
td13
tw7
tw7
IOR
td10
td11
D7 −D0
td10
Valid Data
th11
Valid Data
Figure 7. Read Cycle Timing Waveforms
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RCLK
(Internal)
td12
8 CLKs
Sample Clock
(Internal)
TL16C450 Mode:
RXA, RXB
Start
Data Bits 5− 8
Parity
Stop
Sample Clock
INT
(data ready)
50%
td13
INT
(RCV error)
td14
50%
50%
IOR
(read RBR)
IOR
(read LSR)
50%
50%
50%
Active
Active
td14
Figure 8. Receiver Timing Waveforms
14
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RXA, RXB
Data Bits 5 −8
Stop
Sample Clock
(Internal)
Trigger Level
INT
(FCR6, 7 = 0, 0)
50%
50%
(FIFO at or above
trigger level)
(FIFO below
trigger level)
td13
(see Note A)
INT
Line Status
Interrupt (LSI)
td14
50%
50%
td14
IOR
(RD LSR)
Active
50%
Active
IOR
(RD RBR)
50%
Figure 9. Receive FIFO First Byte (Sets DR Bit) Waveforms
RXA, RXB
Stop
Sample Clock
(Internal)
Time-Out or
Trigger Level
Interrupt
50%
50%
(FIFO below
trigger level)
td13
td14
(see Note A)
50%
Line Status
Interrupt (LSI)
td13
50%
Top Byte of FIFO
td14
IOP
(RD LSR)
IOR
(RD RBR)
(FIFO at or above
trigger level)
50%
50%
Active
50%
Active
Previous Byte
Read From FIFO
Figure 10. Receive FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set) Waveforms
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IOR
(RD RBR)
50%
Active
See Note A
RXA, RXB
(first byte)
Stop
Sample Clock
(Internal)
td13
(see Note B)
td14
50%
50%
RXRDYA, RXRDYB
Figure 11. Receiver Ready (RXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)
IOR
(RD RBR)
Active
50%
See Note A
RXA, RXB
(first byte that reaches
the trigger level)
Sample Clock
(Internal)
td13
(see Note B)
td14
50%
RXRDYA, RXRDYB
50%
Figure 12. Receiver Ready (RXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1)
Start
50%
TXA, TXB
Data Bits
Parity
Stop
td15
INT
(THRE)
50%
Start
50%
td16
50%
50%
50%
50%
td18
td17
td17
IOW 50%
(WR THR)
50%
50%
td19
IOR
50%
Figure 13. Transmitter Timing Waveforms
16
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Byte 1
IOW
(WR THR)
TXA, TXB
50%
Data
Parity
Stop
Start
50%
td21
td20
TXRDYA, TXRDYB
50%
50%
Figure 14. Transmitter Ready (TXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)
Byte 16
IOW
(WR THR)
TXA, TXB
50%
Data
Parity
Stop
td21
td20
TXRDYA, TXRDYB
Start
50%
50%
50%
FIFO Full
Figure 15. Transmitter Ready (TXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1)
IOW
(WR MCR)
50%
50%
td22
td22
RTSA, RTSB, DTRA,
DTRB, OPA, OPB
50%
50%
50%
CTSA, CTSB, DSRA,
DSRB, CDA, CDB
td23
INT
(modem)
50%
50%
50%
td24
IOR
(RD MSR)
50%
td23
RI
50%
Figure 16. Modem Control Timing Waveforms
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tsu4
CTSA, CTSB
50%
50%
td25
TXA, TXB
50%
Midpoint of Stop Bit
Figure 17. CTS and TX Autoflow Control Timing (Start and Stop) Waveforms
Midpoint of Stop Bit
RXA, RXB
td26
RTSA,
RTSB
IOR
td27
50%
50%
50%
Figure 18. Auto-RTS Timing
18
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APPLICATION INFORMATION
A.
Pin numbers shown are for 44-pin PLCC FN package.
Figure 19. Typical TL16C2752 Connection
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PRINCIPLES OF OPERATION
UART Internal Registers
Each of the UART channel in the TL16C2752 has its own set of configuration registers selected by address lines
A0, A1, and A2 with CS and CHSEL selecting the channel. The complete register set is shown in Table 1 and
Table 2.
Table 1. UART Channel A and B UART Internal Registers
ADDRESS
A2–A0
RESET
(HEX)
VALUE
COMMENTS
REGISTER
READ/WRITE
16C550 Compatible Registers
000
XX
XX
000
XX
001
XX
010
00
LCR[7] = 0
LCR[7] = 1, LCR ≠ 0xBF
RHR–Receive Holding Register
THR–Transmit Holding Register
Read only
Write only
DLL–Div Latch Low Byte
Read/Write
DLM–Div Latch High Byte
Read/Write
AFR–Alternate Function Register
Read/Write
Read only
000
00
0A
DLL, DLM = 0x00,
LCR[7] = 1, LCR ≠ 0xBF
DREV–Device Revision Code
001
DVID–Device Identification Code
Read only
001
00
LCR[7] = 0
IER–Interrupt Enable Register
Read/Write
010
01
00
LCR[7] = 0
ISR–Interrupt Status Register
FCR–FIFO Control Register
Read only
Write only
011
00
LCR–Line Control Register
Read/Write
100
00
MCR–Modem Control Register
Read/Write
101
60
LSR–Line Status Register
Reserved
Read only
Write only
110
X0
MSR–Modem Status Register
Reserved
Read only
Write only
111
FF
SPR–Scratch Pad Register
Read/Write
111
00
FLVL–RX/TX FIFO Level Counter Register
Read only
111
80
EMSR–Enhanced Mode Select Register
Write only
LCR ≠ 0xBF
LCR ≠ 0xBF, FCTR[6] = 0
LCR ≠ 0xBF, FCTR[6] = 1
Enhanced Registers
20
000
00
00
TRG–RX/TX FIFO Trigger Level Register
FC–RX/TX FIFO Level Counter Register
Write only
Read only
001
00
FCTR–Feature Control Register
Read/Write
010
00
EFR–Enhanced Function Register
Read/Write
100
00
Xon-1–Xon Character 1
Read/Write
101
00
Xon-2–Xon Character 2
Read/Write
110
00
Xoff-1–Xoff Character 1
Read/Write
111
00
Xoff-2–Xoff Character 2
Read/Write
LCR = 0xBF
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Table 2. Internal Registers Description (1)
Address
A2–A0
Register
Name
Read/
Write
Comments
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
16C550 Compatible Registers
000
RHR
RD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
000
THR
WR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
001
IER
RD/WR
0/
0/
0/
0/
CTS Int.
Enable
RTS Int.
Enable
Xoff Int.
Enable
Sleep Mode
Enable
Modem Stat.
Int. Enable
RX Line Stat.
Int. Enable
TX Empty Int.
Enable
RX Data Int.
Enable
FIFOs
Enabled
FIFOs
Enabled
INT Source Bit
3
INT Source Bit
2
INT Source Bit
1
INT Source Bit
0
RXFIFO
Trigger
RXFIFO
Trigger
DMA Mode
Enable
TX FIFO
Reset
RX FIFO
Reset
FIFOs Enable
Divisor
Enable
Set TX Break
010
010
ISR
FCR
LCR[7] = 0
RD
WR
011
LCR
RD/WR
100
MCR
RD/WR
101
LSR
RD
110
MSR
RD
111
SPR
RD/WR
111
EMSR
WR
111
FLVL
RD
LCR ≠ 0xBF
LCR ≠ 0xBF
FCTR Bit 6 = 0
LDR ≠ 0xBF
FCTR Bit 6 = 1
0/
0/
INT Source Bit
5
INT Source
Bit 4
0/
0/
TXFIFO
Trigger
TXFIFO
Trigger
Set Parity
Even Parity
Parity Enable
Stop Bits
Word Length
Bit 1
Word Length
Bit 0
0/
0/
0/
BRG
Prescaler
IR Mode
Enable
XonAny
Internal
Loopback
Enable
OP2# Output
Control
Rsrvd (OP1#)
RTS# Output
Control
DTR# Output
Control
RX FIFO
Global Error
THR & TSR
Empty
THR Empty
RX Break
RX Framing
Error
RX Parity
Error
RX Overrun
Error
RX Data
Ready
CD# Input
RI# Input
DSR# Input
CTS# Input
Delta CD#
Delta RI#
Delta DSR#
Delta CTS#
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
16X
Sampling
Rate Mode
LSR Error
Interrupt
Imd/Dly#
Auto RTS
Hyst. Bit 3
Auto RTS
Hyst Bit 2
Auto RS485
Output
Inversion
Rsrvd
Rx/Tx FIFO
Count
Rx/Tx FIFo
Count
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 0
Baud-Rate Generator Divisor
000
DLL
RD/WR
001
DLM
RD/WR
LCR[7] = 1 LCR
≠ 0xBF
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Baudout#
Select
Concurrent
Write
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
RXRDY#
Select
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
1
0
1
0
WR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RX IR Input
Inv.
Auto RTS
Hyst Bit 1
Auto RTS
Hyst Bit 0
010
AFR
RD/WR
000
DREV
RD
001
DVID
RD
000
TRG
000
FC
LCR[7] = 1 LCR
≠ 0xBF DLL =
0x00 DLM =
0x00
Enhanced Registers
001
(1)
FCTR
RD/WR
LCR = 0xBF
RX/TX
Mode
SCPAD Swap
Trig Table Bit
1
Trig Table
Bit 0
Auto RS485
Direction
Control
Auto CTS
Enable
Auto RTS
Enable
Special Char
Select
Enable
IER[7:4],
ISR[5:4],
FCT[5:4],
MCR[7:5]
Software Flow
Cntl Bit 3
Software Flow
Cntl Bit 2
Software Flow
Cntl Bit 1
Software Flow
Cntl Bit 0
010
EFR
RD/WR
100
XON1
RD/WR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
101
XON2
RD/WR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
110
XOFF1
RD/WR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
111
XOFF2
RD/WR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Shaded bits are accessible when EFR Bit 4 = 1.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TL16C2752FN
ACTIVE
PLCC
FN
44
26
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
2752FN
TL16C2752IFN
ACTIVE
PLCC
FN
44
26
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
2752IFN
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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