TL16C450N

   
 
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 D Programmable Baud Rate Generator Allows N PACKAGE (TOP VIEW) Division of Any Input Reference Clock by 1 to (216 −1) and Generates an Internal 16 × Clock D0 D1 D2 D3 D4 D5 D6 D7 RCLK SIN SOUT CS0 CS1 CS2 BAUDOUT XTAL1 XTAL2 DOSTR DOSTR VSS D Full Double Buffering Eliminates the Need for Precise Synchronization D Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added or Deleted to or From the Serial Data Stream D Independent Receiver Clock Input D Transmit, Receive, Line Status, and Data Set Interrupts Independently Controlled D Fully Programmable Serial Interface Characteristics: − 5-, 6 -, 7 -, or 8-Bit Characters − Even-, Odd -, or No-Parity Bit Generation and Detection − 1-, 1 1/2 -, or 2-Stop Bit Generation − Baud Generation (dc to 256 Kbit/s) D False Start Bit Detection D Complete Status Reporting Capabilities DTR, RI, and DCD) D Easily Interfaces to Most Popular Microprocessors 38 4 37 5 36 6 35 7 34 8 33 9 32 10 31 11 30 12 29 13 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 D5 D6 D7 RCLK SIN NC SOUT CS0 CS1 CS2 BAUDOUT D Faster Plug-In Replacement for National Semiconductor NS16C450 6 5 4 7 3 2 1 44 43 42 41 40 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 17 29 18 19 20 21 22 23 24 25 26 27 28 MR OUT1 DTR RTS OUT2 NC INTRPT NC A0 A1 A2 XTAL1 XTAL2 DOSTR DOSTR VSS NC DISTR DISTR DDIS CSOUT ADS D Modem Control Functions (CTS, RTS, DSR, 3 VCC RI DCD DSR CTS MR OUT1 DTR RTS OUT2 INTRPT NC A0 A1 A2 ADS CSOUT DDIS DISTR DISTR D4 D3 D2 D1 D0 NC VCC RI DCD DSR CTS D Line Break Generation and Detection D Fully Prioritized Interrupt System Controls 39 FN PACKAGE (TOP VIEW) Bidirectional Data Bus and Control Bus − Loopback Controls for Communications Link Fault Isolation − Break, Parity, Overrun, Framing Error Simulation 40 2 NOTE: 40-pin DIP (N package) will be obsoleted as of 7/30/2006. Please contact your local distributor or TI Sales Office for more information. D 3-State TTL Drive Capabilities for D Internal Diagnostic Capabilities: 1 − No internal connection Please be aware that an important notice concerningNC availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  1988 − 2006, Texas Instruments Incorporated 
 
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SLLS037C − MARCH 1988 − REVISED JANUARY 2006 description The TL16C450 is a CMOS version of an asynchronous communications element (ACE). It typically functions in a microcomputer system as a serial input/output interface. The TL16C450 performs serial-to-parallel conversion on data received from a peripheral device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read and report on the status of the ACE at any point in the ACE’s operation. Reported status information includes the type of transfer operation in progress, the status of the operation, and any error conditions encountered. The TL16C450 ACE includes a programmable, on-board, baud rate generator. This generator is capable of dividing a reference clock input by divisors from 1 to (216 −1) and producing a 16× clock for driving the internal transmitter logic. Provisions are included to use this 16 × clock to drive the receiver logic. Also included in the ACE is a complete modem control capability and a processor interrupt system that may be software tailored to the user’s requirements to minimize the computing required to handle the communications link. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
   
 
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 block diagram Internal Data Bus D7 −D0 2−9 Data Bus Buffer Receiver Shift Register Receiver Buffer Register Line Control Register 11 Receiver Timing and Control 10 SIN RCLK Divisor Latch (LS) Baud Generator 17 BAUDOUT Divisor Latch (MS) A0 A1 A2 CS0 CS1 CS2 ADS MR DISTR DISTR DOSTR DOSTR DDIS CSOUT XTAL1 XTAL2 VCC VSS 31 30 29 14 15 16 28 39 25 24 21 20 26 27 18 19 44 22 Transmitter Timing and Control Line Status Register Select and Control Logic Transmitter Holding Register 13 Modem Control Logic 36 40 37 41 42 43 38 35 Modem Control Register Modem Status Register Power Supply Transmitter Shift Register Interrupt Enable Register Interrupt Control Logic 33 SOUT RTS CTS DTR DSR DCD RI OUT1 OUT2 INTRPT Interrupt I/O Register Terminal numbers shown are for the FN package. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 
   
 
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 Terminal Functions TERMINAL NO.† I/O DESCRIPTION A0 A1 A2 31 30 29 I Register select. A0, A1, and A2 are three inputs used during read and write operations to select the ACE register to read from or write to. Refer to Table 1 for register addresses, also refer to the address strobe (ADS) signal description. ADS 28 I Address strobe. When ADS is active (low), the register select signals (A0, A1, and A2) and chip select signals (CS0, CS1, CS2) drive the internal select logic directly; when high, the register select and chip select signals are held in the state they were in when the low-to-high transition of ADS occurred. BAUDOUT 17 O Baud out. BAUDOUT is a16 × clock signal for the transmitter section of the ACE. The clock rate is established by the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches. BAUDOUT may also be used for the receiver section by tying this output to the RCLK input. CS0 CS1 CS2 14 15 16 I Chip select. When CSx is active (high, high, and low respectively), the ACE is selected. Refer to the ADS signal description. CSOUT 27 O Chip select out. When CSOUT is high, it indicates that the ACE has been selected by the chip select inputs (CS0, CS1, and CS2). CSOUT is low when the chip is deselected. CTS 40 I Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem status register. Bit 0 (DCTS) of the modem status register indicates that this signal has changed states since the last read from the modem status register. If the modem status interrupt is enabled when CTS changes state, an interrupt is generated. 2−9 I/O Data bus. D0 − D7 are 3-state data lines that provide a bidirectional path for data, control, and status information between the ACE and the CPU. DCD 42 I Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the modem status register. Bit 3 (DDCD) of the modem status register indicates that this signal has changed states since the last read from the modem status register. If the modem status interrupt is enabled when the DCD changes state, an interrupt is generated. DDIS 26 O Driver disable. DDIS is active (high) when the CPU is not reading data. When active, this output can disable an external transceiver. DISTR DISTR 25 24 I Data input strobes. When either DISTR or DISTR is active (high or low respectively) while the ACE is selected, the CPU is allowed to read status information or data from a selected ACE register. Only one of these inputs is required for the transfer of data during a read operation. The other input should be tied in its inactive state (i.e., DISTR tied low or DISTR tied high). DOSTR DOSTR 21 20 I Data output strobes. When either DOSTR or DOSTR is active (high or low respectively), while the ACE is selected, the CPU is allowed to write control words or data into a selected ACE register. Only one of these inputs is required to transfer data during a write operation. The other input should be tied in its inactive state (i.e., DOSTR tied low or DOSTR tied high). DSR 41 I Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the modem status register. Bit 1 (DDSR) of the modem status register indicates that this signal has changed state since the last read from the modem status register. If the modem status interrupt is enabled when the DSR changes state, an interrupt is generated. DTR 37 O Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish communication. DTR is placed in the active state by setting the DTR bit of the modem control register to a high level. DTR is placed in the inactive state either as a result of a master reset or during loop mode operation or clearing bit 0 (DTR) of the modem control register. INTRPT 33 O Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. The four conditions that cause an interrupt are: a receiver error, received data is available, the transmitter holding register is empty, or an enabled modem status interrupt. The INTRPT output is reset (inactivated) either when the interrupt is serviced or as a result of a master reset. MR 39 I Master reset. When active (high), MR clears most ACE registers and sets the state of various output signals. Refer to Table 2 for ACE reset functions. NAME D0 − D7 † Terminal numbers shown are for the FN package. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
   
 
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 Terminal Functions (continued) TERMINAL NAME NO.† I/O DESCRIPTION OUT1 OUT2 38 35 O Outputs 1 and 2. OUT1 and OUT2 are user-designated output terminals that are set to their active states by setting their respective modem control register bits (OUT1 and OUT2) high. OUT1 and OUT2 are set to their inactive (high) states as a result of master reset or during loop mode operations or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the MCR. RCLK 10 I Receiver clock. RCLK is the 16 × baud rate clock for the receiver section of the ACE. RI 43 I Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the modem status register. Bit 2 (TERI) of the modem status register indicates that the RI input has transitioned from a low to a high state since the last read from the modem status register. If the modem status interrupt is enabled when this transition occurs, an interrupt is generated. RTS 36 O Request to send. When active, RTS informs the modem or data set that the ACE is ready to transmit data. RTS is set to its active state by setting the RTS modem control register bit and is set to its inactive (high) state either as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the MCR. SIN 11 I Serial input. SIN is the serial data input from a connected communications device. SOUT 13 O Serial output. SOUT is the composite serial data output to a connected communication device. SOUT is set to the marking (set) state as a result of MR. VCC VSS 44 5-V supply voltage 22 Supply common XTAL1 18 I/O External clock. XTAL1 and XTAL2 connect the ACE to the main timing reference (clock or crystal). XTAL2 19 † Terminal numbers shown are for the FN package. absolute maximum ratings over free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range at any input, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Continuous total power dissipation at (or below) 70°C free-air temperature: FN package . . . . . . . 1100 mW N package‡ . . . . . . . . 800 mW Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Case temperature for 10 seconds, TC: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package‡ . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ The N package in Not Recommended for New Designs. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions Supply voltage, VCC High-level input voltage, VIH MIN NOM MAX UNIT 4.75 5 5.25 V V −0.5 VCC 0.8 0 70 °C 2 Low-level input voltage, VIL Operating free-air temperature, TA POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V 5 
   
 
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VOH‡ VOL‡ TEST CONDITIONS HIgh-level output voltage Low-level output voltage MIN IOH = − 1 mA IOL = 1.6 mA TYP† MAX 2.4 IIkg Input leakage current VCC = 5.25 V, VI = 0 to 5.25 V, IOZ High-impedance output current VCC = 5.25 V, VSS = 0, VO = 0 V to 5.25 V, Chip selected, write mode,or chip deselected ICC Supply current 25°C, VCC = 5.25 V, TA = 25 C, SIN, DSR, DCD, CTS, and RI at 2 V, All other inputs at 0.8 V, Baud rate = 50 kbits/s, XTAL1 at 4 MHz, No load on outputs CXTAL1 Clock input capacitance CXTAL2 Clock output capacitance Ci Input capacitance V 0.4 V ± 10 µA A ± 20 µA A 10 mA 15 20 pF 20 30 pF 6 10 pF 10 20 pF VSS = 0, All other terminals floating VCC = 0, VSS = 0, f = 1 MHz, TA = 25°C, All other terminals grounded Co Output capacitance † All typical values are at VCC = 5 V, TA = 25°C. ‡ These parameters apply for all outputs except XTAL2. UNIT system timing requirements over recommended ranges of supply voltage and operating free-air temperature PARAMETER tcR tcW Cycle time, read (tw7 + td8 + td9) tw5 tw6 Pulse duration, ADS low FIGURE Cycle time, write (tw6 + td5 + td6) MIN MAX UNIT 175 ns 175 ns 2, 3 15 ns Pulse duration, write strobe 2 80 ns tw7 twMR Pulse duration, read strobe 3 tsu1 tsu2 Setup time, address valid before ADS↑ Setup time, CS valid before ADS↑ tsu3 th1 Setup time, data valid before WR1↓ or WR2↑ th2 th3 th4§ 80 ns 1000 ns 2, 3 15 ns 2, 3 15 ns 2 15 ns Hold time, address low after ADS↑ 2, 3 0 ns Hold time, CS valid after ADS↑ 2, 3 0 ns Hold time, CS valid after WR1↑ or WR2↓ 2 20 ns Hold time, address valid after WR1↑ or WR2↓ 2 20 ns th5 th6 th7§ Hold time, data valid after WR1↑ or WR2↓ 2 15 ns Hold time, CS valid after RD1↑ or RD2↓ 3 20 ns Hold time, address valid after RD1↑ or RD2↓ 3 20 ns td4§ td5§ Delay time, CS valid before WR1↓ or WR2↑ 2 15 ns Delay time, address valid before WR1↓ or WR2↑ 2 15 ns td6 td7§ Delay time, write cycle, WR1↑ or WR2↓ to ADS↓ 2 80 ns Delay time, CS valid to RD1↓ or RD2↑ 3 15 ns 3 15 ns 3 80 ns Pulse duration, master reset td8§ Delay time, address valid to RD1↓ or RD2↑ td9 Delay time, read cycle, RD1↑ or RD2↓ to ADS↓ § Only applies when ADS is low. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
   
 
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 system switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER tw1 tw2 Pulse duration, clock high td3 td10 Delay time, select to CS output Pulse duration, clock low Delay time, RD1↓ or RD2↑ to data valid td11 Delay time, RD1↑ or RD2↓ to floating data tdis(R) Disable time, RD1↓↑ or RD2↑↓ to DDIS↑↓ † Only applies when ADS is low. FIGURE TEST CONDITIONS MIN 1 f = 9 MHz maximum 50 50 MAX UNIT ns 1 f = 9 MHz maximum 2, 3† CL = 100 pF 70 ns 3 CL = 100 pF 60 ns 3 CL = 100 pF 60 ns 3 CL = 100 pF 60 ns 0 ns baud generator switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER FIGURE TEST CONDITIONS CLK ÷ 1, CLK ÷ 1, MIN MAX UNIT tw3 Pulse duration, BAUDOUT low 1 f = 6.25 MHz, CL = 100 pF tw4 Pulse duration, BAUDOUT high 1 f = 6.25 MHz, CL = 100 pF td1 td2 Delay time, XIN↑ to BAUDOUT↑ 1 CL = 100 pF 125 ns Delay time, XIN↑↓ to BAUDOUT↓ 1 CL = 100 pF 125 ns 80 ns 80 ns receiver switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER FIGURE td12 Delay time, RCLK to sample clock 4 td13 Delay time, stop to set RCV error interrupt or read RDR to LSI interrupt or stop to RXRDY↓ 4 td14 Delay time, read RBR/LSR to reset interrupt 4 TEST CONDITIONS MIN 1 CL = 100 pF MAX UNIT 100 ns 1 140 RCLK cycles ns transmitter switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER FIGURE TEST CONDITIONS MIN MAX UNIT td15 Delay time, INTRPT to transmit start 5 8 24 baudout cycles td16 Delay time, start to interrupt 5 8 8 baudout cycles td17 Delay time, WR THR to reset interrupt 5 td18 Delay time, initial write to interrupt (THRE) 5 td19 Delay time, read IIR to reset interrupt (THRE) 5 POST OFFICE BOX 655303 CL = 100 pF 16 CL = 100 pF • DALLAS, TEXAS 75265 140 ns 32 baudout cycles 140 ns 7 
   
 
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 modem control switching characteristics over recommended ranges of supply voltage and operating free-air temperature FIGURE TEST CONDITIONS MAX UNIT td20 td21 Delay time, WR MCR to output PARAMETER 6 CL = 100 pF 100 ns Delay time, modem interrupt to set interrupt 6 CL = 100 pF 170 ns td22 Delay time, RD MSR to reset interrupt 6 CL = 100 pF 140 ns PARAMETER MEASUREMENT INFORMATION tw1 RCLK (9 MHz Max) 90% 90% 2V 10% 0.8 V tw2 N XTAL1 td2 td1 BAUDOUT (1/1) td2 td1 BAUDOUT (1/2) tw3 tw4 BAUDOUT (1/3) BAUDOUT (1/N) (N > 3) 2XTAL1 Cycles (N-2) XTAL1 Cycles Figure 1. Baud Generator Timing Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN 
   
 
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 PARAMETER MEASUREMENT INFORMATION tw5 ADS 10% 10% tsu1 th1 A0 −A2 90% Valid 10% Valid† 10% tsu2 th2 90% 90% Valid CS0, CS1, CS2 10% CSOUT Valid† 10% th3 td3 td3 90% 90% td4† td5† tw6 th4† td6 90% 90% Active DOSTR, DOSTR 10% tsu3 th5 90% 90% Valid Data D0 −D7 † Applicable only when ADS is tied low. Figure 2. Write Cycle Timing Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 
   
 
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 PARAMETER MEASUREMENT INFORMATION tw5 ADS 10% 10% 10% tsu1 th1 A0 −A2 90% Valid 50% 10% Valid† 10% tsu2 th2 90% 90% Valid CS0, CS1, CS2 Valid† 10% 10% th6 td3† td3† 90% CSOUT 90% tw7 td7† td8† th7† td9 90% 90% Active DISTR, DISTR 10% 10% tdis(R) tdis(R) DDIS 10% 10% td11 td10 90% D0 −D7 Valid Data † Applicable only when ADS is tied low. Figure 3. Read Cycle Timing Waveforms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 50% 
   
 
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 PARAMETER MEASUREMENT INFORMATION RCLK 8 CLKs td12 SAMPLE CLOCK SIN Start Data Bits 5 −8 Parity Stop SAMPLE CLOCK td13 90% INTRPT (RDR/LSI) 10% td14 DISTR, DISTR (RD RBR/LSR) 90% Active Figure 4. Receiver Timing Waveforms SOUT Start Data Bits Parity Stop 50% Start 10% td15 INTRPT (THRE) 90% 90% 50% 50% 10% td18 td17 DOSTR (WR THR) td16 90% 90% td17 90% td19 90% DISTR (RD IIR) Figure 5. Transmitter Timing Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 
   
 
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 PARAMETER MEASUREMENT INFORMATION DOSTR (WR MCR) 10% 10% td20 td20 90% RTS, DTR OUT 1, OUT 2 CTS, DSR, DCD 90% 10% td21 INTRPT (MODEM) 90% 50% 50% td22 DISTR (RD MSR) 50% td21 90% RI Figure 6. Modem Control Timing Waveforms 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
   
 
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 APPLICATION INFORMATION D7 −D0 SOUT D7−D0 MEMR or I/OR RTS MEMW or I/ON EIA 232-D Drivers and Receivers DOSTR DTR INTR INTRPT RESET DSR MR A0 C P U SIN DISTR DCD A0 A1 A1 A2 A2 B u s CTS TL16C450 (ACE) ADS RI XTAL1 DOSTR L 3.072 MHz DISTR CS H CS2 XTAL2 CS1 BAUDOUT CS0 RCLK Figure 7. Basic TL16C450 Configuration Receiver Disable WR Microcomputer System Data Bus DOSTR TL16C450 (ACE) Data Bus D7 −D0 8-Bit Bus Transceiver Driver Disable DDIS Figure 8. Typical Interface for a High-Capacity Data Bus POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 
   
 
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 APPLICATION INFORMATION TL16C450 Alternate Xtal Control XTAL1 A16 −A23 A16 −A23 XTAL2 Address Decoder CS0 BAUDOUT CS1 RCLK CS2 CPU ADS DTR 20 RTS 1 ADS OUT1 RSI/ABT MR AD0 − AD7 AD0 −AD15 A0 −A2 D0 −D7 Buffer PHI1 PHI2 PHI1 PHI2 ADS OUT2 RI 5V DCD 8 DSR 6 CTS 5 SOUT 2 SIN 3 RSTO RO DISTR WR DOSTR TCU AD0 −AD15 INTRPT CSOUT DISTR DDIS 7 NC 1 DOSTR GND (VSS) EIA-232-D Connector 5V (VCC) Figure 9. Typical TL16C450 Connection to a CPU 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
   
 
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION Table 1. Register Selection DLAB† A2 A1 0 L L L Receiver buffer (read), transmitter holding register (write) 0 L L H Interrupt enable X L H L Interrupt identification (read only) X L H H Line control X H L L Modem control X H L H Line status X H H L Modem status X H H H Scratch 1 L L L Divisor latch (LSB) 1 L L H A0 REGISTER Divisor latch (MSB) † The divisor latch access bit (DLAB) is the most significant bit of the line control register. The DLAB signal is controlled by writing to this bit location (see Table 3). Table 2. ACE Reset Functions REGISTER/SIGNAL RESET CONTROL RESET STATE Interrupt enable register Master reset All bits low (0 −3 forced and 4 −7 permanent) Interrupt identification register Master reset Bit 0 is high, bits 1 and 2 are low, and bits 3 −7 are permanently low Line control register All bits low Modem control register Master reset All bits low Line status register Master reset Bits 5 and 6 are high, all other bits are low Modem status register Master reset Bits 0 −3 are low, bits 4 −7 are input signals SOUT Master reset High INTRPT (receiver error flag) Read LSR/MR Low INTRPT (received data available) Read RBR/MR Low INTRPT (transmitter holding register empty) Read IIR/Write THR/MR Low INTRPT (modem status changes) Read MSR/MR Low OUT2 Master reset High RTS Master reset High DTR Master reset High OUT1 Master reset High Scratch register Master reset No effect Divisor latch (LSB and MSB) register Master reset No effect Receiver buffer register Master reset No effect Transmitter holding register Master reset No effect POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 
   
 
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION accessible registers The system programmer, using the CPU, has access to and control over any of the ACE registers that are summarized in Table 3. These registers control ACE operations, receive data, and transmit data. Descriptions of these registers follow Table 3. Table 3. Summary of Accessible Registers REGISTER ADDRESS Bit No. 0 1 2 O DLAB = 0 O DLAB = 0 1 DLAB = 0 2 3 4 5 6 7 O DLAB = 1 1 DLAB =0 Receiver Buffer Register (Read Only) Transmitter Holding Register (Write Only) Interrupt Enable Register IER Interrupt Ident. Register (Read Only) Line Control Register LCR Modem Control Register Line Status Register Modem Status Register Scratch Register Divisor Latch (LSB) Latch (MSB) RBR THR IER IIR LCR MCR LSR MSR SCR DLL DLM Data Bit 0 Enable Received Data Available Interrupt (ERBF) “0” If Interrupt Pending Word Length Select Bit 0 (WLSO) Data Terminal Ready (DTR) Data Ready (DR) Delta Clear to Send (DCTS) Bit 0 Bit 0 Bit 8 Data Bit 1 Enable Transmitter Holding Register Empty Interrupt (ETBE) Interrupt ID Bit (0) Word Length Select Bit 1 (WLS1) Request to Send (RTS) Overrun Error (OE) Delta Data Set Ready (DDSR) Bit 1 Bit 1 Bit 9 Data Bit 2 Enable Receiver Line Status Interrupt (ELSI) Interrupt ID Bit (1) Number of Stop Bits (STB) Out 1 Parity Error (PE) Trailing Edge Ring Indicator (TERI) Bit 2 Bit 2 Bit 10 0 Parity Enable (PEN) Out 2 Framing Error (FE) Delta Data Carrier Detect (DDCD) Bit 3 Bit 3 Bit 11 0 Even Parity Select (EPS) Loop Break Interrupt (BI) Clear to Send (CTS) Bit 4 Bit 4 Bit 12 0 Transmitter Holding Register (THRE) Data Set Ready (DSR) Bit 5 Bit 5 Bit 13 0 Transmitter Empty Ring Indicator (RI) Bit 6 Bit 6 Bit 14 Data Carrier Detect (DCD) Bit 7 Bit 7 Bit 15 Data Bit 0* Data Bit 1 Data Bit 2 3 Data Bit 3 Data Bit 3 Enable Modem Status Interrupt (EDSSI) 4 Data Bit 4 Data Bit 4 0 5 Data Bit 5 Data Bit 5 0 0 Stick Parity 6 Data Bit 6 Data Bit 6 0 0 Set Break 7 Data Bit 7 Data Bit 7 0 0 Divisor Latch Access Bit (DLAB) (TEMT) 0 0 *Bit 0 is the least significant bit. It is the first bit serially transmitted or received. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
   
 
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION interrupt enable register (IER) The IER enables each of the four types of interrupts (refer to Table 4) and the INTRPT output signal in response to an interrupt generation. By clearing bits 0 − 3, the IER can also disable the interrupt system. The contents of this register are summarized in Table 3 and are described in the following bulleted list. D D D D D Bit 0: This bit, when set, enables the received data available interrupt. Bit 1: This bit, when set, enables the THRE interrupt. Bit 2: This bit, when set, enables the receiver line status interrupt. Bit 3: This bit, when set, enables the modem status interrupt. Bits 4 − 7: These bits in the IER are not used and are always cleared. interrupt identification register (IIR) The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with most microprocessors. The ACE provides four prioritized levels of interrupts: D D D D Priority 1 − Receiver line status (highest priority) Priority 2 − Receiver data ready or receiver character time out Priority 3 −Transmitter holding register empty Priority 4 −Modem status (lowest priority) When an interrupt is generated, the IIR indicates that an interrupt is pending and the type of interrupt in its three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 3 and described in Table 4. D Bit 0: This bit can be used either in a hardwire prioritized or polled interrupt system. When bit 0 is cleared, an interrupt is pending. When bit 0 is set, no interrupt is pending. D Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in Table 4. D Bits 3 − 7: These bits in the IIR are not used and are always clear. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 
   
 
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION interrupt identification register (IIR) (continued) Table 4. Interrupt Control Functions INTERRUPT IDENTIFICATION REGISTER PRIORITY LEVEL INTERRUPT TYPE INTERRUPT SOURCE INTERRUPT RESET METHOD None None − BIT 2 BIT 1 BIT 0 0 0 1 None 1 1 0 1 Receiver line status Overrun error, parity error, framing error or break interrupt 1 0 0 2 Received data available Receiver data available Reading the line status register Reading the receiver buffer Buffer register 0 1 0 3 Transmitter holding register empty Transmitter holding register empty Reading the interrupt identification register (if source of interrupt) or writing into the transmitter holding register 0 0 0 4 Modem status Clear to send, data set ready, ring indicator, or data carrier detect Reading the modem status register line control register (LCR) The system programmer controls the format of the asynchronous data communication exchange through the LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates the need for separate storage of the line characteristics in system memory. The contents of this register are summarized in Table 3 and are described in the following bulleted list. D Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character. These bits are encoded as shown in Table 5. Table 5. Serial Character Word Length Bit 1 Bit 0 Word Length 0 0 5 Bits 0 1 6 Bits 1 0 7 Bits 1 1 8 Bits D Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When bit 2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated is dependent on the word length selected with bits 0 and 1. The receiver checks the first stop bit only, regardless of the number of stop bits selected. The number of stop bits generated, in relation to word length and bit 2, is shown in Table 6. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
   
 
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION line control register (LCR) (continued) Table 6. Number of Stop Bits Generated 0 Word Length Selected by Bits 1 and 2 Any word length Number of Stop Bits Generated 1 1 5 bits 1 1/2 1 6 bits 2 1 7 bits 2 1 8 bits 2 Bit 2 D Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in transmitted data between the last data word bit and the first stop bit. In received data, if bit 3 is set, parity is checked. When bit 3 is cleared, no parity is generated or checked. D Bit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set, even parity (an even number of logic 1s is in the data and parity bits) is selected. When parity is enabled (bit 3 is set) and bit 4 is clear, odd parity (an odd number of logic 1s) is selected. D Bit 5: This is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked as cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set. D Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition, i.e, a condition where the serial output terminal (SOUT) is forced to the spacing (cleared) state. When bit 6 is cleared, the break condition is disabled. The break condition has no affect on the transmitter logic, it only affects the serial output. D Bit 7: This bit is the divisor latch access bit (DLAB). Bit 7 must be set to access the divisor latches of the baud generator during a read or write. Bit 7 must be cleared during a read or write to access the receiver buffer, the THR, or the IER. line status register (LSR)† The LSR provides information to the CPU concerning the status of data transfers. The contents of this register are summarized in Table 3 and are described in the following bulleted list. D Bit 0: This bit is the data ready (DR) indicator for the receiver. Bit 0 is set whenever a complete incoming character has been received and transferred into the RBR and is cleared by reading the RBR. D Bit 1‡: This bit is the overrun error (OE) indicator. When bit 1 is set, it indicates that before the character in the RBR was read, it was overwritten by the next character transferred into the register. The OE indicator is cleared every time the CPU reads the contents of the LSR. D Bit 2‡: This bit is the parity error (PE) indicator. When bit 2 is set, it indicates that the parity of the received data character does not match the parity selected in the LCR (bit 4). The PE bit is cleared every time the CPU reads the contents of the LSR. D Bit 3‡: This bit is the framing error (FE) indicator. When bit 3 is set, it indicates that the received character does not have a valid (set) stop bit. The FE bit is cleared every time the CPU reads the contents of the LSR. D Bit4‡: This bit is the break interrupt (BI) indicator. When bit 4 is set, it indicates that the received data input was held clear for longer than a full-word transmission time. A full-word transmission time is defined as the total time of the start, data, parity, and stop bits. The BI bit is cleared every time the CPU reads the contents of the LSR. † The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment. ‡ Bits 1 through 4 are the error conditions that produce a receiver line-status interrupt. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 
   
 
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION line status register (LSR)† (continued) D Bit 5: This bit is the THRE indicator. Bit 5 is set when the THR is empty, indicating that the ACE is ready to accept a new character. If the THRE interrupt is enabled when the THRE bit is set, then an interrupt is generated. THRE is set when the contents of the THR are transferred to the transmitted shift register. This bit is cleared concurrent with the loading of the THR by the CPU. D Bit 6: This bit is the transmitter empty (TEMT) indicator. Bit 6 is set when the THR and the transmitter shift register are both empty. When either the THR or the transmitter shift register contains a data character, the TEMT bit is cleared. D Bit 7: This bit is always clear. modem control register (MCR) The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is emulating a modem. The contents of this register are summarized in Table 3 and are described in the following bulleted list. D Bit 0: This bit (DTR) controls the data terminal ready (DTR) output. Setting bit 0 forces the DTR output to its active state (low). When bit 0 is clear, DTR goes high. D Bit 1: This bit (RTS) controls the request to send (RTS) output in a manner identical to bit 0’s control over the DTR output. D Bit 2: This bit (OUT1) controls the output 1 (OUT1) signal, a user designated output signal, in a manner identical to bit 0’s control over the DTR output. D Bit 3: This bit (OUT2) controls the output 2 (OUT2) signal, a user designated output signal, in a manner identical to bit 0’s control over the DTR output. D Bit 4: This bit provides a local loopback feature for diagnostic testing of the ACE. When bit 4 is set, the following occurs: 1. 2. 3. 4. 5. The SOUT is asserted high. The SIN is disconnected. The output of the transmitter shift register is looped back into the RSR input. The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected. The four modem control outputs (DTR, RTS, OUT1, and OUT2) are internally connected to the four modem control inputs. 6. The four modem control output terminals are forced to their inactive states (high). In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify the transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational. The modem control interrupts are also operational but the modem control interrupt sources are now the lower four bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the IER. D Bits 5 through 7: These bits are clear. † The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
   
 
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION modem status register (MSR) The MSR is an 8-bit register that provides information about the current state of the control lines from the modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provides change information; when a control input from the modem changes state the appropriate bit is set. All four bits are cleared when the CPU reads the MSR. The contents of this register are summarized in Table 3 and are described in the following bulleted list. D Bit 0: This bit is the delta clear to send (DCTS) indicator. Bit 0 indicates that the CTS input has changed states since the last time it was read by the CPU. When this bit is set and the modem status interrupt is enabled, a modem status interrupt is generated. D Bit 1: This bit is the delta data set ready (DDSR) indicator. Bit 1 indicates that the DSR input has changed states since the last time it was read by the CPU. When this bit is set and the modem status interrupt is enabled, a modem status interrupt is generated. D Bit 2: This bit is the trailing edge of ring indicator (TERI) detector. Bit 2 indicates that the RI input to the chip has changed from a low to a high state. When this bit is set and the modem status interrupt is enabled, a modem status interrupt is generated. D Bit 3: This bit is the delta data carrier detect (DDCD) indicator. Bit 3 indicates that the DCD input to the chip has changed state since the last time it was read by the CPU. When this bit is set and the modem status interrupt is enabled, a modem status interrupt is generated. D Bit 4: This bit is the complement of the clear to send (CTS) input. When bit 4 (loop) of the MCR is set, this bit is equivalent to the MCR bit 1 (RTS). D Bit 5: This bit is the complement of the data set ready (DSR) input. When bit 4 (loop) of the MCR is set, this bit is equivalent to the MCR bit 0 (DTR). D Bit 6: This bit is the complement of the ring indicator (RI) input. When bit 4 (loop) of the MCR is set, this bit is equivalent to the MCRs bit 2 (OUT1). D Bit 7: This bit is the complement of the data carrier detect (DCD) input. When bit 4 (loop) of the MCR is set, this bit is equivalent to the MCRs bit 3 (OUT2). programmable baud generator The ACE contains a programmable baud generator that takes a clock input in the range between dc and 9 MHz and divides it by a divisor in the range between 1 and (216 −1). The output frequency of the baud generator is sixteen times (16×) the baud rate. The formula for the divisor is: divisor # = XTAL1 frequency input B (desired baud rate × 16) Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must be loaded during initialization of the ACE in order to ensure desired operation of the baud generator. When either of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load. Tables 7 and 8 illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz and 3.072 MHz, respectively. For baud rates of 38.4 kilobits per second and below, the error obtained is very small. The accuracy of the selected baud rate is dependent on the selected crystal frequency. Refer to Figure 10 for examples of typical clock circuits. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 
   
 
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION Table 7. Baud Rates Using a 1.8432-MHz Crystal DESIRED BAUD RATE DIVISOR USED TO GENERATE 16 × CLOCK 50 2304 75 1536 PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL 110 1047 0.026 134.5 857 0.058 150 768 300 384 600 192 1200 96 1800 64 2000 58 2400 48 3600 32 4800 24 7200 16 9600 12 19200 6 38400 3 56000 2 0.69 2.86 Table 8. Baud Rates Using a 3.072-MHz Crystal DESIRED BAUD RATE 50 22 DIVISOR USED TO GENERATE 16 × CLOCK 3840 PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL 75 2560 110 1745 0.026 134.5 1428 0.034 150 1280 300 640 600 320 1200 160 1800 107 2000 96 2400 80 3600 53 4800 40 7200 27 9600 20 19200 10 38400 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0.312 0.628 1.23 
   
 
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION VCC Driver External Clock XTAL1 Optional Oscillator Clock to Baud Generator Logic Optional Clock Output XTAL2 VCC XTAL1 C1 RP Crystal RX2 Oscillator Clock to Baud Generator Logic XTAL2 C2 TYPICAL CRYSTAL OSCILLATOR NETWORK CRYSTAL RP 1 MΩ RX2 C1 C2 3.1 MHz 1.5 kΩ 10 −30 pF 40 −60 pF 1.8 MHz 1 MΩ 1.5 kΩ 10 −30 pF 40 −60 pF Figure 10. Typical Clock Circuits POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 
   
 
SLLS037C − MARCH 1988 − REVISED JANUARY 2006 PRINCIPLES OF OPERATION receiver buffer register (RBR) The ACE receiver section consists of a receiver shift register and a RBR. Timing is supplied by the 16× receiver clock (RCLK). Receiver section control is a function of the ACE line control register. The ACE receiver shift register receives serial data from the serial input (SIN) terminal. The receiver shift register then converts the data to a parallel form and loads it into the RBR. When a character is placed in the RBR and the received data available interrupt is enabled, an interrupt is generated. This interrupt is cleared when the data is read out of the RBR. scratch register The scratch register is an 8-bit register that is intended for programmer use as a scratchpad, in the sense that it temporarily holds programmer data without affecting any other ACE operation. transmitter holding register (THR) The ACE transmitter section consists of a THR and a transmitter shift register. Timing is supplied by the baud out (BAUDOUT) clock signal. Transmitter section control is a function of the ACE line control register. The ACE THR receives data from the internal data bus and, when the shift register is idle, moves it into the transmitter shift register. The transmitter shift register serializes the data and outputs it at the serial output (SOUT). If the THR is empty and the transmitter holding register empty (THRE) interrupt is enabled, an interrupt is generated. This interrupt is cleared when a character is loaded into the register. 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) TL16C450FN ACTIVE PLCC FN 44 26 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 TL16C450FN TL16C450FNR ACTIVE PLCC FN 44 500 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 TL16C450FN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of