TL16C550C
SLLS177I – MARCH 1994 – REVISED MARCH 2021
TL16C550C Asynchronous Communications Element with Autoflow Control
1 Features
2 Description
•
•
•
The TL16C550C and the TL16C550CI are
functional upgrades of the TL16C550B asynchronous
communications element (ACE), which in turn is a
functional upgrade of the TL16C450. Functionally
equivalent to the TL16C450 on power up (character
or TL16C450 mode), the TL16C550C and the
TL16C550CI, like the TL16C550B, can be placed
in an alternate FIFO mode. This relieves the
CPU of excessive software overhead by buffering
received and transmitted characters. The receiver
and transmitter FIFOs store up to 16 bytes including
three additional bits of error status per byte for the
receiver FIFO. In the FIFO mode, there is a selectable
autoflow control feature that can significantly reduce
software overload and increase system efficiency by
automatically controlling serial data flow using RTS
output and CTS input signals.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Programmable Auto-RTS and Auto-CTS
In Auto-CTSMode, CTS Controls Transmitter
In Auto-RTS Mode, RCV FIFO Contents and
Threshold Control RTS
Serial and Modem Control Outputs Drive a RJ11
Cable Directly When Equipment Is on the Same
Power Drop
Capable of Running With All Existing TL16C450
Software
After Reset, All Registers Are Identical to the
TL16C450 Register Set
Up to 16-MHz Clock Rate for up to 1-Mbaud
Operation
In the TL16C450 Mode, Hold and Shift Registers
Eliminate the Need for Precise Synchronization
Between the CPU and Serial Data
Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1 to (216
−1) and Generates an Internal 16×Clock
Standard Asynchronous Communication Bits
(Start, Stop, and Parity) Added to or Deleted From
the Serial Data Stream
5-V and 3.3-V Operation
Independent Receiver Clock Input
Transmit, Receive, Line Status, and Data Set
Interrupts Independently Controlled
Fully Programmable Serial Interface
Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation and
Detection
– 1-, 1 1/2-, or 2-Stop Bit Generation
– Baud Generation (dc to 1 Mbit/s)
False-Start Bit Detection
Complete Status Reporting Capabilities
3-State Output TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus
Line Break Generation and Detection
Internal Diagnostic Capabilities:
– Loopback Controls for Communications Link
Fault Isolation
– Break, Parity, Overrun, and Framing Error
Simulation
Fully Prioritized Interrupt System Controls
Modem Control Functions (CTS, RTS, DSR, DTR,
RI, and DCD)
The TL16C550C and TL16C550CI perform serialto-parallel conversions on data received from a
peripheral device or modem and parallel-to-serial
conversion on data received from its CPU. The
CPU can read the ACE status at any time. The
ACE includes complete modem control capability
and a processor interrupt system that can be
tailored to minimize software management of the
communications link.
Both the TL16C550C and the TL16C550CI ACE
include a programmable baud rate generator capable
of dividing a reference clock by divisors from 1 to
65535 and producing a 16× reference clock for the
internal transmitter logic. Provisions are included to
use this 16× clock for the receiver logic. The ACE
accommodates a 1-Mbaud serial rate (16-MHz input
clock) so that a bit time is 1 μs and a typical character
time is 10 μs (start bit, 8 data bits, stop bit).
Two of the TL16C450 terminal functions on the
TL16C550C and the TL16C550CI have been changed
to TXRDY and RXRDY, which provide signaling to a
DMA controller.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TL16C550C
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SLLS177I – MARCH 1994 – REVISED MARCH 2021
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 6
5.1 Absolute Maximum Ratings........................................ 6
5.2 Recommended Operating Conditions (Low
Voltage - 3.3 nominal)................................................... 6
5.3 Recommended Operating Conditions (Standard
Voltage - 5 V nominal)................................................... 7
5.4 Thermal Information....................................................7
5.5 Electrical Characteristics (Low Voltage - 3.3 V
nominal).........................................................................8
5.6 Electrical Characteristics (Standard Voltage - 5
V nominal)..................................................................... 8
5.7 System Timing Requirements..................................... 9
5.8 System Switching Characteristics.............................10
5.9 Baud Generator Switching Characteristics............... 10
5.10 Receiver Switching Characteristics.........................10
5.11 Transmitter Switching Characteristics..................... 11
5.12 Modem Control Switching Characteristics.............. 11
6 Parameter Measurement Information.......................... 12
7 Detailed Description......................................................19
7.1 Autoflow Control (see Figure 7-1) ............................ 19
7.2 Auto-RTS (see Figure 7-1) .......................................19
7.3 Auto-CTS (see Figure 7-1) .......................................19
7.4 Enabling Autoflow Control and Auto-CTS ................19
7.5 Auto-CTS and Auto-RTS Functional Timing............. 20
7.6 Functional Block Diagram......................................... 21
7.7 Principles of Operation..............................................21
8 Application Information................................................ 33
9 Device and Documentation Support............................35
9.1 Receiving Notification of Documentation Updates....35
9.2 Support Resources................................................... 35
9.4 Electrostatic Discharge Caution................................35
9.5 Glossary....................................................................35
10 Mechanical, Packaging, and Orderable
Information.................................................................... 36
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (January 2006) to Revision I (March 2021)
Page
• Updated the data sheet format........................................................................................................................... 1
• Added the Pin Configuration and Functions section...........................................................................................3
• Added the Thermal Information table. ............................................................................................................... 7
2
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4 Pin Configuration and Functions
Figure 4-2. FN Package (Top View)
Figure 4-1. N Package (Top View)
Figure 4-3. PT/PFB Package (Top View)
NC - No internal connection
Table 4-1. Pin Functions
TERMINAL
NAME
NO.N(1)
NO.FN
NO.PT
A0
28
31
28
A1
27
30
27
A2
26
29
26
ADS
25
28
24
I/O
DESCRIPTION
I
Register select. A0 −A2 are used during read and write operations to select the
ACE register to read from or write to. Refer to Table 1 for register addresses
and refer to ADS description.
I
Address strobe. When ADS is active (low), A0, A1, and A2 and CS0, CS1,
and CS2 drive the internal select logic directly; when ADS is high, the register
select and chip select signals are held at the logic levels they were in when the
low-to-high transition of ADS occurred
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Table 4-1. Pin Functions (continued)
TERMINAL
I/O
DESCRIPTION
12
O
Baud out. BAUDOUT is a 16 x clock signal for the transmitter section of the
ACE. The clock rate is established by the reference oscillator frequency divided
by a divisor specified by the baud generator divisor latches. BAUDOUT may
also be used for the receiver section by tying this output to RCLK.
14
9
I
15
10
14
16
11
Chip select. When CS0 and CS1 are high and CS2 is low, these three inputs
select the ACE. When any of these inputs are inactive, the ACE remains
inactive (refer to ADS description).
CTS
36
40
38
I
Clear to send. CTS is a modem status signal. Its condition can be checked
by reading bit 4 (CTS) of the modem status register. Bit 0 (ΔCTS) of the
modem status register indicates that CTS has changed states since the last
read from the modem status register. If the modem status interrupt is enabled
when CTS changes levels and the auto-CTS mode is not enabled, an interrupt
is generated. CTS is also used in the auto-CTS mode to control the transmitter
D0
1
2
43
I/O
D1
2
3
44
D2
3
4
45
D3
4
5
46
D4
5
6
47
D5
6
7
2
D6
7
8
3
D7
8
9
4
DCD
38
42
40
I
Data carrier detect. DCD is a modem status signal. Its condition can be checked
by reading bit 7 (DCD) of the modem status register. Bit 3 (ΔDCD) of the
modem status register indicates that DCD has changed states since the last
read from the modem status register. If the modem status interrupt is enabled
when DCD changes levels, an interrupt is generated
DDIS
23
26
22
O
Driver disable. DDIS is active (high) when the CPU is not reading data. When
active, DDIS can disable an external transceiver.
DSR
37
41
39
I
Data set ready. DSR is a modem status signal. Its condition can be checked by
reading bit 5 (DSR) of the modem status register. Bit 1 (ΔDSR) of the modem
status register indicates DSR has changed levels since the last read from the
modem status register. If the modem status interrupt is enabled when DSR
changes levels, an interrupt is generated.
DTR
33
37
33
O
Data terminal ready. When active (low), DTR informs a modem or data set that
the ACE is ready to establish comunication. DTR is placed in the active level
by setting the DTR bit of the modem control register. DTR is placed in the
inactive level either as a result of a master reset, during loop mode operation, or
clearing the DTR bit.
INTRPT
30
33
30
O
Interrupt.When active (high), INTRPT informs the CPU that the ACE has an
interrupt to be serviced. Four conditions that cause an interrupt to be issued
are: a receiver error, received data that is available or timed out (FIFO mode
only), an empty transmitter holding register, or an enabled modem status
interrupt. INTRPT is reset (deactivated) either when the interrupt is serviced
or as a result of a master reset.
MR
35
39
35
I
Master reset. When active (high), MR clears most ACE registers and sets the
levels of various output signals (refer to Table 2).
OUT1
34
38
34
O
OUT2
31
35
31
Outputs 1 and 2. These are user-designated output terminals that are set to
the active (low) level by setting respective modem control register (MCR) bits
(OUT1 and OUT2). OUT1 and OUT2 are set to inactive the (high) level as a
result of master reset, during loop mode operations, or by clearing bit 2 (OUT1)
or bit 3 (OUT2) of the MCR.
RCLK
9
10
5
I
Receiver clock. RCLK is the 16 x baud rate clock for the receiver section of the
ACE.
NO.N(1)
NO.FN
NO.PT
BAUDOUT
15
17
CS0
12
CS1
13
CS2
NAME
4
Data bus. Eight data lines with 3-state outputs provide a bidirectional path for
data, control, and status information between the ACE and the CPU.
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Table 4-1. Pin Functions (continued)
TERMINAL
NAME
NO.N(1)
NO.FN
NO.PT
I/O
DESCRIPTION
I
Read inputs. When either RD1 or RD2 is active (low or high respectively) while
the ACE is selected, the CPU is allowed to read status information or data from
a selected ACE register. Only one of these inputs is required for the transfer of
data during a read operation; the other input should be tied to its inactive level
(i.e., RD2 tied low or RD1 tied high
RD1
21
24
19
RD2
22
25
20
RI
39
43
41
I
Ring indicator. RI is a modem status signal. Its condition can be checked by
reading bit 6 (RI) of the modem status register. Bit 2 (TERI) of the modem
status register indicates that RI has transitioned from a low to a high level since
the last read from the modem status register. If the modem status interrupt is
enabled when this transition occurs, an interrupt is generated
RTS
32
36
32
O
Request to send. When active, RTS informs the modem or data set that the
ACE is ready to receive data. RTS is set to the active level by setting the RTS
modem control register bit and is set to the inactive (high) level either as a
result of a master reset or during loop mode operations or by clearing bit 1
(RTS) ofthe MCR. In the auto-RTS mode, RTS is set to the inactive level by the
receiver threshold control logic
RXRDY
29
32
29
O
Receiver ready. Receiver direct memory access (DMA) signalling is available
with RXRDY. When operating in the FIFO mode, one of two types of DMA
signalling can be selected using the FIFO control register bit 3 (FCR3). When
operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0
supports single-transfer DMA in which a transfer is made between CPU bus
cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made
continuously until the receiver FIFO has been emptied. In DMA mode 0 (FCR0
= 0 or FCR0 =1, FCR3 = 0), when there is at least one character in the receiver
FIFO or receiver holding register, RXRDY is active (low). When RXRDY has
been active but there are no characters in the FIFO or holding register, RXRDY
goes inactive (high).In DMA mode 1 (FCR0 = 1, FCR3 = 1), when the trigger
level or the time-out has been reached, RXRDY goes active (low); when it has
been active but there are no more characters in the FIFO or holding register, it
goes inactive (high).
SIN
10
11
7
I
Serial data input. SIN is serial data input from a connected communications
device.
SOUT
11
13
8
O
Serial data output. SOUT is composite serial data output to a connected
communication device. SOUT is set to the marking (high) level as a result of
master reset.
TXRDY
24
27
23
O
Transmitter ready. Transmitter DMA signalling is available with TXRDY. When
operating in the FIFO mode, one of two types of DMA signalling can be selected
using FCR3. When operating in the TL16C450 mode, only DMA mode 0 is
allowed. Mode 0 supports single-transfer DMA in which a transfer is made
between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple
transfers are made continuously until the transmit FIFO has been filled.
VCC
40
44
42
5-V supply voltage
VSS
20
22
18
Supply common
WR1
18
20
16
WR2
19
21
17
XIN
16
18
14
XOUT
17
19
15
(1)
I
I/O
Write inputs. When either WR1 or WR2 is active (low or high respectively) and
while the ACE is selected,the CPU is allowed to write control words or data into
a selected ACE register. Only one of these inputs is required to transfer data
during a write operation; the other input should be tied to its inactive level (i.e.,
WR2 tied low or WR1 tied high).
External clock. XIN and XOUT connect the ACE to the main timing reference
(clock or crystal).
The N package is Not Recommended for New Designs.
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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
VCC
Supply voltage range(3)
–0.5
7
V
VI
Input voltage range at any input
–0.5
7
V
VO
Output voltage range
–0.5
7
V
TA
Operating free-air temperature range
TL16C550C
0
70
°C
TL16C550CI
–40
85
°C
Tstg
Storage temperature
150
°C
TC
Case temperature for 10 seconds
FN package
260
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
N(1) (2)
260
°C
(1)
–65
or PT package
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The N package is Not Recommended for New Designs.
(3)
All voltage values are with respect to VSS.
5.2 Recommended Operating Conditions (Low Voltage - 3.3 nominal)
Supply voltage, VCC
Input voltage, VI
MIN
NOM
MAX
UNIT
3
3.3
3.6
V
0
High-level input voltage, VIH (1)
VCC
V
0.7 VCC
V
Low-level input voltage, VIL (1)
0.3 VCC
V
VCC
V
High-level output current, IOH (all outputs)
1.8
mA
Low-level output current, IOL (all outputs)
3.2
mA
1
pF
70
°C
Output voltage, VO (2)
0
Input capacitance
Operating free-air temperature, TA
0
25
(3)
0
25
Junction temperature range, TJ
Oscillator/clock speed
115
°C
14.9
MHz
(1)
Meets TTL levels, VIHmin = 2 V and VILmax = 0.8 V on nonhysteresis inputs.
(2)
Applies for external output buffers.
(3)
These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150°C. The customer is
responsible for verifying junction temperature.
6
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5.3 Recommended Operating Conditions (Standard Voltage - 5 V nominal)
Supply voltage, VCC
Input voltage, VI
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
VCC
V
0
Except XIN
High-level input voltage, VIH
2
XIN
V
0.7 VCC
Except XIN
Low-level input voltage, VIL
0.8
XIN
0.3 VCC
Output voltage, VO (1)
0
V
VCC
V
High-level output current, IOH (all outputs)
4
mA
Low-level output current, IOL (all outputs)
4
mA
Input capacitance
1
pF
Operating free-air temperature, TA
0
25
70
°C
Junction temperature range, TJ (2)
0
25
115
°C
16
MHz
Oscillator/clock speed
(1)
Applies for external output buffers.
(2)
These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150°C. The customer is
responsible for verifying junction temperature.
5.4 Thermal Information
THERMAL
METRIC(1)
TL16C550C
TL16C550C
TL16C550C
PT
PFB
FN
48 PINS
48 PINS
44 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
72.5
73.6
62.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
31.0
26.3
37.2
°C/W
RθJB
Junction-to-board thermal resistance
36.2
37.2
39.1
°C/W
ψJT
Junction-to-top characterization parameter
4.4
1.9
19.4
°C/W
ψJB
Junction-to-board characterization parameter
36.0
37.0
38.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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5.5 Electrical Characteristics (Low Voltage - 3.3 V nominal)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
(2)
High-level output voltage
IOH = − 1 mA
VOL (2)
Low-level output voltage
IOL = 1.6 mA
II
Input current
VCC = 3.6 V,
VI = 0 to 3.6 V,
VSS = 0,
All other terminals floating
IOZ
High-impedance-state output
current
VCC = 3.6 V,
VO = 0 to 3.6 V
VSS = 0,
VOH
TYP(1)
MAX
2.4
UNIT
V
0.5
V
10
μA
± 20
μA
8
mA
15
20
pF
20
30
pF
6
10
pF
10
20
pF
MAX
UNIT
Chip selected in write mode or chip deselect
ICC
Supply current
Ci(CLK)
Clock input capacitance
VCC = 3.6 V,
SIN, DSR, DCD, CTS, and
RI at 2V,
All other inputs at 0.8 V,
No load on outputs,
TA = 25°C
XTAL1 at 4 MHz,
Baud rate = 50 kbit/s
VSS = 0,
TA = 25°C
Co(CLK)
Clock output capacitance
VCC= 0,
f =1 MHz,
Ci
Input capacitance
All other terminals grounded
Co
Output capacitance
(1)
All typical values are at VCC = 3.3 V and TA = 25°C.
(2)
These parameters apply for all outputs except XOUT.
5.6 Electrical Characteristics (Standard Voltage - 5 V nominal)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
(2)
High-level output voltage
IOH = − 1 mA
2.4
V
VOL (2)
Low-level output voltage
IOL = 1.6 mA
0.4
V
II
Input current
VCC = 5.25 V,
VI = 0 to 5.25 V,
VSS = 0,
All other terminals floating
10
μA
High-impedance-state output
current
VCC = 5.25 V,
VO = 0 to 5.25 V,
VSS = 0,
IOZ
± 20
μA
10
mA
VOH
Chip selected in write mode or chip deselect
ICC
Supply current
Ci(CLK)
Clock input capacitance
Co(CLK)
Clock output capacitance
Ci
Input capacitance
Co
Output capacitance
VCC = 5.25 V,
SIN, DSR, DCD, CTS, and
RI at 2V,
All other inputs at0.8 V,
No load on outputs,
VCC= 0,
f =1 MHz,
All other terminals
grounded
(1)
All typical values are at VCC = 5 V and TA = 25°C.
(2)
These parameters apply for all outputs except XOUT.
8
TA = 25°C
XTAL1 at 4 MHz,
Baud rate = 50 kbit/s
VSS = 0,
TA = 25°C,
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15
20
pF
20
30
pF
6
10
pF
10
20
pF
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5.7 System Timing Requirements
over recommended ranges of supply voltage and operating free-air temperature
ALT. SYMBOL
FIGURE
TEST CONDITIONS
MIN
MAX
UNIT
tcR
Cycle time, read (tw7 + td8 + td9)
RC
87
ns
tcW
Cycle time, write (tw6 + td5 + td6)
WC
87
ns
tw1
Pulse duration, clock high
tXH
tw2
Pulse duration, clock low
tXL
25
ns
5
f = 16 MHz Max,
VCC = 5 V
tw5
Pulse duration, ADS low
tADS
6.7
9
ns
tw6
Pulse duration, WR
tWR
6
40
ns
7
40
ns
1
ns
6.7
8
ns
6
15
ns
17
10
ns
6.7
0
ns
6
10
ns
6
5
ns
tw7
Pulse duration, RD
tRD
tw8
Pulse duration, MR
tMR
tsu1
Setup time, address valid before ADS↑
tAS
tsu2
Setup time, CS valid before ADS↑
tCS
tsu3
Setup time, data valid before WR1↑ or WR2↓
tDS
tsu4
Setup time, CTS↑ before midpoint of stop bit
th1
Hold time, address low after ADS↑
tAH
th2
Hold time, CS valid after ADS↑
tCH
th3
Hold time, CS valid after WR1↑ or WR2↓
tWCS
th4
Hold time, address valid after WR1↑ or WR2↓
tWA
th5
Hold time, data valid after WR1↑ or WR2↓
tDH
th6
Hold time, chip select valid after RD1↑or RD2↓
tRCS
7
10
ns
th7
Hold time, address valid after RD1↑ or RD2↓
tRA
7
20
ns
td4 (1)
Delay time, CS valid before WR1↓ or WR2↑
tCSW
td5 (1)
Delay time, address valid before WR1↓ or WR2↑
tAW
6
7
ns
td6 (1)
Delay time, write cycle, WR1↑ or WR2↓ to ADS↓
tWC
6
40
ns
td7 (1)
Delay time, CS valid to RD1↓ or RD2↑
tCSR
td8 (1)
Delay time, address valid to RD1↓ or RD2↑
tAR
7
7
ns
td9
Delay time, read cycle, RD1↑ or RD2↓ to ADS↓
tRC
7
40
ns
td10
Delay time, RD1↓ or RD2↑ to data valid
tRVD
7
CL = 75 pF
45
ns
td11
Delay time, RD1↑ or RD2↓ to floating data
tHZ
7
CL = 75 pF
20
ns
(1)
Only applies when ADS is low.
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5.8 System Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature(1)
PARAMETER
tdis(R)
(1)
Disable time, RD1↓↑ or RD2↑↓ to DDIS↑↓
ALT. SYMBOL
FIGURE
TEST CONDITIONS
MIN
tRDD
7
CL = 75 pF
20
MAX
UNIT
ns
Charge and discharge times are determined by VOL, VOH, and external loading.
5.9 Baud Generator Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature, CL = 75 pF
ALT. SYMBOL
FIGURE
TEST CONDITIONS
MIN
tw3
Pulse duration, BAUDOUT low
PARAMETER
tLW
5
tw4
Pulse duration, BAUDOUT high
tHW
5
f = 16 MHz, CLK ÷ 2,
VCC = 5 V
MAX
UNIT
50
td1
Delay time, XIN↑ to BAUDOUT↑
tBLD
5
45
ns
td2
Delay time, XIN↑↓ to BAUDOUT↓
tBHD
5
45
ns
ns
5.10 Receiver Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature(1)
ALT. SYMBOL
FIGURE
MAX
UNIT
td12
Delay time, RCLK to sample
PARAMETER
tSCD
8
10
ns
td13
Delay time, stop to set INTRPT or read RBR to
LSI interrupt or stop to RXRDY↓
tSINT
8, 9, 10, 11, 12
1
RCLK
cycle
td14
Delay time, read RBR/LSR to reset INTRPT
tRINT
8, 9, 10, 11, 12
70
ns
(1)
10
TEST CONDITIONS
CL = 75 pF
MIN
In the FIFO mode, the read cycle (RC) = 425 ns (min) between reads of the receive FIFO and the status registers (interrupt
identification register or line status register).
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5.11 Transmitter Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature
PARAMETER
ALT. SYMBOL
FIGURE
td15
Delay time, initial write to transmit start
tIRS
td16
Delay time, start to INTRPT
td17
MIN
MAX
UNIT
13
8
24
baudout
cycles
tSTI
13
8
10
baudout
cycles
Delay time, WR (WR THR) to reset INTRPT
tHR
13
50
ns
td18
Delay time, initial write to INTRPT (THRE(1))
tSI
13
34
baudout
cycles
td19
Delay time, read IIR(1) to reset INTRPT
(THRE(1))
tIR
13
CL = 75 pF
35
ns
td20
Delay time, write to TXRDY inactive
tWXI
14, 15
CL = 75 pF
35
ns
9
baudout
cycles
t21
(1)
Delay time, start to TXRDY active
tSXA
TEST CONDITIONS
14, 15
CL = 75 pF
16
CL = 75 pF
THRE = transmitter holding register empty; IIR = interrupt identification register.
5.12 Modem Control Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature, CL = 75 pF
PARAMETER
ALT. SYMBOL
FIGURE
MAX
UNIT
tMDO
16
50
ns
Delay time, modem interrupt to set INTRPT
tSIM
16
35
ns
Delay time, RD MSR to reset INTRPT
tRIM
16
40
ns
Delay time, CTS low to SOUT↓
17
24
baudout
cycles
td26
Delay time, RCV threshold byte to RTS↑
18
2
baudout
cycles
td27
Delay time, read of last byte in receive FIFO to RTS↓
18
2
baudout
cycles
td28
Delay time, first data bit of 16th character to RTS↑
19
2
baudout
cycles
td29
Delay time, RBRRD low to RTS↓
19
2
baudout
cycles
td22
Delay time, WR MCR to output
td23
td24
td25
MIN
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6 Parameter Measurement Information
Figure 6-1. Baud Generator Timing Waveforms
12
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Figure 6-2. Write Cycle Timing Waveforms
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Figure 6-3. Read Cycle Timing Waveforms
14
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Figure 6-4. Receiver Timing Waveforms
Figure 6-5. Receive FIFO First Byte (Sets DR Bit) Waveforms
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Figure 6-6. Receive FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set) Waveforms
Figure 6-7. Receiver Ready (RXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)
Figure 6-8. Receiver Ready (RXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1)
16
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Figure 6-9. Transmitter Timing Waveforms
Figure 6-10. Transmitter Ready (TXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)
Figure 6-11. Transmitter Ready (TXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1)
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Figure 6-12. Modem Control Timing Waveforms
Figure 6-13. CTS and SOUT Autoflow Control Timing (Start and Stop) Waveforms
Figure 6-14. Auto-RTS Timing for RCV Threshold of 1, 4, or 8 Waveforms
Figure 6-15. Auto-RTS Timing for RCV Threshold of 14 Waveforms
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7 Detailed Description
7.1 Autoflow Control (see Figure 7-1)
Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input must be active before
the transmitter FIFO can emit data. With auto-RTS, RTS becomes active when the receiver needs more data
and notifies the sending serial device. When RTS is connected to CTS, data transmission does not occur unless
the receiver FIFO has space for the data; thus, overrun errors are eliminated using ACE1 and ACE2 from a
TLC16C550C with the autoflow control enabled. If not, overrun errors occur when the transmit data rate exceeds
the receiver FIFO read latency.
Figure 7-1. Autoflow Control (Auto-RTS and Auto-CTS) Example
7.2 Auto-RTS (see Figure 7-1)
Auto-RTS data flow control originates in the receiver timing and control block (see Section 7.6) and is linked to
the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level of 1, 4, or 8
(see Figure 7-3), RTS is deasserted. With trigger levels of 1, 4, and 8, the sending ACE may send an additional
byte after the trigger level is reached (assuming the sending ACE has another byte to send) because it may
not recognize the deassertion of RTS until after it has begun sending the additional byte. RTS is automatically
reasserted once the RCV FIFO is emptied by reading the receiver buffer register.
When the trigger level is 14 (see Figure 4), RTS is deasserted after the first data bit of the 16th character is
present on the SIN line. RTS is reasserted when the RCV FIFO has at least one available byte space.
7.3 Auto-CTS (see Figure 7-1)
The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the
next byte. To stop the transmitter from sending the following byte, CTS must be released before the middle
of the last stop bit that is currently being sent (see Figure 7-2). The auto-CTS function reduces interrupts to
the host system. When flow control is enabled, CTS level changes do not trigger host interrupts because the
device automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in
the transmit FIFO and a receiver overrun error may result
7.4 Enabling Autoflow Control and Auto-CTS
Autoflowcontrol is enabled by setting modem control register bits 5 (autoflow enable or AFE) and 1 (RTS) to a 1.
Autoflow incorporates both auto-RTS and auto-CTS. When only auto-CTS is desired, bit 1 in the modem control
register should be cleared (this assumes that a control signal is driving CTS).
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7.5 Auto-CTS and Auto-RTS Functional Timing
Figure 7-2. CTS Functional Timing Waveforms
NOTES:
1. When CTS is low, the transmitter keeps sending serial data out.
2. If CTS goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the
current byte but it does not send the next byte.
3. When CTS goes from high to low, the transmitter begins sending data again.
The receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes. These are described in Figure 7-3 and Figure
7-4.
Figure 7-3. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 1, 4, or 8 Bytes
NOTES:
1. N = RCV FIFO trigger level (1, 4, or 8 bytes)
2. The two blocks in dashed lines cover the case where an additional byte is sent as described in the preceding
auto-RTS section.
Figure 7-4. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 14 Bytes
NOTES:
1. RTS is deasserted when the receiver receives the first data bit of the sixteenth byte. The receive FIFO is full
after finishing the sixteenth byte.
2. RTS is asserted again when there is at least one byte of space available and no incoming byte is in
processing or there is more than one byte of space available.
3. When the receive FIFO is full, the first receive buffer register read reasserts RTS.
20
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7.6 Functional Block Diagram
7.7 Principles of Operation
Table 7-1. Register Selection
DLAB(1)
A2
A1
A0
0
L
L
L
REGISTER
Receiver buffer (read), transmitter holding register (write)
0
L
L
H
Interrupt enable register
X
L
H
L
Interrupt identification register (read only)
X
L
H
L
FIFO control register (write)
X
L
H
H
Line control register
X
H
L
L
Modem control register
X
H
L
H
Line status register
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Table 7-1. Register Selection (continued)
DLAB(1)
A2
A1
A0
X
H
H
L
Modem status register
X
H
H
H
Scratch register
1
L
L
L
Divisor latch (LSB)
1
L
L
H
Divisor latch (MSB)
(1)
REGISTER
The divisor latch access bit (DLAB) is the most significant bit of the line control register. The DLAB signal is controlled by writing to this
bit location (see Table 4).
Table 7-2. ACE Reset Functions
REGISTER/SIGNAL
RESET CONTROL
RESET STATE
Interrupt enable register
Master reset
All bits cleared (0 − 3 forced and 4 − 7 permanent)
Interrupt identification register
Master reset
Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared, and
bits 4 − 5 are permanently cleared
FIFO control register
Master reset
All bits cleared
Line control register
Master reset
All bits cleared
Modem control register
Master reset
All bits cleared (6 − 7 permanent)
Line status register
Master reset
Bits 5 and 6 are set; all other bits are cleared
Modem status register
Master reset
Bits 0 − 3 are cleared; bits 4 − 7 are input signals
Master reset
High
Read LSR/MR
Low
SOUT
INTRPT (receiver error flag)
INTRPT (received data available)
INTRPT (transmitter holding register empty)
INTRPT (modem status changes)
Read RBR/MR
Low
Read IR/write THR/MR
Low
Read MSR/MR
Low
OUT2
Master reset
High
RTS
Master reset
High
DTR
Master reset
High
OUT1
Master reset
High
Scratch register
Master reset
No effect
Divisor latch (LSB and MSB) registers
Master reset
No effect
Receiver buffer register
Master reset
No effect
Master reset
No effect
Transmitter holding register
RCVR FIFO
MR/FCR1 −FCR0/ΔFCR0
All bits cleared
XMIT FIFO
MR/FCR2 −FCR0/ΔFCR0
All bits cleared
22
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7.7.1 Accessible Registers
The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 7-2. These registers control ACE operations, receive data, and transmit data. Descriptions
of these registers follow Table 7-3.
Table 7-3. Summary of Accessible Registers
REGISTER ADDRESS
0 DLAB = 0 0 DLAB = 0 1 DLAB = 0
BIT
NO.
0
1
2
2
Receiver
Buffer
Register
(Read
Only)
Transmitter
Holding
Register
(Write
Only)
RBR
THR
IER
IIR
Data Bit 0
Enable
Received
Data
Available
Interrupt
(ERBI)
Data Bit 0(1)
Data Bit 1
Data Bit 2
Interrupt
Enable
Register
2
3
6
7
Interrupt
FIFO
Ident.
Control
Line
Modem
Line
Modem
Scratch
Register Register Control Control Status
Status
Register
(Read
(Write Register Register Register Register
Only)
Only)
0 DLAB = 1 1 DLAB = 1
Divisor
Latch
(LSB)
Latch
(MSB)
LCR
MCR
LSR
MSR
SCR
DLL
DLM
0 if
Interrupt
Pending
FIFO
Enable
Word
Length
Select
Bit 0
(WLS0)
Data
Terminal
Ready
(DTR)
Data
Ready
(DR)
Delta
Clear to
Send
(ΔCTS)
Bit 0
Bit 0
Bit 8
Data Bit 1
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETBEI)
Interrupt
ID Bit 1
Receiver
FIFO
Reset
Word
Length
Select
Bit 1
(WLS1)
Request
to Send
(RTS)
Delta
Overrun
Data Set
Error
Ready
(OE)
(ΔDSR)
Bit 1
Bit 1
Bit 9
Data Bit 2
Enable
Receiver
Line Status
Interrupt
(ELSI)
Interrupt
ID Bit 2
Transmitt
er FIFO
Reset
Number
of Stop
Bits
(STB)
OUT1
Parity
Error
(PE)
Trailing
Edge
Ring
Indicator
(TERI)
Bit 2
Bit 2
Bit 10
Interrupt
ID Bit 3(2)
DMA
Mode
Select
Parity
Enable
(PEN)
OUT2
Framing
Error
(FE)
Delta
Data
Carrier
Detect
(ΔDCD)
Bit 3
Bit 3
Bit 11
0
Reserved
Even
Parity
Select
(EPS)
Loop
Break
Interrupt
(BI)
Clear to
Send
(CTS)
Bit 4
Bit 4
Bit 12
Autoflow Transmitt
Control
er
Data Set
Enable Holding
Ready
(AFE)
Register (DSR)
(THRE)
Bit 5
Bit 5
Bit 13
Transmitt
Ring
er Empty Indicator
(TEMT)
(RI)
Bit 6
Bit 6
Bit 14
Bit 7
Bit 7
Bit 15
3
Data Bit 3
Data Bit 3
4
Data Bit 4
Data Bit 4
0
5
Data Bit 5
Data Bit 5
0
0
Reserved
Stick
Parity
6
Data Bit 6
Data Bit 6
0
FIFOs
Enabled
Receiver
Trigger
(LSB)
Break
Control
0
FIFOs
Enabled
Receiver
Trigger
(MSB)
Divisor
Latch
Access
Bit
(DLAB)
Data Bit 7
5
FCR
Enable
Modem
Status
Interrupt
(EDSSI)
7
4
Data Bit 7
(2)
(2)
0
0
(1)
Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
(2)
These bits are always 0 in the TL16C450 mode.
Error in
RCVR
FIFO(2)
Data
Carrier
Detect
(DCD)
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7.7.2 FIFO Control Register (FCR)
The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables
and clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signalling.
•
•
•
•
•
•
Bit 0: This bit, when set, enables the transmitter and receiver FIFOs. Bit 0 must be set when other FCR bits
are written to or they are not programmed. Changing this bit clears the FIFOs.
Bit 1: This bit, when set, clears all bytes in the receiver FIFO and clears its counter. The shift register is not
cleared. The 1 that is written to this bit position is self clearing.
Bit 2: This bit, when set, clears all bytes in the transmit FIFO and clears its counter. The shift register is not
cleared. The 1 that is written to this bit position is self clearing.
Bit 3: When FCR0 is set, setting FCR3 causes RXRDY and TXRDY to change from level 0 to level 1.
Bits 4 and 5: These two bits are reserved for future use.
Bits 6 and 7: These two bits set the trigger level for the receiver FIFO interrupt (see Table 7-4).
Table 7-4. Receiver FIFO Trigger
Level
BIT 7
BIT 6
RECEIVER FIFO
TRIGGER LEVEL
(BYTES)
0
0
01
0
1
04
1
0
08
1
1
14
7.7.3 FIFO Interrupt Mode Operation
When the receiver FIFO and receiver interrupts are enabled (FCR0 = 1, IER0 = 1, IER2 = 1), a receiver interrupt
occurs as follows:
1. The received data available interrupt is issued to the microprocessor when the FIFO has reached its
programmed trigger level. It is cleared when the FIFO drops below its programmed trigger level.
2. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and like the
interrupt, it is cleared when the FIFO drops below the trigger level.
3. The receiver line status interrupt (IIR = 06) has higher priority than the received data available (IIR = 04)
interrupt.
4. The data ready bit (LSR0) is set when a character is transferred from the shift register to the receiver FIFO.
It is cleared when the FIFO is empty.
When the receiver FIFO and receiver interrupts are enabled:
1. • At least one character is in the FIFO.
• The most recent serial character was received more than four continuous character times ago (if two stop
bits are programmed, the second one is included in this time delay).
• The most recent microprocessor read of the FIFO has occurred more than four continuous character
times before. This causes a maximum character received command to interrupt an issued delay of 160
ms at a 300 baud rate with a 12-bit character.
2. Character times are calculated by using the RCLK input for a clock signal (makes the delay proportional to
the baud rate).
3. When a time-out interrupt has occurred, it is cleared and the timer is cleared when the microprocessor reads
one character from the receiver FIFO.
4. When a time-out interrupt has not occurred, the time-out timer is cleared after a new character is received or
after the microprocessor reads the receiver FIFO.
When the transmitter FIFO and THRE interrupt are enabled (FCR0 = 1, IER1 = 1), transmit interrupts occur as
follows:
24
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1. The transmitter holding register empty interrupt [IIR (3 −0) = 2] occurs when the transmit FIFO is empty. It is
cleared [IIR (3 −0) = 1] when the THR is written to (1 to 16 characters may be written to the transmit FIFO
while servicing this interrupt) or the IIR is read.
2. The transmitter holding register empty interrupt is delayed one character time minus the last stop bit time
when there have not been at least two bytes in the transmitter FIFO at the same time since the last time that
the FIFO was empty. The first transmitter interrupt after changing FCR0 is immediate if it is enabled.
7.7.4 FIFO Polled Mode Operation
With FCR0 = 1 (transmitter and receiver FIFOs enabled), clearing IER0, IER1, IER2, IER3, or all four to 0 puts
the ACE in the FIFO polled mode of operation. Since the receiver and transmitter are controlled separately,
either one or both can be in the polled mode of operation.
In this mode, the user program checks receiver and transmitter status using the LSR. As stated previously:
• LSR0 is set as long as there is one byte in the receiver FIFO.
• LSR1 − LSR 4 specify which error(s) have occurred. Character error status is handled the same way as when
in the interrupt mode; the IIR is not affected since IER2 = 0.
• LSR5 indicates when the THR is empty.
• LSR6 indicates that both the THR and TSR are empty.
• LSR7 indicates whether there are any errors in the receiver FIFO.
There is no trigger level reached or time-out condition indicated in the FIFO polled mode. However, the receiver
and transmitter FIFOs are still fully capable of holding characters.
7.7.5 Interrupt Enable Register (IER)
The IER enables each of the five types of interrupts (refer to Table 7-5) and enables INTRPT in response to an
interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The contents of
this register are summarized in Table 7-3 and are described in the following bullets.
•
•
•
•
•
Bit 0: When set, this bit enables the received data available interrupt.
Bit 1: When set, this bit enables the THRE interrupt.
Bit 2: When set, this bit enables the receiver line status interrupt.
Bit 3: When set, this bit enables the modem status interrupt.
Bits 4 through 7: These bits are not used (always cleared).
7.7.6 Interrupt Identification Register (IIR)
The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with
most popular microprocessors.
The ACE provides four prioritized levels of interrupts:
•
•
•
•
Priority 1 − Receiver line status (highest priority).
Priority 2 − Receiver data ready or receiver character time-out.
Priority 3 − Transmitter holding register empty.
Priority 4 − Modem status (lowest priority).
When an interrupt is generated, the IIR indicates that an interrupt is pending and encodes the type of interrupt
in its three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 7-3 and
described in Table 7-5. Detail on each bit is as follows:
•
•
•
•
Bit 0: This bit is used either in a hardwire prioritized or polled interrupt system. When bit 0 is cleared, an
interrupt is pending If bit 0 is set, no interrupt is pending.
Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in Table 3.
Bit 3: This bit is always cleared in TL16C450 mode. In FIFO mode, bit 3 is set with bit 2 to indicate that a
time-out interrupt is pending.
Bits 4 and 5: These two bits are not used (always cleared).
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•
Bits 6 and 7: These bits are always cleared in TL16C450 mode. They are set when bit 0 of the FIFO control
register is set.
Table 7-5. Interrupt Control Functions
INTERRUPT IDENTIFICATION
REGISTER
PRIORITY
LEVEL
INTERRUPT SOURCE
INTERRUPT RESET METHOD
None
None
None
1
Receiver line status
Overrun error, parity error,
framing error, or break interrupt
Read the line status register
2
Received data
available
Receiver data available in the
TL16C450 mode or trigger level
reached in the FIFO mode
Read the receiver buffer register
2
Character time-out
indication
No characters have been
removed from or input to the
receiver FIFO during the last four
Read the receiver buffer register
character times, and there is at
least one character in it during
this time
Transmitter holding register
empty
Read the interrupt identification
register(if source of interrupt)
or writing into the transmitter
holding register
Clear to send, data set ready,
ring indicator, or data carrier
detect
Read the modem status register
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
1
None
0
1
1
0
0
1
0
0
1
26
1
0
0
INTERRUPT TYPE
0
0
1
0
3
Transmitter holding
register empty
0
0
0
0
4
Modem status
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7.7.7 Line Control Register (LCR)
The system programmer controls the format of the asynchronous data communication exchange through the
LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates
the need for separate storage of the line characteristics in system memory. The contents of this register are
summarized in Table 7-3 and described in the following bulleted list.
•
Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character. These
bits are encoded as shown in Table 7-6.
Table 7-6. Serial Character Word
Length
•
BIT 1
BIT 0
WORD LENGTH
0
0
5 bits
0
1
6 bits
1
0
7 bits
1
1
8 bits
Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When bit
2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated is
dependent on the word length selected with bits 0 and 1. The receiver clocks only the first stop bit regardless
of the number of stop bits selected. The number of stop bits generated in relation to word length and bit 2 are
shown in Table 7-7.
Table 7-7. Number of Stop Bits Generated
•
•
•
•
•
BIT 2
WORD LENGTH
SELECTED BY BITS
1 AND 2
0
Any word length
1
1
5 bits
1 1/2
1
6 bits
2
1
7 bits
2
1
8 bits
2
NUMBER OF STOP
BITS GENERATED
Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in transmitted data between
the last data word bit and the first stop bit. In received data, if bit 3 is set, parity is checked. When bit 3 is
cleared, no parity is generated or checked.
Bit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set even parity (an
even number of logic 1s in the data and parity bits) is selected. When parity is enabled and bit 4 is cleared,
odd parity (an odd number of logic 1s) is selected.
Bit 5: This bit is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked as
cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set. If bit 5
is cleared, stick parity is disabled.
Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition; i.e., a condition where SOUT is
forced to the spacing (cleared) state. When bit 6 is cleared, the break condition is disabled and has no affect
on the transmitter logic; it only effects SOUT.
Bit 7: This bit is the divisor latch access bit (DLAB). Bit 7 must be set to access the divisor latches of the baud
generator during a read or write. Bit 7 must be cleared during a read or write to access the receiver buffer, the
THR, or the IER.
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7.7.8 Line Status Register (LSR)
1The
LSR provides information to the CPU concerning the status of data transfers. The contents of this register
are summarized in Table 7-3 and described in the following bulleted list.
•
•
•
•
•
•
•
•
Bit 0: This bit is the data ready (DR) indicator for the receiver. DR is set whenever a complete incoming
character has been received and transferred into the RBR or the FIFO. DR is cleared by reading all of the
data in the RBR or the FIFO.
Bit 12:This bit is the overrun error (OE) indicator. When OE is set, it indicates that before the character in the
RBR was read, it was overwritten by the next character transferred into the register. OE is cleared every time
the CPU reads the contents of the LSR. If the FIFO mode data continues to fill the FIFO beyond the trigger
level, an overrun error occurs only after the FIFO is full and the next character has been completely received
in the shift register. An overrun error is indicated to the CPU as soon as it happens. The character in the shift
register is overwritten, but it is not transferred to the FIFO.
Bit 2 (see Footnote 2): This bit is the parity error (PE) indicator. When PE is set, it indicates that the parity
of the received data character does not match the parity selected in the LCR (bit 4). PE is cleared every
time the CPU reads the contents of the LSR. In the FIFO mode, this error is associated with the particular
character in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at
the top of the FIFO.
Bit 3 (see Footnote 2): This bit is the framing error (FE) indicator. When FE is set, it indicates that the
received character didnot have a valid (set) stop bit. FE is cleared every time the CPU reads the contents
of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it
applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. The ACE
tries to resynchronize after a framing error. To accomplish this, it is assumed that the framing error is due to
the next start bit. The ACE samples this start bit twice and then accepts the input data.
Bit 4 (see Footnote 2): This bit is the break interrupt (BI) indicator. When BI is set, it indicates that the
received data input was held low for longer than a full-word transmission time. A full-word transmission time
is defined as the total time to transmit the start, data, parity, and stop bits. BI is cleared every time the CPU
reads the contents of the LSR. In the FIFO mode, this error is associated with the particular character in the
FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of the
FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character transfer is
enabled after SIN goes to the marking state for at least two RCLK samples and then receives the next valid
start bit.
Bit 5: This bit is the THRE indicator. THRE is set when the THR is empty, indicating that the ACE is ready to
accept a new character. If the THRE interrupt is enabled when THRE is set, an interrupt is generated. THRE
is set when the contents of the THR are transferred to the TSR. THRE is cleared concurrent with the loading
of the THR by the CPU. In the FIFO mode, THRE is set when the transmit FIFO is empty; it is cleared when
at least one byte is written to the transmit FIFO.
Bit 6: This bit is the transmitter empty (TEMT) indicator. TEMT bit is set when the THR and the TSR are
bothempty. When either the THR or the TSR contains a data character, TEMT is cleared. In the FIFO mode,
TEMT is set when the transmitter FIFO and shift register are both empty.
Bit 7: In the TL16C550C mode, this bit is always cleared. In the TL16C450 mode, this bit is always cleared. In
the FIFO mode, LSR7 is set when there is at least one parity, framing, or break error in the FIFO. It is cleared
when the microprocessor reads the LSR and there are no subsequent errors in the FIFO.
1
2
28
The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing
environment.
Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.
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7.7.9 Modem Control Register (MCR)
The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is
emulating a modem. The contents of this register are summarized in Table 7-3 and are described in the following
bulleted list.
•
•
•
•
Bit 0: This bit (DTR) controls the DTR output
Bit 1: This bit (RTS) controls the RTS output
Bit 2: This bit (OUT1) controls OUT1, a user-designated output signal.
Bit 3: This bit (OUT2) controls OUT2, a user-designated output signal.
When any of bits 0 through 3 are set, the associated output is forced low. When any of these bits are cleared,
the associated output is forced high.
•
•
•
Bit 4: This bit (LOOP) provides a local loop back feature for diagnostic testing of the ACE. When LOOP is set,
the following occurs:
– The transmitter SOUT is set high.
– The receiver SIN is disconnected.
– The output of the TSR is looped back into the receiver shift register input.
– The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected.
– The four modem control outputs (DTR, RTS, OUT1, and OUT2) are internally connected to the four
modem control inputs.
– The four modem control outputs are forced to the inactive (high) levels.
Bit 5: This bit (AFE) is the autoflow control enable. When set, the autoflow control as described in the detailed
description is enabled.
In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify the
transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational. The
modem control interrupts are also operational, but the modem control interrupt’s sources are now the lower four
bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the IER.
The ACE flow can be configured by programming bits 1 and 5 of the MCR as shown in Table 7-8.
Table 7-8. ACE Flow Configuration
MCR BIT 5 (AFE)
MCR BIT 1 (RTS)
1
1
ACE FLOW CONFIGURATION
Auto-RTS and auto-CTS enabled (autoflow control enabled)
1
0
Auto-CTS only enabled
0
X
Auto-RTS and auto-CTS disabled
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7.7.10 Modem Status Register (MSR)
The MSR is an 8-bit register that provides information about the current state of the control lines from the
modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide change
information; when a control input from the modem changes state, the appropriate bit is set. All four bits are
cleared when the CPU reads the MSR. The contents of this register are summarized in Table 7-3 and are
described in the following bulleted list.
•
•
•
•
•
•
•
•
30
Bit 0: This bit is the change in clear-to-send (ΔCTS) indicator. ΔCTS indicates that the CTS input has
changed state since the last time it was read by the CPU. When ΔCTS is set (autoflow control is not enabled
and the modem status interrupt is enabled), a modem status interrupt is generated. When autoflow control is
enabled (ΔCTS is cleared), no interrupt is generated.
Bit 1: This bit is the change in data set ready (ΔDSR) indicator. ΔDSR indicates that the DSR input has
changed state since the last time it was read by the CPU. When ΔDSR isset and the modem status interrupt
is enabled, a modem status interrupt is generated.
Bit 2: This bit is the trailing edge of the ring indicator (TERI) detector. TERI indicates that the RI input to the
chip has changed from a low to a high level. When TERI is set and the modem status interrupt is enabled, a
modem status interrupt is generated.
Bit 3: This bit is the change in data carrier detect (ΔDCD) indicator. ΔDCD indicates that the DCD input to the
chip has changed state since the last time it was read by the CPU. When ΔDCD is set and the modem status
interrupt is enabled, a modem status interrupt is generated.
Bit 4: This bit is the complement of the clear-to-send (CTS) input. When the ACE is in the diagnostic test
mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 1 (RTS).
Bit 5: This bit is the complement of the data set ready (DSR) input. When the ACE is in the diagnostic test
mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 0 (DTR).
Bit 6: This bit is the complement of the ring indicator (RI) input. When the ACE is in the diagnostic test mode
(LOOP [MCR4] = 1), this bit is equal to the MCR bit 2 (OUT1).
Bit 7: This bit is the complement of the data carrier detect (DCD) input. When the ACE is in the diagnostic test
mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 3 (OUT2).
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7.7.11 Programming Baud Generator
The ACE contains a programmable baud generator that takes a clock input in the range between dc and 16 MHz
and divides it by a divisor in the range between 1 and (216−1).The output frequency of the baud generator is
sixteen times (16 x) the baud rate. The formula for the divisor is:
divisor = XIN frequency input ÷ (desired baud rate x 16)
(1)
Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must
be loaded during initialization of the ACE in order to ensure desired operation of the baud generator. When either
of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.
Table 7-9 and Table 7-10 illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz and
3.072 MHz respectively. For baud rates of 38.4 kbits/s and below, the error obtained is very small. The accuracy
of the selected baud rate is dependent on the selected crystal frequency (refer to Figure 7-5 for examples of
typical clock circuits).
Table 7-9. Baud Rates Using a 1.8432-MHz Crystal
DESIRED BAUD RATE
DIVISOR USED TO GENERATE 16 x CLOCK
50
2304
PERCENT ERROR DIFFERENCE BETWEEN
DESIRED AND ACTUAL
75
1536
110
1047
0.026
134.5
857
0.058
150
768
300
384
600
192
1200
96
1800
64
2000
58
2400
48
3600
32
4800
24
7200
16
9600
12
19200
6
38400
3
56000
2
0.69
2.86
Table 7-10. Baud Rates Using a 3.072-MHz Crystal
DESIRED BAUD RATE
DIVISOR USED TO GENERATE 16 x CLOCK
50
3840
PERCENT ERROR DIFFERENCE BETWEEN
DESIRED AND ACTUAL
75
2560
110
1745
0.026
134.5
1428
0.034
150
1280
300
640
600
320
1200
160
1800
107
2000
96
2400
80
3600
53
4800
40
0.312
0.628
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Table 7-10. Baud Rates Using a 3.072-MHz Crystal (continued)
DESIRED BAUD RATE
DIVISOR USED TO GENERATE 16 x CLOCK
PERCENT ERROR DIFFERENCE BETWEEN
DESIRED AND ACTUAL
1.23
7200
27
9600
20
19200
10
38400
5
Figure 7-5. Typical Clock Circuits
Table 7-11. TYPICAL CRYSTAL OSCILLATOR
NETWORK
CRYSTAL
RP
RX2
C1
C2
3.072 MHz
1 MW
1.5 kW
10 − 30 pF
40 − 60 pF
1.8432 MHz
1 MW
1.5 kW
10 − 30 pF
40 − 60 pF
7.7.12 Receiver Buffet Register (RBR)
The ACE receiver section consists of a receiver shift register (RSR) and a RBR. The RBR is actually a 16-byte
FIFO. Timing is supplied by the 16 x receiver clock (RCLK). Receiver section control is a function of the ACE line
control register.
The ACE RSR receives serial data from SIN. The RSR then concatenates the data and moves it into the RBR
FIFO. In the TL16C450 mode, when a character is placed in the RBR and the received data available interrupt is
enabled (IER0 = 1), an interrupt is generated. This interrupt is cleared when the data is read out of the RBR. In
the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register.
7.7.13 Scratch Register
The scratch register is an 8-bit register that is intended for the programmer’s use as a scratchpad in the sense
that it temporarily holds the programmer’s data without affecting any other ACE operation.
7.7.14 Transmitter Holding Register (THR)
The ACE transmitter section consists of a THR and a transmitter shift register (TSR). The THR is actually a
16-byte FIFO. Timing is supplied by BAUDOUT. Transmitter section control is a function of the ACE line control
register.
The ACE THR receives data off the internal data bus and when the shift register is idle, moves it into the
TSR. The TSR serializes the data and outputs it at SOUT. In the TL16C450 mode, if the THR is empty and
the transmitter holding register empty (THRE) interrupt is enabled (IER1 = 1), an interrupt is generated. This
interrupt is cleared when a character is loaded into the register. In the FIFO mode, the interrupts are generated
based on the control setup in the FIFO control register.
32
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8 Application Information
Figure 8-1. Basic TL16C550C Configuration
Figure 8-2. Typical Interface for a High Capacity Data Bus
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Figure 8-3. Typical TL16C550C Connection to a CPU
(2)
34
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9 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
9.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
36
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PACKAGE OPTION ADDENDUM
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27-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TL16C550CFNR
ACTIVE
PLCC
FN
44
500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
TL16C550CFN
TL16C550CFNRG4
ACTIVE
PLCC
FN
44
500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
TL16C550CFN
TL16C550CIFNR
ACTIVE
PLCC
FN
44
500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TL16C550CIFN
TL16C550CIFNRG4
ACTIVE
PLCC
FN
44
500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TL16C550CIFN
TL16C550CIPTR
ACTIVE
LQFP
PT
48
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TA550CI
TL16C550CIPTRG4
ACTIVE
LQFP
PT
48
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TA550CI
TL16C550CPFBR
ACTIVE
TQFP
PFB
48
1000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
TA550CPFB
TL16C550CPTR
ACTIVE
LQFP
PT
48
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
TA550C
TL16C550CPTRG4
ACTIVE
LQFP
PT
48
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
TA550C
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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