TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
D Integrated Asynchronous-Communications
D
D
D
D
D
D
D
D
Element
Consists of Four Improved TL16C550C
ACEs Plus Steering Logic
In FIFO Mode, Each ACE Transmitter and
Receiver Is Buffered With 16-Byte FIFO to
Reduce the Number of Interrupts to CPU
In TL16C450 Mode, Hold and Shift
Registers Eliminate Need for Precise
Synchronization Between the CPU and
Serial Data
Up to 16-MHz Clock Rate for up to 1-Mbaud
Operation with VCC = 3.3 V and 5 V
Programmable Baud-Rate Generators
Which Allow Division of Any Input
Reference Clock by 1 to (216 − 1) and
Generate an Internal 16 × Clock
Adds or Deletes Standard Asynchronous
Communication Bits (Start, Stop, and
Parity) to or From the Serial-Data Stream
Independently Controlled Transmit,
Receive, Line Status, and Data Set
Interrupts
5-V and 3.3-V Operation
D Fully Programmable Serial Interface
D
D
D
D
D
D
D
D
D
D
Characteristics:
− 5-, 6-, 7-, or 8-Bit Characters
− Even-, Odd-, or No-Parity Bit
− 1-, 1 1/2-, or 2-Stop Bit Generation
− Baud Generation (DC to 1-Mbit Per
Second)
False Start Bit Detection
Complete Status Reporting Capabilities
Line Break Generation and Detection
Internal Diagnostic Capabilities:
− Loopback Controls for Communications
Link Fault Isolation
− Break, Parity, Overrun, Framing Error
Simulation
Fully Prioritized Interrupt System Controls
Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
3-State Outputs Provide TTL Drive
Capabilities for Bidirectional Data Bus and
Control Bus
Programmable Auto-RTS and Auto-CTS
CTS Controls Transmitter in Auto-CTS
Mode,
RCV FIFO Contents and Threshold Control
RTS in Auto-RTS Mode,
description
The TL16C554A is an enhanced quadruple version of the TL16C550C asynchronous-communications element
(ACE). Each channel performs serial-to-parallel conversion on data characters received from peripheral
devices or modems and parallel-to-serial conversion on data characters transmitted by the CPU. The complete
status of each channel of the quadruple ACE can be read by the CPU at any time during operation. The
information obtained includes the type and condition of the operation performed and any error conditions
encountered.
The TL16C554A quadruple ACE can be placed in an alternate FIFO mode, which activates the internal FIFOs
to allow 16 bytes (plus three bits of error data per byte in the receiver FIFO) to be stored in both receive and
transmit modes. In the FIFO mode of operation, there is a selectable autoflow control feature that can
significantly reduce software overhead and increase system efficiency by automatically controlling serial-data
flow using RTS output and CTS input signals. All logic is on the chip to minimize system overhead and maximize
system efficiency. Two terminal functions allow signaling of direct-memory access (DMA) transfers. Each ACE
includes a programmable baud-rate generator that can divide the timing reference clock input by a divisor
between 1 and 216 −1.
The TL16C554A is available in a 68-pin plastic-leaded chip-carrier (PLCC) FN package, 64-pin plastic quad
flatpack (PQFP) PM package and in an 80-pin (TQFP) PN package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2010, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
DCDA
RIA
RXA
GND
D7
D6
D5
D4
D3
D2
D1
D0
INTN
VCC
RXD
RID
DCDD
FN PACKAGE
(TOP VIEW)
9
10
8 7
6
5 4 3 2
1 68 67 66 65 64 63 62 61
60
11
59
12
58
13
57
14
56
15
55
16
54
17
53
18
52
19
51
20
50
21
49
22
48
23
47
24
46
25
45
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
DCDB
RIB
RXB
VCC
NC
A2
A1
A0
XTAL1
XTAL2
RESET
RXRDY
TXRDY
GND
RXC
RIC
DCDC
DSRA
CTSA
DTRA
VCC
RTSA
INTA
CSA
TXA
IOW
TXB
CSB
INTB
RTSB
GND
DTRB
CTSB
DSRB
NC − No internal connection
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
DSRD
CTSD
DTRD
GND
RTSD
INTD
CSD
TXD
IOR
TXC
CSC
INTC
RTSC
VCC
DTRC
CTSC
DSRC
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
DSRD
CTSD
DTRD
GND
RTSD
INTD
CSD
TXD
IOR
TXC
CSC
INTC
RTSC
VCC
DTRC
CTSC
PM PACKAGE
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
32
50
31
51
30
52
29
53
28
54
27
55
26
56
25
57
24
58
23
59
22
60
21
61
20
62
19
63
18
64
1
2 3 4
5
6
7
17
8 9 10 11 12 13 14 15 16
DSRC
DCDC
RIC
RXC
GND
RESET
XTAL2
XTAL1
A0
A1
A2
VCC
RXB
RIB
DCDB
DSRB
DSRA
CTSA
DTRA
VCC
RTSA
INTA
CSA
TXA
IOW
TXB
CSB
INTB
RTSB
GND
DTRB
CTSB
DCDD
RID
RXD
VCC
D0
D1
D2
D3
D4
D5
D6
D7
GND
RXA
RIA
DCDA
NC − No internal connection
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
RIB
DCDB
NC
NC
DCDC
RIC
RXC
GND
TXRDY
RXRDY
RESET
NC
XTAL2
XTAL1
NC
A0
A1
A2
VCC
RXB
PN PACKAGE
(TOP VIEW)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
NC
DSRC
CTSC
DTRC
VCC
RTSC
INTC
CSC
TXC
IOR
NC
TXD
CSD
INTD
RTSD
GND
DTRD
CTSD
DSRD
NC
61
40
62
39
63
38
64
37
65
36
66
35
67
34
68
33
69
32
70
31
71
30
72
29
73
28
74
27
75
26
76
25
77
24
78
23
79
22
80
4 5
6
21
7 8 9 10 11 12 13 14 15 16 17 18 19 20
NC
DCDD
RID
RXD
VCC
INTN
D0
D1
D2
NC
D3
D4
D5
D6
D7
GND
RXA
RIA
DCDA
NC
1 2 3
NC − No internal connection
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
NC
DSRB
CTSB
DTRB
GND
RTSB
INTB
CSB
TXB
IOW
NC
TXA
CSA
INTA
RTSA
VCC
DTRA
CTSA
DSRA
NC
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
functional block diagram (per channel)
5 − 66
D(7 − 0)
Data
Bus
Buffer
Internal
Data
Bus
8
S
e
l
e
c
t
Receiver
FIFO
8
Receiver
Shift
Register
Receiver
Buffer
Register
Receiver
Timing and
Control
Line
Control
Register
A0
A1
A2
CSA
CSB
CSC
CSD
RESET
IOR
IOW
TXRDY
XTAL1
XTAL2
RXRDY
INTN
7
RXA
14
34
Divisor
Latch (LS)
33
32
Baud
Generator
Divisor
Latch (MS)
16
Line
Status
Register
20
50
54
37
52
Transmitter
Timing and
Control
Select
and
Control
Logic
Transmitter
FIFO
Transmitter
Holding
Register
18
39
8
S
e
l
e
c
t
8
Transmitter
Shift
Register
Autoflow
Control
(AFE)
17
TXA
35
Modem
Control
Register
36
38
8
11
12
65
Modem
Status
Register
8
Modem
Control
Logic
10
9
8
13, 30, 47, 64
VCC
GND
RTSA
6, 23, 40, 57
Power
Supply
Interrupt
Enable
Register
Interrupt
Identification
Register
8
Interrupt
Control
Logic
CTSA
DTRA
DSRA
DCDA
RIA
15 INTA
8
FIFO
Control
Register
NOTE A: Terminal numbers shown are for the FN package and channel A.
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• DALLAS, TEXAS 75265
5
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
Terminal Functions
TERMINAL
FN
NO.
PM
NO.
PN
NO.
I/O
DESCRIPTION
34
33
32
22,
23,
24
48
47
46
I
Register select terminals. A0, A1, and A2 are three inputs used during read and write
operations to select the ACE register to read or write.
CSA, CSB,
CSC, CSD
16, 20,
50, 54
7, 11,
38, 42
28, 33,
68, 73
I
Chip select. Each chip select (CSx) enables read and write operations to its respective
channel.
CTSA, CTSB,
CTSC, CTSD
11, 25,
45, 59
2, 16,
33, 47
23, 38,
63, 78
I
Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit
4 (CTS) of the modem-status register. Bit 0 (ΔCTS) of the modem-status register indicates
that CTS has changed state since the last read from the modem-status register. If the
modem-status interrupt is enabled when CTS changes levels and the auto-CTS mode is
not enabled, an interrupt is generated. CTS is also used in the auto-CTS mode to control
the transmitter.
D7 −D0
66 −68
1 −5
53−60
15−11,
9−7
I/O
Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control,
and status information between the TL16C554A and the CPU. D0 is the least-significant
bit (LSB).
DCDA, DCDB,
DCDC, DCDD
9, 27,
43, 61
18, 31,
49, 64
19,42,
59, 2
I
Data carrier detect. A low on DCDx indicates the carrier has been detected by the modem.
The condition of this signal is checked by reading bit 7 of the modem-status register.
DSRA, DSRB,
DSRC, DSRD
10, 26,
44, 60
1, 17,
32, 48
22, 39,
62, 79
I
Data set ready. DSRx is a modem-status signal. Its condition can be checked by reading
bit 5 (DSR) of the modem-status register. DSR has no effect on the transmit or receive
operation.
DTRA, DTRB,
DTRC, DTRD
12, 24,
46, 58
3, 15,
34, 46
24, 37,
64, 77
O
Data terminal ready. DTRx is an output that indicates to a modem or data set that the ACE
is ready to establish communications. It is placed in the active state by setting the DTR bit
of
the
modemcontrol register. DTRx is placed in the inactive state (high) either as a result of the master
reset during loop-mode operation, or when clearing bit 0 (DTR) of the modem-control
register.
GND
6, 23,
40, 57
14,
28, 45,
61
16, 36,
56, 76
INTN
65
NAME
A0
A1
A2
INTA, INTB,
INTC, INTD
6
Signal and power ground
I
Interrupt normal. INTN operates in conjunction with bit 3 of the modem-status register and
affects operation of the interrupts (INTA, INTB, INTC, and INTD) for the four universal
asynchronous receiver/transceivers (UARTs) per the following table.
INTN
OPERATION OF INTERRUPTS
Brought low or
allowed to float
Interrupts are enabled according to the state of OUT2 (MCR bit 3). When
the MCR bit 3 is cleared, the 3-state interrupt output of that UART is in
the high-impedance state. When the MCR bit 3 is set, the interrupt output
of the UART is enabled.
Brought high
Interrupts are always enabled, overriding the OUT2 enables.
15, 21,
49, 55
6, 12,
37, 43
27, 34,
67, 74
O
External interrupt output. The INTx outputs go high (when enabled by the interrupt register)
and inform the CPU that the ACE has an interrupt to be serviced. Four conditions that cause
an interrupt to be issued are: receiver error, receiver data available or timeout (FIFO mode
only), transmitter holding register empty, and an enabled modem-status interrupt. The
interrupt is disabled when it is serviced or as the result of a master reset.
IOR
52
40
70
I
Read strobe. A low level on IOR transfers the contents of the selected register to the
external CPU bus.
IOW
18
9
31
I
Write strobe. IOW allows the the CPU to write to the register selected by the address.
RESET
37
27
53
I
Master reset. When active, RESET clears most ACE registers and sets the state of various
signals. The transmitter output and the receiver input are disabled during reset time.
6
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• DALLAS, TEXAS 75265
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
Terminal Functions (Continued)
TERMINAL
PM
NO.
PN
NO.
I/O
DESCRIPTION
RIA, RIB,
RIC, RID
19, 30,
50, 63
18, 43,
58, 3
I
Ring detect indicator. A low on RIx indicates the modem has received a ring signal from
the telephone line. The condition of this signal can be checked by reading bit 6 of the
modem-status register.
RTSA, RTSB,
RTSC, RTSD
5, 13,
36, 44
26, 35,
66, 75
O
Request to send. When active, RTS informs the modem or data set that the ACE is ready
to receive data. RTS is set to the active level by setting the RTS modem-control register
bit, and is set to the inactive (high) level either as a result of a master reset, or during
loop-mode operations, or by clearing bit 1 (RTS) of the MCR. In the auto-RTS mode, RTS
is set to the inactive level by the receiver threshold-control logic.
20, 29,
51, 62
17, 44,
57, 4
I
Serial input. RXx is a serial-data input from a connected communications device. During
loopback mode, the RXx input is disabled from external connection and connected to the
TXx output internally.
54
O
Receive ready. RXRDY goes low when the receive FIFO is full. It can be used as a single
transfer or multitransfer.
29, 32,
69, 72
O
Transmit outputs. TXx is a composite serial-data output connected to a communications
device. TXA, TXB, TXC, and TXD are set to the marking (high) state as a result of reset.
55
O
Transmit ready. TXRDY goes low when the transmit FIFO is full. It can be used as a single
transfer or multitransfer function.
NAME
RXA, RXB
RXC, RXD
RXRDY
TXA, TXB
TXC, TXD
TXRDY
VCC
FN
NO.
7, 29,
41, 63
38
17, 19,
51, 53
8, 10,
39, 41
39
13, 30,
47, 64
21, 35,
52
5, 25,
45, 65
Power supply
XTAL1
35
25
50
I
Crystal input 1 or external clock input. A crystal can be connected to XTAL1 and XTAL2 to
utilize the internal oscillator circuit. An external clock can be connected to drive the
internal-clock circuits.
XTAL2
36
26
51
O
Crystal output 2 or buffered clock output (see XTAL1).
absolute maximum ratings over free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range at any input, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 3 V
Continuous total-power dissipation at (or below) 70°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
Operating free-air temperature range, TA: TL16C554A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
TL16C554AI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage levels are with respect to GND.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
recommended operating conditions, standard voltage (5 V-nominal)
Supply voltage, VCC
Clock high-level input voltage at XTAL1, VIH(CLK)
Clock low-level input voltage at XTAL1, VIL(CLK)
High-level input voltage, VIH
Low-level input voltage, VIL
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
2
VCC
V
−0.5
0.8
V
2
VCC
V
−0.5
0.8
V
Clock frequency, fclock
Operating free-air
free air temperature,
temperature TA
16
MHz
TL16C554A
0
70
°C
TL16C554AI
−40
85
°C
electrical characteristics over recommended ranges of operating free-air temperature and supply
voltage, standard voltage (5-V nominal) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
‡
High-level output voltage
IOH = − 1 mA
VOL‡
Low-level output voltage
IOL = 1.6 mA
IIkg
Input leakage current
VCC = 5.25 V,
VI = 0 to 5.25 V,
IOZ
High-impedance output
current
VCC = 5.25 V,
GND = 0, VO = 0 to 5.25 V,
Chip selected in write mode or chip deselected
ICC
Supply current
VCC = 5.25 V,
TA = 25°C,
RX, DSR, DCD, CTS, and RI at 2 V,
All other inputs at 0.8 V, XTAL1 at 4 MHz,
No load on outputs,
Baud rate = 50 kilobits per second
Ci(XTAL1)
Clock input capacitance
Co(XTAL2)
Clock output capacitance
Ci
Input capacitance
Co
Output capacitance
VOH
†
‡
8
MIN
TYP†
MAX
2.4
V
0.4
V
± 10
μA
± 20
μA
50
mA
15
20
pF
20
30
pF
6
10
pF
10
20
pF
GND = 0,
All other terminals floating
VCC = 0, VSS = 0, all other terminals grounded,
f = 1 MHz, TA = 25°C
All typical values are at VCC = 5 V, TA = 25°C.
These parameters apply for all outputs except XTAL2.
POST OFFICE BOX 655303
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UNIT
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
recommended operating conditions, low voltage (3.3-V nominal)
MIN
NOM
Supply voltage, VCC
3
3.3
3.6
V
Clock high-level input voltage at XTAL1, VIH(CLK)
2
VCC
V
−0.5
0.8
V
2
VCC
V
−0.5
0.8
V
Clock low-level input voltage at XTAL1, VIL(CLK)
High-level input voltage, VIH
Low-level input voltage, VIL
Clock frequency, fclock
Operating free-air
free air temperature,
temperature TA
MAX
UNIT
16
MHz
TL16C554A
0
70
°C
TL16C554AI
−40
85
°C
electrical characteristics over recommended ranges of operating free-air temperature and supply
voltage, low voltage (3.3-V nominal) (unless otherwise noted)
PARAMETER
High-level output voltage
IOH = − 1 mA
VOL‡
Low-level output voltage
IOL = 1.6 mA
IIkg
Input leakage current
VCC = 3.6 V,
VI = 0 to 3.6 V,
IOZ
High-impedance output
current
VCC = 3.6 V,
GND = 0, VO = 0 to 3.6 V,
Chip selected in write mode or chip deselected
ICC
Supply current
VCC = 3.6 V,
TA = 25°C,
RX, DSR, DCD, CTS, and RI at 2 V,
All other inputs at 0.8 V, XTAL1 at 4 MHz,
No load on outputs,
Baud rate = 50 kilobits per second
Ci(XTAL1)
Clock input capacitance
Co(XTAL2)
Clock output capacitance
Ci
Input capacitance
Co
Output capacitance
VOH
†
‡
TEST CONDITIONS
‡
MIN
TYP†
MAX
2.4
V
0.4
V
± 10
μA
± 20
μA
40
mA
15
20
pF
20
30
pF
6
10
pF
10
20
pF
GND = 0,
All other terminals floating
VCC = 0, VSS = 0, all other terminals grounded,
f = 1 MHz, TA = 25°C
UNIT
All typical values are at VCC = 3.3 V, TA = 25°C.
These parameters apply for all outputs except XTAL2.
clock timing requirements over recommended ranges of operating free-air temperature and supply
voltage (see Figure 1)
MIN
MAX
UNIT
tw1
Pulse duration, clock high (external clock)
31
ns
tw2
Pulse duration, clock low (external clock)
31
ns
tw3
Pulse duration, RESET
1000
ns
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
read cycle timing requirements over recommended ranges of operating free-air temperature and
supply voltage (see Figure 4)
MIN
MAX
UNIT
tw4
Pulse duration, IOR low
75
ns
tsu1
Setup time, CSx valid before IOR low (see Note 2)
10
ns
tsu2
Setup time, A2 −A0 valid before IOR low (see Note 2)
15
ns
th1
Hold time, A2 −A0 valid after IOR high (see Note 2)
0
ns
th2
Hold time, CSx valid after IOR high (see Note 2)
0
ns
td1
Delay time, tsu2 + tw4 + td2 (see Note 3)
140
ns
td2
Delay time, IOR high to IOR or IOW low
50
ns
NOTES: 2. The internal address strobe is always active.
3. In the FIFO mode, td1 = 425 ns (min) between reads of the receiver FIFO and the status registers (interrupt-identification register
and line-status register).
write cycle timing requirements over recommended ranges of operating free-air temperature and
supply voltage (see Figure 5)
MIN
MAX
UNIT
tw5
Pulse duration, IOW↓
50
ns
tsu3
Setup time, CSx valid before IOW↓ (see Note 2)
10
ns
tsu4
Setup time, A2 −A0 valid before IOW↓ (see Note 2)
15
ns
tsu5
Setup time, D7 −D0 valid before IOW↑
10
ns
th3
Hold time, A2 −A0 valid after IOW↑ (see Note 2)
5
ns
th4
Hold time, CSx valid after IOW↑ (see Note 2)
th5
Hold time, D7 −D0 valid after IOW↑
td3
Delay time, tsu4 + tw5 + td4
td4
Delay time, IOW↑ to IOW or IOR↓
5
ns
25
ns
120
ns
55
ns
NOTE 2: The internal address strobe is always active.
read cycle switching characteristics over recommended ranges of operating free-air temperature
and supply voltage, CL = 100 pF (see Note 4 and Figure 4)
PARAMETER
ten
Enable time, IOR↓ to D7 −D0 valid
tdis
Disable time, IOR↑ to D7 −D0 released
MIN
0
NOTE 4: VOL and VOH (and the external loading) determine the charge and discharge time.
10
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MAX
UNIT
30
ns
20
ns
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
transmitter switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figures 6, 7, and 8)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
td5
Delay time, INTx↓ to TXx↓ at start
See Note 7
8
24
RCLK
cycles
td6
Delay time, TXx↓ at start to INTx↑
See Note 5
8
8
RCLK
cycles
td7
Delay time, IOW high or low (WR THR) to INTx↑
See Note 5
16
32
RCLK
cycles
td8
Delay time, TXx↓ at start to TXRDY↓
CL = 100 pF
8
RCLK
cycles
tpd1
Propagation delay time, IOW (WR THR)↓ to INTx↓
CL = 100 pF
35
ns
tpd2
Propagation delay time, IOR (RD IIR)↑ to INTx↓
CL = 100 pF
30
ns
tpd3
Propagation delay time, IOW (WR THR)↑ to TXRDY↑
CL = 100 pF
50
ns
NOTE 5: If the transmitter interrupt delay is active, this delay is lengthened by one character time minus the last stop-bit time.
receiver switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figures 9 through 13)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
td9
Delay time, stop bit to INTx↑ or stop bit to RXRDY↓ or read RBR to set interrupt
See Note 6
1
RCLK
cycle
tpd4
Propagation delay time, Read RBR/LSR to INTx↓/LSR interrupt↓
CL = 100 pF,
See Note 7
40
ns
tpd5
Propagation delay time, IOR RCLK↓ to RXRDY↑
See Note 7
30
ns
NOTES: 6. The receiver data available indicator, the overrun error indicator, the trigger level interrupts, and the active RXRDY indicator are
delayed three RCLK (internal receiver timing clock) cycles in the FIFO mode (FCR0 = 1). After the first byte has been received, status
indicators (PE, FE, BI) are delayed three RCLK cycles. These indicators are updated immediately for any further bytes received after
IOR goes active for a read from the RBR register. There are eight RCLK cycle delays for trigger change level interrupts.
7. RCLK and baudout are internal signals derived from divisor latches LSB (DLL) and MSB (DLM) and input clock.
modem control switching characteristics over recommended ranges of operating free-air
temperature and supply voltage, CL = 100 pF (see Figures 14, 15, 16, and 17)
PARAMETER
MIN
MAX
UNIT
tpd6
Propagation delay time, IOW (WR MCR)↑ to RTSx, DTRx↑
50
ns
tpd7
Propagation delay time, modem input CTSx, DSRx, and DCDx ↓↑ to INTx↑
30
ns
tpd8
Propagation delay time, IOR (RD MSR)↑ to interrupt↓
35
ns
tpd9
Propagation delay time, RIx↑ to INTx↑
30
ns
tpd10
Propagation delay time, CTS low to SOUT↓ (See Note 7)
24
baudout
cycles
tsu6
Setup time CTS high to midpoint of Tx stop bit
2
baudout
cycles
tpd11
Propagation delay time, RCV threshold byte to RTS↑
2
baudout
cycles
tpd12
Propagation delay time, IOR (RD RBR) low (read of last byte in receive FIFO) to RTS↓
2
baudout
cycles
tpd13
Propagation delay time, first data bit of 16th character to RTS↑
2
baudout
cycles
tpd14
Propagation delay time, IOR (RD RBR) low to RTS↓
2
baudout
cycles
7. RCLK and baudout are internal signals derived from divisor latches LSB (DLL) and MSB (DLM) and input clock.
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ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
PARAMETER MEASUREMENT INFORMATION
tw1
Clock
(XTAL1)
2V
2V
2V
0.8 V
0.8 V
0.8 V
tw2
fclock = 16 MHz MAX
(a) CLOCK INPUT VOLTAGE WAVEFORM
RESET
tw3
(b) RESET VOLTAGE WAVEFORM
Figure 1. Clock Input and RESET Voltage Waveforms
2.54 V
Device Under Test
680 Ω
TL16C554
82 pF
(see Note A)
NOTE A: This includes scope and jig capacitance.
Figure 2. Output Load Circuit
Data Bus
Serial
Channel 1
Buffers
9-Pin D Connector
Serial
Channel 2
Buffers
9-Pin D Connector
Serial
Channel 3
Buffers
9-Pin D Connector
Serial
Channel 4
Buffers
9-Pin D Connector
Address Bus
Control Bus
TL16C554A
Quadruple
ACE
Figure 3. Basic Test Configuration
12
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TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
PARAMETER MEASUREMENT INFORMATION
A2, A1, A0
Valid
50%
50%
th1
Valid
CSx
50%
50%
tsu1
th2
td1
tsu2
IOR
50%
Active
50%
50%
td2
tw4
IOW
or
50%
ten
Active
Active
tdis
D7 −D0
Valid Data
Figure 4. Read Cycle Timing Waveforms
A2, A1, A0
Valid
50%
50%
th3
Valid
CSx
50%
50%
th4
tsu3
td3
tsu4
IOW
50% Active
50%
tw5
50%
td4
Active
or
50%
Active
IOR
th5
tsu5
D7 −D0
Valid Data
Figure 5. Write Cycle Timing Waveforms
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ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
PARAMETER MEASUREMENT INFORMATION
Start
Data (5 −8)
50%
TXx
Parity
td5
INTx
Start
50%
Stop (1 −2)
50%
50%
50%
td6
50%
50%
tpd1
td7
IOW
50%
(WR THR)
tpd1
50%
50%
tpd2
IOR
(RD IIR)
50%
Figure 6. Transmitter Timing Waveforms
IOW
(WR THR)
TXx
Byte #1
50%
Data
Parity
Stop
50%
Start
td8
tpd3
TXRDY
50%
FIFO Empty
50%
Figure 7. Transmitter Ready Mode 0 Timing Waveforms
IOW
(WR THR)
Byte #16
50%
Start
TXx
Parity
Data
Stop
Start
50%
tpd3
TXRDY
td8
50%
FIFO Full
Figure 8. Transmitter Ready Mode 1 Timing Waveforms
14
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50%
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
PARAMETER MEASUREMENT INFORMATION
TL16C450 Mode:
SIN
(receiver input data)
Start
Data Bits (5 −8)
Parity
Stop
Sample Clock
td9
INTx
(data ready or
RCVR ERR)
50%
50%
tpd4
Active
50%
IOR
Figure 9. Receiver Timing Waveforms
RXx
Start
Data Bits (5 −8)
Parity
Stop
Sample
Clock
INTx (trigger
interrupt)
(FCR6, 7 = 0, 0)
50%
50%
tpd4
td9
IOR
(RD RBR)
LSR
Interrupt
50%
50%
(FIFO at or
above trigger
level)
(FIFO below
trigger level)
Active
50%
tpd4
IOR
(RD LSR)
50%
Active
Figure 10. Receiver FIFO First Byte (Sets RDR) Waveforms
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ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
PARAMETER MEASUREMENT INFORMATION
RXx
Stop
Sample
Clock
td9 (see Note A)
INTx
(time-out or
trigger level)
Interrupt
50%
(FIFO at or above
trigger level)
50%
(FIFO below
trigger level)
tpd4
INTx
Interrupt
50%
Top Byte of FIFO
td9
tpd4
IOR
(RD LSR)
Active
Active
IOR
(RD RBR)
50%
50%
50%
50%
Active
Previous BYTE
Read From FIFO
NOTE A: This is the reading of the last byte in the FIFO.
Figure 11. Receiver FIFO After First Byte (After RDR Set) Waveforms
IOR
(RD RBR)
50%
Active
(see Note A)
RXx
Stop
Sample
Clock
td9
(see Note B)
RXRDY
50%
50%
tpd5
NOTES: A. This is the reading of the last byte in the FIFO.
B. If FCR0 = 1, then td9 = 3 RCLK cycles. For a time-out interrupt, td9 = 8 RCLK cycles.
Figure 12. Receiver Ready Mode 0 Timing Waveforms
16
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TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
PARAMETER MEASUREMENT INFORMATION
IOR
(RD RBR)
50%
Active
(see Note A)
SIN
(first byte that reaches
the trigger level)
Stop
Sample
Clock
td9
(see Note B)
50%
RXRDY
50%
tpd5
NOTES: A. This is the reading of the last byte in the FIFO.
B. If FCR0 = 1, td9 = 3 RCLK cycles. For a trigger change level interrupt, td9 = 8 RCLK.
Figure 13. Receiver Ready Mode 1 Timing Waveforms
IOW
(WR MCR)
50%
50%
tpd6
50%
50%
RTSx, DTRx
CTSx, DSRx,
DCDx
50%
50%
tpd7
INTx
tpd6
tpd7
50%
50%
50%
tpd8
IOR
(RD MSR)
50%
tpd9
50%
50%
RIx
Figure 14. Modem Control Timing Waveforms
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ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
tsu6
CTS
50%
50%
tpd10
TXx
50%
Midpoint of Stop Bit
Figure 15. CTS and TX Autoflow Control Timing (Start and Stop) Waveforms
Midpoint of Stop Bit
RXx
tPD11
tPD12
50%
50%
RTSx
IOR
50%
RD RBR
Figure 16. Auto-RTS Timing for RCV Threshold of 1, 4, or 8 Waveforms
Midpoint of Data Bit 0
RXx
15th Character
16th Character
tpd14
tpd13
50%
50%
RTSx
IOR
50%
RD RBR
Figure 17. Auto-RTS Timing for RCV Threshold of 14 Waveforms
18
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TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
PRINCIPLES OF OPERATION
Three types of information are stored in the internal registers used in the ACE: control, status, and data. Mnemonic
abbreviations for the registers are shown in Table 1. Table 2 defines the address location of each register and whether
it is read only, write only, or read writable.
Table 1. Internal Register Mnemonic Abbreviations
CONTROL
MNEMONIC
STATUS
MNEMONIC
DATA
MNEMONIC
Line-control register
LCR
Line-status register
LSR
Receiver-buffer register
RBR
FIFO-control register
FCR
Modem-status register
MSR
Transmitter-holding register
THR
Modem-control register
MCR
Divisor-latch LSB
DLL
Divisor-latch MSB
DLM
Interrupt enable register
IER
Table 2. Register Selection†
DLAB‡
A2§
A1§
A0§
0
0
0
0
READ MODE
Receiver-buffer register
WRITE MODE
Transmitter-holding register
0
0
0
1
X
0
1
0
Interrupt-enable register
X
0
1
1
X
1
0
0
X
1
0
1
X
1
1
0
Modem-status register
X
1
1
1
Scratchpad register
1
0
0
0
LSB divisor-latch
1
0
0
1
MSB divisor-latch
Interrupt-identification register
FIFO-control register
Line-control register
Modem-control register
Line-status register
Scratchpad register
X = irrelevant, 0 = low level, 1 = high level
† The serial channel is accessed when either CSA or CSD is low.
‡ DLAB is the divisor-latch access bit, located in bit 7 of the LCR.
§ A2 −A0 are device terminals.
Individual bits within the registers with the bit number in parenthesis are referred to by the register mnemonic. For
example, LCR7 refers to line-control register bit 7. The transmitter-buffer register and the receiver-buffer register are
data registers that hold from five to eight bits of data. If less than eight data bits are transmitted, data is right-justified
to the LSB. Bit 0 of a data word is always the first serial-data bit received and transmitted. The ACE data registers
are double buffered (TL16450 mode) or FIFO buffered (FIFO mode) so that read and write operations can be
performed when the ACE is performing the parallel-to-serial or serial-to-parallel conversion.
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ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
PRINCIPLES OF OPERATION
accessible registers
The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 1. These registers control ACE operations, receive data, and transmit data. Descriptions
of these registers follow Table 3.
Table 3. Summary of Accessible Registers
REGISTER ADDRESS
ADDRES
S
REGISTER
MNEMONIC
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
RBR
(read only)
Data Bit 7
(MSB)
Data Bit 6
Data Bit 5
Data
Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
Data Bit 0
(LSB)
0
THR
(write only)
Data BIt 7
Data BIt 6
Data BIt 5
Data
BIt 4
Data BIt 3
Data BIt 2
Data BIt 1
Data BIt 0
0†
DLL
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1†
DLM
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
IER
0
0
0
0
(EDSSI)
Enable
modem
status
interrupt
(ERLSI)
Enable
receiver
line status
interrupt
(ETBEI)
Enable
transmitter
holding
register empty
interrupt
(ERBI)
Enable
received
data
available
interrupt
2
FCR
(write only)
Receiver
Trigger
(MSB)
Receiver
Trigger
(LSB)
Reserved
Reserved
DMA
mode
select
Transmit
FIFO reset
Receiver
FIFO reset
FIFO Enable
2
IIR
(read only)
FIFOs
Enabled‡
FIFOs
Enabled‡
0
0
Interrupt
ID Bit (3)‡
Interrupt ID
Bit (2)
Interrupt ID
Bit (1)
0 If interrupt
pending
3
LCR
(DLAB)
Divisor
latch
access bit
Set break
Stick parity
(EPS)
Evenparity
select
(PEN)
Parity
enable
(STB)
Number of
stop bits
(WLSB1)
Word-length
select bit 1
(WLSB0)
Word-length
select bit 0
4
MCR
0
0
Autoflow
control
enable
(AFE)
Loop
OUT2
Enable
external
interrupt
(INT)
Reserved
(RTS)
Request to
send
(DTR) Data
terminal
ready
5
LSR
Error in
receiver
FIFO‡
(TEMT)
Transmitter
registers
empty
(THRE)
Transmitter
holding
register
empty
(BI)
Break
interrupt
(FE)
Framing
error
(PE)
Parity error
(OE)
Overrun error
(DR)
Data ready
6
MSR
(DCD)
Data
carrier
detect
(RI)
Ring
indicator
(DSR)
Data set
ready
(CTS)
Clear to
send
(Δ DCD)
Delta data
carrier
detect
(TERI)
Trailing
edge ring
indicator
(Δ DSR)
Delta data
set ready
(Δ CTS)
Delta
clear to send
7
SCR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
†
DLAB = 1
‡ These bits are always 0 when FIFOs are disabled.
20
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PRINCIPLES OF OPERATION
FIFO-control register (FCR)
The FCR is a write-only register at the same location as the IIR. It enables the FIFOs, sets the trigger level of
the receiver FIFO, and selects the type of DMA signalling.
D Bit 0: FCR0 enables the transmit and receive FIFOs. All bytes in both FIFOs can be cleared by clearing
FCR0. Data is cleared automatically from the FIFOs when changing from the FIFO mode to the TL16C450
mode (see FCR bit 0) and vice versa. Programming of other FCR bits is enabled by setting FCR0.
D Bit 1: When set, FCR1 clears all bytes in the receiver FIFO and resets its counter. This does not clear the
shift register.
D Bit 2: When set, FCR2 clears all bytes in the transmit FIFO and resets the counter. This does not clear the
shift register.
D Bit 3: When set, FCR3 changes RXRDY and TXRDY from mode 0 to mode 1 if FCR0 is set.
D Bits 4 and 5: FCR4 and FCR5 are reserved for future use.
D Bits 6 and 7: FCR6 and FCR7 set the trigger level for the receiver FIFO interrupt and the auto-RTS flow
control (see Table 4).
Table 4. Receiver FIFO Trigger Level
BIT
7
6
RECEIVER FIFO
TRIGGER LEVEL (BYTES)
0
0
01
0
1
04
1
0
08
1
1
14
FIFO interrupt mode operation
The following receiver status occurs when the receiver FIFO and the receiver interrupts are enabled:
1. LSR0 is set when a character is transferred from the shift register to the receiver FIFO. When the FIFO is
empty, it is reset.
2. IIR = 06 receiver line status interrupt has higher priority than the receive data available interrupt
IIR = 04.
3. Receive data available interrupt is issued to the CPU when the programmed trigger level is reached by the
FIFO. As soon as the FIFO drops below its programmed trigger level, it is cleared.
4. IIR = 04 (receive data available indicator) also occurs when the FIFO reaches its trigger level. It is cleared
when the FIFO drops below the programmed trigger level.
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PRINCIPLES OF OPERATION
FIFO interrupt mode operation (continued)
The following receiver FIFO character time-out status occurs when receiver FIFO and the receiver interrupts
are enabled.
1. When the following conditions exist, a FIFO character time-out interrupt occurs:
a. Minimum of one character in FIFO
b. No new serial characters have been received for at least four character times. At 300 baud and 12-bit
characters, the FIFO time-out interrupt causes a latency of 160 ms maximum from received character
to interrupt generation.
c.
The receive FIFO has not been read for at least four character times.
2. By using the XTAL1 input for a clock signal, the character times can be calculated. The delay is proportional
to the baud rate.
3. The time-out timer is reset after the CPU reads the receiver FIFO or after a new character is received. This
occurs when there has been no time-out interrupt.
4. A time-out interrupt is cleared and the timer is reset when the CPU reads a character from the receiver FIFO.
Transmit interrupts occurs as follows when the transmitter and transmit FIFO interrupts are enabled
(FCR0 =1, IER1 = 1).
1. When the transmitter FIFO is empty, the transmitter holding register interrupt (IIR = 02) occurs. The interrupt
is cleared when the transmitter holding register is written to or the IIR is read. One to sixteen characters can
be written to the transmit FIFO when servicing this interrupt.
2. The transmitter FIFO empty indicators are delayed one character time minus the last stop-bit time whenever
the following occurs:
THRE = 1, and there have not been at least two bytes in transmit FIFO since the last THRE = 1. The first
transmitter interrupt comes immediately after changing FCR0, assuming the interrupt is enabled.
Receiver FIFO trigger level and character time-out interrupts have the same priority as the receive data
available interrupt. The transmitter holding register empty interrupt has the same priority as the transmitter FIFO
empty interrupt.
FIFO polled mode operation
When the FIFOs are enabled and all interrupts are disabled, the device is in the FIFO polled mode.
In the FIFO polled mode, there is no time-out condition indicated or trigger level reached. However, the receive
and transmit FIFOs still have the capability of holding characters. The LSR must be read to determine the ACE
status.
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PRINCIPLES OF OPERATION
interrupt-enable register (IER)
The IER independently enables the four serial channel interrupt sources that activate the interrupt (INTA, B, C,
D) output. All interrupts are disabled by clearing IER0 − IER3 of the IER. Interrupts are enabled by setting the
appropriate bits of the IER. Disabling the interrupt system inhibits the IIR and the active (high) interrupt output.
All other system functions operate in their normal manner, including the setting of the LSR and MSR. The
contents of the IER are shown in Table 3 and described in the following bulleted list:
D Bit 0:
When IER0 is set, IER0 enables the received data available interrupt and the timeout interrupts in
the FIFO mode.
D
D
D
D
Bit 1:
When IER1 is set, the transmitter holding register empty interrupt is enabled.
Bit 2:
When IER2 is set, the receiver line status interrupt is enabled.
Bit 3:
When IER3 is set, the modem-status interrupt is enabled.
Bits 4 − 7: IER4 − IER7. These four bits of the IER are cleared.
interrupt-identification register (IIR)
In order to minimize software overhead during data character transfers, the serial channel prioritizes interrupts
into four levels as follows:
D
D
D
D
Priority 1 − Receiver line status (highest priority)
Priority 2 − Receiver data ready or receiver character timeout
Priority 3 −Transmitter holding register empty
Priority 4 −Modem status (lowest priority)
The IIR stores information indicating that a prioritized interrupt is pending and the type of interrupt. The IIR
indicates the highest priority interrupt pending. The contents of the IIR are indicated in Table 5.
Table 5. Interrupt Control Functions
INTERRUPT
IDENTIFICATION
REGISTER
INTERRUPT SET AND RESET FUNCTIONS
PRIORITY
LEVEL
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
1
—
0
1
1
0
First
0
1
0
0
1
1
0
0
0
0
0
INTERRUPT TYPE
INTERRUPT SOURCE
None
INTERRUPT
RESET CONTROL
None
—
Receiver line status
OE, PE, FE, or BI
LSR read
Second
Received data available
Receiver data available or
trigger level reached
RBR read until FIFO
drops below the trigger
level
0
Second
Character time-out
indicator
No characters have been
removed from or input to the
receiver FIFO during the last
four character times, and there
is at least one character in it
during this time.
RBR read
1
0
Third
THRE
THRE
IIR read (if THRE is the
interrupt source), or
THR write
0
0
Fourth
Modem status
CTS, DSR, RI, or DCD
MSR read
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PRINCIPLES OF OPERATION
interrupt-identification register (IIR) (continued)
D Bit 0: IIR0 indicates whether an interrupt is pending. When IIR0 is cleared, an interrupt is pending.
D Bits 1 and 2: IIR1 and IIR2 identify the highest priority interrupt pending as indicated in Table 5.
D Bit 3: IIR3 is always cleared in the TL16C450 mode. This bit, along with bit 2, is set when in the FIFO mode
and a character time-out interrupt is pending.
D Bits 4 and 5: IIR4 and IIR5 are always cleared.
D Bits 6 and 7: IIR6 and IIR7 are set when FCR0 = 1.
line-control register (LCR)
The format of the data character is controlled by LCR. LCR may be read. Its contents are described in the
following bulleted list and shown in Figure 18.
D Bits 0 and 1: LCR0 and LCR1 are word-length select bits. These bits program the number of bits in each
serial character and are shown in Figure 18.
D Bit 2: LCR2 is the stop-bit select bit. This bit specifies the number of stop bits in each transmitted character.
The receiver always checks for one stop bit.
D Bit 3: LCR3 is the parity-enable bit. When LCR3 is set, a parity bit between the last data word bit and the
stop bit is generated and checked.
D Bit 4: LCR4 is the even-parity select bit. When this bit is set and parity is enabled (LCR3 is set), even parity
is selected. When this bit is cleared and parity is enabled, odd parity is selected.
D Bit 5: LCR5 is the stick-parity bit. When parity is enabled (LCR3 is set) and this bit is set, the transmission
and reception of a parity bit is placed in the opposite state from the value of LCR4. This forces parity to a
known state and allows the receiver to check the parity bit in a known state.
D Bit 6: LCR6 is a break-control bit. When this bit is set, the serial outputs TXx are forced to the spacing state
(low). The break-control bit acts only on the serial output and does not affect the transmitter logic. If the
following sequence is used, no invalid characters are transmitted because of the break.
Step 1.
Load a zero byte in response to the transmitter holding register empty (THRE) status indicator.
Step 2.
Set the break in response to the next THRE status indicator.
Step 3.
Wait for the transmitter to be idle when transmitter empty status signal is set (TEMT = 1); then
clear the break when the normal transmission has to be restored.
D Bit 7: LCR7 is the divisor-latch access bit (DLAB) bit. This bit must be set to access the divisor latches DLL
and DLM of the baud-rate generator during a read or write operation. LCR7 must be cleared to access the
receiver-buffer register, the transmitter-holding register, or the interrupt-enable register.
24
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PRINCIPLES OF OPERATION
line-control register (LCR) (continued)
LINE CONTROL REGISTER
LCR
7
LCR LCR
6
5
LCR
4
LCR
3
LCR LCR
2
1
LCR
0
Word-Length
Select
0
0
1
1
0 = 5 Data Bits
1 = 6 Data Bits
0 = 7 Data Bits
1 = 8 Data bits
Stop-Bit
Select
0 = 1 Stop Bit
1 = 1.5 Stop Bits if 5 Data Bits Selected
2 Stop Bits if 6, 7, 8 Data Bits Selected
Parity Enable
0 = Parity Disabled
1 = Parity Enabled
Even-Parity
Select
0 = Odd Parity
1 = Even Parity
Stick Parity
0 = Stick Parity Disabled
1 = Stick Parity Enabled
Break Control
0 = Break Disabled
1 = Break Enabled
Divisor-Latch
Access BIt
0 = Access Receiver Buffer
1 = Access Divisor Latches
Figure 18. Line-Control Register Contents
line-status register (LSR)
The LSR is a single register that provides status indicators. The LSR shown in Table 6 is described in the
following bulleted list:
D Bit 0: LSR0 is the data ready (DR) bit. Data ready is set when an incoming character is received and
transferred to the receiver-buffer register or to the FIFO. LSR0 is cleared by a CPU read of the data in the
receiver-buffer register or in the FIFO.
D Bit 1: LSR1 is the overrun error (OE) bit. An overrun error indicates that data in the receiver-buffer register
is not read by the CPU before the next character is transferred to the receiver-buffer register, therefore
overwriting the previous character. The OE indicator is cleared whenever the CPU reads the contents of
the LSR. An overrun error occurs in the FIFO mode after the FIFO is full and the next character is completely
received. The overrun error is detected by the CPU on the first LSR read after it occurs. The character in
the shift register is not transferred to the FIFO, but it is overwritten.
D Bit 2: LSR2 is the parity error (PE) bit. A parity error indicates that the received data character does not
have the correct parity as selected by LCR3 and LCR4. The PE bit is set upon detection of a parity error
and is cleared when the CPU reads the contents of the LSR. In the FIFO mode, the parity error is associated
with a particular character in the FIFO. LSR2 reflects the error when the character is at the top of the FIFO.
D Bit 3: LSR3 is the framing error (FE) bit. A framing error indicates that the received character does not have
a valid stop bit. LSR3 is set when the stop bit following the last data bit or parity bit is detected as a zero
bit (spacing level). The FE indicator is cleared when the CPU reads the contents of the LSR. In the FIFO
mode, the framing error is associated with a particular character in the FIFO. LSR3 reflects the error when
the character is at the top of the FIFO.
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PRINCIPLES OF OPERATION
line-status register (LSR) (continued)
D Bit 4: LSR4 is the break interrupt (BI) bit. Break interrupt is set when the received data input is held in the
spacing (low) state for longer than a full word transmission time (start bit + data bits + parity + stop bits).
The BI indicator is cleared when the CPU reads the contents of the LSR. In the FIFO mode, this is associated
with a particular character in the FIFO. LSR2 reflects the BI when the break character is at the top of the
FIFO. The error is detected by the CPU when its associated character is at the top of the FIFO during the
first LSR read. Only one zero character is loaded into the FIFO when BI occurs.
LSR1 − LSR4 are the error conditions that produce a receiver line status interrupt (priority 1 interrupt in the
interrupt-identification register) when any of the conditions are detected. This interrupt is enabled by setting
IER2 in the interrupt-enable register.
D Bit 5: LSR5 is the transmitter holding register empty (THRE) bit. THRE indicates that the ACE is ready to
accept a new character for transmission. The THRE bit is set when a character is transferred from the
transmitter holding register (THR) to the transmitter shift register (TSR). LSR5 is cleared when the CPU
loads THR. LSR5 is not cleared by a CPU read of the LSR. In the FIFO mode, this bit is set when the transmit
FIFO is empty, and it is cleared when one byte is written to the transmit FIFO. When the THRE interrupt
is enabled by IER1, THRE causes a priority 3 interrupt in the IIR. If THRE is the interrupt source indicated
by IIR, INTRPT is cleared by a read of the IIR.
D Bit 6: LSR6 is the transmitter register empty (TEMT) bit. TEMT is set when both THR and TSR are empty.
LSR6 is cleared when a character is loaded into THR, and remains low until the character is transferred out
of TXx. TEMT is not cleared by a CPU read of the LSR. In the FIFO mode, this bit is set when both the
transmitter FIFO and shift register are empty.
D Bit 7: LSR7 is the receiver FIFO error bit. The LSR7 bit is cleared in the TL16C450 mode (see FCR bit 0).
In the FIFO mode, it is set when at least one of the following data errors is in the FIFO: parity error, framing
error, or break interrupt indicator. It is cleared when the CPU reads the LSR, unless there are subsequent
errors in the FIFO.
NOTE
The LSR may be written. However, this function is intended only for factory test. It should be considered as read
only by applications software.
Table 6. Line-Status Register BIts
LSR BITS
LSR0 data ready (DR)
0
Ready
Not ready
LSR1 overrun error (OE)
Error
No error
LSR2 parity error (PE)
Error
No error
LSR3 framing error (FE)
Error
No error
LSR4 break interrupt (BI)
Break
No break
LSR5 transmitter holding register empty (THRE)
Empty
Not empty
LSR6 transmitter register empty (TEMT)
LSR7 receiver FIFO error
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PRINCIPLES OF OPERATION
modem-control register (MCR)
The MCR controls the interface with the modem or data set as described in Figure 19. The MCR can be written
and read. Outputs RTS and DTR are directly controlled by their control bits in this register. A high input asserts
a low signal (active) at the output terminals. MCR bits 0, 1, 2, 3, and 4 are shown as follows:
D Bit 0: When MCR0 is set, the DTR output is forced low. When MCR0 is cleared, the DTR output is forced
high. The DTR output of the serial channel may be input into an inverting line driver in order to obtain the
proper polarity input at the modem or data set.
D Bit1: When MCR1 is set, the RTS output is forced low. When MCR1 is cleared, the RTS output is forced
high. The RTS output of the serial channel may be input into an inverting line driver to obtain the proper
polarity input at the modem or data set.
D Bit 2: MCR2 has no effect on operation.
D Bit 3: When MCR3 is set, the external serial channel interrupt is enabled.
D Bit 4: MCR4 provides a local loopback feature for diagnostic testing of the channel. When MCR4 is set,
serial output TXx is set to the marking (high) state and SIN is disconnected. The output of the TSR is looped
back into the RSR input. The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected. The
four modem control output bits (DTR, RTS, OUT1, and OUT2) are internally connected to the four modem
control input bits (DSR, CTS, RI, and DCD), respectively. The modem control output terminals are forced
to their inactive (high) state. In the diagnostic mode, data transmitted is received by its own receiver. This
allows the processor to verify the transmit and receive data paths of the selected serial channel. Interrupt
control is fully operational; however, modem-status interrupts are generated by controlling the lower four
MCR bits internally. Interrupts are not generated by activity on the external terminals represented by those
four bits.
D Bit 5: This bit is the autoflow control enable (AFE). When set, the autoflow control is enabled, as described
in the detailed description.
The ACE flow control can be configured by programming bits 1 and 5 of the MCR, as shown in Table 7.
Table 7. ACE Flow Configuration
MSR BIT 5
(AFE)
MSR BIT 1
(RTS)
ACE FLOW CONFIGURATION
1
1
Auto-RTS and auto-CTS enabled (autoflow control enabled)
1
0
Auto-CTS only enabled
0
X
Auto-RTS and auto-CTS disabled
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modem-control register (MCR) (continued)
D Bit 6 − Bit 7: MCR5, MCR6, and MCR7 are permanently cleared.
MODEM CONTROL REGISTER
MCR MCR MCR MCR MCR
7
6
5
4
3
MCR MCR
1
2
MCR
0
Data Terminal
Ready
0 = DTR Output Inactive (high)
1 = DTR Output Active (low)
Request
to Send
0 = RTS Output Inactive (high)
1 = RTS Output Active (low)
Out1 (internal)
No effect on external operation
Out2 (internal)
0 = External Interrupt Disabled
1 = External Interrupt Enabled
Loop
0 = Loop Disabled
1 = Loop Enabled
AFE
0 = AFE Disabled
1 = AFE Enabled
Bits Are Set to Logic 0
Figure 19. Modem-Control Register Contents
modem-status register (MSR)
The MSR provides the CPU with status of the modem input lines for the modem or peripheral devices. The MSR
allows the CPU to read the serial channel modem signal inputs by accessing the data bus interface of the ACE.
It also reads the current status of four bits of the MSR that indicate whether the modem inputs have changed
since the last reading of the MSR. The delta status bits are set when a control input from the modem changes
states, and are cleared when the CPU reads the MSR.
The modem input lines are CTS, DSR, RI, and DCD. MSR4 − MSR7 are status indicators of these lines. A status
bit = 1 indicates the input is low. When the status bit is cleared, the input is high. When the modem-status
interrupt in the IER is enabled (IIR3 is set), an interrupt is generated whenever any one of MSR0 − MSR3 is set,
except as noted below in the delta CTS description. The MSR is a priority 4 interrupt. The contents of the MSR
are described in Table 8.
D Bit 0: MSR0 is the delta clear-to-send (Δ CTS) bit. ΔCTS indicates that the CTS input to the serial channel
has changed state since it was last read by the CPU. No interrupt will be generated if auto-CTS mode is
enabled.
D Bit 1: MSR1 is the delta data set ready (Δ DSR) bit. Δ DSR indicates that the DSR input to the serial channel
has changed states since the last time it was read by the CPU.
D Bit 2: MSR2 is the trailing edge of ring indicator (TERI) bit. TERI indicates that the RI input to the serial
channel has changed states from low to high since the last time it was read by the CPU. High-to-low
transitions on RI do not activate TERI.
D Bit 3: MSR3 is the delta data carrier detect (Δ DCD) bit. Δ DCD indicates that the DCD input to the serial
channel has changed states since the last time it was read by the CPU.
D Bit 4: MSR4 is the clear-to-send (CTS) bit. CTS is the complement of the CTS input from the modem
indicating to the serial channel that the modem is ready to receive data from SOUT. When the serial channel
is in the loop mode (MCR4 = 1), MSR4 reflects the value of RTS in the MCR.
D Bit 5: MSR5 is the data set ready DSR bit. DSR is the complement of the DSR input from the modem to
the serial channel that indicates that the modem is ready to provide received data from the serial channel
receiver circuitry. When the channel is in the loop mode (MCR4 is set), MSR5 reflects the value of DTR in
the MCR.
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PRINCIPLES OF OPERATION
modem-status register (MSR) (continued)
D Bit 6: MSR6 is the ring indicator (RI) bit. RI is the complement of the RIx inputs. When the channel is in the
loop mode (MCR4 is set), MSR6 reflects the value of OUT1 in the MCR.
D Bit 7: MSR7 is the data carrier detect (DCD) bit. Data carrier detect indicates the status of the data carrier
detect (DCD) input. When the channel is in the loop mode (MCR4 is set), MSR7 reflects the value of OUT2
in the MCR.
Reading the MSR clears the delta modem status indicators but has no effect on the other status bits. For LSR
and MSR, the setting of status bits is inhibited during status register read operations. If a status condition is
generated during a read IOR operation, the status bit is not set until the trailing edge of the read. When a status
bit is set during a read operation and the same status condition occurs, that status bit is cleared at the trailing
edge of the read instead of being set again. In the loopback mode, CTS, DSR, RI, and DCD inputs are ignored
when modem-status interrupts are enabled; however, a modem-status interrupt can still be generated by writing
to MCR3 −MCR0. Applications software should not write to the MSR.
Table 8. Modem-Status Register BIts
MSR BIT
MNEMONIC
MSR0
Δ CTS
Delta clear to send
DESCRIPTION
MSR1
Δ DSR
Delta data set ready
MSR2
TERI
Trailing edge of ring indicator
MSR3
Δ DCD
Delta data carrier detect
MSR4
CTS
Clear to send
MSR5
DSR
Data set ready
MSR6
RI
Ring indicator
MSR7
DCD
Data carrier detect
programming
The serial channel of the ACE is programmed by control registers LCR, IER, DLL, DLM, MCR, and FCR. These
control words define the character length, number of stop bits, parity, baud rate, and modem interface.
While the control registers can be written in any order, the IER should be written last because it controls the
interrupt enables. Once the serial channel is programmed and operational, these registers can be updated any
time the ACE serial channel is not transmitting or receiving data.
programmable baud-rate generator
The ACE serial channel contains a programmable baud-rate generator (BRG) that divides the clock (dc to
8 MHz) by any divisor from 1 to 216 −1. Two 8-bit divisor-latch registers store the divisor in a 16-bit binary format.
These divisor-latch registers must be loaded during initialization. A 16-bit baud counter is immediately loaded
upon loading of either of the divisor latches. This prevents long counts on initial load. The BRG can use any of
three different popular frequencies to provide standard baud rates. These frequencies are 1.8432 MHz,
3.072 MHz, 8 MHz, and 16 MHz. With these frequencies, standard bit rates from 50 kbps to 512 kbps are
available. Tables 9, 10, 11, and 12 illustrate the divisors needed to obtain standard rates using these three
frequencies. The output frequency of the baud-rate generator is 16 times the data rate [divisor # = clock + (baud
rate × 16)]. RCLK runs at this frequency.
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PRINCIPLES OF OPERATION
programmable baud-rate generator (continued)
Table 9. Baud Rates Using a 1.8432-MHz Crystal
BAUD RATE
DESIRED
DIVISOR (N) USED TO
GENERATE 16 × CLOCK
PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL
50
2304
—
75
1536
—
110
1047
0.026
134.5
857
0.058
150
768
—
300
384
—
600
192
—
1200
96
—
1800
64
—
2000
58
0.690
2400
48
—
3600
32
—
4800
24
—
7200
16
—
9600
12
—
19200
6
—
38400
3
—
56000
2
2.860
Table 10. Baud Rates Using a 3.072-MHz Crystal
BAUD RATE
DESIRED
30
DIVISOR (N) USED TO
GENERATE 16 × CLOCK
PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL
50
3840
—
75
2560
—
110
1745
0.026
134.5
1428
0.034
150
1280
—
300
640
—
—
600
320
1200
160
—
1800
107
0.312
2000
96
—
2400
80
—
3600
53
0.628
4800
40
—
7200
27
1.230
9600
20
—
19200
10
—
38400
5
—
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PRINCIPLES OF OPERATION
programmable baud-rate generator (continued)
Table 11. Baud Rates Using an 8-MHz Clock
BAUD RATE
DESIRED
DIVISOR (N) USED TO
GENERATE 16 × CLOCK
PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL
50
10000
—
75
6667
0.005
110
4545
0.010
134.5
3717
0.013
150
333
0.010
300
1667
0.020
600
883
0.040
1200
417
0.080
1800
277
0.080
2000
250
—
2400
208
0.160
3600
139
0.080
4800
104
0.160
7200
69
0.644
9600
52
0.160
19200
26
0.160
38400
13
0.160
56000
9
0.790
128000
4
2.344
256000
2
2.344
512000
1
2.400
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Table 12. Baud Rates Using an 16-MHz Clock
BAUD RATE
DESIRED
DIVISOR (N) USED TO
GENERATE 16 × CLOCK
PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL
50
20000
0
75
13334
0.00
110
9090
0.01
134.5
7434
0.01
150
6666
0.01
300
3334
−0.02
600
1666
0.04
1200
834
−0.08
1800
554
0.28
2000
500
0.00
2400
416
0.16
3600
278
−0.08
4800
208
0.16
7200
138
0.64
9600
104
0.16
19200
52
0.16
38400
26
0.16
56000
18
−0.79
128000
8
−2.34
256000
4
−2.34
512000
2
−2.34
1000000
1
0.00
receiver
Serial asynchronous data is input into the RXx terminal. The ACE continually searches for a high-to-low
transition. When the transition is detected, a circuit is enabled to sample incoming data bits at the optimum point,
which is the center of each bit. The start bit is valid when RXx is still low at the sample point. Verifying the start
bits prevents the receiver from assembling a false data character due to a low-going noise spike on the RXx
input.
The number of data bits in a character is controlled by LCR0 and LCR1. Parity checking, generation, and polarity
are controlled by LCR3 and LCR4. Receiver status is provided in the LSR. When a full character is received,
including parity and stop bits, the data received indicator in LSR0 is set. In non-FIFO mode, the CPU reads the
RBR, which clears LSR0. If the character is not read prior to a new character transfer from RSR to RBR, an
overrun occurs and the overrun error status indicator is set in LSR1. If there is a parity error, the parity error is
set in LSR2. If a stop bit is not detected, a framing error indicator is set in LSR3.
In the FIFO mode, the data character and the associated error bits are stored in the receiver FIFO. If the data
in RXx is a symmetrical square wave, the center of the data cells occurs within ± 3.125% of the actual center,
providing an error margin of 46.875%. The start bit can begin as much as one 16 × clock cycles prior to being
detected.
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PRINCIPLES OF OPERATION
autoflow control (see Figure 20)
Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input must be active before
the transmitter FIFO can send data. With auto-RTS, RTS becomes active when the receiver can handle more
data and notifies the sending serial device. When RTS is connected to CTS, data transmission does not occur
unless the receiver FIFO has space for the data; thus, overrun errors are eliminated using ACE1 and ACE2 from
a TL16C554A with the autoflow control enabled. Otherwise, overrun errors may occur when the transmit-data
rate exceeds the receiver FIFO read latency.
ACE1
RCV
FIFO
ACE2
SIN
Serial to
Parallel
RTS
Flow
Control
SOUT
CTS
Parallel
to Serial
XMT
FIFO
Flow
Control
D7 −D0
D7 −D0
XMT
FIFO
Parallel
to Serial
SOUT
Flow
Control
CTS
SIN
RTS
Serial to
Parallel
RCV
FIFO
Flow
Control
Figure 20. Autoflow Control (Auto-RTS and Auto-CTS) Example
auto-RTS (see Figure 20)
Auto-RTS data flow control originates in the receiver timing and control block (see functional block diagram)
and is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level
of 1, 4, or 8 (see Figure 22) RTS is deasserted. With trigger levels of 1, 4, and 8, the sending ACE may send
an additional byte after the trigger level is reached (assuming the sending ACE has another byte to send)
because it may not recognize the deassertion of RTS until after it has begun sending the additional byte. RTS
is automatically reasserted once the RCV FIFO is emptied by reading the receiver-buffer register.
When the trigger level is 14 (see Figure 23), RTS is deasserted after the first data bit of the 16th character is
present on the SIN line. RTS is reasserted when the RCV FIFO has at least one available byte space.
auto-CTS (see Figure 20)
The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the next
byte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the
last stop bit currently being sent (see Figure 21). The auto-CTS function reduces interrupts to the host system.
When flow control is enabled, CTS level changes do not trigger host interrupts because the device automatically
controls its own transmitter. Without auto-CTS the transmitter sends any data present in the transmit FIFO and
a receiver overrun error may result.
enabling autoflow control and auto-CTS
Autoflow control is enabled by setting modem-control register bits 5 (autoflow enable or AFE) and 1 (RTS) to
a 1. Autoflow incorporates both auto-RTS and auto-CTS. When only auto-CTS is desired, bit 1 in the modemcontrol register should be cleared (this assumes that an external control signal is driving CTS).
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PRINCIPLES OF OPERATION
auto-CTS and auto-RTS functional timing
Start
SOUT
Bits 0 −7
Start
Stop
Bits 0 −7 Stop
Start
Bits 0 −7 Stop
CTS
NOTES: A. When CTS is low, the transmitter keeps sending serial data out.
B. If CTS goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte but it does
not send the next byte.
C. When CTS goes from high to low, the transmitter begins sending data again.
Figure 21. CTS Functional Timing Waveforms
The receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes. These are described in Figures 3 and 4.
SIN
Start
Byte N
Stop
Start
Byte N+1
Start
Stop
Byte
Stop
RTS
RD
(RD RBR)
1
2
N
N+1
NOTES: A. N = RCV FIFO trigger level (1, 4, or 8 bytes)
B. The two blocks in dashed lines cover the case where an additional byte is sent as described in the preceding auto-RTS section.
Figure 22. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 1, 4, or 8 Bytes
SIN
RTS
Byte 14
Byte 15
Start
Byte 16
Stop
Start
Byte 18 Stop
RTS Released After the
First Data Bit of Byte 16
RD
(RD RBR)
NOTES: A. RTS is deasserted when the receiver receives the first data bit of the sixteenth byte. The receive FIFO is full after finishing the
sixteenth byte.
B. RTS is asserted again when there is at least one byte of space available and no incoming byte is in processing or there is more than
one byte of space available.
C. When the receive FIFO is full, the first receive buffer register read reasserts RTS.
Figure 23. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 14 Bytes
34
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TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
PRINCIPLES OF OPERATION
reset
After power up, the ACE RESET input should be held high for one microsecond to reset the ACE circuits to an
idle mode until initialization. A high on RESET causes the following:
1. Initializes the transmitter and receiver internal clock counters.
2. Clears the LSR, except for transmitter register empty (TEMT) and transmit holding register empty (THRE),
which are set. The MCR is also cleared. All of the discrete lines, memory elements, and miscellaneous logic
associated with these register bits are also cleared or turned off. The LCR, divisor latches, RBR, and
transmitter-buffer register are not affected.
RXRDY operation
In mode 0, RXRDY is asserted (low) when the receive FIFO is not empty; it is released (high) when the FIFO
is empty. In this way, the receiver FIFO is read when RXRDY is asserted (low).
In mode 1, RXRDY is asserted (low) when the receive FIFO has filled to the trigger level or a character time-out
has occurred (four character times with no transmission of characters); it is released (high) when the FIFO is
empty. In this mode, many received characters are read by the DMA device, reducing the number of times it
is interrupted.
RXRDY and TXRDY outputs from each of the four internal ACEs of the TL16C554A are ANDed together
internally. This combined signal is brought out externally to RXRDY and TXRDY.
Following the removal of the reset condition (RESET low), the ACE remains in the idle mode until programmed.
A hardware reset of the ACE sets the THRE and TEMT status bits in the LSR. When interrupts are subsequently
enabled, an interrupt occurs due to THRE. A summary of the effect of a reset on the ACE is given in Table 13.
Table 13. RESET Effects on Registers and Signals
REGISTER/SIGNAL
RESET CONTROL
RESET STATE
Interrupt-enable register
Reset
All bits cleared (0 −3 forced and 4 −7 permanent)
Interrupt-identification register
Reset
Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared,
Bits 4 −5 are permanently cleared
Line-control register
Reset
All bits cleared
Modem-control register
Reset
All bits cleared (5 −7 permanent)
FIFO-control register
Reset
All bits cleared
Line-status register
Reset
All bits cleared, except bits 5 and 6 are set
Modem-status register
Reset
Bits 0 −3 cleared, bits 4 −7 input signals
TXx
Reset
High
Interrupt (RCVR ERRS)
Read LSR/reset
Low
Interrupt (receiver data ready)
Read RBR/reset
Low
Read IIR/write THR/reset
Low
Read MSR/reset
Low
RTS
Reset
High
DTR
Reset
High
Interrupt (THRE)
Interrupt (modem status changes)
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TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
PRINCIPLES OF OPERATION
scratchpad register
The scratchpad register is an 8-bit read/write register that has no effect on any ACE channel. It is intended to
be used by the programmer to hold data temporarily.
TXRDY operation
In mode 0, TXRDY is asserted (low) when the transmit FIFO is empty; it is released (high) when the FIFO
contains at least one byte. In this way, the FIFO is written with 16 bytes when TXRDY is asserted (low).
In mode 1, TXRDY is asserted (low) when the transmit FIFO is not full; in this mode, the transmit FIFO is written
with another byte when TXRDY is asserted (low).
VCC
Driver
VCC
XTAL1
External
Clock
XTAL1
C1
Crystal
RP
Optional
Driver
Optional
Clock
Output
RX2
Oscillator Clock
to Baud
Generator Logic
XTAL2
Oscillator Clock
to Baud
Generator Logic
XTAL2
C2
TYPICAL CRYSTAL OSCILLATOR NETWORK
CRYSTAL
RP
RX2
C1
C2
3.1 MHz
1 MΩ
1.5 kΩ
10 − 30 pF
40 − 60 pF
1.8 MHz
1 MΩ
1.5 kΩ
10 −30 pF
40 −60 pF
Figure 24. Typical Clock Circuits
36
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TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
Revision History
DATE
REV
PAGE
02 JUNE 2010
E
7
23 FEB 2010
C
37
25 AUG 2005
B
1
29 JUL 2003
A
Changes unknown
01 AUG 2001
*
Original version
NOTE:
SECTION
terminal functions table
DESCRIPTION
Added pin numbers to PN package
48-pin PM package drawing and terminal function descriptions were added for
the new TL16C554APM device
features
Added voltage information to Up to 16−MHZ Clock Rate ....
Page numbers for previous revisions may differ from page numbers in the current version.
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37
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
Revision History
DATE
REV
PAGE
3/2/06
B
21
—
Near middle of page, changed
—
—
Changed from Product Preview to Production Data.
—
Typical Characteristics
Added Typical Characteristics.
1
Description
Split first paragraph into two and started second paragraph on next column to
improve flow.
3, 4
5, 6
7, 8
2/25/05
A
SECTION
Electrical Characteristics
(+5V)
Electrical Characteristics
(+3.3V)
DESCRIPTION
(FCR0 = 1, IER = 1). to (FCR0 =1, IER1 = 1).
Changed condition note to refer to placeholder Figure XXX.
Changed condition note to refer to placeholder Figure X.
Changed condition note to refer to placeholder Figure XX.
Changed part number in Figures 6 and 10 to read OPA2832.
9 10
9,
10
Changed condition note to refer to placeholder Figure X.
13, 14
Changed part number in Figures 29, 32, and 34 to read OPA2832.
Typical Characteristics
(+3.3V)
Changed part number in Figure 49 to read OPA2832.
Global
Product Preview information.
Front Page Diagram
Added image title.
Logo
Changed logo from TI to Burr-Brown Products from Texas Instruments
Front Page Diagram
Added the word “Chebyshev” to diagram title.
Features
Changed 350V/ns to 350V/μs in sixth bullet.
2
Pin Out
Changed pin out drawing.
3
Electrical Characteristics
(±5V)
7, 8
Electrical Characteristics
(+3.3V)
17, 18
See
Note
1
*
Added note “One Channel Only” to Figure 11.
12−15
17
2/8/05
Changed condition note to refer to placeholder Figure XXX.
Typical
T
i l Ch
Characteristics
t i ti
(+5V)
Changed condition note to refer to placeholder Figure XX.
Added em-dash (—) to +25°C column of Input Bias Current Drift line under DC
Performance section of table.
Changed columns 2, 3, 4, 5, 7, and 9 to eliminate unnatural breaks in table and
improve appearance.
Deleted unnecessary sixth column of table.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
38
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TL16C554AFN
ACTIVE
PLCC
FN
68
18
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
TL16C554A
TL16C554AFNG4
ACTIVE
PLCC
FN
68
18
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
TL16C554A
TL16C554AFNR
ACTIVE
PLCC
FN
68
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
TL16C554A
TL16C554AIFN
ACTIVE
PLCC
FN
68
18
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TL16C554AI
TL16C554AIFNR
ACTIVE
PLCC
FN
68
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TL16C554AI
TL16C554AIPN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TL16C554AI
TL16C554AIPNG4
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TL16C554AI
TL16C554AIPNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TL16C554AI
TL16C554APN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
TL16C554A
TL16C554APNG4
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
TL16C554A
TL16C554APNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
TL16C554A
TL16CP554AIPM
ACTIVE
LQFP
PM
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TL16CP554AIPM
TL16CP554APM
ACTIVE
LQFP
PM
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
TL16CP554APM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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