TL16C750PM

TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 D D D D D D D D D D D D D Pin-to-Pin Compatible With the Existing TL16C550B/C Programmable 16- or 64-Byte FIFOs to Reduce CPU Interrupts Programmable Auto-RTS and Auto-CTS In Auto-CTS Mode, CTS Controls Transmitter In Auto-RTS Mode, Receiver FIFO Contents and Threshold Control RTS Serial and Modem Control Outputs Drive a RJ11 Cable Directly When Equipment Is on the Same Power Drop Capable of Running With All Existing TL16C450 Software After Reset, All Registers Are Identical to the TL16C450 Register Set Up to 16-MHz Clock Rate for Up to 1-Mbaud Operation In the TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data Programmable Baud Rate Generator Allows Division of Any Input Reference Clock by 1 to (216 – 1) and Generates an Internal 16 × Clock Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added or Deleted to or From the Serial Data Stream 5-V and 3-V Operation D D D D D D D D D D D D D Register Selectable Sleep Mode and Low-Power Mode Independent Receiver Clock Input Independently Controlled Transmit, Receive, Line Status, and Data Set Interrupts Fully Programmable Serial Interface Characteristics: – 5-, 6-, 7-, or 8-Bit Characters – Even-, Odd-, or No-Parity Bit Generation and Detection – 1-, 1 1/2-, or 2-Stop Bit Generation – Baud Generation (DC to 1 Mbits Per Second) False Start Bit Detection Complete Status Reporting Capabilities 3-State Output CMOS Drive Capabilities for Bidirectional Data Bus and Control Bus Line Break Generation and Detection Internal Diagnostic Capabilities: – Loopback Controls for Communications Link Fault Isolation – Break, Parity, Overrun, Framing Error Simulation Fully Prioritized Interrupt System Controls Modem Control Functions (CTS, RTS, DSR, DTR, RI, and DCD) Available in 44-Pin PLCC and 64-Pin SQFP Industrial Temperature Range Available for 64-Pin SQFP description The TL16C750 is a functional upgrade of the TL16C550C asynchronous communications element (ACE), which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up (character or TL16C450 mode), the TL16C750, like the TL16C550C, can be placed in an alternate mode (FIFO mode). This relieves the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 64 bytes including three additional bits of error status per byte for the receiver FIFO. The user can choose between a 16-byte FIFO mode or an extended 64-byte FIFO mode. In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software overload and increase system efficiency by automatically controlling serial data flow through the RTS output and the CTS input signals (see Figure 1). The TL16C750 performs serial-to-parallel conversion on data received from a peripheral device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read the ACE status at any time. The ACE includes complete modem control capability and a processor interrupt system that can be tailored to minimize software management of the communications link. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 description (continued) The TL16C750 ACE includes a programmable baud rate generator capable of dividing a reference clock by divisors from 1 to (216 – 1) and producing a 16 × reference clock for the internal transmitter logic. Provisions are also included to use this 16 × clock for the receiver logic. The ACE accommodates a 1-Mbaud serial rate (16-MHz input clock) so a bit time is 1 µs and a typical character time is 10 µs (start bit, 8 data bits, stop bit). Two of the TL16C450 terminal functions have been changed to TXRDY and RXRDY, which provide signaling to a direct memory access (DMA) controller. D4 D3 D2 D1 D0 NC VCC RI DCD DSR CTS FN PACKAGE (TOP VIEW) 6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 17 29 18 19 20 21 22 23 24 25 26 27 28 MR OUT1 DTR RTS OUT2 NC INTRPT RXRDY A0 A1 A2 XIN XOUT WR1 WR2 VSS NC RD1 RD2 DDIS TXRDY ADS D5 D6 D7 RCLK SIN NC SOUT CS0 CS1 CS2 BAUDOUT 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A2 A1 NC A0 RXRDY NC INTRPT NC OUT2 RTS NC DTR NC OUT1 NC MR XIN XOUT NC WR1 NC WR2 NC VSS RD1 RD2 NC DDIS TXRDY NC ADS NC D6 D5 NC BAUDOUT NC CS2 CS1 NC CS0 SOUT NC NC SIN RCLK NC D7 PM PACKAGE (TOP VIEW) NC – No internal connection 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D4 NC D3 D2 NC D1 D0 NC VCC NC RI NC DCD DSR NC CTS TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 functional block diagram Internal Data Bus 9–2 D(7 – 0) 8 Data Bus Buffer S e l e c t Receiver FIFO 8 Receiver Shift Register Receiver Buffer Register A1 A2 CS0 CS1 CS2 ADS MR RD1 RD2 WR1 WR2 DDIS TXRDY XIN SIN 10 Receiver Timing and Control Line Control Register A0 11 RCLK 36 RTS 31 30 29 Divisor Latch (LS) 14 Divisor Latch (MS) Baud Generator 17 15 16 28 39 24 25 Transmitter Timing and Control Line Status Register Select and Control Logic Transmitter FIFO Transmitter Holding Register 20 21 8 S e l e c t 8 Transmitter Shift Register BAUDOUT Autoflow Control Enable (AFE) 13 SOUT 26 Modem Control Register 27 18 8 40 37 XOUT 19 32 RXRDY Modem Status Register 8 Modem Control Logic 41 42 43 VCC 44 22 VSS 38 Power Supply Interrupt Enable Register Interrupt Identification Register 8 Interrupt Control Logic CTS DTR DSR DCD RI OUT1 35 OUT2 33 INTRPT 8 FIFO Control Register NOTE A: Terminal numbers shown are for the FN package. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 Terminal Functions TERMINAL NO. FN NO. PM I/O DESCRIPTION A0 A1 A2 31 30 29 20 18 17 I Register select. A0 – A2 are used during read and write operations to select the ACE register to read from or write to. Refer to Table 1 for register addresses and ADS signal description. ADS 28 15 I Address strobe. When ADS is active (low), the register select signals (A0, A1, and A2) and chip select signals (CS0, CS1, CS2) drive the internal select logic directly; when ADS is high, the register select and chip select signals are held at the logic levels they were in when the low-to-high transition of ADS occurred. BAUDOUT 17 64 O Baud out. BAUDOUT is a 16 × clock signal for the transmitter section of the ACE. The clock rate is established by the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches. BAUDOUT can also be used for the receiver section by tying this output to RCLK. CS0 CS1 CS2 14 15 16 59 61 62 I Chip select. When CS0 and CS1 are high and CS2 is low, the ACE is selected. When any of these inputs are inactive, the ACE remains inactive. Refer to the ADS signal description. CTS 40 33 I Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem status register. Bit 0 (∆CTS) of the modem status register indicates that CTS has changed states since the last read from the modem status register. When the modem status interrupt is enabled, CTS changes states, and the auto-CTS mode is not enabled, an interrupt is generated. CTS is also used in the auto-CTS mode to control the transmitter. D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 42 43 45 46 48 50 51 52 I/O Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status information between the ACE and the CPU. As inputs, they use fail safe CMOS compatible input buffers. DCD 42 36 I Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the modem status register. Bit 3 (∆DCD) of the modem status register indicates that DCD has changed states since the last read from the modem status register. When the modem status interrupt is enabled and DCD changes state, an interrupt is generated. DDIS 26 12 O Driver disable. DDIS is active (high) when the CPU is not reading data. When active, DDIS can disable an external transceiver. DSR 41 35 I Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the modem status register. Bit 1 (∆DSR) of the modem status register indicates DSR has changed states since the last read from the modem status register. When the modem status interrupt is enabled and the DSR changes states, an interrupt is generated. DTR 37 28 O Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish communication. DTR is placed in the active state by setting the DTR bit of the modem control register to one. DTR is placed in the inactive condition either as a result of a master reset, during loop mode operation, or clearing the DTR bit. INTRPT 33 23 O Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. Four conditions that cause an interrupt to be issued are: a receiver error, received data that is available or timed out (FIFO mode only), an empty transmitter holding register, or an enabled modem status interrupt. INTRPT is reset (deactivated) either when the interrupt is serviced or as a result of a master reset. MR 39 32 I Master reset. When active (high), MR clears most ACE registers and sets the levels of various output signals (refer to Table 2). OUT1 OUT2 38 35 30 25 O Outputs 1 and 2. These are user-designated output terminals that are set to their active (low) level by setting their respective modem control register (MCR) bits (OUT1 and OUT2). OUT1 and OUT2 are set to their inactive (high) level as a result of master reset, during loop mode operations, or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the MCR. RCLK 10 54 I Receiver clock. RCLK is the 16× baud rate clock for the receiver section of the ACE. NAME 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 Terminal Functions (Continued) TERMINAL NO. FN NO. PM I/O DESCRIPTION RD1 RD2 24 25 9 10 I Read inputs. When either RD1 or RD2 is active (low or high respectively) while the ACE is selected, the CPU is allowed to read status information or data from a selected ACE register. Only one of these inputs is required for the transfer of data during a read operation; the other input should be tied in its inactive state (i.e., RD2 tied low or RD1 tied high). RI 43 38 I Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the modem status register. Bit 2 (TERI) of the modem status register indicates that RI has transitioned from a low to a high level since the last read from the modem status register. If the modem status interrupt is enabled when this transition occurs, an interrupt is generated. RTS 36 26 O Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive data. RTS is set to its active level by setting the RTS MCR bit and is set to its inactive (high) level either as a result of a master reset, during loop mode operations, or by clearing bit 1 (RTS) of the MCR. In the auto-RTS mode, RTS is set to its inactive level by the receiver threshold control logic. RXRDY 32 21 O Receiver ready. Receiver direct memory access (DMA) signalling is available with RXRDY. When operating in the FIFO mode, one of two types of DMA signalling can be selected through the FIFO control register bit 3 (FCR3). When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the receiver FIFO has been emptied. In DMA mode 0 (FCR0 = 0 or FCR0 = 1, FCR3 = 0), when there is at least one character in the receiver FIFO or receiver holding register, RXRDY is active (low). When RXRDY has been active but there are no characters in the FIFO or holding register, RXRDY goes inactive (high). In DMA mode 1 (FCR0 = 1, FCR3 = 1), when the trigger level or the timeout has been reached, RXRDY goes active (low); when it has been active but there are no more characters in the FIFO or holding register, it goes inactive (high). SIN 11 55 I Serial data. SIN is the input from a connected communications device. SOUT 13 58 O Composite serial data output to a connected communication device. SOUT is set to the marking (high) level as a result of master reset. TXRDY 27 13 O Transmitter ready. Transmitter DMA signalling is available with TXRDY. When operating in the FIFO mode, one of two types of DMA signalling can be selected through FCR3. When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the transmit FIFO has been filled. VCC VSS 44 40 22 8 WR1 WR2 20 21 4 6 I XIN XOUT 18 19 1 2 I/O NAME 5-V supply voltage Supply common Write inputs. When either input is active (low or high respectively) and while the ACE is selected, the CPU is allowed to write control words or data into a selected ACE register. Only one of these inputs is required to transfer data during a write operation; the other input should be tied in its inactive state (i.e., WR2 tied low or WR1 tied high). External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal). detailed description autoflow control Auto-flow control is composed of auto-CTS and auto-RTS. With auto-CTS, CTS must be active before the transmit FIFO can emit data (see Figure 1). With auto-RTS, RTS becomes active when the receiver is empty or the threshold has not been reached. When RTS is connected to CTS, data transmission does not occur unless the receive FIFO has empty space. Thus, overrun errors are eliminated when ACE1 and ACE2 are TLC16C750s with enabled autoflow control. If not, overrun errors occur if the transmit data rate exceeds the receive FIFO read latency. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 autoflow control (continued) ACE1 ACE2 Serial to Parallel RCV FIFO Flow Control SIN SOUT CTS RTS Parallel to Serial XMT FIFO Flow Control D7– D0 D7– D0 Parallel to Serial XMT FIFO Flow Control SOUT SIN RTS CTS Serial to Parallel RCV FIFO Flow Control Figure 1. Autoflow Control (auto-RTS and auto-CTS) Example auto-RTS (see Figure 1) Auto-RTS data flow control originates in the receiver timing and control block (see functional block diagram) and is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level of 1, 4, 8, or 14 in 16-byte mode or 1, 16, 32, or 56 in 64-byte mode, RTS is deasserted. The sending ACE may send an additional byte after the trigger level is reached (assuming the sending ACE has another byte to send) because it may not recognize the deassertion of RTS until after it has begun sending the additional byte. RTS is automatically reasserted once the receiver FIFO is emptied by reading the receiver buffer register. The reassertion signals the sending ACE to continue transmitting data. auto-CTS (see Figure 1) The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, the transmitter sends the next byte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the last stop bit that is currently being sent. The auto-CTS function reduces interrupts to the host system. When flow control is enabled, the CTS state changes and does not trigger host interrupts because the device automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the transmit FIFO and a receiver overrun error can result. enabling auto-RTS and auto-CTS The auto-RTS and auto-CTS modes of operation are activated by setting bit 5 of the modem control register (MCR) to 1 (see Figure 2). SOUT Start Bits 0 – 7 Stop Start Bits 0 – 7 Stop Start Bits 0 – 7 Stop CTS NOTES: A. When CTS is low, the transmitter keeps sending serial data out. B. When CTS goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte but it does not send the next byte. C. When CTS goes from high to low, the transmitter begins sending data again. Figure 2. CTS Functional Timing 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 enabling auto-RTS and auto-CTS (continued) The receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes for the 16-byte mode and 1, 16, 32, or 56 bytes for 64-byte mode (see Figure 3). SIN Start Byte N Stop Start Byte N+1 Start Stop Byte Stop RTS RD (RD RBR) 1 2 N N+1 NOTES: A. N = receiver FIFO trigger level B. The two blocks in dashed lines cover the case where an additional byte is sent as described in auto-RTS. Figure 3. RTS Functional Timing, Receiver FIFO Trigger Level absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6 V Input voltage range, VI: Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6.5 V Output voltage range, VO: Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6.5 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Operating free-air temperature range, TA (TL16C750I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. This applies for external input and bidirectional buffers. VI > VCC does not apply to fail safe terminals. 2. This applies for external output and bidirectional buffers. VO > VCC does not apply to fail safe terminals. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 recommended operating conditions low voltage (3.3 V nominal) MIN NOM MAX Supply voltage, VCC 3 3.3 3.6 V Input voltage, VI 0 VCC V High-level input voltage, VIH (see Note 3) 0.7 VCC V Low-level input voltage, VIL (see Note 3) Output voltage, VO (see Note 4) UNIT 0 High-level output current, IOH (all outputs) Low-level output current, IOL (all outputs) Input capacitance, cI 0.3 VCC V VCC 1.8 V mA 3.2 mA 1 pF Operating free-air temperature, TA 0 25 70 °C Junction temperature range, TJ (see Note 5) 0 25 115 °C 14 MHz Oscillator/clock speed NOTES: 3. Meets TTL levels, VIHmin = 2 V and VILmax = 0.8 V on nonhysteresis inputs 4. Applies for external output buffers 5. These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150°C. The customer is responsible for verifying junction temperature. standard voltage (5 V nominal) Supply voltage, VCC Input voltage, VI MIN NOM 4.75 5 0 High-level input voltage, VIH MAX UNIT 5.25 V VCC V 0.7 VCC V Low-level input voltage, VIL 0.2 VCC V VCC 4 V mA Low-level output current, IOL (all outputs) 4 mA Input capacitance, cI 1 pF Output voltage, VO (see Note 4) 0 High-level output current, IOH (all outputs) Operating free-air temperature, TA 0 25 70 °C Junction temperature range, TJ (see Note 5) 0 25 115 °C 16 MHz Oscillator/clock speed NOTES: 4. Applies for external output buffers 5. These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150°C. The customer is responsible for verifying junction temperature. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) low voltage (3.3 V nominal) VOH VOL IOZ IIL PARAMETER High-level output voltage† TEST CONDITIONS IOH = – 1.8 mA IOL = 3.2 mA Low-level output voltage† High-impedance 3-state output current (see Note 6) Low-level input current (see Note 7) MIN MAX VCC – 0.55 VI = VCC or GND VI = GND IIH High-level input current (see Note 8) VI = VCC † For all outputs except XOUT NOTES: 6. The 3-state or open-drain output must be in the high-impedance state. 7. Specifications only apply with pullup termination turned off. 8. Specifications only apply with pulldown termination turned off. UNIT V 0.5 V ± 10 µA –1 µA 1 µA standard voltage (5 V nominal) VOH VOL IOZ IIL PARAMETER High-level output voltage† TEST CONDITIONS IOH = – 4 mA IOL = 4 mA Low-level output voltage† High-impedance 3-state output current (see Note 6) Low-level input current (see Note 7) VI = VCC or GND VI = GND IIH High-level input current (see Note 8) VI = VCC † For all outputs except XOUT NOTES: 6. The 3-state or open-drain output must be in the high-impedance state. 7. Specifications only apply with pullup termination turned off. 8. Specifications only apply with pulldown termination turned off. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN MAX VCC – 0.8 UNIT V 0.5 V ± 10 µA –1 µA 1 µA 9 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 system timing requirements over recommended ranges of supply voltage and operating free-air temperature PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS tcR tcW Cycle time, read (tw7 + td8 + td9) RC Cycle time, write (tw6 + td5 + td6) WC tw1 tw2 Pulse duration, clock (XIN) high tXH tXL 4 f = 16 MHz maximum 4 f = 16 MHz maximum tw5 tw6 Pulse duration, ADS low tADS tWR tw7 tw8 Pulse duration, read strobe tsu1 tsu2 Setup time, address valid before ADS↑ tRD tMR tAS tsu3 tsu4† Setup time, data valid before WR1↓ or WR2↑ th1 th2 Hold time, address low after ADS↑ th3 th4† Hold time, CS valid after WR1↑ or WR2↓ th5 th6 th7† Hold time, data valid after WR1↑ or WR2↓ td4† td5 td6† Delay time, CS valid before WR1↓ or WR2↑ td7† td8† Delay time, CS valid to RD1↓ or RD2↑ td9 td10 Delay time, read cycle, RD1↑ or RD2↓ to ADS↓ Pulse duration, clock (XIN) low Pulse duration, write strobe Pulse duration, MR Setup time, CS valid before ADS↑ tCS tDS Setup time, CTS↑ before midpoint of stop bit Hold time, CS valid after ADS↑ Hold time, address valid after WR1↑ or WR2↓ Hold time, CS valid after RD1↑ or RD2↓ Hold time, address valid after RD1↑ or RD2↓ Delay time, address valid before WR1↓ or WR2↑ Delay time, write cycle, WR1↑ or WR2↓ to ADS↓ Delay time, address valid to RD1↓ or RD2↑ Delay time, RD1↓ or RD2↑ to data valid td11 Delay time, RD1↑ or RD2↓ to floating data † Only applies when ADS is low MIN MAX UNIT 87 ns 87 ns 25 ns 25 ns 5, 6 9 ns 5 40 ns 6 40 ns 1 µs 8 ns 5, 6 8 ns 5 15 5, 6 16 ns 10 ns tAH tCH 5, 6 0 ns 5, 6 0 ns tWCS tWA 5 10 ns 5 10 ns tDH 5 5 ns tRCS tRA 6 10 ns 6 20 ns tCSW tAW 5 7 ns 5 7 ns tWC tCSR 5 40 ns 6 7 ns tAR tRC 6 7 ns 40 ns tRVD tHZ 6 CL = 75 pF 45 ns 6 CL = 75 pF 20 ns 6 system switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 9) PARAMETER tdis(R) Disable time, RD1↓↑ or RD2↑↓ to DDIS↑↓ ALT. SYMBOL FIGURE TEST CONDITIONS tRDD 6 CL = 75 pF MIN MAX 20 UNIT ns NOTE 9: Charge and discharge times are determined by VOL, VOH, and external loading. baud generator switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 75 pF PARAMETER tw3 tw4 Pulse duration, BAUDOUT low td1 td2 Delay time, XIN↑ to BAUDOUT↑ 10 Pulse duration, BAUDOUT high Delay time, XIN↑↓ to BAUDOUT↓ ALT. SYMBOL FIGURE TEST CONDITIONS MIN tLW tHW 4 f = 16 MHz, CLK ÷ 2 50 ns 4 f = 16 MHz, CLK ÷ 2 50 ns tBLD tBHD 4 45 ns 4 45 ns POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 commercial maximum switching characteristics, VCC = 4.75 V, TJ = 115°C PARAMETER tPLH tPHL INTRINSIC DELAY (ns) DELTA DELAY (ns/pF) CL = 15 pF CL = 50 pF CL = 85 pF CL = 100 pF – 0.92 0.571 7.65 27.66 47.66 56.23 – 0.79 0.312 3.89 14.83 25.76 30.45 Output rise time, XO 10.86 40.42 69.98 82.65 Output fall time, XO 5.47 20.90 36.34 42.95 FROM (INPUT) TO (OUTPUT) XIN XO tr tf DELAY (ns) commercial maximum switching characteristics, VCC = 3 V, TJ = 115°C PARAMETER tPLH tPHL INTRINSIC DELAY (ns) DELTA DELAY (ns/pF) CL = 15 pF CL = 50 pF CL = 85 pF CL = 100 pF – 4.69 1.017 10.57 46.16 81.75 97.00 – 3.05 0.442 3.58 19.04 34.51 41.13 Output rise time, XO 14.39 64.87 115.35 136.98 Output fall time, XO 5.06 26.53 48.01 57.21 FROM (INPUT) TO (OUTPUT) XIN XO tr tf DELAY (ns) receiver switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 10) PARAMETER ALT. SYMBOL FIGURE td12 Delay time, RCLK to sample clock tSCD 7 TEST CONDITIONS MIN 10 ns td13 Delay time, stop to set receiver error interrupt or read RBR to LSI interrupt or stop to RXRDY↓ tSINT 7, 8, 9, 10, 11 2 RCLK cycle td14 Delay time, read RBR/LSR low to reset interrupt low tRINT 7, 8, 9, 10, 11 CL = 75 pF MAX 120 UNIT ns NOTE 10: In the FIFO mode, the read cycle (RC) = 425 ns (minimum) between reads of the receive FIFO and the status registers (interrupt identification register or line status register). transmitter switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER† ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT td15 Delay time, INTRPT to transmit start tIRS 12 8 24 baudout cycles td16 Delay time, start to interrupt tSTI 12 8 10 baudout cycles td17 Delay time, WR THR to reset interrupt tHR 12 CL = 75 pF ns 34 baudout cycles ns td18 Delay time, initial write to interrupt (THRE) tSI 12 td19 td20 Delay time, read IIR to reset interrupt (THRE) tIR 12 CL = 75 pF 70 tWXI 13, 14 CL = 75 pF 75 ns 9 baudout cycles td21 Delay time, write to TXRDY inactive Delay time, start to TXRDY active tSXA 13, 14 16 50 CL = 75 pF † THRE = transmitter holding register empty, IIR = interrupt identification register. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 modem control switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 75 pF PARAMETER ALT. SYMBOL FIGURE 15 60 ns Delay time, modem interrupt to set interrupt tMDO tSIM 15 35 ns Delay time, RD MSR to reset interrupt tRIM 15 45 ns td22 td23 Delay time, WR MCR to output td24 MIN MAX UNIT td25 Delay time, CTS low to SOUT↓ 16 24 baudout cycles td26 Delay time, receiver threshold byte to RTS↑ 17 2 baudout cycles td27 Delay time, read of last byte in receive FIFO to RTS↓ 17 3 baudout cycles PARAMETER MEASUREMENT INFORMATION N tw1 tw2 XIN td2 td1 BAUDOUT (1/1) td1 td2 BAUDOUT (1/2) tw3 tw4 BAUDOUT (1/3) BAUDOUT (1/N) (N > 3) 2 XIN Cycles (N – 2) XIN Cycles Figure 4. Baud Generator Timing Waveforms 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PARAMETER MEASUREMENT INFORMATION tw5 50% ADS 50% 50% tsu1 th1 A0 – A2 50% 50% Valid † Valid 50% tsu2 th2 CS0, CS1, CS2 50% th3 tw6 td4 td5 WR1, WR2 Valid † Valid 50% th4† td6 50% Active 50% tsu3 th5 Valid Data D7 – D0 † Applicable only when ADS is low Figure 5. Write Cycle Timing Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PARAMETER MEASUREMENT INFORMATION tw5 50% ADS 50% 50% tsu1 th1 A0 – A2 Valid 50% 50% Valid† 50% tsu2 th2 CS0, CS1, CS2 50% Valid td7† td8† RD1, RD2 50% 50% Valid† th6 tw7 th7† td9 Active 50% tdis(R) DDIS 50% tdis(R) 50% 50% td10 td11 Valid Data D7 – D0 † Applicable only when ADS is low Figure 6. Read Cycle Timing Waveforms 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PARAMETER MEASUREMENT INFORMATION RCLK td12 8 Clocks Sample Clock TL16C450 Mode: SIN Start Data Bits 5 – 8 Parity Stop Sample Clock INTRPT (data ready) 50% td13 INTRPT (receiver error) 50% td14 50% 50% RD1, RD2 (read RBR) 50% RD1, RD2 (read LSR) 50% Active Active td14 Figure 7. Receiver Timing Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PARAMETER MEASUREMENT INFORMATION SIN Data Bits 5 – 8 Stop Sample Clock Trigger Level INTRPT (FCR6, 7 = 0, 0) 50% (FIFO at or above trigger level) 50% (FIFO below trigger level) td13 (see Note A) td14 Line Status INTRPT (LSI) 50% 50% td14 RD1 (RD LSR) Active 50% Active RD1 (RD RBR) 50% NOTE A: For a time-out interrupt, td13 = 9 RCLKs. Figure 8. Receive FIFO First Byte (Sets DR Bit) Waveforms SIN Stop Sample Clock Time-Out or Trigger Level INTRPT 50% 50% (FIFO below trigger level) td13 (see Note A) td14 50% Line Status INTRPT (LSI) 50% Top Byte of FIFO td13 td14 RD1, RD2 (RD LSR) RD1, RD2 (RD RBR) (FIFO at or above trigger level) 50% Active 50% 50% Active Previous Byte Read From FIFO NOTE A: For a time-out interrupt, td13 = 9 RCLKs. Figure 9. Receive FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set) Waveforms 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PARAMETER MEASUREMENT INFORMATION RD (RD RBR) 50% Active See Note A SIN (first byte) Stop Sample Clock td13 (see Note B) RXRDY td14 50% 50% NOTES: A. This is the reading of the last byte in the FIFO. B. For a time-out interrupt, td13 = 9 RCLKs. Figure 10. Receiver Ready (RXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0) RD (RD RBR) 50% Active See Note A SIN (first byte that reaches the trigger level) Sample Clock td13 (see Note B) RXRDY td14 50% 50% NOTES: A. This is the reading of the last byte in the FIFO. B. For a time-out interrupt, td13 = 9 RCLKs. Figure 11. Receiver Ready (RXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PARAMETER MEASUREMENT INFORMATION Start 50% SOUT Data Bits Parity td15 INTRPT (THRE) Start 50% Stop td16 50% 50% 50% 50% 50% td18 td17 td17 WR THR 50% 50% 50% td19 RD IIR 50% Figure 12. Transmitter Timing Waveforms WR (WR THR) SOUT Byte #1 50% Data Parity Stop Start 50% td21 td20 TXRDY 50% 50% Figure 13. Transmitter Ready (TXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0) Byte #16 WR (WR THR) SOUT 50% Data Parity Stop td21 td20 TXRDY Start 50% 50% FIFO Full 50% Figure 14. Transmitter Ready (TXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1) 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PARAMETER MEASUREMENT INFORMATION WR (WR MCR) 50% 50% td22 td22 RTS, DTR, OUT1, OUT2 50% 50% 50% CTS, DSR, DCD td23 INTRPT (modem) 50% 50% 50% td24 td23 RD2 (RD MSR) 50% RI 50% Figure 15. Modem Control Timing Waveforms tsu4 CTS 50% 50% td25 SOUT 50% Midpoint of Stop Bit Figure 16. CTS and SOUT Autoflow Control Timing (Start and Stop) Waveforms Midpoint of Stop Bit SIN td26 RTS td27 50% 50% 50% RBRRD Figure 17. Auto-RTS Timing for Receiver Threshold at All Trigger Levels Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PARAMETER MEASUREMENT INFORMATION SOUT D7 – D0 D7 – D0 MEMR or I/OR MEMW or I/ON INTR C P U B U S RESET A0 RD1 RTS WR1 DTR INTRPT DSR MR DCD A0 A1 A1 A2 SIN EIA 232-D Drivers and Receivers CTS TL16C750 (ACE) RI A2 ADS XIN WR2 L 3.072 MHz RD2 CS H CS2 XOUT CS1 BAUDOUT CS0 RCLK Figure 18. Basic TL16C750 Configuration APPLICATION INFORMATION Receiver Disable WR WR1 TL16C750 (ACE) Microcomputer System Data Bus Data Bus 8-Bit Bus Transceiver D7 – D0 DDIS Driver Disable Figure 19. Typical Interface for a High-Capacity Data Bus 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 APPLICATION INFORMATION TL16C750 XIN A16 – A23 A16 – A23 XOUT 18 Alternate Crystal Control 19 17 14 BAUDOUT CS0 Address Decoder CPU 15 16 RCLK CS1 CS2 DTR 28 ADS RTS 36 1 OUT2 35 A0 – A2 AD0 – AD7 D0 – D2 Buffer 43 RI 42 PHI1 20 OUT1 MR AD0 – AD15 37 38 ADS 39 RSI/ABT 10 DCD PHI2 8 41 6 DSR CTS PHI1 ADS PHI2 RSTO RD 24 TCU 20 WR RD1 40 5 13 SOUT 2 WR1 11 SIN INTRPT 3 33 27 AD0 – AD15 TXRDY 25 21 RD2 DDIS WR2 GND (VSS) RXRDY 22 26 32 44 7 1 EIA-232-D Connector 5V (VCC) NOTE A: Terminal numbers shown are for the FN package. Figure 20. Typical TL16C750 Connection to a CPU POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PRINCIPLES OF OPERATION Table 1. Register Selection DLAB† A2 A1 A0 0 L L L Receiver buffer (read), transmitter holding register (write) 0 L L H Interrupt enable register X L H L Interrupt identification register (read only) X L H L FIFO control register (write) X L H H Line control register X H L L Modem control register X H L H Line status register X H H L Modem status register X H H H Scratch register 1 L L L Divisor latch (LSB) REGISTER 1 L L H Divisor latch (MSB) † The divisor latch access bit (DLAB) is the most significant bit of the line control register. The DLAB signal is controlled by writing to this bit location (see Table 3). Table 2. ACE Reset Functions REGISTER/SIGNAL RESET CONTROL RESET STATE Interrupt Enable Register Master Reset All bits cleared (0 – 5 forced and 6 – 7 permanent) Interrupt Identification Register Master Reset Bit 0 is set, bits 1 – 4 are cleared, and bits 5 – 7 are cleared FIFO Control Register Master Reset All bits cleared Line Control Register Master Reset All bits cleared Modem Control Register Master Reset All bits cleared (6 – 7 permanent) Line Status Register Master Reset Bits 5 and 6 are set, all other bits are cleared Modem Status Register Master Reset Bits 0 – 3 are cleared, bits 4 – 7 are input signals SOUT Master Reset High INTRPT (receiver error flag) Read LSR/MR Low INTRPT (received data available) Read RBR/MR Low Read IR/Write THR/MR Low Read MSR/MR Low OUT2 Master Reset High RTS Master Reset High DTR Master Reset High OUT1 Master Reset High Scratch Register Master Reset No effect Divisor Latch (LSB and MSB) Registers Master Reset No effect Receiver Buffer Registers Master Reset No effect Transmitter Holding Registers Master Reset No effect INTRPT (transmitter holding register empty) INTRPT (modem status changes) Receiver FIFO MR/FCR1 – FCR0/ ∆FCR0 All bits cleared XMIT FIFO MR/FCR2 – FCR0/ ∆FCR0 All bits cleared 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PRINCIPLES OF OPERATION accessible registers The system programmer, through the CPU, has access to and control over any of the ACE registers. These registers control ACE operations, receive data, and transmit data. Descriptions of these registers follow in Table 3. Table 3. Summary of Accessible Registers REGISTER ADDRESS Bit No. 0 1 2 3 0 DLAB = 0 0 DLAB = 0 Receiver Buffer Register (Read Only) Transmitter Holding Register (Write Only) RBR Data Bit 0† Data Bit 1 Data Bit 2 Data Bit 3 1 DLAB = 0 2 2 3 4 5 6 7 0 DLAB = 1 1 DLAB = 1 Interrupt Enable Register Interrupt Ident. Register (Read Only) FIFO Control Register (Write Only) Line Control Register Modem Control Register Line Status Register Modem Status Register Scratch Register Divisor Latch (LSB) Latch (MSB) THR IER IIR FCR LCR MCR LSR MSR SCR DLL DLM Data Bit 0 Enable Received Data Available Interrupt (ERBI) 0 when interrupt Pending FIFO Enable Word Length Select Bit 0 (WLS0) Data Terminal Ready (DTR) Data Ready (DR) Delta Clear to Send Bit 0 Bit 0 Bit 8 Enable Transmitter Holding Register Empty Interrupt (ETBEI) Interrupt ID Bit 1 Receiver FIFO Reset Word Length Select Bit 1 (WLS1) Request to Send (RTS) Overrun Error (OE) Bit 1 Bit 1 Bit 9 Data Bit 2 Enable Receiver Line Status Interrupt (ELSI) Interrupt ID Bit 2 Transmitter FIFO Reset Number of Stop Bits (STB) OUT1 Parity Error (PE) Trailing Edge Ring Indicator (TERI) Bit 2 Bit 2 Bit 10 Data Bit 3 Enable Modem Status Interrupt (EDSSI) Interrupt ID Bit 2 (see Note 4) DMA Mode Select Parity Enable (PEN) OUT2 Framing Error (FE) Delta Data Carrier Detect Bit 3 Bit 3 Bit 11 Loop Break Interrupt (BI) Clear to Send (CTS) Bit 4 Bit 4 Bit 12 Data Bit 1 (∆CTS) Delta Data Set Ready (∆DSR) (∆DCD) 4 Data Bit 4 Data Bit 4 Sleep Mode Enable 0 Reserved Even Parity Select (EPS) 5 Data Bit 5 Data Bit 5 Low Power Mode Enable 64 Byte FIFO Enabled 64 Byte FIFO Enable‡ Stick Parity Flow Control Enable (AFE) Transmitter Holding Register (THRE) Data Set Ready (DSR) Bit 5 Bit 5 Bit 13 6 Data Bit 6 Data Bit 6 0 FIFOs Enabled (see Note 11) Receiver Trigger (LSB) Break Control 0 Transmitter Empty (TEMT) Ring Indicator (RI) Bit 6 Bit 6 Bit 14 7 Data Bit 7 Data Bit 7 0 FIFOs Enabled (see Note 11) Receiver Trigger (MSB) Divisor Latch Access Bit (DLAB)‡ 0 Error in Receiver FIFO (see Note 12) Data Carrier Detect (DCD) Bit 7 Bit 7 Bit 15 † Bit 0 is the least significant bit. It is the first bit serially transmitted or received. ‡ Access to DLAB LSB, MSB, and FCR bit 5 require LCR bit 7 = 1 NOTE 11: These bits are always 0 in the TL16C450 mode. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PRINCIPLES OF OPERATION FIFO control register (FCR) The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables the FIFOs, clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signaling. D D D D D D D Bit 0: FCR0 when set enables the transmit and receive FIFOs. This bit must be set when other FCR bits are written to or they are not programmed. Changing this bit clears the FIFOs. Bit 1: FCR1 when set clears all bytes in the receiver FIFO and resets its counter. The RSR is not cleared. The logic 1 that is written to this bit position is self clearing. Bit 2: FCR2 when set clears all bytes in the transmit FIFO and resets its counter to 0. The TSR is not cleared. The logic 1 that is written to this bit position is self clearing. Bit 3: When FCR0 is set, setting FCR3 causes the RXRDY and TXRDY to change from mode 0 to mode 1. Bit 4: Reserved for future use. Bit 5: When this bit is set 64-byte mode of operation is selected. When cleared, the 16-byte mode is selected. A write to FCR bit 5 is protected by setting the line control register (LCR) bit 7 = 1. LCR bit 7 needs to cleared for normal operation. Bits 6 and 7: FCR6 and FCR7 set the trigger level for the receiver FIFO interrupt (see Table 4). Table 4. Receiver FIFO Trigger Level BIT 7 BIT 6 16-BYTE RECEIVER FIFO TRIGGER LEVEL (BYTES) 64-BYTE RECEIVER FIFO TRIGGER LEVEL (BYTES) 0 0 01 01 0 1 04 16 1 0 08 32 1 1 14 56 FIFO interrupt mode operation When the receiver FIFO and receiver interrupts are enabled (FCR0 = 1, IER0 = 1, IER2 = 1), a receiver interrupt occurs as follows: 1. The received data available interrupt is issued to the microprocessor when the FIFO has reached its programmed trigger level. It is cleared when the FIFO drops below its programmed trigger level. 2. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and as the interrupt, is cleared when the FIFO drops below the trigger level. 3. The receiver line status interrupt (IIR = 06 or 0110h) has higher priority than the received data available (IIR = 04) interrupt. 4. The data ready bit (LSR0) is set when a character is transferred from the shift register to the receiver FIFO. It is cleared when the FIFO is empty. When the receiver FIFO and receiver interrupts are enabled: 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PRINCIPLES OF OPERATION FIFO interrupt mode operation (continued) 1. FIFO time-out interrupt occurs when the following conditions exist: a. At least one character is in the FIFO. b. The most recent serial character was received more than four continuous character times ago (if two stop bits are programmed, the second one is included in this time delay). c. The most recent microprocessor read of the FIFO occurred more than four continuous character times ago. This causes a maximum character received to interrupt an issued delay of 160 ms at 300 baud with a 12-bit character. 2. Character times are calculated by using RCLK for a clock signal (makes the delay proportional to the baud rate). 3. When a time-out interrupt has occurred, the FIFO interrupt is cleared. The timer is reset when the microprocessor reads one character from the receiver FIFO. When a time-out interrupt has not occurred, the time-out timer is reset after a new character is received or after the microprocessor reads the receiver FIFO. When the transmitter FIFO and THRE interrupt are enabled (FCR0 = 1, IER1 = 1), transmit interrupts occur as follows: 1. The transmitter holding register interrupt [IIR (3 –0) = 2] occurs when the transmit FIFO is empty. The transmit FIFO is cleared [IIR (3 –0) = 1] when the THR is written to (1 to 16 characters may be written to the transmit FIFO while servicing this interrupt) or the IIR is read. 2. The transmit FIFO empty indicator (LSR5 (THRE) = 1) is delayed one character time minus the last stop bit time when there have not been at least two bytes in the transmit FIFO at the same time since the last time that THRE = 1. The first transmitter interrupt after changing FCR0 is immediate when it is enabled. Character time-out and receiver FIFO trigger level interrupts have the same priority as the current received data available interrupt; transmit FIFO empty has the same priority as the current THRE interrupt. FIFO polled mode operation With FCR0 = 1 (transmitter and receiver FIFOs enabled), clearing IER0, IER1, IER2, IER3, or all four to 0 puts the ACE in the FIFO polled mode of operation. Since the receiver and transmitter are controlled separately, either one or both can be in the polled mode of operation. In this mode, the user program checks receiver and transmitter status using the LSR. As stated previously: • • • • • LSR0 is set when there is at least one byte in the receiver FIFO. LSR (1 – 4) specify which error(s) have occurred. Character error status is handled the same way as when in the interrupt mode; the IIR is not affected since IER2 = 0. LSR5 indicates when the THR is empty. LSR6 indicates that both the THR and TSR are empty. LSR7 indicates whether there are any errors in the receiver FIFO. There is no trigger level reached or time-out condition indicated in the FIFO polled mode. However, the receiver and transmitter FIFOs are still fully capable of holding characters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PRINCIPLES OF OPERATION interrupt enable register (IER) The IER enables each of the five types of interrupts (refer to Table 5) and the INTRPT signal in response to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The contents of this register are summarized in Table3 and are described in the following bulleted list. D D D D D D D Bit 0: When set, this bit enables the received data available interrupt. Bit 1: When set, this bit enables the THRE interrupt. Bit 2: When set, this bit enables the receiver line status interrupt. Bit 3: When set, this bit enables the modem status interrupt. Bit 4: When set, this bit enables sleep mode. The ACE is always awake when there is a byte in the transmitter, activity on the SIN, or when the device is in the loopback mode. The ACE is also awake when either ∆CTS, ∆DSR, ∆DCD, or TERI = 1. Bit 4 must be set to enable sleep mode. Bit 5: When set, this bit enables low-power mode. Low-power mode functions similar to sleep mode. However, this feature powers down the clock to the ACE only, while keeping the oscillator running. Bit 5 must be set to enable low-power mode. Bits 6 and 7: Not used (always cleared) interrupt identification register (IIR) The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with most popular microprocessors. The ACE provides four prioritized levels of interrupts: D D D D Priority 1 – Receiver line status (highest priority) Priority 2 – Receiver data ready or receiver character timeout Priority 3 – Transmitter holding register empty Priority 4 – Modem status (lowest priority) When an interrupt is generated, the IIR indicates that an interrupt is pending and provides the type of interrupt in its three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 3 and described in Table 5. Details on each bit are as follows: D D D D D 26 Bit 0: This bit can be used either in a hardwire prioritized, or polled interrupt system. When this bit is cleared, an interrupt is pending. When bit 0 is set, no interrupt is pending. Bits 1 and 2: Used to identify the highest priority interrupt pending as indicated in Table 3. Bit 3: This bit is always cleared in the TL16C450 mode. In FIFO mode, this bit is set with bit 2 to indicate that a time-out interrupt is pending. Bit 4: Not used (always cleared) Bits 5, 6, and 7: These bits are to verify the FIFO operation. When all 3 bits are cleared, TL16C450 mode is chosen. When bits 6 and 7 are set and bit 5 is cleared, 16-byte mode is chosen. When bits 5, 6, and 7 are set, 64-byte mode is chosen. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PRINCIPLES OF OPERATION interrupt identification register (IIR) (continued) Table 5. Interrupt Control Functions INTERRUPT IDENTIFICATION REGISTER BIT 3 BIT 2 BIT 1 BIT 0 0 0 0 1 PRIORITY LEVEL INTERRUPT TYPE None None INTERRUPT SOURCE INTERRUPT RESET METHOD None None 0 1 1 0 1 Receiver line status Overrun error, parity error, framing error or break interrupt 0 1 0 0 2 Received data available Receiver data available in the TL16C450 mode or trigger level reached in the FIFO mode. Reading the receiver buffer register Reading the receiver buffer register Reading the line status register 1 1 0 0 2 Character time-out indication No characters have been removed from or input to the receiver FIFO during the last four character times, and there is at least one character in it during this time 0 0 1 0 3 Transmitter holding register empty Transmitter holding register empty Reading the interrupt identification register (if source of interrupt) or writing into the transmitter holding register 0 0 0 0 4 Modem status Clear to send, data set ready, ring indicator, or data carrier detect Reading the modem status register line control register (LCR) The system programmer controls the format of the asynchronous data communication exchange through the LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates the need for separate storage of the line characteristics in system memory. The contents of this register are summarized in Table 3 and described in the following bulleted list. D Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character. These bits are encoded as shown in Table 6. Table 6. Serial Character Word Length D BIT 1 BIT 0 WORD LENGTH 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When bit 2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated is dependent on the word length selected with bits 0 and 1. The receiver clocks only the first stop bit, regardless of the number of stop bits selected. The number of stop bits generated, in relation to word length and bit 2, is shown in Table 7. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PRINCIPLES OF OPERATION line control register (LCR) (continued) Table 7. Number of Stop Bits Generated D D D D D BIT 2 WORD LENGTH SELECTED BY BITS 1 AND 2 NUMBER OF STOP BITS GENERATED 0 Any word length 1 1 5 bits 1 1/2 1 6 bits 2 1 7 bits 2 1 8 bits 2 Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in data transmitted between the last data word bit and the first stop bit. In received data, when bit 3 is set, parity is checked. When bit 3 is cleared, no parity is generated or checked. Bit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set, even parity (an even number of logic 1s in the data and parity bits) is selected. When parity is enabled and bit 4 is cleared, odd parity (an odd number of logic 1s) is selected. Bit 5: This is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked as cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set. When bit 5 is cleared, stick parity is disabled. Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition; i.e., a condition where SOUT is forced to the spacing (low) state. When bit 6 is cleared, the break condition is disabled and has no affect on the transmitter logic; it only affects the serial output. Bit 7: This bit is the divisor latch access bit (DLAB). Bit 7 must be set to access the divisor latches of the baud generator during a read or write or access bit 5 of the FCR. Bit 7 must be cleared during a read or write to access the receiver buffer, the THR, or the IER. line status register (LSR)† The LSR provides information to the CPU concerning the status of data transfers. The contents of this register are described in the following bulleted list and summarized in Table 3. D Bit 0: This bit is the data ready (DR) indicator for the receiver. DR is set when a complete incoming character is received and transferred into the RBR or the FIFO. DR is cleared by reading all of the data in the RBR or the FIFO. D Bit 1‡: This bit is the overrun error (OE) indicator. When OE is set, it indicates that before the character in the RBR was read, it was overwritten by the next character transferred into the register. OE is cleared every time the CPU reads the contents of the LSR. When the FIFO mode data continues to fill the FIFO beyond the trigger level, an OE occurs only after the FIFO is full and the next character has been completely received in the shift register. An OE is indicated to the CPU as soon as it happens. The character in the shift register is overwritten, but it is not transferred to the FIFO. D Bit 2‡: This bit is the parity error (PE) indicator. When PE is set, it indicates that the parity of the received data character does not match the parity selected in the LCR (bit 4). PE is cleared every time the CPU reads the contents of the LSR. In the FIFO mode, PE is associated with the particular character in the FIFO to which it applies. PE is revealed to the CPU when its associated character is at the top of the FIFO. † The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment. ‡ Bits 1 through 4 are the error conditions that produce a receiver line status interrupt. 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PRINCIPLES OF OPERATION line status register (LSR)† (continued) D D D D D Bit 3‡: This bit is the framing error (FE) indicator. When FE is set, it indicates that the received character does not have a valid (set) stop bit. FE is cleared every time the CPU reads the contents of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies. FE is revealed to the CPU when its associated character is at the top of the FIFO. The ACE tries to resynchronize after a FE. To accomplish this, it is assumed that the FE is due to the next start bit. The ACE samples this start bit twice and then accepts the input data. Bit 4: This bit is the break interrupt (BI) indicator. When BI is set, it indicates that the received data input was held in the low state for longer than a full-word transmission time. A full-word transmission time is defined as the total time to transmit the start, data, parity, and stop bits. BI is cleared every time the CPU reads the contents of the LSR. In the FIFO mode, BI is associated with the particular character in the FIFO to which it applies. BI is revealed to the CPU when its associated character is at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character transfer is enabled after SIN goes to the marking state for at least two RCLK samples and then receives the next valid start bit. Bit 5: This bit is the transmitter holding register empty (THRE) indicator. THRE is set when the THR is empty, indicating that the ACE is ready to accept a new character. If the THRE interrupt is enabled when THRE is set, an interrupt is generated. THRE is set when the contents of the THR are transferred to the TSR. THRE is cleared concurrent with the loading of the THR by the CPU. In the FIFO mode, THRE is set when the transmit FIFO is empty; it is cleared when at least one byte is written to the transmit FIFO. Bit 6: This bit is the transmitter empty (TEMT) indicator. TEMT bit is set when the THR and the TSR are both empty. When either the THR or the TSR contains a data character, TEMT is cleared. In the FIFO mode, TEMT is set when the transmitter FIFO and TSR are both empty. Bit 7: In TL16C750 mode and in TL16C450 mode, this bit is always cleared. In the FIFO mode, LSR7 is set when there is at least one parity, framing, or break error in the FIFO. It is cleared when the microprocessor reads the LSR and there are no subsequent errors in the FIFO. modem control register (MCR) The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is emulating a modem. The contents of this register are summarized in Table 3 and are described in the following bulleted list. D D D D Bit 0: This bit (DTR) controls the DTR output. Bit 1: This bit (RTS) controls RTS output. Bit 2: This bit (OUT1) controls OUT1 signal. Bit 3: This bit (OUT2) controls the OUT2 signal. When any of bits 0 through 3 is set, the associated output is forced low; a cleared bit forces the associated output high. † The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment. ‡ Bits 1 through 4 are the error conditions that produce a receiver line status interrupt. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PRINCIPLES OF OPERATION modem control register (MCR) (continued) D D Bit 4: This bit (LOOP) provides a local loop back feature for diagnostic testing of the ACE. When LOOP is set, the following occurs: – SOUT is asserted high. – SIN is disconnected. – The output of the TSR is looped back into the RSR input. – The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected. – The four modem control outputs (DTR, RTS, OUT1, and OUT2) are internally connected to the four modem control inputs. – The four modem control outputs are forced to their inactive (high) states. Bit 5: This bit (AFE) is the autoflow control enable. When bit 5 is set, the autoflow control, as described in the detailed description, is enabled. In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify the transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational. The modem control interrupts are also operational, but the modem control interrupt sources are now the lower four bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the IER. The ACE flow can be configured by programming bits 1 and 5 of the MCR as shown in Table 8. Table 8. ACE Flow Configuration MCR BIT 5 (AFE) MCR BIT 1 (RTS) ACE FLOW CONFIGURATION 1 1 Auto-RTS and auto-CTS enabled (autoflow control enabled) 1 0 Auto-CTS only enabled 0 X Auto-RTS and auto-CTS disabled When bit 5 of the FCR is cleared, there is a 16-byte AFC. When bit 5 of the FCR is set, there is a 64-byte AFC. modem status register (MSR) The MSR is an 8-bit register that provides information about the current state of the control lines from the modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide change information. When a control input from the modem changes state, the appropriate bit is set. All four bits are cleared when the CPU reads the MSR. The contents of this register are summarized in Table 3 and are described in the following bulleted list. 30 D Bit 0: This bit is the change in clear-to-send (∆ CTS) indicator. ∆ CTS indicates that CTS has changed states since the last time it was read by the CPU. When ∆ CTS is set (autoflow control is not enabled and the modem status interrupt is enabled), a modem status interrupt is generated. When autoflow control is enabled, no interrupt is generated. When ∆CTS is set, sleep or low-power modes are avoided. D Bit 1: This bit is the change in data set ready (∆ DSR) indicator. ∆ DSR indicates that DSR has changed states since the last time it was read by the CPU. When ∆ DSR is set and the modem status interrupt is enabled, a modem status interrupt is generated. When ∆DSR is set, the sleep or low-power modes are avoided. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PRINCIPLES OF OPERATION modem status register (MSR) (continued) D D D D D D Bit 2: This bit is the trailing edge of the ring indicator (TERI) detector. TERI indicates that RI to the chip has changed from a low to a high level. When TERI is set and the modem status interrupt is enabled, a modem status interrupt is generated. When TERI is set, sleep or low-power modes are avoided. Bit 3: This bit is the change in data carrier detect (∆ DCD) indicator. ∆ DCD indicates that DCD to the chip has changed states since the last time it was read by the CPU. When ∆ DCD is set and the modem status interrupt is enabled, a modem status interrupt is generated. When ∆DCD is set, sleep or low-power modes are avoided. Bit 4: This bit is the complement of CTS. When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 1 (RTS). Bit 5: This bit is the complement of DSR input. When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 0 (DTR). Bit 6: This bit is the complement of RI. When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 2 (OUT1). Bit 7: This bit is the complement of DCD. When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 3 (OUT2). programmable baud generator The ACE contains a programmable baud generator that takes a clock input in the range between dc and 16 MHz and divides it by a divisor in the range between 1 and (216 –1). The output frequency of the baud generator is 16 × the baud rate. The formula for the divisor is: divisor = XIN frequency input ÷ (desired baud rate × 16) Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must be loaded during initialization of the ACE to ensure desired operation of the baud generator. When either of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load. Tables 9 and 10 illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz and 3.072 MHz respectively. For baud rates of 38.4 kbits/s and below, the error obtained is very small. The accuracy of the selected baud rate is dependent on the selected crystal frequency (see Figure 21). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PRINCIPLES OF OPERATION programmable baud generator (continued) Table 9. Baud Rates Using a 1.8432-MHz Crystal DESIRED BAUD RATE DIVISOR USED TO GENERATE 16 × CLOCK PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL 50 2304 75 1536 110 1047 0.026 134.5 857 0.058 150 768 300 384 600 192 1200 96 1800 64 2000 58 2400 48 3600 32 4800 24 7200 16 9600 12 19200 6 38400 3 56000 2 0.69 2.86 Table 10. Baud Rates Using a 3.072-MHz Crystal DESIRED BAUD RATE 32 DIVISOR USED TO GENERATE 16 × CLOCK 50 3840 PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL 75 2560 110 1745 0.026 134.5 1428 0.034 150 1280 300 640 600 320 1200 160 1800 107 2000 96 2400 80 3600 53 4800 40 7200 27 9600 20 19200 10 38400 5 POST OFFICE BOX 655303 0.312 0.628 1.23 • DALLAS, TEXAS 75265 TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997 PRINCIPLES OF OPERATION programmable baud generator (continued) VCC VCC Driver XIN XIN External Clock C1 Crystal RP Optional Driver Optional Clock Output RX2 Oscillator Clock to Baud Generator Logic XOUT Oscillator Clock to Baud Generator Logic XOUT C2 TYPICAL CRYSTAL/ OSCILLATOR NETWORK CRYSTAL RP 1 MΩ RX2 C1 C2 3.072 MHz 1.5 kΩ 10 – 30 pF 40 – 60 pF 1.8432 MHz 1 MΩ 1.5 kΩ 10 – 30 pF 40 – 60 pF Figure 21. Typical Clock Circuits receiver buffer register (RBR) The ACE receiver section consists of a RSR and a RBR. The RBR is actually a 64-byte FIFO. Timing is supplied by the 16× receiver clock (RCLK). Receiver section control is a function of the ACE line control register. The ACE RSR receives serial data from the SIN terminal. The RSR then deserializes the data and moves it into the RBR FIFO. In the TL16C450 mode, when a character is placed in the RBR and the received data available interrupt is enabled, an interrupt is generated. This interrupt is cleared when the data is read out of the RBR. In the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register. scratch register The scratch register is an 8-bit register used by the programmer as a scratchpad that temporarily holds the programmer data without affecting any other ACE operation. transmitter holding register (THR) The ACE transmitter section consists of a THR and a transmitter shift register (TSR). The THR is actually a 64-byte FIFO. Timing is supplied by the baud out (BAUDOUT) clock signal. Transmitter section control is a function of the ACE line control register. The ACE THR receives data off the internal data bus and when the shift register is idle, moves it into the TSR. The TSR serializes the data and outputs it at the SOUT terminal. In the TL16C450 mode, when the THR is empty and the transmitter holding register empty (THRE) interrupt is enabled (IER1 = 1), an interrupt is generated. This interrupt is cleared when a character is loaded into the register. In the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 33 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) TL16C750FN ACTIVE PLCC FN 44 26 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 TL16C750FN TL16C750FNR ACTIVE PLCC FN 44 500 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 TL16C750FN TL16C750PM ACTIVE LQFP PM 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 TL16C750PM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of