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TL16C752CI-Q1
SLLSEQ9A – OCTOBER 2015 – REVISED FEBRUARY 2016
TL16C752CI-Q1 Dual UART With 64-Byte FIFO
1 Features
•
•
1
•
•
•
•
•
•
•
•
•
Q100 Automotive Qualified
SC16C752B and XR16M752 Pin Compatible With
Additional Enhancements
Support 1.8-V, 2.5-V, 3.3-V, or 5-V Supply
Characterized for Operation from –40°C to
+105°C
Supports up to:
– 48-MHz Oscillator Input Clock (3 Mbps) for 5-V
Operation
– 32-MHz Oscillator Input Clock (2 Mbps) for
3.3-V Operation
– 24-MHz Input Clock (1.5 Mbps) for 2.5-V
Operation
– 16-MHz Input Clock (1 Mbps) for 1.8-V
Operation
64-Byte Transmit/Receive FIFO
Software-Selectable Baud-Rate Generator
Programmable and Selectable Transmit and
Receive FIFO Trigger Levels for DMA, Interrupt
Generation, and Software or Hardware Flow
Control
Software/Hardware Flow Control
– Programmable Xon and Xoff Characters With
Optional Xon Any Character
– Programmable Auto-RTS and Auto-CTSModem Control Functions (CTS, RTS, DSR,
DTR, RI, and CD)
DMA Signaling Capability for Both Received and
Transmitted Data on PN Package
RS-485 Mode Support
•
•
•
•
•
Infrared Data Association (IrDA) Capability
Programmable Sleep Mode
Programmable Serial Interface Characteristics
– 5, 6, 7, or 8-Bit Characters With 1, 1.5, or 2
Stop Bit Generation
– Even, Odd, or No Parity Bit Generation and
Detection
False Start Bit and Line Break Detection
Internal Test and Loopback Capabilities
2 Applications
•
•
•
•
•
•
GPS Systems
Ethernet Network Routers
Infrared Transceivers
Domestic Applications
Portable Applications
Factory Automation and Process Control
3 Description
The
TL16C752CI-Q1
is
a
dual
universal
asynchronous receiver transmitter (UART) with 64byte FIFOs, automatic hardware and software flow
control, and data rates up to 3 Mbps. The device
offers enhanced features. It has a transmission
Character control register (TCR) that stores received
FIFO threshold level to start or stop transmission
during hardware and software flow control.
Device Information(1)
PART NUMBER
TL16C752CI-Q1
PACKAGE
TQFP (48)
BODY SIZE (NOM)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Block Diagram
UART Channel A
A2 to A0
D7 to D0
CSA
64-Byte TX FIFO
UART Regs
CSB
IOR
IOW
INTA
INTB
TXRDYA
TXRDYB
RXRDYA
RXRDYB
TX
Baud
Rate
64-Byte RX FIFO
Generator
DSRA, RIA, CDA
RTSA
RX
RXA
Data Bus
Interface
UART Channel B
64-Byte TX FIFO
TX
UART Regs
RESET
XTAL1
XTAL2
TXA
CTSA
OPA, DTRA
Baud
Rate
64-Byte RX FIFO
Generator
Crystal
Oscillator
Buffer
TXB
CTSB
OPB, DTRB
DSRB, RIB, CDB
RTSB
RX
RXB
VCC
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TL16C752CI-Q1
SLLSEQ9A – OCTOBER 2015 – REVISED FEBRUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configurations and Function .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
1
1
1
2
3
4
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 8
Electrical Characteristics........................................... 8
Timing Requirements .............................................. 10
Typical Characteristics ............................................ 14
Detailed Description ............................................ 16
8.1 Overview ................................................................. 16
8.2 Functional Block Diagram ....................................... 16
8.3 Feature Description................................................. 17
8.4 Device Functional Modes........................................ 27
8.5 Register Maps ......................................................... 29
9
Application and Implementation ........................ 45
9.1 Application Information............................................ 45
9.2 Typical Application .................................................. 45
10 Power Supply Recommendations ..................... 48
11 Layout................................................................... 48
11.1 Layout Guidelines ................................................. 48
11.2 Layout Example .................................................... 49
12 Device and Documentation Support ................. 50
12.1
12.2
12.3
12.4
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
50
50
50
50
13 Mechanical, Packaging, and Orderable
Information ........................................................... 50
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (October 2015) to Revision A
Page
•
Changed the operating temperature range from –40°C to 85°C to –40°C to +105°C ........................................................... 1
•
Changed the Device Information table Body Size column From: 3.67 mm x 3.67 mm To: 7.00 mm x 7.00 mm ................. 1
•
Changed NC pin number 35 to 25 ........................................................................................................................................ 5
•
Changed the CDM value from ±500 to ±1000 ....................................................................................................................... 6
2
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SLLSEQ9A – OCTOBER 2015 – REVISED FEBRUARY 2016
5 Description (continued)
With the FIFO RDY register, the software gets the status of TXRDY or RXRDY for all two ports in one access.
On-chip status registers provide the user with error indications, operational status, and modem interface control.
System interrupts may be tailored to meet user requirements. An internal loop-back capability allows onboard
diagnostics. The TL16C752CI-Q1 incorporates the functionality of two UARTs, each UART having its own
register set and FIFOs. The two UARTs share only the data bus interface and clock source, otherwise they
operate independently. Another name for the UART function is asynchronous communications element (ACE),
and these terms are used interchangeably. The bulk of this document describes the behavior of each ACE, with
the understanding that two such devices are incorporated into the TL16C752CI-Q1 device.
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SLLSEQ9A – OCTOBER 2015 – REVISED FEBRUARY 2016
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6 Pin Configurations and Function
D2
D1
D0
TXRDYA
D3
V
RIA
CDA
DSRA
CTSA
NC
47
46
45
44
43
42
41
40
39
38
37
CC
D4
48
PFB Package
48-Pin TQFP
Top View
TXA
7
30
INTA
TXB
8
29
INTB
OPB
9
28
A0
CSA
10
27
A1
CSB
11
26
A2
NC
12
25
NC
24
RXRDYA
NC
31
23
6
CTSB
TXRDYB
22
OPA
RTSB
32
21
5
RIB
RXA
20
RTSA
DSRB
33
19
4
IOR
RXB
18
DTRA
RXRDYB
34
17
3
GND
D7
16
DTRB
CDB
35
15
2
IOW
D6
14
RESET
XTAL2
36
13
1
XTAL1
D5
NC – No internal connection
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
A0
28
I
Address bit 0 select. Internal registers address selection. Refer to Figure 26 for register address map.
A1
27
I
Address bit 1 select. Internal registers address selection. Refer to Figure 26 for register address map.
4
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Pin Functions (continued)
PIN
NAME
NO.
A2
26
CDA
40
CDB
16
CSA
10
CSB
11
CTSA
38
CTSB
23
D0
44
D1
45
D2
46
D3
47
D4
48
D5
1
D6
2
D7
3
DSRA
39
DSRB
20
DTRA
34
DTRB
35
GND
17
INTA
30
INTB
29
IOR
TYPE
DESCRIPTION
I
Address bit 2 select. Internal registers address selection. Refer to Figure 26 for register address map.
I
Carrier detect (active low). These inputs are associated with individual UART channels A and B. A
low on these pins indicates that a carrier has been detected by the modem for that channel.
I
Chip select A and B (active low). These pins enable data transfers between the user CPU and the
TL16C752CI-Q1 for the channel or channels addressed. Individual UART sections (A and B) are
addressed by providing a low on the respective CSA and CSB pin.
I
Clear to send (active low). These inputs are associated with individual UART channels A and B. A
low on the CTS pins indicates the modem or data set is ready to accept transmit data from the
TL16C752CI-Q1 device. Status can be checked by reading MSR[4]. These pins only affect the
transmit and receive operations when auto CTS function is enabled through the enhanced feature
register (EFR[7]), for hardware flow control operation.
I/O
Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring information to or
from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive
serial data stream.
I
Data set ready (active low). These inputs are associated with individual UART channels A through B.
A low on these pins indicates the modem or data set is powered on and is ready for data exchange
with the UART.
O
Data terminal ready (active low). These outputs are associated with individual UART channels A
through B. A low on these pins indicates that the TL16C752CI-Q1 is powered on and ready. These
pins can be controlled through the modem control register. Writing a 1 to MCR[0] sets the DTR output
to low, enabling the modem. The output of these pins is high after writing a 0 to MCR[0], or after a
reset. These pins can also be used in the RS-485 mode to control an external RS-485 driver or
transceiver.
Pwr
Power signal and power ground
O
Interrupt A and B (active high). These pins provide individual channel interrupts, INTA-B. INTA-B are
enabled when MCR[3] is set to a 1, interrupts are enabled in the interrupt enable register (IER) and
when an interrupt condition exists. Interrupt conditions include: receiver errors, available receiver
buffer data, transmit buffer empty, or when a modem status flag is detected. INTA-B are in the highimpedance state after reset.
19
I
Read input (active low strobe). A valid low level on IOR loads the contents of an internal register
defined by address bits A0 through A2 onto the TL16C752CI-Q1 device data bus (D0 through D7) for
access by an external CPU.
IOW
15
I
Write input (active low strobe). A valid low level on IOW transfers the contents of the data bus (D0
through D7) from the external CPU to an internal register that is defined by address bits A0 through
A2.
NC
12
NC
24
NC
25
NC
37
OPA
32
OPB
9
RESET
36
RIA
41
RIB
21
—
No internal connection
O
User defined outputs. This function is associated with individual channels A and B. The state of these
pins is defined by the user through the software settings of the MCR register, bit 3. INTA-B are set to
active mode and OP to a logic 0 when the MCR-3 is set to a logic 1. INTA-B are set to the 3-state
mode and OP to a logic 1 when MCR-3 is set to a logic 0. See bit 3, modem control register (MCR bit
3). The output of these two pins is high after reset.
I
Reset. RESET resets the internal registers and all the outputs. The UART transmitter output and the
receiver input are disabled during reset time. For initialization details, see TL16C752CI-Q1 device
external reset conditions. RESET is an active high input.
I
Ring indicator (active low). These inputs are associated with individual UART channels A and B. A
logic low on these pins indicates the modem has received a ringing signal from the telephone line. A
low-to-high transition on these input pins generates a modem status interrupt, if enabled. The state of
these inputs is reflected in the modem status register (MSR).
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Pin Functions (continued)
PIN
NAME
NO.
RTSA
33
RTSB
22
RXA
5
RXB
4
RXRDYA
31
RXRDYB
18
TXA
7
TYPE
DESCRIPTION
O
Request to send (active low). These outputs are associated with individual UART channels A and B.
A low on the RTS pins indicates the transmitter has data ready and waiting to send. Writing a 1 in the
modem control register (MCR[1]) sets these pins to low, indicating data is available. After a reset,
these pins are set to 1. These pins only affect the transmit and receive operation when auto-RTS
function is enabled through the enhanced feature register (EFR[6]), for hardware flow control
operation.
I
Receive data input. These inputs are associated with individual serial channel data to the
TL16C752CI-Q1 device. During the local loopback mode, these RX input pins are disabled and TX
data is internally connected to the UART RX input internally. During normal mode, RXn should be
held high when no data is being received. These inputs also can be used in IrDA mode. For more
information, see IrDA Overview.
O
Receive ready (active low). RXRDYA and RXRDYB go low when the trigger level has been reached
or a timeout interrupt occurs. They go high when the RX FIFO is empty or there is an error in RX
FIFO.
O
Transmit data. These outputs are associated with individual serial transmit channel data from the
TL16C752CI-Q1 device. During the local loopback mode, the TX input pin is disabled and TX data is
internally connected to the UART RX input.
O
Transmit ready (active low). TXRDYA and TXRDYB go low when there are a trigger level number of
spares available. They go high when the TX buffer is full.
TXB
8
TXRDYA
43
TXRDYB
6
VCC
42
PWR
XTAL1
13
I
Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock input. A
crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit.
Alternatively, an external clock can be connected to XTAL1 to provide custom data rates.
XTAL2
14
O
Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a crystal
oscillator output or buffered clock output.
Power supply inputs
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VCC
Supply voltage
–0.5
6
V
VI
Input voltage
–0.5
VCC + 0.5
V
VO
Output voltage
–0.5
VCC + 0.5
V
TA
Operating free-air temperature
–40
105
°C
Tstg
Storage temperature
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
6
Electrostatic
discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per AEC Q100-011
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
1.8
MAX
UNIT
1.98
V
0.9 × VCC
V
VCC = 1.8 V ±10%
VCC
Supply voltage
1.62
VI
Input voltage
–0.3
VIH
High-level input voltage
VIL
Low-level input voltage
VO
Output voltage
IOH
High-level output current
All outputs
IOL
Low-level output current
All outputs
1.4
V
0.4
0
Oscillator/clock speed
V
VCC
V
–0.5
mA
1
mA
16
MHz
VCC = 2.5 V ±10%
VCC
Supply voltage
2.25
VI
Input voltage
–0.3
2.5
2.75
V
0.9 × VCC
VIH
High-level input voltage
V
VIL
Low-level input voltage
VO
Output voltage
IOH
High-level output current
All outputs
–1
mA
IOL
Low-level output current
All outputs
2
mA
24
MHz
3.6
V
VCC
V
1.8
V
0.6
0
VCC
Oscillator/clock speed
V
V
VCC = 3.3 V ±10%
VCC
Supply voltage
VI
Input voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VO
Output voltage
IOH
High-level output current
IOL
Low-level output current
3
3.3
–0.3
0.7 × VCC
V
0.8
V
VCC
V
All outputs
–1.8
mA
All outputs
3.2
mA
32
MHz
5.5
V
VCC
V
0
Oscillator or clock speed
VCC = 5 V ±10%
VCC
Supply voltage
VI
Input voltage
4.5
VIH
High-level input voltage
VIL
Low-level input voltage
VO
Output voltage
IOH
High-level output current
All outputs
–4
mA
IOL
Low-level output current
All outputs
4
mA
48
MHz
–0.3
Except XTAL1
XTAL1
2
V
0.7 × VCC
Except XTAL1
0.8
XTAL1
0.3 × VCC
0
Oscillator or clock speed
5
VCC
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V
V
7
TL16C752CI-Q1
SLLSEQ9A – OCTOBER 2015 – REVISED FEBRUARY 2016
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7.4 Thermal Information
TL16C752CI-Q1
THERMAL METRIC (1)
PFB (TQFP)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJC(bot)
(1)
61
°C/W
Junction-to-case (top) thermal resistance
17.3
°C/W
Junction-to-case (bottom) thermal resistance
N/A
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC = 1.8 V
VOH
High-level output voltage IOH = –0.5 mA
VOL
Low-level output voltage
IOL = 1 mA
II
Input current
VCC = 1.98 V,
VI = 0 to 1.98 V,
VSS = 0,
All other terminals floating
High-impedance state
output current
VCC = 1.98 V,
VO = 0 to 1.98 V,
VSS = 0,
IOZ
Supply current
V
0.5
V
10
μA
±20
μA
4.5
mA
Chip selected in write mode or chip deselect
VCC = 1.98 V,
ICC
1.3
TA = 70°C,
DSR, CTS, and RI at 2 V,
All other inputs at 0.4 V,
No load on outputs,
XTAL1 at 16 MHz,
Baud rate = 1 Mbps
CI(CLK)
Clock input capacitance
VCC = 0,
f = 1 MHz,
All other terminals grounded
VSS = 0,
TA = 25°C,
5
7
pF
CO(CLK)
VCC = 0,
Clock output capacitance f = 1 MHz,
All other terminals grounded
VSS = 0,
TA = 25°C,
5
7
pF
CI
Input capacitance
VCC = 0,
f = 1 MHz,
All other terminals grounded
VSS = 0,
TA = 25°C,
6
10
pF
CO
Output capacitance
VCC = 0,
f = 1 MHz,
All other terminals grounded
VSS = 0,
TA = 25°C,
10
15
pF
VCC = 2.5 V
VOH
High-level output voltage IOH = –1 mA
1.8
VOL
Low-level output voltage
IOL = 2 mA
II
Input current
VCC = 2.75 V,
VI = 0 to 2.75 V,
VSS = 0,
All other terminals floating
High-impedance state
output current
VCC = 2.75 V,
VO = 0 to 2.75 V,
VSS = 0,
IOZ
Supply current
0.5
V
10
μA
±20
μA
9
mA
Chip selected in write mode or chip deselect
VCC = 2.75 V,
ICC
V
TA = 70°C,
DCD, CTS, and RI at 2 V,
All other inputs at 0.6 V,
No load on outputs,
XTAL1 at 24 MHz,
Baud rate = 1.5 Mbps
CI(CLK)
Clock input capacitance
VCC = 0,
f = 1 MHz,
All other terminals grounded
VSS = 0,
TA = 25°C,
5
7
pF
CO(CLK)
VCC = 0,
Clock output capacitance f = 1 MHz,
All other terminals grounded
VSS = 0,
TA = 25°C,
5
7
pF
8
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CI
Input capacitance
VCC = 0,
f = 1 MHz,
All other terminals grounded
VSS = 0,
TA = 25°C,
6
10
pF
CO
Output capacitance
VCC = 0,
f = 1 MHz,
All other terminals grounded
VSS = 0,
TA = 25°C,
10
15
pF
VCC = 3.3 V
VOH
High-level output voltage IOH = –1.8 mA
VOL
Low-level output voltage
IOL = 3.2 mA
II
Input current
VCC = 3.6 V,
VI = 0 to 3.6 V,
VSS = 0,
All other terminals floating
High-impedance state
output current
VCC = 3.6 V,
VO = 0 to 3.6 V,
VSS = 0,
IOZ
Supply current
V
0.5
V
10
μA
±20
μA
16
mA
Chip selected in write mode or chip deselect
VCC = 3.6 V,
ICC
2.4
TA = 70°C,
DSR, CTS, and RI at 2 V,
All other inputs at 0.8 V,
No load on outputs,
XTAL1 at 32 MHz,
Baud rate = 2 Mbps
CI(CLK)
Clock input capacitance
VCC = 0,
f = 1 MHz,
All other terminals grounded
VSS = 0,
TA = 25°C,
5
7
pF
CO(CLK)
VCC = 0,
Clock output capacitance f = 1 MHz,
All other terminals grounded
VSS = 0,
TA = 25°C,
5
7
pF
CI
Input capacitance
VCC = 0,
f = 1 MHz,
All other terminals grounded
VSS = 0,
TA = 25°C,
6
10
pF
CO
Output capacitance
VCC = 0,
f = 1 MHz,
All other terminals grounded
VSS = 0,
TA = 25°C,
10
15
pF
VCC = 5 V
VOH
High-level output voltage IOH = –4 mA
VOL
Low-level output voltage
IOL = 4 mA
4
II
Input current
VCC = 5.5 V,
VI = 0 to 5.5 V,
VSS = 0,
All other terminals floating
High-impedance state
output current
VCC = 5.5 V,
VO = 0 to 5.5 V,
VSS = 0,
IOZ
Supply current
V
10
μA
±20
μA
40
mA
Chip selected in write mode or chip deselect
VCC = 5.5 V,
ICC
V
0.5
TA = 70°C,
DSR, CTS, and RI at 2 V,
All other inputs at 0.8 V,
No load on outputs,
XTAL1 at 48 MHz,
Baud rate = 3 Mbps
CI(CLK)
Clock input capacitance
VCC = 0,
f = 1 MHz,
All other terminals grounded
VSS = 0,
TA = 25°C,
5
7
pF
CO(CLK)
VCC = 0,
Clock output capacitance f = 1 MHz,
All other terminals grounded
VSS = 0,
TA = 25°C,
5
7
pF
CI
Input capacitance
VCC = 0,
f = 1 MHz,
All other terminals grounded
VSS = 0,
TA = 25°C,
6
10
pF
CO
Output capacitance
VCC = 0,
f = 1 MHz,
All other terminals grounded
VSS = 0,
TA = 25°C,
10
15
pF
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7.6 Timing Requirements
TA = 0°C to 70°C, VCC = 1.8 V to 5 V ±10% (unless otherwise noted)
LIMITS
tRESET Reset pulse width
CP
CP clock period
t3w
Oscillator or clock speed
t6s
Address setup time
t6h
Address hold time
t7w
t9d
1.8 V
2.5 V
3.3 V
5V
MIN MAX
MIN MAX
MIN MAX
MIN MAX
200
200
200
200
ns
63
42
32
20
ns
16
24
32
UNIT
48
MHz
20
15
10
5
ns
See Figure 1 and Figure 2
15
10
7
5
ns
IOR strobe width
See Figure 1 and Figure 2
85
70
50
40
ns
Read cycle delay
See Figure 2
85
70
60
50
t12d
Delay from IOR to data
See Figure 2
t12h
Data disable time
t13w
IOW strobe width
See Figure 1
85
70
50
40
ns
t15d
Write cycle delay
See Figure 1
85
70
60
50
ns
t16s
Data setup time
See Figure 1
40
30
20
15
ns
t16h
Data hold time
See Figure 1
35
t17d
Delay from IOW to output
50-pF load, see Figure 3
60
40
30
20
ns
t18d
Delay to set interrupt from
MODEM input
50-pF load, see Figure 3
70
55
45
35
ns
t19d
Delay to reset interrupt from IOR 50-pF load
80
55
40
30
ns
t20d
Delay from stop to set interrupt
1
1
1
1
baudrate
t21d
Delay from IOR to reset interrupt 50-pF load, see Figure 4
55
45
35
25
ns
t22d
Delay from stop to interrupt
See Figure 7
1
1
1
1
baudrate
t23d
Delay from initial IOW reset to
transmit start
See Figure 7
24
baudrate
t24d
Delay from IOW to reset
interrupt
See Figure 7
t25d
Delay from stop to set RXRDY
t26d
Delay from IOR to reset RXRDY
t27d
Delay from IOW to set TXRDY
t28d
65
50
35
See Figure 4
8
35
25
20
25
24
15
8
24
8
ns
25
ns
15
ns
10
24
8
ns
75
45
35
25
ns
See Figure 5 and Figure 6
1
1
1
1
baudrate
See Figure 5 and Figure 6
1
1
1
1
μs
See Figure 8 and Figure 9
70
60
50
40
ns
Delay from start to reset TXRDY See Figure 8 and Figure 9
16
16
16
16
baudrate
A[2:0]
Valid Address
Valid Address
t 6s
t 6s
t 6h
t 6h
t 13w
CS
t 15d
t 13w
IOW
t 16s
D[7:0]
t 16h
Valid Data
t 16s
t 16h
Valid Data
Figure 1. General Write Timing
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A[2:0]
Valid Address
Valid Address
t 6s
t 6s
t 6h
t 6h
t 7w
CS
t 9d
t 7w
IOR
t 12d
t 12d
t 12h
t 12h
Valid Data
D[7:0]
Valid Data
Figure 2. General Read Timing
IOW
Active
t17d
RTS (A–B)
DTR (A–B)
Change of State
Change of State
CD (A–B)
Change of State
CTS (A–B)
DSR (A–B)
t18d
t18d
INT (A–B)
Active
Active
Active
t19d
Active
IOR
Active
Active
t18d
Change of State
RI (A–B)
Figure 3. Modem or Output Timing
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Start
Bit
Stop
Bit
Data Bits (5–8)
D0
RX (A–B)
D1
D3
D2
D5
D4
D6
D7
Parity
Bit
5 Data Bits
Next
Data
Start
Bit
6 Data Bits
7 Data Bits
t20d
INT (A–B)
Active
t21d
Active
IOR
16-Baud Rate Clock
Figure 4. Receive Timing
Start
Bit
Stop
Bit
Data Bits (5–8)
D0
RX (A–B)
D1
D2
D3
D4
D5
D6
D7
Parity
Bit
Next
Data
Start
Bit
t25d
Active
Data
Ready
RXRDY (A–B)
RXRDY
t26d
Active
IOR
Figure 5. Receive Ready Timing in Non-FIFO Mode
Start
Bit
Stop
Bit
Data Bits (5–8)
RX (A–B)
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Bit
First Byte
That Reaches
The Trigger
Level
t25d
Active
Data
Ready
RXRDY (A–B)
RXRDY
t26d
Active
IOR
Figure 6. Receive Timing in FIFO Mode
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Start
Bit
Stop
Bit
Data Bits (5–8)
D0
TX (A–B)
D1
D3
D2
D4
D5
D6
D7
Parity
Bit
5 Data Bits
Next
Data
Start
Bit
6 Data Bits
7 Data Bits
t22d
INT (A–B)
Active
Tx Ready
t24d
t23d
Active
Active
IOW
16-Baud Rate Clock
Figure 7. Transmit Timing
Start
Bit
Stop
Bit
Data Bits (5–8)
D0
TX (A–B)
D1
D2
D3
D4
D5
D6
D7
Next
Data
Start
Bit
Parity
Bit
IOW
D0–D7
Active
Byte 1
t 28d
T27d
Active
Transmitter Ready
TXRDY (A–B)
TXRDY
Transmitter
Not Ready
Figure 8. Transmit Ready Timing in Non-FIFO Mode
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Start
Bit
Stop
Bit
Data Bits (5–8)
D0
TX (A–B)
D1
D3
D2
D5
D4
D6
D7
Parity
Bit
5 Data Bits
6 Data Bits
7 Data Bits
IOW
D0–D7
Active
Trigger
Level
t28d
t27d
TXRDY (A–B)
TXRDY
Trigger
Level
Figure 9. Transmit Timing in FIFO Mode
7.7 Typical Characteristics
all channels active, TA = 25°C, unless otherwise noted
2
4.5
Supply Current, ICC (mA)
Supply Current, I CC (mA)
3.75
1.5
1
0.5
VCC = 1.62 V
VCC = 1.8 V
VCC = 1.98 V
2.25
1.5
VCC = 2.25 V
VCC = 2.5 V
VCC = 2.75 V
0.75
0
0
0
4
8
Frequency, g (MHz)
12
16
0
4
D001
Figure 10. Supply Current vs Frequency
(VCC = 1.62, 1.8, and 1.98 V)
14
3
8
12
16
Frequency, g (MHz)
20
24
D002
Figure 11. Supply Current vs Frequency
(VCC = 2.25, 2.5, and 2.75 V)
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Typical Characteristics (continued)
all channels active, TA = 25°C, unless otherwise noted
30
8
TA = 25°C
25
Div = 1
6
Supply Current, ICC (mA)
Supply CUrrent, I CC (mA)
VCC = 5 V,
4
2
VCC = 3 V
VCC = 3.3 V
VCC = 3.5 V
8
16
Frequency, g (MHz)
24
15
10
5
0
0
Div = 10
20
32
D003
0
0
4
8
12
16
20
24
Frequency, f (MHz)
Figure 12. Supply Current vs Frequency
(VCC = 3, 3.3, and 3.5 V)
Figure 13. Supply Current vs Frequency
(VCC = 5 V)
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8 Detailed Description
8.1 Overview
The TL16C752CI-Q1 UART is pin-compatible with the ST16C2550 UART in the PFB package. It provides more
enhanced features. All additional features are provided through a special enhanced feature register.
The TL16C752CI-Q1 UART will perform serial-to-parallel conversion on data characters received from peripheral
devices or modems and parallel-to-parallel conversion on data characters transmitted by the processor. The
complete status of each channel of the TL16C752CI-Q1 UART can be read at any time during functional
operation by the processor.
Each UART transmits data sent to it from the peripheral 8-bit bus on the TX signal and receives characters on
the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO and
transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own
desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity
and 1-, 1.5-, or 2-stop bits. The receiver can detect break, idle or framing errors, FIFO overflow, and parity errors.
The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control
operations, and software flow control and hardware flow control capabilities.
8.2 Functional Block Diagram
UART Channel A
A2 to A0
D7 to D0
CSA
64-Byte TX FIFO
UART Regs
CSB
IOR
IOW
INTA
INTB
TXRDYA
TXRDYB
RXRDYA
RXRDYB
TX
Baud
Rate
64-Byte RX FIFO
Generator
DSRA, RIA, CDA
RTSA
RX
RXA
Data Bus
Interface
UART Channel B
64-Byte TX FIFO
TX
UART Regs
RESET
XTAL1
XTAL2
TXA
CTSA
OPA, DTRA
Baud
Rate
64-Byte RX FIFO
Generator
TXB
CTSB
OPB, DTRB
DSRB, RIB, CDB
RTSB
RX
RXB
Crystal
Oscillator
Buffer
VCC
GND
Figure 14. TL16C752CI-Q1 Functional Block Diagram
16
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Functional Block Diagram (continued)
Modem Control Signals
Control Signals
Bus
Interface
Status Signals
Control
and
Status Block
Divisor
Control Signals
Baud-Rate
Generator
Status Signals
UART_CLK
RX
Int_Rx
64-Byte
Receiver FIFO
Receiver Block
Logic
IrDA
Vote
Logic
RX
TX
64-Byte
Transmitter FIFO
Transmitter Block
Logic
Int_Tx
IrDA
TX
NOTE: The vote logic determines whether the RX data is a logic 1 or 0. It takes three samples of the RX line and uses a
majority vote to determine the logic level received. The vote logic operates on all bits received.
Figure 15. TL16C752CI-Q1 Functional Block Diagram – Control Blocks
8.3 Feature Description
8.3.1 Functional Description
The TL16C752CI-Q1 UART can be placed in an alternate mode (FIFO mode) relieving the processor of
excessive software overhead by buffering received and transmitted characters. Both the receiver and transmitter
FIFOs can store up to 64 bytes (including three additional bits of error status per byte for the receiver FIFO) and
have selectable or programmable trigger levels. Primary outputs RXRDY and TXRDY allow signaling of DMA
transfers.
The TL16C752CI-Q1 UART has selectable hardware flow control and software flow control. Both schemes
significantly reduce software overhead and increase system efficiency by automatically controlling serial data
flow. Hardware flow control uses the RTS output and CTS input signals. Software flow control uses
programmable Xon and Xoff characters.
The TL16C752CI-Q1 device includes a programmable baud rate generator that can divide the timing reference
clock by a divisor between 1 and 65535. A bit (MCR7) can be used to invoke a prescaler (divide by 4) off the
reference clock, prior to the baud rate generator input. The divide by 4 prescaler is selected when MCR7 is set to
1.
8.3.1.1 Trigger Levels
The TL16C752CI-Q1 UART provides independent selectable and programmable trigger levels for both receiver
and transmitter DMA and interrupt generation. After reset, both transmitter and receiver FIFOs are disabled and
so, in effect, the trigger level is the default value of one byte. The selectable trigger levels are available through
the FCR. The programmable trigger levels are available through the TLR.
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Feature Description (continued)
8.3.1.2 Hardware Flow Control
Hardware flow control is composed of auto-CTS and auto-RTS. Auto-CTS and auto-RTS can be enabled or
disabled independently by programming EFR[7:6].
With auto-CTS, CTS must be active before the UART can transmit data. Auto-RTS only activates the RTS output
when there is enough room in the FIFO to receive data and deactivates the RTS output when the RX FIFO is
sufficiently full. The HALT and RESTORE trigger levels in the TCR determine the levels at which RTS is
activated or deactivated. If both auto-CTS and auto-RTS are enabled, when RTS is connected to CTS, data
transmission does not occur unless the receiver FIFO has empty space. Thus, overrun errors are eliminated
during hardware flow control. If not enabled, overrun errors occur if the transmit data rate exceeds the receive
FIFO servicing latency.
8.3.1.3 Auto-RTS
Auto-RTS data flow control originates in the receiver block (see Figure 14). Figure 16 shows RTS functional
timing. The receiver FIFO trigger levels used in Auto-RTS are stored in the TCR. RTS is active if the RX FIFO
level is below the HALT trigger level in TCR[3:0]. When the receiver FIFO HALT trigger level is reached, RTS is
deasserted. The sending device (for example, another UART) may send an additional byte after the trigger level
is reached (assuming the sending UART has another byte to send) because it may not recognize the deassertion
of RTS until it has begun sending the additional byte. RTS is automatically reasserted once the receiver FIFO
reaches the RESUME trigger level programmed via TCR[7:4]. This reassertion allows the sending device to
resume transmission.
RX
Start
Byte N
Stop
Start
Byte N+1
Stop
Start
RTS
IOR
1
N
2
N+1
A.
N = receiver FIFO trigger level B.
B.
The two blocks in dashed lines cover the case where an additional byte is sent as described in Auto-RTS.
Figure 16. RTS Functional Timing
8.3.1.4 Auto-CTS
The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, the transmitter
sends the next byte. To stop the transmitter from sending the following byte, CTS must be deasserted before the
middle of the last stop bit that is currently being sent. The auto-CTS function reduces interrupts to the host
system. When flow control is enabled, the CTS state changes and need not trigger host interrupts because the
device automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the
transmit FIFO and a receiver overrun error can result. Figure 17 shows CTS functional timing, and Figure 18
shows an example of autoflow control.
18
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Feature Description (continued)
Start
TX
Byte 0–7
Stop
Start
Byte 0–7
Stop
CTS
A.
When CTS is low, the transmitter keeps sending serial data out.
B.
When CTS goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the
current byte, but it does not send the next byte.
C.
When CTS goes from high to low, the transmitter begins sending data again.
Figure 17. CTS Functional Timing
UART 1
UART 2
Serial to
Parallel
RX
TX
Parallel to
Serial
RX
FIFO
TX
FIFO
Flow
Control
RTS
CTS
Flow
Control
D7 – D0
D7 – D0
Parallel to
Serial
TX
RX
Serial to
Parallel
TX
FIFO
RX
FIFO
Flow
Control
CTS
RTS
Flow
Control
Figure 18. Autoflow Control (Auto-RTS and Auto-CTS) Example
8.3.1.5 Software Flow Control
Software flow control is enabled through the enhanced feature register and the modem control register. Different
combinations of software flow control can be enabled by setting different combinations of EFR[3−0]. Table 1
shows software flow control options.
Two other enhanced features relate to software flow control:
• Xon Any Function [MCR(5): Operation resumes after receiving any character after recognizing the Xoff
character.
• Special Character [EFR(5)]: Incoming data is compared to Xoff2. Detection of the special character sets the
Xoff interrupt [IIR(4)] but does not halt transmission. The Xoff interrupt is cleared by a read of the IIR. The
special character is transferred to the RX FIFO.
NOTE
It is possible for an Xon1 character to be recognized as an Xon Any character, which
could cause an Xon2 character to be written to the RX FIFO.
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Table 1. Software Flow Control Options EFR[3:0]
BIT 3
BIT 2
BIT 1
BIT 0
0
0
X
X
No transmit flow control
TX, RX SOFTWARE FLOW CONTROLS
1
0
X
X
Transmit Xon1, Xoff1
0
1
X
X
Transmit Xon2, Xoff2
1
1
X
X
Transmit Xon1, Xon2: Xoff1, Xoff2
X
X
0
0
No receive flow control
X
X
1
0
Receiver compares Xon1, Xoff1 X X 0 1
X
X
0
1
Receiver compares Xon2, Xoff2
1
0
1
1
Transmit Xon1, Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0
1
1
1
Transmit Xon2, Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1
1
1
1
Transmit Xon1, Xon2: Xoff1, Xoff2
Receiver compares Xon1 and Xon2: Xoff1 and Xoff2
0
0
1
1
No transmit flow control
Receiver compares Xon1 and Xon2: Xoff1 and Xoff2
When software flow control operation is enabled, the TL16C752CI-Q1 device compares incoming data with Xoff1
and Xoff2 programmed characters (in certain cases Xoff1 and Xoff2 must be received sequentially). (1) When an
Xoff character is received, transmission is halted after completing transmission of the current character. Xoff
character detection also sets IIR[4] and causes INT to go high (if enabled via IER[5]).
To resume transmission an Xon1 and Xon2 character must be received (in certain cases Xon1 and Xon2 must
be received sequentially). When the correct Xon characters are received IIR[4] is cleared and the Xoff interrupt
disappears.
NOTE
If a parity, framing, or break error occurs while receiving a software flow control character,
this character is treated as normal data and is written to the RCV FIFO.
Xoff1 and Xoff2 characters are transmitted when the RX FIFO has passed the programmed trigger level
TCR[3:0].
Xon1 and Xon2 characters are transmitted when the RX FIFO reaches the trigger level programmed via
TCR[7:4].
NOTE
If, after an Xoff character has been sent, software flow control is disabled, the UART
transmits Xon characters automatically to enable normal transmission to proceed. A
feature of the TL16C752CI-Q1 UART design is that if the software flow combination
(EFR[3:0]) changes after an Xoff has been sent, the originally programmed Xon is
automatically sent. If the RX FIFO is still above the trigger level, the newly programmed
Xoff1 or Xoff2 is transmitted.
The transmission of Xoff and Xon follows the exact same protocol as transmission of an ordinary byte from the
FIFO. This means that even if the word length is set to be 5, 6, or 7 characters, then the 5, 6, or 7 least
significant bits of Xoff1, Xoff2 and Xon1, Xon2 are transmitted. The transmission of 5, 6, or 7 bits of a character
is seldom done, but this functionality is included to maintain compatibility with earlier designs.
It is assumed that software flow control and hardware flow control are never enabled simultaneously. Figure 19
shows a software flow control example.
(1)
20
When pairs of Xon and Xoff characters are programmed to occur sequentially, received Xon1 and Xoff1 characters will be written to the
RX FIFO if the subsequent character is not Xon2 and Xoff2.
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UART 1
UART 2
Transmit
FIFO
Receive
FIFO
Data
Parallel to Serial
Serial to Parallel
Xoff − Xon − Xoff
Serial to Parallel
Parallel to Serial
Xon-1 Word
Xon-1 Word
Xon-2 Word
Xon-2 Word
Xoff-1 Word
Xoff-1 Word
Compare
Programmed
Xon −Xoff
Characters
Xoff-2 Word
Xoff-2 Word
Figure 19. Software Flow Control Example
8.3.1.6 Software Flow Control Example
Assumptions: UART1 is transmitting a large text file to UART2. Both UARTs are using software flow control with
single character Xoff (0F) and Xon (0D) tokens. Both have Xoff threshold (TCR [3:0] = F) set to 60 and Xon
threshold (TCR[7:4] = 8) set to 32. Both have the interrupt receive threshold (TLR[7:4] = D) set to 52.
UART1 begins transmission and sends 52 characters, at which point UART2 generates an interrupt to its
processor to service the RCV FIFO, but assumes the interrupt latency is fairly long. UART1 continues sending
characters until a total of 60 characters have been sent. At this time UART2 transmits a 0F to UART1, informing
UART1 to halt transmission. UART1 likely sends the 61st character while UART2 is sending the Xoff character.
Now, UART2 is serviced and the processor reads enough data out of the RCV FIFO that the level drops to 32.
UART2 now sends a 0D to UART1, informing UART1 to resume transmission.
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8.3.1.7 Reset
Table 2 summarizes the state of outputs after reset.
Table 2. Register Reset Functions (1)
REGISTER
RESET CONTROL
RESET STATE
Interrupt enable register
RESET
All bits cleared
Interrupt identification register
RESET
Bit 0 is set. All other bits cleared.
FIFO control register
RESET
All bits cleared
Line control register
RESET
Reset to 00011101 (1D hex)
Modem control register
RESET
All bits cleared
Line status register
RESET
Bits 5 and 6 set. All other bits cleared.
Modem status register
RESET
Bits 0 to 3 cleared. Bits 4 to 7 input signals.
Enhanced feature register
RESET
All bits cleared
Receiver holding register
RESET
Pointer logic cleared
Transmitter holding register
RESET
Pointer logic cleared
Transmission control register
RESET
All bits cleared
Trigger level register
RESET
All bits cleared
Alternate function register
RESET
All bits (except AFR4) cleared; AFR4 set
(1)
Registers DLL, DLH, SPR, Xon1, Xon2, Xoff1, and Xoff2 are not reset by the top-level reset signal
RESET, that is, they hold their initialization values during reset.
Table 3 summarizes the state of outputs after reset.
Table 3. Signal Reset Functions
SIGNAL
22
RESET CONTROL
RESET STATE
TX
RESET
High
RTS
RESET
High
DTR
RESET
High
RXRDYA–B
RESET
High
TXRDYA–B
RESET
Low
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8.3.1.8 Interrupts
The TL16C752CI-Q1 UART has interrupt generation and prioritization (six prioritized levels of interrupts)
capability. The interrupt enable register (IER) enables each of the six types of interrupts and the INT signal in
response to an interrupt generation. The IER also can disable the interrupt system by clearing bits 0 to 3, 5 to 7.
When an interrupt is generated, the interrupt identification register (IIR) indicates that an interrupt is pending and
provides the type of interrupt through IIR[5−0]. Table 4 summarizes the interrupt control functions.
Table 4. Interrupt Control Functions
IIR[5–0]
PRIORITY
LEVEL
INTERRUPT
TYPE
000001
None
None
000110
1
Receiver line
status
001100
2
RX timeout
000100
2
RHR interrupt
000010
3
000000
010000
100000
INTERRUPT SOURCE
INTERRUPT RESET METHOD
None
None
OE, FE, PE, or BI errors occur in
characters in the RX FIFO
FE < PE < BI: All erroneous characters are
read from the RX FIFO. OE: Read LSR
Stale data in RX FIFO
Read RHR
DRDY (data ready)
(FIFO disable)
RX FIFO above trigger level (FIFO enable)
Read RHR
THR interrupt
TFE (THR empty)
(FIFO disable)
TX FIFO passes above trigger level (FIFO
enable)
Read IIR or a write to the THR
4
Modem status
MSR[3:0] = 0
Read MSR
5
Xoff interrupt
Receive Xoff character or
characters/special character
Receive Xon character or characters/Read of
IIR
6
CTS, RTS
RTS pin or CTS pin change state from
active (low) to inactive (high)
Read IIR
It is important to note that for the framing error, parity error, and break conditions, LSR[7] generates the interrupt.
LSR[7] is set when there is an error anywhere in the RX FIFO and is cleared only when there are no more errors
remaining in the FIFO. LSR[4–2] always represent the error status for the received character at the top of the RX
FIFO. Reading the RX FIFO updates LSR[4–2] to the appropriate status for the new character at the top of the
FIFO. If the RX FIFO is empty, then LSR[4–2] is all 0.
For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt is cleared by an Xon
flow character detection. If a special character detection caused the interrupt, the interrupt is cleared by a read of
the ISR.
8.3.1.9 Interrupt Mode Operation
In interrupt mode (if any bit of IER[3:0] is 1), the processor is informed of the status of the receiver and
transmitter by an interrupt signal, INT. Therefore, it is not necessary to continuously poll the line status register
(LSR) to see if any interrupt needs to be serviced. Figure 20 shows interrupt mode operation.
IER
IOW/IOR
Processor
0
INT
0
0
0
IIR
THR
RHR
Figure 20. Interrupt Mode Operation
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8.3.1.10 Polled Mode Operation
In polled mode (IER[3:0] = 0000), the status of the receiver and transmitter can then be checked by polling the
line status register (LSR). This mode is an alternative to the interrupt mode of operation where the status of the
receiver and transmitter is automatically known by means of interrupts sent to the CPU. Figure 21 shows polled
mode operation.
LSR
IOW/IOR
Processor
IER
0
THR
0
0
0
RHR
Figure 21. FIFO Polled Mode Operation
8.3.1.11 Break and Timeout Conditions
An RX timeout condition is detected when the receiver line, RX, has been high for a time equivalent to (4 ×
programmed word length) + 12 bits and there is at least one byte stored in the RX FIFO.
When a break condition occurs, the TX line is pulled low. A break condition is activated by setting LCR[6].
24
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8.3.1.12 Programmable Baud Rate Generator
The TL16C752CI-Q1 UART contains a programmable baud generator that divides reference clock by a divisor in
the range between 1 and (216 − 1). The output frequency of the baud rate generator is 16× the baud rate. An
additional divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in the following. The
formula for the divisor is:
Divisor = (XTAL crystal input frequency / prescaler) / (desired baud rate X 16)
Where
1 when CLKSEL = high during reset, or MCR[7] is set to 0 after reset
prescaler =
4 when CLKSEL = high during reset, or MCR[7] is set to 1 after reset
Figure 22 shows the internal prescaler and baud rate generator circuitry.
Prescaler Logic
(Divide By 1)
XTAL1
XTAL2
Internal
Oscillator
Logic
MCR[7] = 0
Input Clock
Reference
Clock
Prescaler Logic
(Divide By 4)
Band Rate
Generator
Logic
Internal
Band Bate Clock
For Transmitter
and Receiver
MCR[7] = 1
Figure 22. Prescaler and Baud Rate Generator Block Diagram
DLL and DLH must be written to to program the baud rate. DLL and DLH are the least significant and most
significant byte of the baud rate divisor. If DLL and DLH are both 0, the UART is effectively disabled, because no
baud clock is generated. The programmable baud rate generator is provided to select both the transmit and
receive clock rates. Table 5 and Table 6 show the baud rate and divisor correlation for the crystal with frequency
1.8432 and 3.072 MHz, respectively.
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Table 5. Baud Rates Using a 1.8432-MHz Crystal
DESIRED
BAUD RATE
DIVISOR USED TO
GENERATE 16×
CLOCK
50
2304
75
1536
110
1047
0.026
134.5
857
0.058
150
768
300
384
600
192
1200
96
1800
64
2000
58
2400
48
3600
32
4800
24
7200
16
9600
12
19200
6
38400
3
56000
2
PERCENT ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL
0.69
2.86
Table 6. Baud Rates Using a 3.072-MHz Crystal
26
DESIRED
BAUD RATE
DIVISOR USED TO
GENERATE 16×
CLOCK
50
3840
75
2560
110
1745
0.026
134.5
1428
0.034
150
1280
300
640
600
320
1200
160
1800
107
2000
96
2400
80
3600
53
4800
40
7200
27
9600
20
19200
10
38400
5
PERCENT ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL
0.312
0.628
1.23
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Figure 23 shows the crystal clock circuit reference.
VCC
Driver
VCC
XTAL1
XTAL1
External
Clock
C1
Crystal
Rp
Optional
Driver
Optional
Clock
Output
Oscillator Clock
to Baud Generator
Logic
XTAL2
RX2
Oscillator Clock
to Baud Generator
Logic
XTAL2
C2
A.
For crystal with fundamental frequency from 1 to 24 MHz
B.
For input clock frequency higher than 24 MHz, the crystal is not allowed and the oscillator must be used, because the
TL16C752CI-Q1 internal oscillator cell can only support the crystal frequency up to 24 MHz.
Figure 23. Typical Crystal Clock Circuits
8.4 Device Functional Modes
8.4.1 DMA Signaling
There are two modes of DMA operation, DMA mode 0 or 1, selected by FCR[3].
In DMA mode 0 or FIFO disable (FCR[0] = 0), DMA occurs in single character transfers. In DMA mode 1,
multicharacter (or block) DMA transfers are managed to relieve the processor for longer periods of time.
8.4.1.1 Single DMA Transfers (DMA Mode0 or FIFO Disable)
Transmitter: When empty, the TXRDY signal becomes active. TXRDY goes inactive after one character has
been loaded into it.
Receiver: RXRDY is active when there is at least one character in the FIFO. It becomes inactive when the
receiver is empty.
Figure 24 shows TXRDY and RXRDY in DMA mode 0 or FIFO disable.
RX
TX
RXRDY
TXRDY
wrptr
rdptr
At Least One
Location Filled
At Least One
Location Filled
RXRDY
TXRDY
wrptr
FIFO Empty
rdptr
FIFO Empty
Figure 24. TXRDY and RXRDY in DMA Mode 0 or FIFO Disable
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Device Functional Modes (continued)
8.4.1.2 Block DMA Transfers (DMA Mode 1)
Transmitter: TXRDY is active when a trigger level number of spaces are available. It becomes inactive when the
FIFO is full.
Receiver: RXRDY becomes active when the trigger level has been reached or when a timeout interrupt occurs. It
goes inactive when the FIFO is empty or an error in the RX FIFO is flagged by LSR(7).
Figure 25 shows TXRDY and RXRDY in DMA mode 1.
wrptr
TX
RX
Trigger
Level
TXRDY
RXRDY
rdptr
At Least One
Location Filled
Trigger
Level
TXRDY
wrptr
RXRDY
rdptr
FIFO Empty
Figure 25. TXRDY and RXRDY in DMA Mode 1
8.4.2 Sleep Mode
Sleep mode is an enhanced feature of the TL16C752CI-Q1 UART. It is enabled when EFR[4], the enhanced
functions bit, is set and when IER[4] is set. Sleep mode is entered when:
• The serial data input line, RX, is idle (see Break and Timeout Conditions).
• The TX FIFO and TX shift register are empty.
• There are no interrupts pending except THR and timeout interrupts.
Sleep mode is not entered if there is data in the RX FIFO.
In sleep mode, the UART clock and baud rate clock are stopped. Because most registers are clocked using
these clocks, the power consumption is greatly reduced. The UART wakes up when any change is detected on
the RX line, when there is any change in the state of the modem input pins, or if data is written to the TX FIFO.
NOTE
Writing to the divisor latches, DLL and DLH, to set the baud clock, must not be done
during sleep mode. Therefore, TI recommends to disable sleep mode using IER[4] before
writing to DLL or DLH.
28
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8.5 Register Maps
8.5.1 Principals of Operation
Each register is selected using address lines A[0], A[1], A[2], and in some cases, bits from other registers. The
programming combinations for register selection are shown in Figure 26.
Accessible only when LCR[7] = 1
Accessible only when LCR[7:5] = 100
Accessible only when LCR = 1011 1111 (0xBF)
Accessible only when EFR[4] = 1 and MCR[6] = 1
Accessible when any CS A-B = 0, MCR[2] = 1 and loopback MCR[4] = 0 is disabled
NOTE: MCR[7:5], FCR[5:4], and IER[7:4] can only be modified when EFR[4] is set.
Figure 26. Register Map – Read and Write Properties
Table 7 lists and describes the TL16C752CI-Q1 internal registers.
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Table 7. TL16C752CI-Q1 Internal Registers (1)
ADDRESS
000
001
REGISTER
R/W
(3)
RHR
R
THR
W
DLL (4)
RW
ACCESS
CONSIDERATION
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
bit 7
0
bit 6
0
bit 5
0
bit 4
0
bit 3
0
bit 2
0
bit 1
0
bit 0
0
bit 7
0
bit 6
0
bit 5
0
bit 4
0
bit 3
0
bit 2
0
bit 1
0
bit 0
0
LCR[7] = 1
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RTS# Interrupt
enable (1)
0
Xoff Interrupt
enable (1)
0
Sleep
mode (1)
0
Modem status
interrupt
0
RX line status
interrupt
0
THR empty
interrupt
0
RX data available
interrupt
0
LCR[7] = 0
IER
RW
LCR[7] = 0
CTS#
Interrupt
enable (1)
0
DLH (4)
RW
LCR[7] = 1
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IIR
R
FCR(0)
0
FCR(0)
0
CTS# / RTS#
0
Xoff
0
Interrupt
priority bit 2
0
Interrupt
priority bit 1
0
Interrupt
priority bit 0
0
Interrupt status
1
RX trigger
level
0
RX trigger level
0
TX trigger
level (1)
0
TX trigger
level (1)
0
DMA mode
select
0
Resets TX
FIFO
0
Resets RX
FIFO
0
Enable FIFOs
0
LCR[7] = 0
FCR
W
AFR (5)
RW
LCR[7:5] = 100
DLY2
0
DLY1
0
DLY0
0
RCVEN
1
485LG
0
485RN
0
IREN
0
CONC
0
EFR (6)
RW
LCR[7:0] =
10111111
Auto CTS#
0
Auto RTS#
0
Special
character
detect
0
Enable
enhanced
functions
0
S/W flow
control bit 3
0
S/W flow
control bit 2
0
S/W flow
control bit 1
0
S/W flow control
bit 0
0
LCR
RW
None
DLAB & EFR
enable
0
Break control
bit
0
Sets parity
0
Parity type
select
1
Parity enable
1
No. of stop bits
1
Word length
0
Word length
1
MCR
RW
LCR[7:0] ≠
10111111
1x / 4x
clock (1)
0
TCR & TLR
enable (1)
0
Xon any (1)
0
Enable
loopback
0
IRQ enable
0
FIFORdy
enable
0
RTS#
0
DTR#
0
Xon1 (6)
RW
LCR[7:0] =
10111111
bit 7
1
bit 6
1
bit 5
1
bit 4
1
bit 3
1
bit 2
1
bit 1
1
bit 0
1
LSR
R
LCR[7:0] ≠
10111111
Error in RX
FIFO
0
THR & TSR
empty
1
THR empty
1
Break
interrupt
0
Framing error
0
Parity error
0
Overrun error
0
Data in receiver
0
Xon2 (6)
RW
LCR[7:0] =
10111111
bit 7
1
bit 6
1
bit 5
1
bit 4
0
bit 3
1
bit 2
1
bit 1
1
bit 0
1
010
011
100
101
(1)
(2)
(3)
(4)
(5)
(6)
30
(2)
Bits represented by the blue shaded cells can only be modified if EFR[4] is enabled, that is, if enhanced functions are enabled.
For more register access information, see Figure 26.
Read = R; Write = W
This register is only accessible when LCR[7] = 1
This register is only accessible LCR[7:5] = 100
This register is only accessible when LCR = 1011 1111 (0xBF)
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Table 7. TL16C752CI-Q1 Internal Registers() () (continued)
ADDRESS
110
111
(7)
(8)
(3)
ACCESS
CONSIDERATION
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MSR
R
LCR[7:0] ≠
10111111
CD#
1
RI#
1
DSR#
1
CTS#
0
∆CD#
0
∆RI#
0
∆DSR#
0
∆CTS#
0
Xoff1 (6)
RW
LCR[7:0] =
10111111
bit 7
1
bit 6
1
bit 5
1
bit 4
1
bit 3
1
bit 2
1
bit 1
1
bit 0
1
TCR (7)
RW
EFR[4] = 1 &
MCR[6] = 1
bit 7
0
bit 6
0
bit 5
0
bit 4
0
bit 3
0
bit 2
0
bit 1
0
bit 0
0
SPR
RW
LCR[7:0] ≠
10111111
bit 7
1
bit 6
1
bit 5
1
bit 4
1
bit 3
1
bit 2
1
bit 1
1
bit 0
1
Xoff2 (6)
RW
LCR[7:0] =
10111111
bit 7
1
bit 6
1
bit 5
1
bit 4
1
bit 3
1
bit 2
1
bit 1
1
bit 0
1
TLR (7)
RW
EFR[4] = 1 &
MCR[6] = 1
bit 7
0
bit 6
0
bit 5
0
bit 4
0
bit 3
0
bit 2
0
bit 1
0
bit 0
0
FIFORdy (8)
R
MCR[4] = 0 &
MCR[2] = 1
RX FIFO D
status
0
RX FIFO C
status
0
RX FIFO B
status
0
RX FIFO A
status
0
TX FIFO D
status
0
TX FIFO C
status
0
TX FIFO B
status
0
TX FIFO A status
0
REGISTER
R/W
This register is only accessible when EFR[4] = 1 and MCR[6] = 1
This register is accessible when any CS A-B = 0, MCR[2] = 1, and loopback MCR[4] = 0 is disabled
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8.5.2 Receiver Holding Register (RHR)
The receiver section consists of the RHR and the receiver shift register (RSR). The RHR is actually a 64-byte
FIFO. The RSR receives serial data from RX terminal. The data is converted to parallel data and moved to the
RHR. The receiver section is controlled by the line control register. If the FIFO is disabled, location 0 of the FIFO
is used to store the characters. If overflow occurs, characters are lost. The RHR also stores the error status bits
associated with each character.
8.5.3 Transmit Holding Register (THR)
The transmitter section consists of the THR and the transmitter shift register (TSR). The transmit holding register
is actually a 64-byte FIFO. The THR receives data and shifts it into the TSR where it is converted to serial data
and moved out on the TX terminal. If the FIFO is disabled, location 0 of the FIFO is used to store the byte.
Characters are lost if overflow occurs.
8.5.4 FIFO Control Register (FCR)
This is a write-only register which is used for enabling the FIFOs, clearing the FIFOs, setting transmitter and
receiver trigger levels, and selecting the type of DMA signaling. Table 8 shows FIFO control register bit settings.
Table 8. FCR Bit Settings
BIT
0
1
0 = No change
1 = Clears the receive FIFO and resets its counter logic to 0. Returns to 0 after clearing FIFO.
2
0 = No change
1 = Clears the transmit FIFO and resets its counter logic to 0. Returns to 0 after clearing FIFO.
3
0 = DMA mode 0
1 = DMA mode 1
5:4
(1)
7:6
(1)
32
BIT SETTINGS
0 = Disable the transmit and receive FIFOs
1 = Enable the transmit and receive FIFOs
Sets the trigger level for the TX FIFO:
00 – 8 spaces
01 – 16 spaces
10 – 32 spaces
11 – 56 spaces
Sets the trigger level for the RX FIFO:
00 – 1 characters
01 – 4 characters
10 – 56 characters
11 – 60 characters
FCR[5−4] can be modified and enabled only when EFR[4] is set. This is because the transmit trigger level is regarded as an enhanced
function.
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8.5.5 Line Control Register (LCR)
This register controls the data communication format. The word length, number of stop bits, and parity type are
selected by writing the appropriate bits to the LCR. Table 9 shows line control register bit settings.
Table 9. LCR Bit Settings
BIT
1:0
BIT SETTINGS
Specifies the word length to be transmitted or received
00 – 5 bits
01 – 6 bits
10 − 7 bits
11 – 8 bits
2
Specifies the number of stop bits:
0 – 1 stop bits (Word length = 5, 6, 7, 8)
1 – 1.5 stop bits (Word length = 5)
1 – 2 stop bits (Word length = 6, 7, 8) 3
3
0 = No parity
1 = A parity bit is generated during transmission and the receiver checks for received parity.
4
0 = Odd parity is generated (if LCR[3] = 1)
1 = Even parity is generated (if LCR[3] = 1)
5
Selects the forced parity format (if LCR(3) = 1)
If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data.
If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received data.
6
Break control bit
0 = Normal operating condition
1 = Forces the transmitter output to go low to alert the communication terminal.
7
0 = Normal operating condition
1 = Divisor latch enable
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8.5.6 Line Status Register (LSR)
Table 10 shows line status register bit settings.
Table 10. LSR Bit Settings
BIT
BIT SETTINGS
0
0 = No data in the receive FIFO
1 = At least one character in the RX FIFO
1
0 = No overrun error
1 = Overrun error has occurred.
2
0 = No parity error in data being read from RX FIFO
1 = Parity error in data being read from RX FIFO
3
0 = No framing error in data being read from RX FIFO
1 = Framing error occurred in data being read from RX FIFO (that is, received data did not have a valid stop bit)
4
0 = No break condition
1 = A break condition occurred and associated byte is 00 (that is, RX was low for at least one character time frame)
5
0 = Transmit hold register is not empty
1 = Transmit hold register is empty. The processor can now load up to 64 bytes of data into the THR if the TX FIFO is
enabled.
6
0 = Transmitter hold and shift registers are not empty.
1 = Transmitter hold and shift registers are empty.
7
0 = Normal operation
1 = At least one parity error, framing error or break indication are stored in the receiver FIFO. Bit 7 is cleared when no
errors are present in the FIFO.
When the LSR is read, LSR[4:2] reflects the error bits [BI, FE, PE] of the character at the top of the RX FIFO
(next character to be read). The LSR[4:2] registers do not physically exist, as the data read from the RX FIFO is
output directly onto the output data-bus, DI[4:2], when the LSR is read. Therefore, errors in a character are
identified by reading the LSR and then reading the RHR.
LSR[7] is set when there is an error anywhere in the RX FIFO and is cleared only when there are no more errors
remaining in the FIFO.
NOTE
Reading the LSR does not cause an increment of the RX FIFO read pointer. The RX FIFO
read pointer is incremented by reading the RHR.
34
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8.5.7 Modem Control Register (MCR)
The MCR controls the interface with the modem, data set, or peripheral device that is emulating the modem.
Table 11 shows modem control register bit settings.
Table 11. MCR Bit Settings (1)
BIT
(1)
BIT SETTINGS
0
0 = Force DTR output to inactive (high)
1 = Force DTR output to active (low). In loopback controls MSR[5]
1
0 = Force RTS output to inactive (high)
1 = Force RTS output to active (low)
In loopback controls MSR[4]
If Auto-RTS is enabled the RTS output is controlled by hardware flow control
2
0 Disables the FIFORdy register
1 Enable the FIFORdy register
In loopback controls MSR[6]
3
0 = Forces the IRQ(A-B) outputs to high-impedance state
1 = Forces the IRQ(A-B) outputs to the active state
In loopback controls MSR[7]
4
0 = Normal operating mode
1 = Enable local loopback mode (internal)
In this mode, the MCR[3:0] signals are looped back into MSR[3:0] and the TX output is looped back to the RX input
internally
5
0 = Disable Xon Any function
1 = Enable Xon Any function
6
0 = No action
1 = Enable access to the TCR and TLR registers
7
0 = Divide by one clock input
1 = Divide by four clock input
This bit reflects the inverse of the CLKSEL pin value at the trailing edge of the RESET pulse
MCR[7:5] can be modified only when EFR[4] is set, that is, EFR[4] is a write enable.
8.5.8 Modem Status Register (MSR)
This 8-bit register provides information about the current state of the control lines from the modem, data set, or
peripheral device to the processor. It also indicates when a control input from the modem changes state.
Table 12 shows modem status register bit settings.
Table 12. MSR Bit Settings (1)
BIT
(1)
BIT SETTINGS
0
Indicates that CTS input (or MCR[1] in loopback) has changed state. Cleared on a read.
1
Indicates that DSR input (or MCR[0] in loopback) has changed state. Cleared on a read.
2
Indicates that RI input (or MCR[2] in loopback) has changed state from low to high. Cleared on a read.
3
Indicates that CD input (or MCR[3] in loopback) has changed state. Cleared on a read.
4
This bit is equivalent to MCR[1] during local loop-back mode. It is the complement to the CTS input.
5
This bit is equivalent to MCR[0] during local loop-back mode. It is the complement to the DSR input.
6
This bit is equivalent to MCR[2] during local loop-back mode. It is the complement to the RI input.
7
This bit is equivalent to MCR[3] during local loop-back mode. It is the complement to the CD input.
The primary inputs RI, CD, CTS, and DSR are all active low, but their registered equivalents in the MSR and MCR (in loopback)
registers are active high.
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8.5.9 Interrupt Enable Register (IER)
The interrupt enable register (IER) enables each of the six types of interrupt, receiver error, RHR interrupt, THR
interrupt, Xoff received, or CTS/RTS change of state from low to high. The INT output signal is activated in
response to interrupt generation. Table 13 shows interrupt enable register bit settings.
Table 13. Interrupt Enable Register (IER) Bit Settings (1)
BIT
(1)
36
BIT SETTINGS
0
0 = Disable the RHR interrupt
1 = Enable the RHR interrupt
1
0 = Disable the THR interrupt
1 = Enable the THR interrupt
2
0 = Disable the receiver line status interrupt
1 = Enable the receiver line status interrupt
3
0 = Disable the modem status register interrupt
1 = Enable the modem status register interrupt
4
0 = Disable sleep mode
1 = Enable sleep mode
5
0 = Disable the Xoff interrupt
1 = Enable the Xoff interrupt
6
0 = Disable the RTS interrupt
1 = Enable the RTS interrupt
7
0 = Disable the CTS interrupt
1 = Enable the CTS interrupt
IER[7:4] can be modified only if EFR[4] is set, that is, EFR[4] is a write enable.
Re-enabling IER[1] causes a new interrupt, if the THR is below the threshold.
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8.5.10 Interrupt Identification Register (IIR)
The IIR is a read-only 8-bit register, which provides the source of the interrupt in a prioritized manner. Table 14
shows interrupt identification register bit settings.
Table 14. IIR Bit Settings
BIT
BIT SETTINGS
0 = An interrupt is pending
1 = No interrupt is pending
0
3:1
3-Bit encoded interrupt. See Table 13
4
1 = Xoff or special character has been detected
5
CTS/RTS low to high change of state
7:6
Mirror the contents of FCR[0]
The interrupt priority list is illustrated in Table 15.
Table 15. Interrupt Priority List
PRIORITY
LEVEL
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
1
0
0
0
1
1
0
Receiver line status error
2
0
0
1
1
0
0
Receiver timeout interrupt
2
0
0
0
1
0
0
RHR interrupt
3
0
0
0
0
1
0
THR interrupt
4
0
0
1
0
0
0
Modem interrupt
5
0
1
0
0
0
0
Received Xoff signal or special character
6
1
0
0
0
0
0
CTS, RTS change of state from active (low) to inactive (high)
INTERRUPT SOURCE
8.5.11 Enhanced Feature Register (EFR)
This 8-bit register enables or disables the enhanced features of the UART. Table 16 shows the enhanced feature
register bit settings.
Table 16. EFR Bit Settings
BIT
3:0
BIT SETTINGS
Combinations of software flow control can be selected by programming bit 3 to bit 0. See Table 1.
4
Enhanced functions enable bit.
0 = Disables enhanced functions and writing to IER[7:4], FCR[5:4], MCR[7:5]
1 = Enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5] can be modified, that is, this bit is therefore a
write enable
5
0 = Normal operation
1 = Special character detect. Received data is compared with Xoff-2 data. If a match occurs, the received data is
transferred to FIFO and IIR[4] is set to 1 to indicate a special character has been detected.
6
RTS flow control enable bit
0 = Normal operation
1 = RTS flow control is enabled, that is, RTS pin goes high when the receiver FIFO HALT trigger level TCR[3:0] is
reached, and goes low when the receiver FIFO RESTORE transmission trigger level TCR[7:4] is reached.
7
CTS flow control enable bit
0 = Normal operation
1 = CTS flow control is enabled, that is, transmission is halted when a high signal is detected on the CTS pin
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8.5.12 Divisor Latches (DLL, DLH)
Two 8-bit registers store the 16-bit divisor for generation of the baud clock in the baud rate generator. DLH,
stores the most significant part of the divisor. DLL stores the least significant part of the division.
DLL and DLH can only be written to before sleep mode is enabled (that is, before IER[4] is set).
8.5.13 Transmission Control Register (TCR)
This 8-bit register is used to store the receive FIFO threshold levels to start or stop transmission during hardware
or software flow control. Table 17 shows transmission control register bit settings.
Table 17. TCR Bit Settings
BIT
BIT SETTINGS
3:0
RCV FIFO trigger level to HALT transmission (0 to 60)
7:4
RCV FIFO trigger level to RESTORE transmission (0 to 60)
TCR trigger levels are available from 0 to 60 bytes with a granularity of four.
TCR can be written to only when EFR[4] = 1 and MCR[6] = 1. The programmer must program the TCR such that
TCR[3:0] > TCR[7:4]. There is no built-in hardware check to make sure this condition is met. Also, the TCR must
be programmed with this condition before Auto-RTS or software flow control is enabled to avoid spurious
operation of the device.
8.5.14 Trigger Level Register (TLR)
This 8-bit register is used to store the transmit and received FIFO trigger levels used for DMA and interrupt
generation. Trigger levels from 4 to 60 can be programmed with a granularity of 4. Table 18 shows trigger level
register bit settings.
Table 18. TLR Bit Settings
BIT
BIT SETTINGS
3:0
Transmit FIFO trigger levels (4 to 60), number of spaces available
7:4
RCV FIFO trigger levels (4 to 60), number of characters available
TLR can be written to only when EFR[4] = 1 and MCR[6] = 1. If TLR[3:0] or TLR[7:4] are 0, then the selectable
trigger levels via the FIFO control register (FCR) are used for the transmit and receive FIFO trigger levels.
Trigger levels from 4 to 60 bytes are available with a granularity of 4. The TLR should be programmed for N / 4,
where N is the desired trigger level.
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8.5.15 FIFO Ready Register
The FIFO ready register provides realtime status of the transmit and receive FIFOs of both channels. Table 19
shows the FIFO ready register bit settings. The trigger level mentioned in Table 19 refers to the setting in either
FCR (when TLR value is 0), or TLR (when it has a nonzero value).
Table 19. FIFO Ready Register
BIT
BIT SETTINGS
0
0 = There are fewer than a TX trigger level number of spaces available in the TX FIFO of channel A.
1 = There are at least a TX trigger level number of spaces available in the TX FIFO of channel A.
1
0 = There are fewer than a TX trigger level number of spaces available in the TX FIFO of channel B.
1 = There are at least a TX trigger level number of spaces available in the TX FIFO of channel B.
3:2
Unused, always 0
4
0 = There are fewer than a RX trigger level number of characters in the RX FIFO of channel A.
1 = The RX FIFO of channel A has more than a RX trigger level number of characters available for reading or a timeout
condition has occurred.
5
0 = There are fewer than a RX trigger level number of characters in the RX FIFO of channel B.
1 = The RX FIFO of channel B has more than a RX trigger level number of characters available for reading or a timeout
condition has occurred.
7:6
Unused, always 0
The FIFORdy register is a read only register and can be accessed when any of the two UARTs are selected.
CSA or CSB = 0, MCR[2] (FIFORdy Enable) is a logic 1, and loopback is disabled. Its address is 111.
8.5.16 Alternate Function Register (AFR)
The AFR is used to enable some extra functionality beyond the capabilities of the original TL16C752B. The first
of these is a concurrent write mode, which can be useful in more expediently setting up all four UART channels.
The second addition is the IrDA mode, which supports Standard IrDA (SIR) mode with baud rates from 2400 to
115.2 bps. The third addition is support for RS-485 bus drivers or transceivers by providing an output pin (DTRx)
per channel, which is timed to keep the RS-485 driver enabled as long as transmit data is pending.
The AFR is located at A[2:0] = 010 when LCR[7:5] = 100.
Table 20. AFR Bit Settings
BIT
BIT SETTINGS
0
CONC enables the concurrent write of all four (754) or two (752) channels simultaneously, which helps speed up
initialization. Ensure that any indirect addressing modes have been enabled before using.
1
IREN enables the IrDA SIR mode. This mode is only specified to 115.2 bps; TI does not recommend the use of this
mode at higher speeds.
2
485EN enables the half duplex RS-485 mode and causes the DTRx output to be set high whenever there is any data in
the THR or TSR and to be held high until the delay set by DLY2:0 has expired, at which time it is set low. The DTRx
output is intended to drive the enabled input of an RS-485 driver. When this bit is set, the transmitter interrupts are held
off until the TSR is empty, unless 485LG is set.
3
485LG is set when the 485EN is set. This bit indicates that a relatively large data block is being set, requiring more than
a single load of the xmt fifo. In this case, the transmitter interrupts occur as in the standard RS-232 mode, either when
the xmt fifo contents drop below the xmt threshold or when the xmt fifo is empty.
4
RCVEN is valid only when 485EN or IREN is set, and allows the serial receiver to listen in or snoop on the RS485 traffic
or IrDA traffic. RS485 mode is generally considered half duplex, and usually a node is either driving or receiving, but
there can be cases when it is advantageous to verify what you are sending. This can be used to detect collisions or as
part of an arbitration mechanism on the bus. When both RCVEN and 485EN are set, the receiver stores any data
presented on RX, if any. Note that implies that the external RS485 receiver is enabled. Whenever 485EN is cleared, the
serial receiver is enabled for normal full duplex RS232 traffic. If RCVEN is cleared while 485EN is set, the receiver is
disabled while that channel is transmitting. SIR is also considered half duplex. Often the light energy from the transmitting
LED is coupled back into the receiving PIN diode, which creates an input data stream that is not of interest to the host.
Disabling the receiver (clearing RCVEN) prevents this reception, and eliminates the task of unloading the data. On the
other hand, for diagnostic or other purposes, it may be useful to observe this data stream. For example, a mirror could be
used to intentionally couple the output LED to the input PIN. For these cases, RCVEN could be set to enable the
receiver.
NOTE: When RCVEN is cleared (set to 0), the character timeout interrupt is not available, even in RSA-232 mode. This
can be useful when checking code for valid threshold interrupts, as the timeout interrupt will not override the threshold
interrupt.
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Table 20. AFR Bit Settings (continued)
BIT
7:5
BIT SETTINGS
DLY2 to DLY0 sets a delay after the last stop bit of the last data byte being set before the DTRx is set low, to allow for
long cable runs. The delay is in number of bit times and is enabled by 485EN. The delay starts only when both the xmt
serial shift register (TSR) is empty and the xmt fifo (THR) is empty, and if started, will be cleared by any data being
written to the THR.
Table 21. LOOP and RCVEN Functionality
LOOP MODE
RCVEN
RCVEN = 1
LOOP mode off,
MCR4 = 0,
RX, TX active
RCVEN = 0
RCVEN = 1
LOOP mode on,
MCR4 = 1,
RX, TX inactive
RCVEN = 0
AFR
MODE
DESCRIPTION
AFR = 10
RS-232
Receive threshold, timeout, and error detection interrupts available
Data stored in receive FIFO
AFR = 14
RS-485
Receive threshold, timeout, and error detection interrupts available
Data stored in receive FIFO
AFR = 12
IrDA
Receive threshold, timeout, and error detection interrupts available
Data stored in receive FIFO
AFR = 00
RS-232
Receive threshold and error detection interrupts available
Data stored in receive FIFO
AFR = 04
RS-485
No data stored in receive FIFO, hence no interrupts available
AFR = 02
IrDA
No data stored in receive FIFO, hence no interrupts available
AFR = 10
RS-232
Receive threshold, timeout, and error detection interrupts available
Data stored in receive FIFO
AFR = 14
RS-485
Receive threshold, timeout, and error detection interrupts available
Data stored in receive FIFO
AFR = 12
IrDA
Receive threshold, timeout, and error detection interrupts available
Data stored in receive FIFO
AFR = 00
RS-232
Receive threshold and error detection interrupts available
Data stored in receive FIFO
AFR = 04
RS-485
Receive threshold and error detection interrupts available
Data stored in receive FIFO
AFR = 02
IrDA
Receive threshold and error detection interrupts available
Data stored in receive FIFO
8.5.17 RS-485 Mode
The RS-485 mode is intended to simplify the interface between the UART channel and an RS-485 driver or
transceiver. When enabled by setting 485EN, the DTRx output goes high one bit time before the first stop bit of
the first data byte being sent, and remains high as long as there is pending data in the TSR or THR (xmt fifo).
After both are empty (after the last stop bit of the last data byte), the DTRx output stays high for a programmable
delay of 0 to 15 bit times, as set by DLY[2:0]. This helps preserve data integrity over long signal lines. This is
illustrated in the following.
Often RS-485 packets are relatively short and the entire packet can fit within the 64 byte xmt fifo. In this case, it
goes empty when the TSR goes empty. But in cases where a larger block needs to be sent, it is advantageous to
reload the xmt fifo as soon as it is depleted. Otherwise, the transmission stalls while waiting for the xmt fifo to be
reloaded, which varies with processor load. In this case, it is best to also set 485LG (large block), which causes
the transmit interrupt to occur wither when the THR becomes empty (if the xmt fifo level was not above the
threshold), or when the xmt fifo threshold is crossed. The reloading of the xmt fifo occurs while some data is
being shifted out, eliminating fifo underrun. If desired, when the last bytes of a current transmission are being
loaded in the xmt fifo, 485LG can be cleared before the load and the transmit interrupt occurs on the TSR going
empty.
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WR THR
TX
1 Baud Time
Controlled by DLY[2:0]
DTRx
A.
Waveforms are not shown to scale, as the WR THR pulses typically are less than 100 ns, where the TX waveform
varies with baud rate but is typically in the microsecond range.
Figure 27. DTRx and Transmit Data Relationship
RS-485 XCVR
TX
TSR
RS-485 BUS
DEN
DTR
Loopback
REN
RX
RSR
48SEN
RCVEN
UART
Figure 28. RS-485 Application Example 1
RS-485 XCVR
TX
TSR
DTR
Loopback
RS-485 BUS
DEN
REN
RX
RSR
48SEN
RCVEN
UART
Figure 29. RS-485 Application Example 2
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8.5.18 IrDA Overview
Transmit Shift Register
Receive Shift Register
Int_TX
TX
To Optoelectronic
LED
Int_RX
RX
From
Optoelectronic
Pin Diode
IREN
IrDA Converter
RCVEN
Baud Clock
Reset
Figure 30. IrDA Mode
The IrDA defines several protocols for sending and receiving serial infrared data, including rates of 115.2 kbps,
0.576 Mbps, 1.152 Mbps, and 4 Mbps. The low rate of 115.2 kbps was specified first and the others must
maintain downward compatibility with it. At the 115.2 kbps rate, the protocol implemented in the hardware is fairly
simple. It primarily defines a serial infrared data word to be surrounded by a start bit equal to 0 and a stop bit
equal to 1. Individual bits are encoded or decoded the same whether they are start, data, or stop bits. The IrDA
engine in the TL16C752CI-Q1 device only evaluates single bits and follows the 115.2-kbps protocol. The 115.2kbps rate is a maximum rate. When both ends of the transfer are setup to a lower but matching speed, the
protocol still works. The clock used to code or sample the data is 16 times the baud rate, or 1.843-MHz
maximum. To code a 1, no pulse is sent or received for 1-bit time period, or 16 clock cycles. To code a 0, one
pulse is sent or received within a 1-bit time period, or 16 clock cycles. The pulse must be at least 1.6-μs wide
and 3 clock cycles long at 1.843 MHz. At lower baud rates the pulse can be 1.6 μs wide or as long as 3 clock
cycles. The transmitter output, TX, is intended to drive a LED circuit to generate an infrared pulse. The LED
circuits work on positive pulses. A terminal circuit is expected to create the receiver input, RX. Most, but not all,
PIN circuits have inversion and generate negative pulses from the detected infrared light. Their output is normally
high. The TL16C752CI-Q1 device can decode either negative or positive pulses on RX.
8.5.19 IrDA Encoder Function
Serial data from a UART is encoded to transmit data to the optoelectronics. While the serial data input to this
block (Int_TX) is high, the output (TX) is always low, and the counter used to form a pulse on TX is continuously
cleared. After Int_TX resets to 0, TX rises on the falling edge of the 7th 16XCLK. On the falling edge of the 10th
16XCLK pulse, TX falls, creating a 3-clock-wide pulse. While Int_TX stays low, a pulse is transmitted during the
seventh to tenth clocks of each 16-clock bit cycle.
16 Cycles
Int_TX
16 Cycles
16 Cycles
16 Cycles
16XCLK
16XCLK
Int_TX
1 2 3 4 5 6 7 8
10
12
14
16
TX
TX
Figure 31. IrDA-SIR Encoding Scheme – Detailed
Timing Diagram
Figure 32. Encoding Scheme – Macro View
After reset, Int_RX is high and the 4-bit counter is cleared. When a falling edge is detected on RX, Int_RX falls
on the next rising edge of 16XCLK with sufficient setup time. Int_RX stays low for 16 cycles (16XCLK) and then
returns to high as required by the IrDA specification. As long as no pulses (falling edges) are detected on RX,
Int_RX remains high.
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16 Cycles
Int_TX
16 Cycles
16 Cycles
16 Cycles
16XCLK
RX
16XCLK
1 2 3 4 5 6 7 8
10
12
14
16
Int_RX
TX
Figure 33. IrDA-SIR Decoding Scheme – Detailed
Timing Diagram
Figure 34. IrDA-SIR Decoding Scheme – Macro
View
It is possible for jitter or slight frequency differences to cause the next falling edge on RX to be missed for one
16XCLK cycle. In that case, a 1-clock-wide pulse appears on Int_RX between consecutive 0s. It is important for
the UART to strobe Int_RX in the middle of the bit time to avoid latching this 1-clock-wide pulse. The TL16C550C
UART already strobes incoming serial data at the proper time. Otherwise, note that data is required to be framed
by a leading 0 and a trailing 1. The falling edge of that first 0 on Int_RX synchronizes the read strobe. The strobe
occurs on the 8th 16XCLK pulse after the Int_RX falling edge and once every 16 cycles thereafter until the stop
bit occurs.
RX
16XCLK
1 2 3 4 5 6 7 8
10
12
14
16
1 2 3
4 5 6 7 8
10
12
14
16
Int_RX
Figure 35. Timing Causing 1-Clock-Wide Pulse Between Consecutive Ones
16 Cycles
16 Cycles
16XCLK
RX
Int_RX
External Strobe
7 Cycles
16 Cycles
Figure 36. Recommended Strobing for Decoded Data
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The TL16C752CI-Q1 device can decode positive pulses on RX. The timing is different, but the variation is
invisible to the UART. The decoder, which works from the falling edge, now recognizes a 0 on the trailing edge of
the pulse rather than on the leading edge. As long as the pulse duration is fairly constant, as defined by the
specification, the trailing edges should also be 16 clock cycles apart and data can readily be decoded. The 0
appears on Int_RX after the pulse rather than at the start of it.
RX
16XCLK
1
2
3
4
5
6
7
8
10
12
14
16
Int_RX
Figure 37. Positive RX Pulse Decode – Detailed View
16
Cycles
16
Cycles
16
Cycles
16
Cycles
16XCLK
RX
Int_RX
Figure 38. Positive RX Pulse Decode – Macro View
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The typical implementation is to use the TL16C752CI-Q1 as a dual RS-232 interface, which is intended to
operate with a 5-V microprocessor.
9.2 Typical Application
Voltage
Regulator
UART Ch 1
Data
MAX232
Address
Microcontroller
IOW, IOR, Reset
TL16C752C
Chip Select
UART Ch 2
Int and RDY
MAX232
XTAL1
XTAL2 (optional)
Crystal/
Oscillator
1.8432 MHz
Figure 39. Typical Application Dual RS-232 Interface
9.2.1 Design Requirements
Include the recommended operating conditions for 3.3 V provided by the controller board, but with the input clock
equal to 1.8432 MHz, and include the Operating free-air temperature conditions. The controller must have two 8bit ports, one for the control signals and another for the I/O data. A third port is optional to monitor the
interruptions and TX/RX ready signals (if it is needed).
9.2.2 Detailed Design Procedure
1. Implement the schematic as is shown in Figure 39.
2. Implement on the controller the READ and WRITE routines to meet the timing requirements of the Timing
Requirements, use Figure 1 and Figure 2 as a guideline.
3. Initialize all the configuration registers. TI recommends not to obviate the default settings and initialize all of
the set of configuration registers. The base set of registers that are used during high-speed data transfer
have a straightforward access method. The extended function registers require special access bits to be
decoded along with the address lines. The following guide helps with programming these registers. Note that
the descriptions are for individual register access. Some streamlining through interleaving can be obtained
when programming all the registers.
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Typical Application (continued)
(a) Set baud rate to VALUE1, VALUE2 Read LCR (03), save in temp Set LCR (03) to 80 Set DLL (00) to
VALUE1 Set DLM (01) to VALUE2 Set LCR (03) to temp
(b) Set Xoff1, Xon1 to VALUE1, VALUE2 Read LCR (03), save in temp Set LCR (03) to BF Set Xoff1 (06) to
VALUE1 Set Xon1 (04) to VALUE2 Set LCR (03) to temp
(c) Set Xoff2, Xon2 to VALUE1, VALUE2 Read LCR (03), save in temp Set LCR (03) to BF Set Xoff2 (07) to
VALUE1 Set Xon2 (05) to VALUE2 Set LCR (03) to temp
(d) Set software flow control mode to VALUE Read LCR (03), save in temp Set LCR (03) to BF Set EFR
(02) to VALUE Set LCR (03) to temp
(e) Set flow control threshold to VALUE Read LCR (03), save in temp1 Set LCR (03) to BF Read EFR (02),
save in temp2 Set EFR (02) to 10 + temp2 Set LCR (03) to 00 Read MCR (04), save in temp3 Set MCR
(04) to 40 + temp3 Set TCR (06) to VALUE Set LCR (03) to BF Set EFR (02) to temp2 Set LCR (03) to
temp1 Set MCR (04) to temp3
(f) Set xmt and rcv FIFO thresholds to VALUE Read LCR (03), save in temp1 Set LCR (03) to BF Read
EFR (02), save in temp2 Set EFR (02) to 10 + temp2 Set LCR (03) to 00 Read MCR (04), save in temp3
Set MCR (04) to 40 + temp3 Set TLR (07) to VALUE Set LCR (03) to BF Set EFR (02) to temp2 Set
LCR (03) to temp1 Set MCR (04) to temp3
(g) Read FIFORdy register Read MCR (04), save in temp1 Set temp2 = temp1 × EF Set MCR (04), save in
temp2 Read FRR (07), save in temp2 Pass temp2 back to host Set MCR (04) to temp1
The designer can use Figure 39 as a guideline to configure each channel of the UART.
9.2.3 Application Curves
Figure 40. Typical Two Bytes Transmission With 6 Bits of
Data (0x15 and 0X21), Odd Parity and One Stop Bit
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Figure 41. Typical Fall Time
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Typical Application (continued)
Figure 42. Typical Rise Time
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10 Power Supply Recommendations
The power supply must provide a constant voltage with a 10% maximum variation of the nominal value and has
to be able to provide at least the maximum current consumption of the device for the selected nominal voltage
only for the UART device:
• 4.5 mA for VCC = 1.8 V
• 9 mA for VCC = 2.5 V
• 16 mA for VCC = 3.3 V
• 40 mA for VCC = 5 V
The VCC pin must have a 1-µF bypass capacitor placed as close as possible to this pin. Also, TI recommends to
include two extra capacitors in parallel, which should also be placed as close as possible to the VCC pin. The
suggested values for these extra capacitors are 0.1 µF and 0.01 µF, respectively.
VCC_UART
C14
C15
C16
1 µF
0.1 µF
0.01 µF
Place as close as possible to the VCC pin of the UART.
Figure 43. Recommended Bypass Capacitors Array
11 Layout
11.1 Layout Guidelines
Traces, Vias, and Other PCB Components: A right angle in a trace can cause more radiation. The capacitance
increases in the region of the corner, and the characteristic impedance changes. This impedance change causes
reflections.
• Avoid right-angle bends in a trace and try to route them at least with two 45° corners. To minimize any
impedance change, the best routing would be a round bend (see Figure 24).
• Separate high-speed signals (for example, clock signals) from low-speed signals and digital from analog
signals; again, placement is important.
• To minimize crosstalk not only between two signals on one layer but also between adjacent layers, route
them with 90° to each other
Figure 44. Layout Do's and Don'ts
48
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Product Folder Links: TL16C752CI-Q1
TL16C752CI-Q1
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SLLSEQ9A – OCTOBER 2015 – REVISED FEBRUARY 2016
11.2 Layout Example
Figure 45. RS232 Channel Layout Example
Figure 46. Footprint Example
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Product Folder Links: TL16C752CI-Q1
49
TL16C752CI-Q1
SLLSEQ9A – OCTOBER 2015 – REVISED FEBRUARY 2016
www.ti.com
12 Device and Documentation Support
12.1 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
50
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Product Folder Links: TL16C752CI-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
TL16C752CIPFBRQ1
ACTIVE
TQFP
PFB
48
1000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
T16C752DQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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