TL3472QDRQ1

TL3472-Q1 www.ti.com SLOS573 – MARCH 2008 HIGH-SLEW-RATE SINGLE-SUPPLY OPERATIONAL AMPLIFIER FEATURES 1 • • • • • • • Qualified for Automotive Applications Wide Gain-Bandwidth Product: 4 MHz High Slew Rate: 13 V/µs Fast Settling Time: 1.1 µs to 0.1% Wide-Range Single-Supply Operation: 4 V to 36 V Wide Input Common-Mode Range Includes Ground (VCC–) Low Total Harmonic Distortion: 0.02% • • Large-Capacitance Drive Capability: 10,000 pF Output Short-Circuit Protection D PACKAGE (TOP VIEW) 1OUT 1 8 VCC+ 1IN– 2 7 2OUT 1IN+ 3 6 2IN– VCC–/GND 4 5 2IN+ DESCRIPTION/ORDERING INFORMATION Quality, low-cost, bipolar fabrication with innovative design concepts is employed for the TL3472 operational amplifier. This device offers 4 MHz of gain-bandwidth product, 13-V/µs slew rate, and fast settling time, without the use of JFET device technology. Although the TL3472 can be operated from split supplies, it is particularly suited for single-supply operation because the common-mode input voltage range includes ground potential (VCC–). With a Darlington transistor input stage, this device exhibits high input resistance, low input offset voltage, and high gain. The all-npn output stage, characterized by no dead-band crossover distortion and large output voltage swing, provides high-capacitance drive capability, excellent phase and gain margins, low open-loop high-frequency output impedance, and symmetrical source/sink ac frequency response. This low-cost amplifier is an alternative to the MC33072 and the MC34072 operational amplifiers. ORDERING INFORMATION (1) PACKAGE (2) TA –40°C to 125°C (1) (2) SOIC – D Reel of 2500 ORDERABLE PART NUMBER TL3472QDRQ1 TOP-SIDE MARKING T3472Q For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated TL3472-Q1 www.ti.com SLOS573 – MARCH 2008 SCHEMATIC (EACH AMPLIFIER) VCC+ OUT IN- IN+ VCC- /GND 2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated TL3472-Q1 www.ti.com SLOS573 – MARCH 2008 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VCC+ VCC– 18 V Supply voltage (2) –18 V VID Differential input voltage ±36 V VI Input voltage (any input) VCC± II Input current (each input) ±1 mA IO Output current ±80 mA Total current into VCC+ 80 mA Total current out of VCC– 80 mA Duration of short-circuit current at (or below) 25°C (3) θJA Package thermal impedance (4) (5) TJ Operating virtual junction temperature Unlimited 97°C/W 150°C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds Tstg (1) (2) (3) (4) (5) 260°C Storage temperature range –65°C to 150°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC–. The output can be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum dissipation rating is not exceeded. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can impact reliability. The package thermal impedance is calculated in accordance with JESD 51-7. RECOMMENDED OPERATING CONDITIONS MIN VCC± Supply voltage VIC Common-mode input voltage TA Operating free-air temperature Copyright © 2008, Texas Instruments Incorporated VCC = 5 V VCC± = ±15 V MAX 4 36 0 2.8 –15 12.8 –40 125 Submit Documentation Feedback UNIT V V °C 3 TL3472-Q1 www.ti.com SLOS573 – MARCH 2008 ELECTRICAL CHARACTERISTICS at specified free-air temperature, VCC± = ±15 V (unless otherwise noted) PARAMETER TEST CONDITIONS VCC = 5 V VIC = 0, VO = 0, RS = 50 Ω VIO Input offset voltage αVIO Temperature coefficient of input offset voltage VIC = 0, VO = 0, RS = 50 Ω VCC = ±15 V IIO Input offset current VIC = 0, VO = 0, RS = 50 Ω VCC = ±15 V IIB Input bias current VIC = 0, VO = 0, RS = 50 Ω VCC = ±15 V VICR Common-mode input voltage range VCC = ±15 V High-level output voltage RL = 10 kΩ RL = 2 kΩ VOL Low-level output voltage 1.5 16 25°C 1 17 Full range Full range 10 25°C 6 Full range 75 300 25°C 100 Full range 500 700 25°C –15 to 12.8 Full range –15 to 12.8 25°C 3.7 4 25°C 13.6 14 Full range 13.4 0.1 0.3 –14.3 RL = 2 kΩ Full range CMRR Common-mode rejection ratio VIC = VICR(min), RS = 50 Ω kSVR Supply-voltage rejection ratio (ΔVCC±/ΔVIO) VCC± = ±13.5 V to ±16.5 V, RS = 100 Ω ICC Supply current (per channel) Source: VID = 1 V, VO = 0 Sink: VID = –1 V, VO = 0 VO = 0, No load VCC+ = 5 V, VO = 2.5 V, VCC– = 0, No load nA V –14.7 Short-circuit output current nA V 25°C IOS mV µV/°C 25°C VO = ±10 V, RL = 2 kΩ UNIT 22 RL = 10 kΩ Large-signal differential voltage amplification 4 MAX 25°C VCC+ = 5 V, VCC– = 0, RL = 2 kΩ AVD (1) (2) MIN TYP (2) RS = 50 Ω VCC+ = 5 V, VCC– = 0, RL = 2 kΩ VOH TA (1) V –13.5 25°C 25 Full range 20 100 V/mV –10 –34 20 27 25°C 65 97 dB 25°C 70 97 dB 25°C mA 25°C 3.5 4.5 Full range 4.5 5.5 25°C 3.5 4.5 mA Full range TA = –40°C to 125°C All typical values are at TA = 25°C. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated TL3472-Q1 www.ti.com SLOS573 – MARCH 2008 OPERATING CHARACTERISTICS VCC± = ±15 V, TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 8 10 V/µs AV = –1 13 V/µs To 0.1% 1.1 To 0.01% 2.2 SR+ Positive slew rate VI = –10 V to 10 V, RL = 2 kΩ, CL = 300 pF SR– Negative slew rate VI = –10 V to 10 V, RL = 2 kΩ, CL = 300 pF ts Settling time AVD = –1, 10-V step Vn Equivalent input noise voltage f = 1 kHz, RS = 100 Ω 49 nV/√Hz In Equivalent input noise current f = 1 kHz 0.22 pA/√Hz THD Total harmonic distortion VO(PP) = 2 V to 20 V, RL = 2 kΩ, AVD = 10, f = 10 kHz 0.02 % GBW Gain-bandwidth product f =100 kHz BW Power bandwidth VO(PP) = 20 V, RL = 2 kΩ, AVD = 1, THD = 5.0% φm AV = 1 3 µs 4 MHz 160 kHz CL = 0 70 CL = 300 pF 50 CL = 0 12 Phase margin RL = 2 kΩ Gain margin RL = 2 kΩ ri Differential input resistance VIC = 0 150 Ci Input capacitance VIC = 0 2.5 pF Channel separation f = 10 kHz 101 dB Open-loop output impedance f = 1 MHz, AV = 1 20 Ω zo Copyright © 2008, Texas Instruments Incorporated CL = 300 pF 4 Submit Documentation Feedback deg dB MΩ 5 PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 ) 4 5 B 8X .012-.020 [0.31-0.51] .010 [0.25] C A B .150-.157 [3.81-3.98] NOTE 4 .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A (.041) [1.04] TYPICAL 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X METAL SOLDER MASK OPENING EXPOSED METAL .0028 MAX [0.07] ALL AROUND SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. 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