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TL2842, TL2843, TL2844, TL2845
TL3842, TL3843, TL3844, TL3845
SLVS038I – JANUARY 1989 – REVISED JULY 2016
TLx84x Current-Mode PWM Controllers
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
•
The TL284x and TL384x series of control integrated
circuits provide the features that are necessary to
implement off-line or DC-to-DC fixed-frequency
current-mode control schemes, with a minimum
number of external components. Some of the
internally implemented circuits are an undervoltage
lockout (UVLO), featuring a start-up current of less
than 1 mA, and a precision reference trimmed for
accuracy at the error amplifier input. Other internal
circuits include logic to ensure latched operation, a
pulse-width modulation (PWM) comparator (that also
provides current-limit control), and a totem-pole
output stage designed to source or sink high-peak
current. The output stage, suitable for driving Nchannel MOSFETs, is low when it is in the off state.
1
Optimized for Off-Line and DC-to-DC Converters
Low Start-Up Current (< 1 mA)
Automatic Feed-forward compensation
Pulse-by-Pulse Current Limiting
Enhanced Load-Response Characteristics
Undervoltage Lockout With Hysteresis
Double-Pulse Suppression
High-Current Totem-Pole Output
Internally Trimmed Bandgap Reference
500-kHz Operation
Error Amplifier With Low Output Resistance
Designed to be Interchangeable with UC2842 and
UC3842 Series
PART NUMBER
2 Applications
•
•
Device Information(1)
Switching regulators of any polarity
Transformer-coupled DC/DC convertors
TLx84x
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
SOIC (14)
8.65 mm × 3.91 mm
PDIP (8)
9.81 mm × 6.35 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Device Pinout Drawing SOIC (14)
COMP
1
14
REF
NC
2
13
NC
VFB
3
12
VCC
NC
4
11
VC
ISENSE
5
10
OUTPUT
NC
6
9
GND
RT/CT
7
8
POWER_GROUND
Device Pinout Drawing SOIC or PDIP (8)
COMP
1
8
REF
VFB
2
7
VCC
ISENSE
3
6
OUTPUT
RT/CT
4
5
GND
Not to scale
NC — No internal connection
Not to scale
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TL2842, TL2843, TL2844, TL2845
TL3842, TL3843, TL3844, TL3845
SLVS038I – JANUARY 1989 – REVISED JULY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
7.4 Device Functional Modes.......................................... 9
8
Application and Implementation ........................ 10
8.1 Typical Application .................................................. 10
9 Power Supply Recommendations...................... 12
10 Layout................................................................... 13
10.1 Layout Guidelines ................................................. 13
10.2 Layout Example .................................................... 14
11 Device and Documentation Support ................. 15
11.1
11.2
11.3
11.4
11.5
11.6
Receiving Notification of Documentation Updates
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
15
15
12 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (January 2015) to Revision I
Page
•
Updated pinout images........................................................................................................................................................... 3
•
Changed TL984x to TL384x in Recommended Operating Conditions................................................................................... 4
•
Changed TLx842, TLx844 to TLx842, TLx843 and TLx843, TLx845 to TLx844, TLx845 in Pulse-Width-Modulator
Section.................................................................................................................................................................................... 6
•
Added Receiving Notification of Documentation Updates section and Community Resources section .............................. 15
Changes from Revision G (February 2008) to Revision H
Page
•
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
2
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SLVS038I – JANUARY 1989 – REVISED JULY 2016
5 Pin Configuration and Functions
D Package
14-Pin SOIC
Top View
D or P Package
8-Pin SOIC or PDIP
Top View
COMP
1
14
REF
NC
2
13
NC
VFB
3
12
VCC
NC
4
11
VC
ISENSE
5
10
OUTPUT
NC
6
9
GND
RT/CT
7
8
POWER_GROUND
COMP
1
8
REF
VFB
2
7
VCC
ISENSE
3
6
OUTPUT
RT/CT
4
5
GND
Not to scale
NC — No internal connection
Not to scale
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
D
D or P
COMP
1
1
I/O
Error amplifier compensation pin
GND
9
5
—
Device power supply ground terminal
ISENSE
5
3
I
2, 4, 6, 13
—
—
Do not connect
OUTPUT
10
6
O
PWM Output
POWER
GROUND
8
—
—
Output PWM ground terminal
REF
14
8
O
Oscillator voltage reference
RT/CT
7
4
I/O
Oscillator RC input
VC
11
—
—
Output PWM positive voltage supply
VCC
12
7
—
Device positive voltage supply
VFB
3
2
I
NC
Copyright © 1989–2016, Texas Instruments Incorporated
Current sense comparator input
Error amplifier input
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VCC
Supply Voltage (2)
Self limiting
VI
Analog input voltage range, VFB and ISENSE
–0.3
6.3
V
VO
Output Voltage
35
V
VI
Input Voltage, VC and D Package only
35
V
ICC
Supply current
30
mA
IO
Output current
±1
A
error amplifier output sink current
10
mA
150
°C
TJ
—
Virtual junction temperature
Output energy (capacitive load)
Tstg
(1)
(2)
Storage temperature
–65
5
µJ
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to the device GND pin.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
3000
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
3000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VCC and VC (1)
Supply Voltage
VI, RT/CT
Input Voltage
VI, VFB and ISENSE
Input Voltage
VO, OUTPUT
TYP
MAX
UNIT
30
V
0
5.5
V
0
5.5
V
Output voltage
0
30
V
VO, POWER
GROUND (1)
Output voltage
–0.1
1
V
ICC
Supply current, externally limited
25
mA
IO
Average output current
200
mA
IO(ref)
Reference output current
fOSC
Oscillator frequency
TA
Operating free-air temperature
(1)
100
–20
mA
500
kHz
TL284x
–40
85
TL384x
0
70
°C
These recommended voltages for VC and POWER GROUND apply only to the D package.
6.4 Thermal Information
TLx84x
THERMAL METRIC (1)
RθJA
(1)
4
Junction-to-ambient thermal resistance
D (SOIC)
D (SOIC)
P (PDIP)
8 PINS
14 PINS
8 PINS
97
86
85
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLVS038I – JANUARY 1989 – REVISED JULY 2016
6.5 Electrical Characteristics
over operating free-air temperature range, VCC = 15 V (1), RT = 10 kΩ, CT = 3.3 nF (unless otherwise noted)
TEST CONDITIONS (2)
PARAMETER
TL284x
TL384x
UNIT
MIN
TYP (2)
MAX
MIN
TYP (2)
MAX
4.95
5
5.05
4.9
5
5.1
V
6
20
6
20
mV
Reference Section
Output voltage
IO = 1 mA, TA = 25°C
Line regulation
VCC = 12 V to 25 V
Load regulation
IO = 1 mA to 20 mA
Temperature coefficient of output voltage
Output voltage with worst-case variation
VCC = 12 V to 25 V, IO = 1
mA to 20 mA
Output noise voltage
f = 10 Hz to 10 kHz, TA =
25°C
Output-voltage long-term drift
After 1000 h at TA = 25°C
Short-circuit output current
6
25
6
25
mV
0.2
0.4
0.2
0.4
mV/°C
5.18
V
4.9
5.1
4.82
50
50
µV
5
25
5
25
mV
–30
–100
–180
–30
–100
–180
mA
47
52
57
47
52
57
kHz
2
10
Oscillator Section
Oscillator frequency (3)
TA = 25°C
Frequency change with supply voltage
VCC = 12 V to 25 V
2
10 Hz/kHz
Frequency change with temperature
50
50
Hz/kHz
peak-to-peak amplitude at RT/CT
1.7
1.7
V
Error-Amplifier Section
Feedback input voltage
COMP at 2.5 V
2.45
Input bias current
Open-loop voltage amplification
VO = 2 V to 4 V
Gain-bandwidth product
2.50
2.55
–0.3
–1
2.42
2.50
2.58
V
–0.3
–2
µA
65
90
65
90
dB
0.7
1
0.7
1
MHz
Supply-voltage rejection ratio
VCC = 12 V to 25 V
60
70
60
70
dB
Output sink current
VFB, at 2.7 V, COMP at 1.1
V
2
6
2
6
mA
Output source current
VFB, at 2.3 V, COMP at 5 V
–0.5
–0.8
–0.5
–0.8
mA
Hihg-level output voltage
VFB, at 2.3 V, RL = 15 kΩ to
GND
5
6
5
6
Low-level output voltage
VFB, at 2.7 V, RL = 15 kΩ to
GND
0.7
1.1
2.85
3
3.13
0.9
1
1.1
V
0.7
1.1
V
2.85
3
3.15
V/V
0.9
1
1.1
Current-sense Section
Voltage amplification
See (4) (5)
Current-sense comparator threshold
COMP at 5 V, see (4)
Supply-voltage rejection ratio
VCC = 12 V to 25 V, see (4)
70
Input bias current
Delay time to output
70
V
dB
–2
–10
–2
–10
µA
150
300
150
300
ns
Output Section
High-level output voltage
IOH = –20 mA
13
13.5
13
13.5
IOH = –200 mA
12
13.5
13
13.5
V
IOH = 20 mA
0.1
0.4
0.1
0.4
IOH = 200 mA
1.5
2.2
1.5
2.2
Rise time
CL = 1 nF, TA = 25°C
50
150
50
150
ns
fall time
CL = 1 nF, TA = 25°C
50
150
50
150
ns
Low-level output voltage
V
Undervoltage-Lockout Section
Start threshold voltage
(1)
(2)
(3)
(4)
(5)
TLx842, TLx844
15
16
17
14.5
16
17.5
TLx843, TLx845
7.8
8.4
9
7.8
8.4
9
V
Adjust VCC above the start threshold before setting it to 15 V.
All typical values are at TA = 25°C.
Output frequency equals oscillator frequency for the TLx842 and TLx843. Output frequency is one-half the oscillator frequency for the
TLx844 and TLx845.
These parameters are measured at the trip point of the latch, with VFB at 0 V.
Voltage amplification is measured between ISENSE and COMP, with the input changing from 0 V to 0.8 V.
Copyright © 1989–2016, Texas Instruments Incorporated
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Electrical Characteristics (continued)
over operating free-air temperature range, VCC = 15 V(1), RT = 10 kΩ, CT = 3.3 nF (unless otherwise noted)
Minimum operating voltage
after startup
TL284x
TEST CONDITIONS (2)
PARAMETER
MIN
TYP (2)
TL384x
MAX
MIN
TYP (2)
MAX
TLx842, TLx844
9
10
11
8.5
10
11.5
TLx843, TLx845
7
7.6
8.2
7
7.6
8.02
TLx842, TLx843
95%
97%
100%
95%
97%
100%
TLx844, TLx845
46%
48%
50%
46%
48%
50%
UNIT
V
Pulse-Width-Modulator Section
Maximum duty cycle
Minimum duty cycle
0%
0%
Supply Voltage
Start-up current
0.5
1
0.5
1
mA
Operating supply current
VFB and ISENSE at 0 V
11
17
11
17
mA
Limiting voltage
ICC = 25 mA
34
34
V
6.6 Typical Characteristics
9.2
VTH, Current Sense Input Threshold (A)
1.2
9
IDISCHARGE (mA)
8.8
8.6
8.4
8.2
8
7.8
7.6
7.4
-75
1
0.8
0.6
0.4
Ta = 125 C
Ta = 25 C
Ta = -55 C
0.2
0
-50
-25
0
25
50
75
Temperature (C)
100
125
150
0
Figure 1. Oscillator Discharge Current
vs
Temperature for VIN = 15 V and VOSC = 2V
100
40
50
20
0
-50
100
1000
10000 100000 1000000
Freq (Hz)
-100
1E+7
D003
Figure 3. Error Amplifier Open-Loop Gain and Phase
vs
Frequency VCC = 15 V, RL = 100 kΩ, and TA = 25 °C
6
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DMAX, Maximum Output Duty Cycle (%)
Gain (dB)
150
60
-20
10
D002
100
200
Gain
Phase
0
8
Figure 2. Current Sense Input Threshold
vs
Error Amplifier Output Voltage for VIN = 15 V
100
80
2
4
6
VO, Error Amp Output Voltage (V)
D001
90
80
70
60
50
40
0.1
0.2
0.3
0.5 0.7 1
2
3
RT, Timing Resistor (kOhm)
4 5 6 7 8 10
D004
Figure 4. Max Output Duty Cycle
vs
Timing Resistor for VCC = 15, CT = 3.3 nF, TA = 25 °C
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SLVS038I – JANUARY 1989 – REVISED JULY 2016
10
9
-2
8
-3
-6
7
Source Saturation at 25 C
Source Saturation at -55 C 6
Sink Saturation at -55 C
5
Sink Saturation at 25 C
4
-7
3
-8
2
-9
1
-4
-5
-10
0
100
200
300
400
500
600
IO, Output Load Current (mA)
700
180
160
140
ISC (mA)
0
-1
Sink Saturation Voltage (V)
Source Saturation Voltage (V)
Typical Characteristics (continued)
120
100
80
60
40
-75
0
800
Figure 5. Output Saturation Voltage
vs
Load Current for VCC = 15 V with 5-ms Input Pulses
-25
0
25
50
75
Temperature (C)
100
125
150
D006
Figure 6. Reference Short Circuit Current
vs
Temperature for VIN = 15 V
0
5.2
Ta = 125 C
Ta = 25 C
Ta = -40 C
-10
5.15
5.1
-20
VREF (V)
Reference Voltage Delta (mV)
-50
D005
-30
5.05
5
4.95
-40
4.9
-50
4.85
-60
0
20
40
60
80
100
Source Current (mA)
120
140
160
D007
4.8
-75
-50
-25
0
25
50
75
Temperature (C)
100
125
Figure 7. Reference Voltage vs Source Current
Figure 8. Reference Voltage vs Temperature
Figure 9. Dead Time vs Timing Capacitance
Figure 10. Timing Resistance vs Frequency
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D008
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7 Detailed Description
7.1 Overview
The TL284x and TL384x series of control integrated circuits provide the features that are necessary to implement
off-line or DC-to-DC fixed-frequency current-mode control schemes, with a minimum number of external
components. Some of the internally implemented circuits are an undervoltage lockout (UVLO), featuring a startup current of less than 1 mA, and a precision reference trimmed for accuracy at the error amplifier input. Other
internal circuits include logic to ensure latched operation, a pulse-width modulation (PWM) comparator (that also
provides current-limit control), and a totem-pole output stage designed to source or sink high-peak current. The
output stage, suitable for driving N-channel MOSFETs, is low when it is in the off state.
Major differences between members of these series are the UVLO thresholds and maximum duty-cycle ranges.
Typical UVLO thresholds of 16 V (on) and 10 V (off) on the TLx842 and TLx844 devices make them ideally
suited to off-line applications. The corresponding typical thresholds for the TLx843 and TLx845 devices are 8.4 V
(on) and 7.6 V (off). The TLx842 and TLx843 devices can operate to duty cycles approaching 100%. A dutycycle range of 0 to 50% is obtained by the TLx844 and TLx845 by the addition of an internal toggle flip-flop,
which blanks the output off every other clock cycle.
The TL284x-series devices are characterized for operation from −40°C to +85°C. The TL384x devices are
characterized for operation from 0°C to 70°C.
7.2 Functional Block Diagram
A
A.
The toggle flip-flop is present only in TL2844, TL2845, TL3844, and TL3845. Pin numbers shown are for the D (14pin) package.
7.3 Feature Description
7.3.1 Pulse-by-Pulse Current Limiting
Pulse-by-pulse limiting is inherent in the control scheme. An upper limit on the peak current can be established
by simply clamping the error voltage. Accurate current limiting allows optimization of magnetic and power
semiconductor elements while ensuring reliable supply operation
8
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Feature Description (continued)
7.3.2 Error Amplifier With Low Output Resistance
With a low output resistance, various impedance networks may be used on the compensation pin input for error
amplifier feedback.
7.3.3 High-Current Totem-Pole Output
The output of the TLx84x devices can sink or source up to 1 A of current.
7.4 Device Functional Modes
7.4.1 Shutdown Technique
The PWM controller (see Figure 11) can be shut down by two methods: either raise the voltage at ISENSE
above 1 V or pull the COMP terminal below a voltage two diode drops above ground. Either method causes the
output of the PWM comparator to be high (see Functional Block Diagram). The PWM latch is reset dominant so
that the output remains low until the next clock cycle after the shutdown condition at the COMP or ISENSE
terminal is removed. In one example, an externally latched shutdown can be accomplished by adding an SCR
that resets by cycling VCC below the lower UVLO threshold. At this point, the reference turns off, allowing the
SCR to reset.
Figure 11. Shutdown Techniques
7.4.2 Slope Compensation
A fraction of the oscillator ramp can be summed resistively with the current-sense signal to provide slope
compensation for converters requiring duty cycles over 50% (see Figure 12).
NOTE
Capacitor C forms a filter with R2 to suppress the leading-edge switch spikes.
Figure 12. Slope Compensation
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Typical Application
The following application is an open-loop laboratory test fixture. This circuit demonstrates the setup and use of
the TL284x and TL384x devices and their internal circuitry.
In the open-loop laboratory test fixture (see Figure 13), high peak currents associated with loads necessitate
careful grounding techniques. Timing and bypass capacitors should be connected close to the GND terminal in a
single-point ground. The transistor and 5-kΩ potentiometer sample the oscillator waveform and apply an
adjustable ramp to the ISENSE terminal.
Figure 13. Open-Loop Laboratory Test Fixture
8.1.1 Design Requirements
The design techniques in the following sections may be used for power supply PWM applications which fall within
the following requirements.
• 500-kHz or lower operation
• 30-V or less output voltage
• 200-mA or less output current
10
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Typical Application (continued)
8.1.2 Detailed Design Procedure
8.1.2.1 Current-Sense Circuit
A.
Peak current (IS) is determined by the formula:
may be required to suppress switch transients.
IS(max ) =
1V
RS A small RC filter formed by resistor Rf and capacitor Cf
Figure 14. Current-Sense Circuit Schematic
8.1.2.2 Error-Amplifier Configuration
A.
Error amplifier can source or sink up to 0.5 mA.
Figure 15. Error-Amplifier Configuration Schematic
8.1.2.3 Oscillator Section
A.
For RT > 5 kΩ:
f»
1.72
R T CT
Figure 16. Oscillator Section Schematic
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TL2842, TL2843, TL2844, TL2845
TL3842, TL3843, TL3844, TL3845
SLVS038I – JANUARY 1989 – REVISED JULY 2016
www.ti.com
Typical Application (continued)
8.1.3 Application Curve
The application curve shows oscillator characteristics for chosen capacitor and resistor values.
ICC, Supply Current (mA)
25
TL2845 where VCC is swept 37 V to 0 V
TL2845 where VCC is swept 0 V to 37 V
TL2842 where VCC is swept 37 V to 0 V
TL2842 where VCC is swept 0 V to 37 V
20
15
10
5
0
0
5
10
15
20
25
30
VCC, Supply Voltage (V)
35
40
D009
Figure 17. Supply Current vs Supply Voltage
9 Power Supply Recommendations
See Recommended Operating Conditions for the recommended power supply voltages for the TL284x and
TL384x devices. TI also recommends to have a decoupling capacitor on the output of the device's power supply
to limit noise on the device input.
12
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Copyright © 1989–2016, Texas Instruments Incorporated
Product Folder Links: TL2842 TL2843 TL2844 TL2845 TL3842 TL3843 TL3844 TL3845
TL2842, TL2843, TL2844, TL2845
TL3842, TL3843, TL3844, TL3845
www.ti.com
SLVS038I – JANUARY 1989 – REVISED JULY 2016
10 Layout
10.1 Layout Guidelines
Always try to use a low EMI inductor with a ferrite type closed core. Some examples would be toroid and
encased E core inductors. Open core can be used if they have low EMI characteristics and are located a bit
more away from the low power traces and components. Make the poles perpendicular to the PCB as well if using
an open core. Stick cores usually emit the most unwanted noise.
10.1.1 Feedback Traces
Try to run the feedback trace as far from the inductor and noisy power traces as possible. Also, keep the
feedback trace to be as direct as possible and somewhat thick. These two sometimes involve a trade-off, but
keeping it away from inductor EMI and other noise sources is the more critical of the two. Run the feedback trace
on the side of the PCB opposite of the inductor with a ground plane separating the two.
10.1.2 Input/Output Capacitors
When using a low value ceramic input filter capacitor, it should be located as close to the VCC pin of the IC as
possible. This will eliminate as much trace inductance effects as possible and give the internal IC rail a cleaner
voltage supply. Some designs require the use of a feed-forward capacitor connected from the output to the
feedback pin as well, usually for stability reasons. In this case it should also be positioned as close to the IC as
possible. Using surface mount capacitors also reduces lead length and lessens the chance of noise coupling into
the effective antenna created by through-hole components.
10.1.3 Compensation Components
External compensation components for stability should also be placed close to the IC. Surface mount
components are recommended here as well for the same reasons discussed for the filter capacitors. These
should not be located very close to the inductor either.
10.1.4 Traces and Ground Planes
Make all of the power (high current) traces as short, direct, and thick as possible. It is good practice on a
standard PCB board to make the traces an absolute minimum of 15 mils (0.381 mm) per Ampere. The inductor,
output capacitors, and output diode should be as close to each other possible. This helps reduce the EMI
radiated by the power traces due to the high switching currents through them. This will also reduce lead
inductance and resistance as well, which in turn reduces noise spikes, ringing, and resistive losses that produce
voltage errors.
The grounds of the IC, input capacitors, output capacitors, and output diode (if applicable) should be connected
close together directly to a ground plane. It would also be a good idea to have a ground plane on both sides of
the PCB. This will reduce noise as well by reducing ground loop errors as well as by absorbing more of the EMI
radiated by the inductor. For multi-layer boards with more than two layers, a ground plane can be used to
separate the power plane (where the power traces and components are) and the signal plane (where the
feedback and compensation and components are) for improved performance. On multi-layer boards the use of
vias will be required to connect traces and different planes. It is good practice to use one standard via per 200
mA of current if the trace will need to conduct a significant amount of current from one plane to the other.
Arrange the components so that the switching current loops curl in the same direction. Due to the way switching
regulators operate, there are two power states. One state when the switch is on and one when the switch is off.
During each state there will be a current loop made by the power components that are currently conducting.
Place the power components so that during each of the two states the current loop is conducting in the same
direction. This prevents magnetic field reversal caused by the traces between the two half-cycles and reduces
radiated EMI.
Copyright © 1989–2016, Texas Instruments Incorporated
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Product Folder Links: TL2842 TL2843 TL2844 TL2845 TL3842 TL3843 TL3844 TL3845
13
TL2842, TL2843, TL2844, TL2845
TL3842, TL3843, TL3844, TL3845
SLVS038I – JANUARY 1989 – REVISED JULY 2016
www.ti.com
10.2 Layout Example
LEGEND
Power or GND Plane
VIA to Power Plane
VIA to GND Plane
VCC
Error signal
Current Sense
1
COMP
2
VFB
3
ISENSE
4
RT/CT
TLx84x
REF
16
VCC
15
OUTPUT
14
GND
13
Output
Figure 18. Layout of D-8 or P Package for TLx84x Devices
14
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Copyright © 1989–2016, Texas Instruments Incorporated
Product Folder Links: TL2842 TL2843 TL2844 TL2845 TL3842 TL3843 TL3844 TL3845
TL2842, TL2843, TL2844, TL2845
TL3842, TL3843, TL3844, TL3845
www.ti.com
SLVS038I – JANUARY 1989 – REVISED JULY 2016
11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TL2842
Click here
Click here
Click here
Click here
Click here
TL2843
Click here
Click here
Click here
Click here
Click here
TL2844
Click here
Click here
Click here
Click here
Click here
TL2845
Click here
Click here
Click here
Click here
Click here
TL3842
Click here
Click here
Click here
Click here
Click here
TL3843
Click here
Click here
Click here
Click here
Click here
TL3844
Click here
Click here
Click here
Click here
Click here
TL3845
Click here
Click here
Click here
Click here
Click here
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 1989–2016, Texas Instruments Incorporated
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Product Folder Links: TL2842 TL2843 TL2844 TL2845 TL3842 TL3843 TL3844 TL3845
15
PACKAGE OPTION ADDENDUM
www.ti.com
9-Nov-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TL2842D
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TL2842
TL2842D-8
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TL2842
TL2842DR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TL2842
TL2842DR-8
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TL2842
TL2842P
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
TL2842P
TL2843D-8
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL2843
TL2843DG4-8
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL2843
TL2843DR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL2843
TL2843DR-8
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL2843
TL2843DRE4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL2843
TL2843DRG4-8
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL2843
TL2843P
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
TL2843P
TL2844D
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL2844
TL2844D-8
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL2844
TL2844DR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL2844
TL2844DR-8
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL2844
TL2844DRG4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL2844
TL2844P
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
TL2844P
TL2844PE4
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
TL2844P
TL2845D
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL2845
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
9-Nov-2021
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TL2845D-8
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL2845
TL2845DG4-8
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL2845
TL2845DR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL2845
TL2845DR-8
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL2845
TL2845DRG4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TL2845
TL2845P
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
TL2845P
TL3842D-8
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
TL3842
TL3842DR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
TL3842
TL3842DR-8
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
TL3842
TL3842DRE4-8
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
TL3842
TL3842P
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL3842P
TL3842PE4
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL3842P
TL3843D
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL3843
TL3843D-8
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL3843
TL3843DR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL3843
TL3843DR-8
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL3843
TL3843P
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL3843P
TL3844D
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL3844
TL3844D-8
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL3844
TL3844DR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL3844
TL3844DR-8
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL3844
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
9-Nov-2021
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TL3844P
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL3844P
TL3844PE4
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL3844P
TL3845D
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL3845
TL3845D-8
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL3845
TL3845DR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL3845
TL3845DR-8
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TL3845
TL3845P
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL3845P
TL3845PE4
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TL3845P
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of