TL4050-Q1
www.ti.com
SLOS588F – JUNE 2008 – REVISED APRIL 2013
PRECISION MICROPOWER SHUNT VOLTAGE REFERENCE
Check for Samples: TL4050-Q1
FEATURES
1
•
•
•
•
•
•
Qualified for Automotive Applications
Fixed Output Voltages of 2.048 V, 2.5 V,
4.096 V, 5 V
Tight Output Tolerances and Low Temperature
Coefficient
– Max 0.1%, 50 ppm/°C – A Grade
– Max 0.2%, 50 ppm/°C – B Grade
– Max 0.5%, 50 ppm/°C – C Grade
Low Output Noise: 41 μVRMS Typ
Wide Operating Current Range:
60 μA Typ to 15 mA
Stable With All Capacitive Loads; No Output
DBZ (SOT-23-3) PACKAGE
(TOP VIEW)
CATHODE
1
3 *
ANODE 2
«
Pin 3 is attached to Substrate and must
be connected to ANODE or left open.
•
Capacitor Required
Available in Extended Temperature Range:
–40°C to 125°C
APPLICATIONS
•
•
•
•
•
•
•
•
Data-Acquisition Systems
Power Supplies and Power-Supply Monitors
Instrumentation and Test Equipment
Process Controls
Precision Audio
Automotive Electronics
Energy Management
Battery-Powered Equipment
DCK (SC-70) PACKAGE
(TOP VIEW)
ANODE
NC
CATHODE
1
5
NC
4
NC
2
3
NC – No internal connection
DESCRIPTION
The TL4050-Q1 family of shunt voltage references are versatile easy-to-use references suitable for a wide array
of applications. The two-terminal fixed-output device requires no external capacitors for operation and is stable
with all capacitive loads. Additionally, the reference offers low dynamic impedance, low noise, and low
temperature coefficient to ensure a stable output voltage over a wide range of operating currents and
temperatures.
The TL4050-Q1 is available in three initial tolerances, ranging from 0.1% (maximum) for the A grade to
0.5% (maximum) for the C grade. Thus, a great deal of flexibility is available to designers in choosing the best
cost-to-performance ratio for their applications. Packaged in the space-saving SOT-23-3 and SC-70 packages
and requiring a minimum current of 45 μA (typical), the TL4050-Q1 also is ideal for portable applications.
The TL4050x-Q1 characterization is for operation over an ambient temperature range of –40°C to 125°C.
PACKAGE AND ORDERING INFORMATION
For the most-current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI Web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated
TL4050-Q1
SLOS588F – JUNE 2008 – REVISED APRIL 2013
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
CATHODE
+
_
ANODE
ABSOLUTE MAXIMUM RATINGS (1)
over free-air temperature range (unless otherwise noted)
MIN
IZ
Continuous cathode current
TJ
Operating virtual junction temperature
Tstg
Storage temperature range
(1)
2
–10
–65
MAX
UNIT
20
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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Copyright © 2008–2013, Texas Instruments Incorporated
TL4050-Q1
www.ti.com
SLOS588F – JUNE 2008 – REVISED APRIL 2013
THERMAL INFORMATION
TL4050-Q1
THERMAL METRIC (1)
Junction-to-ambient thermal resistance (2)
θJA
(3)
DBZ
DCK
3 PINS
5 PINS
UNIT
331.1
289.9
°C/W
θJCtop
Junction-to-case (top) thermal resistance
107.5
56.4
°C/W
θJB
Junction-to-board thermal resistance (4)
63.4
93
°C/W
ψJT
Junction-to-top characterization parameter (5)
4.9
0.7
°C/W
ψJB
Junction-to-board characterization parameter
(6)
61.7
91.4
°C/W
θJCbot
Junction-to-case (bottom) thermal resistance (7)
N/A
N/A
°C/W
(1)
(2)
(3)
(4)
(5)
(6)
(7)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
RECOMMENDED OPERATING CONDITIONS
IZ
TA
(1)
MIN
MAX
(1)
15
I temperature
–40
85
Q temperature
–40
125
Cathode current
Free-air temperature
UNIT
mA
°C
See parametric tables
Copyright © 2008–2013, Texas Instruments Incorporated
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TL4050-Q1
SLOS588F – JUNE 2008 – REVISED APRIL 2013
www.ti.com
TL4050x20-Q1 ELECTRICAL CHARACTERISTICS
at extended temperature range, full range TA = –40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VZ
Reverse
breakdown
voltage
IZ = 100 μA
ΔVZ
Reverse
breakdown
voltage
tolerance
IZ = 100 μA
IZ,min
Minimum
cathode
current
αVZ
IZ = 10 mA
Average
temperature IZ = 1 mA
coefficient of
reverse
breakdown
IZ = 100 μA
voltage
DVZ
DI Z
Reverse
breakdown
voltage
change with
cathode
current
change
TA
TL4050A20-Q1
MIN
25°C
TYP
2.048
TYP
TL4050C20-Q1
MAX
MIN
2.048
TYP
MAX
2.048
2.048
–4.096
4.096
–10.24
10.24
Full
range
–12.288
12.288
–14.7456
14.7456
–17.2032
17.2032
41
60
41
65
60
41
65
±20
±20
±20
25°C
±15
±15
±15
25°C
±15
±15
±15
Full
range
25°C
±50
0.3
Full
range
25°C
0.8
±50
0.3
1.2
2.3
Full
range
6
0.8
8
6
μA
ppm/°C
±50
0.3
1.2
2.3
mV
60
65
25°C
UNIT
V
–2.048
Full
range
1 mA < IZ < 15 mA
MIN
25°C
25°C
IZ,min < IZ < 1 mA
TL4050B20-Q1
MAX
0.8
1.2
2.3
8
6
mV
8
ZZ
Reverse
dynamic
impedance
IZ = 1 mA,
f = 120 Hz,
IAC = 0.1 IZ
25°C
0.3
0.3
0.3
Ω
eN
Wideband
noise
IZ = 100 μA,
10 Hz ≤ f ≤ 10 kHz
25°C
34
34
34
μVRMS
Long-term
stability of
reverse
breakdown
voltage
t = 1000 h,
TA = 25°C ± 0.1°C,
IZ = 100 μA
120
120
120
ppm
Thermal
hysteresis (1)
ΔTA = –40°C to 125°C
0.7
0.7
0.7
mV
VHYST
(1)
4
Thermal hysteresis is defined as VZ,25°C (after cycling to –40°C) – VZ,25°C (after cycling to 125°C).
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TL4050-Q1
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SLOS588F – JUNE 2008 – REVISED APRIL 2013
TL4050x25-Q1 ELECTRICAL CHARACTERISTICS
at extended temperature range, full range TA = –40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
TL4050B25-Q1
MIN
TYP
MAX
Reverse breakdown voltage IZ = 100 μA
25°C
ΔVZ
Reverse breakdown voltage
IZ = 100 μA
tolerance
25°C
–5
5
Full range
–18
18
IZ,min
Minimum cathode current
αVZ
Average temperature
coefficient of reverse
breakdown voltage
VZ
DVZ
DI Z
Reverse breakdown voltage
change with cathode
current change
2.5
25°C
41
Full range
25°C
±20
IZ = 1 mA
25°C
±15
25°C
±15
IZ,min < IZ < 1 mA
1 mA < IZ < 15 mA
V
mV
60
μA
65
IZ = 10 mA
IZ = 100 μA
UNIT
Full range
ppm/°C
±50
25°C
0.3
Full range
0.8
1.2
25°C
2.3
Full range
mV
6
8
ZZ
Reverse dynamic
impedance
IZ = 1 mA,
f = 120 Hz,
IAC = 0.1 IZ
eN
Wideband noise
IZ = 100 μA,
10 Hz ≤ f ≤ 10 kHz
Long-term stability of
reverse breakdown voltage
t = 1000 h,
TA = 25°C ± 0.1°C,
IZ = 100 μA
120
ppm
Thermal hysteresis (1)
ΔTA = –40°C to 125°C
0.7
mV
VHYST
(1)
25°C
0.3
Ω
25°C
41
μVRMS
Thermal hysteresis is defined as VZ,25°C (after cycling to –40°C) – VZ,25°C (after cycling to 125°C).
Copyright © 2008–2013, Texas Instruments Incorporated
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TL4050-Q1
SLOS588F – JUNE 2008 – REVISED APRIL 2013
www.ti.com
TL4050x41-Q1 ELECTRICAL CHARACTERISTICS
at extended temperature range, full range TA = –40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
TL4050B41-Q1
MIN
TYP
MAX
Reverse breakdown voltage IZ = 100 μA
25°C
ΔVZ
Reverse breakdown voltage
IZ = 100 μA
tolerance
25°C
–8.2
8.2
Full range
–29
29
IZ,min
Minimum cathode current
αVZ
Average temperature
coefficient of reverse
breakdown voltage
VZ
DVZ
DI Z
Reverse breakdown voltage
change with cathode
current change
25°C
25°C
±30
IZ = 1 mA
25°C
±20
25°C
±20
IZ = 100 μA
IZ,min < IZ < 1 mA
1 mA < IZ < 15 mA
Reverse dynamic
impedance
eN
Wideband noise
IZ = 100 μA,
10 Hz ≤ f ≤ 10 kHz
Long-term stability of
reverse breakdown voltage
t = 1000 h,
TA = 25°C ± 0.1°C,
IZ = 100 μA
Thermal hysteresis (1)
ΔTA = –40°C to 125°C
6
V
68
78
IZ = 10 mA
ZZ
(1)
52
Full range
IZ = 1 mA,
f = 120 Hz,
IAC = 0.1 IZ
VHYST
4.096
Full range
UNIT
mV
μA
ppm/°C
±50
25°C
0.2
Full range
0.9
1.2
25°C
2
Full range
7
mV
10
25°C
0.5
Ω
25°C
93
μVRMS
120
ppm
1.148
mV
Thermal hysteresis is defined as VZ,25°C (after cycling to –40°C) – VZ,25°C (after cycling to 125°C).
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TL4050-Q1
www.ti.com
SLOS588F – JUNE 2008 – REVISED APRIL 2013
TL4050x50-Q1 ELECTRICAL CHARACTERISTICS
at extended temperature range, full range TA = –40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
TL4050A50-Q1
MIN
TYP
TL4050B50-Q1
MAX
MIN
TYP
TL4050C50-Q1
MAX
MIN
TYP
MAX
VZ
Reverse
breakdown
voltage
IZ = 100 μA
25°C
Reverse
breakdown
IZ = 100 μA
voltage tolerance
25°C
–5
5
–10
10
–25
25
ΔVZ
Full
range
–30
30
–35
35
–50
50
IZ,min
Minimum
cathode current
IZ = 10 mA
25°C
±30
±30
±30
IZ = 1 mA
25°C
±20
±20
±20
αVZ
Average
temperature
coefficient of
reverse
breakdown
voltage
25°C
±20
±20
±20
Reverse
breakdown
voltage change
with cathode
current change
IZ,min < IZ < 1 mA
25°C
IZ = 100 μA
1 mA < IZ < 15 mA
I = 1 mA,
Reverse dynamic Z
f = 120 Hz,
impedance
IAC = 0.1 IZ
eN
Wideband noise
IZ = 100 μA,
10 Hz ≤ f ≤ 10 kHz
Long-term
stability of
reverse
breakdown
voltage
Thermal
hysteresis (1)
(1)
5
74
5
56
74
90
Full
range
0.2
1
0.2
1
Full
range
8
8
12
mV
74
μA
ppm/°C
±50
0.2
1.4
2
V
90
±50
1.4
2
56
90
±50
Full
range
25°C
ZZ
VHYST
56
Full
range
25°C
DVZ
DI Z
5
UNIT
1
1.4
2
12
8
mV
12
25°C
0.5
0.5
0.5
Ω
25°C
93
93
93
μVRMS
t = 1000 h,
TA = 25°C ± 0.1°C,
IZ = 100 μA
120
120
120
ppm
ΔTA = –40°C to 125°C
1.4
1.4
1.4
mV
Thermal hysteresis is defined as VZ,25°C (after cycling to –40°C) – VZ,25°C (after cycling to 125°C).
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TL4050-Q1
SLOS588F – JUNE 2008 – REVISED APRIL 2013
www.ti.com
TYPICAL CHARACTERISTICS
OUTPUT IMPEDANCE
versus
FREQUENCY
1000
IZ = IZ(MIN) + 100 µA
IZ = 1 mA
Output Impedance – W
Output Impedance – W
1000
OUTPUT IMPEDANCE
versus
FREQUENCY
100
VKA = 10 V
10
VKA = 2.5 V
1
100
10
VKA = 10 V
1
VKA = 2.5 V
0.1
100
1k
10k
100k
0.1
100
1M
1k
1M
Figure 2.
REVERSE CHARACTERISTICS
AND
MINIMUM OPERATING CURRENT
NOISE VOLTAGE
versus
FREQUENCY
100
10
80
8
Noise Voltage – µV/ÖHz
Reverse Current – A
100k
Frequency – Hz
Frequency – Hz
Figure 1.
VKA = 2.5 V
60
10k
VKA = 10 V
40
20
6
4
VKA = 10 V
2
VKA = 2.5 V
0
0
0
1
2
3
4
5
6
7
Reverse Voltage (V)
Figure 3.
8
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8
9
10
1
10
100
1k
10k
100k
Frequency – Hz
Figure 4.
Copyright © 2008–2013, Texas Instruments Incorporated
TL4050-Q1
www.ti.com
SLOS588F – JUNE 2008 – REVISED APRIL 2013
TYPICAL CHARACTERISTICS (continued)
LARGE SIGNAL PULSE RESPONSE
LARGE SIGNAL PULSE RESPONSE
6
20
VKA = 2.5 V
VKA = 10 V
5
15
Voltage – V
Voltage – V
4
3
2
10
5
1
0
0
-1
-20
0
20
40
60
Time – µs
Figure 5.
Copyright © 2008–2013, Texas Instruments Incorporated
80
-5
-100
0
100
200
300
400
Time – µs
Figure 6.
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TL4050-Q1
SLOS588F – JUNE 2008 – REVISED APRIL 2013
www.ti.com
APPLICATION INFORMATION
RS
VIN
TL4050-Q1
VZ
1-Hz Rate
Figure 7. Start-Up Test Circuit
Output Capacitor
The TL4050-Q1 does not require an output capacitor across cathode and anode for stability. However, in an
application using an output bypass capacitor, the TL4050-Q1 is stable with all capacitive loads.
SOT-23-3 Pin Connections
There is a parasitic Schottky diode connected between pins 2 and 3 of the SOT-23-3 packaged device. Thus,
pin 3 of the SOT-23-3 package must be left floating or connected to pin 2.
Use With ADCs or DACs
The design of the TL4050x41-Q1 is as a cost-effective voltage reference, as required in 12-bit data-acquisition
systems. For 12-bit systems operating from 5-V supplies, such as the ADS7842 (see Figure 8), the TL4050x41Q1 (4.096 V) permits operation with an LSB of 1 mV.
ADS7842
0 V to VREF
1 AIN0
5V
2 AIN1
909
+
2.2 mF
TL4050B41-Q1
VANA
VDIG
28
27
3 AIN2
A1 26
4 AIN3
A0 25
5 VREF
CLK 24
6 AGND
7 DB11
+
0.1 mF
+
5-V Analog Supply
10 mF
3.2-MHz Clock
BUSY
23
BUSY Output
Write Input
WR
22
8 DB10
CS
21
9 DB9
RD
20
10 DB8
DB0 19
11 DB7
DB1 18
12 DB6
DB2 17
13 DB5
DB3 16
14 DGND
DB4 15
Read Input
Figure 8. Data-Acquisition Circuit With TL4050x41-Q1
10
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TL4050-Q1
www.ti.com
SLOS588F – JUNE 2008 – REVISED APRIL 2013
Cathode and Load Currents
In a typical shunt-regulator configuration (see Figure 9), an external resistor, RS, connects between the supply
and the cathode of the TL4050-Q1. Proper choice of RS is essential, as RS sets the total current available to
supply the load (IL) and bias the TL4050-Q1 (IZ). In all cases, IZ must stay within a specified range for proper
operation of the reference. Taking into consideration one extreme in the variation of the load and supply voltage
(maximum IL and minimum VS), RS must be small enough to supply the minimum IZ required for operation of the
regulator, as given by data-sheet parameters. At the other extreme, maximum VS and minimum IL, RS must be
large enough to limit IZ to less than its maximum-rated value of 15 mA.
Equation 1 calculates RS:
ǒVS * VZǓ
RS +
(I L ) I Z)
(1)
VS
RS
IZ + IL
IL
VZ
TL4050-Q1
IZ
Figure 9. Shunt Regulator
Copyright © 2008–2013, Texas Instruments Incorporated
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11
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TL4050A50QDBZRQ1
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLGU
TL4050A50QDCKRQ1
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
7GU
TL4050B25QDBZRQ1
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLHU
TL4050B25QDCKRQ1
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
7HU
TL4050B41QDBZRQ1
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TMXU
TL4050B50QDBZRQ1
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLJU
TL4050B50QDCKRQ1
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
7JU
TL4050C20QDBZRQ1
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TMYU
TL4050C50QDBZRQ1
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TKZU
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(3)
15-Apr-2013
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TL4050A50-Q1, TL4050B25-Q1, TL4050B41-Q1, TL4050B50-Q1, TL4050C50-Q1 :
• Catalog: TL4050A50, TL4050B25, TL4050B41, TL4050B50, TL4050C50
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
SOT-23
DBZ
3
3000
179.0
8.4
TL4050A50QDCKRQ1
SC70
DCK
5
3000
179.0
8.4
2.2
TL4050B25QDBZRQ1
SOT-23
DBZ
3
3000
179.0
8.4
3.15
TL4050B25QDCKRQ1
SC70
DCK
5
3000
179.0
8.4
2.2
TL4050B41QDBZRQ1
SOT-23
DBZ
3
3000
179.0
8.4
TL4050A50QDBZRQ1
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
2.95
1.22
4.0
8.0
Q3
2.5
1.2
4.0
8.0
Q3
2.95
1.22
4.0
8.0
Q3
2.5
1.2
4.0
8.0
Q3
3.15
2.95
1.22
4.0
8.0
Q3
3.15
W
Pin1
(mm) Quadrant
TL4050B50QDBZRQ1
SOT-23
DBZ
3
3000
179.0
8.4
3.15
2.95
1.22
4.0
8.0
Q3
TL4050B50QDCKRQ1
SC70
DCK
5
3000
179.0
8.4
2.2
2.5
1.2
4.0
8.0
Q3
TL4050C20QDBZRQ1
SOT-23
DBZ
3
3000
179.0
8.4
3.15
2.95
1.22
4.0
8.0
Q3
TL4050C50QDBZRQ1
SOT-23
DBZ
3
3000
179.0
8.4
3.15
2.95
1.22
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TL4050A50QDBZRQ1
SOT-23
DBZ
3
3000
203.0
203.0
35.0
TL4050A50QDCKRQ1
SC70
DCK
5
3000
203.0
203.0
35.0
TL4050B25QDBZRQ1
SOT-23
DBZ
3
3000
203.0
203.0
35.0
TL4050B25QDCKRQ1
SC70
DCK
5
3000
203.0
203.0
35.0
TL4050B41QDBZRQ1
SOT-23
DBZ
3
3000
203.0
203.0
35.0
TL4050B50QDBZRQ1
SOT-23
DBZ
3
3000
203.0
203.0
35.0
TL4050B50QDCKRQ1
SC70
DCK
5
3000
203.0
203.0
35.0
TL4050C20QDBZRQ1
SOT-23
DBZ
3
3000
203.0
203.0
35.0
TL4050C50QDBZRQ1
SOT-23
DBZ
3
3000
203.0
203.0
35.0
Pack Materials-Page 2
4203227/C
PACKAGE OUTLINE
DBZ0003A
SOT-23 - 1.12 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
2.64
2.10
1.4
1.2
PIN 1
INDEX AREA
1.12 MAX
B
A
0.1 C
1
0.95
3.04
2.80
1.9
3X
3
0.5
0.3
0.2
2
(0.95)
C A B
0.25
GAGE PLANE
0 -8 TYP
0.10
TYP
0.01
0.20
TYP
0.08
0.6
TYP
0.2
SEATING PLANE
4214838/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration TO-236, except minimum foot length.
www.ti.com
EXAMPLE BOARD LAYOUT
DBZ0003A
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X (0.95)
2
(R0.05) TYP
(2.1)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214838/C 04/2017
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBZ0003A
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X(0.95)
2
(R0.05) TYP
(2.1)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214838/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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