TL7705BCDRE4

TL7702B, TL7705B, TL7733B TL7702B, TL7705B, TL7733B SLVS037O – SEPTEMBER 1989 – REVISED DECEMBER 2020 SLVS037O – SEPTEMBER 1989 – REVISED DECEMBER 2020 www.ti.com TL7702B, TL7733B, and TL7705B Supply-Voltage Supervisors 1 Features 3 Description • • • • • • • The TL7702B, TL7705B, and TL7733B are integratedcircuit supply-voltage supervisors designed for use as reset controllers in microcomputer and microprocessor systems. The supply-voltage supervisor monitors the supply for undervoltage conditions at the SENSE input. When an undervoltage condition occurs during normal operation, outputs RESET and RESET go active. Power-On Reset Generator Automatic Reset Generation After Voltage Drop RESET Output Defined From VCC ≥ 1 V Precision Voltage Sensor Temperature-Compensated Voltage Reference True and Complement Reset Outputs Externally Adjustable Pulse Duration 2 Applications • • • • • • The TL7702BC, TL7705BC, and TL7733BC are characterized for operation from 0°C to 70°C. The TL7702BI, TL7705BI, and TL7733BI are characterized for operation from –40°C to 85°C. The TL7705BQ is characterized for operation from –40°C to 125°C. Wireless communication systems Factory automation Building automation Servers Notebooks and Desktop computers STB and DVR Device Information (1) PART NUMBER BODY SIZE (NOM) TL77xxBD SOIC (8) 4.90 mm × 3.91 mm TL77xxBP PDIP (8) 9.81 mm × 6.35 mm (1) VCC PACKAGE For all available packages, see the orderable addendum at the end of the data sheet. 8 Reference Voltage 1 CT SENSE 6 3 + VX 7 R1 (see Note 1) Reference Voltage 2 ± 5 RESET RESET + R2 (see Note 1) RESIN ± 2 1 GND REF 4 Copyright © 2016, Texas Instruments Incorporated Functional Block Diagram An©IMPORTANT NOTICEIncorporated at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Copyright 2020 Texas Instruments Submit Document Feedback intellectual property matters and other important disclaimers. PRODUCTION DATA. 1 TL7702B, TL7705B, TL7733B www.ti.com SLVS037O – SEPTEMBER 1989 – REVISED DECEMBER 2020 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 Pin Functions.................................................................... 3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions.........................4 6.4 Thermal Information....................................................5 6.5 Electrical Characteristics: TL77xxBC, TL77xxBI, and TL7705BQ.............................................................. 6 6.6 Switching Characteristics: TL77xxBC, TL77xxBI, and TL7705BQ.............................................................. 6 6.7 Timing Diagrams......................................................... 7 6.8 Typical Characteristics................................................ 8 7 Parameter Measurement Information............................ 9 8 Detailed Description......................................................10 8.1 Overview................................................................... 10 8.2 Functional Block Diagram......................................... 10 8.3 Feature Description...................................................11 8.4 Device Functional Modes..........................................11 9 Application and Implementation.................................. 12 9.1 Application Information............................................. 12 9.2 Typical Application.................................................... 12 10 Power Supply Recommendations..............................14 11 Layout........................................................................... 15 11.1 Layout Guidelines................................................... 15 11.2 Layout Example...................................................... 15 12 Device and Documentation Support..........................16 12.1 Related Links.......................................................... 16 12.2 Receiving Notification of Documentation Updates..16 12.3 Support Resources................................................. 16 12.4 Trademarks............................................................. 16 12.5 Electrostatic Discharge Caution..............................16 12.6 Glossary..................................................................16 13 Mechanical, Packaging, and Orderable Information.................................................................... 16 4 Revision History Changes from Revision N (September 2016) to Revision O (December 2020) Page • Updated the numbering format for tables, figures, and cross-references throughout the document..................1 • Corrected the RESIN pin description..................................................................................................................3 • Corrected the ICC parameter units from µA to mA in Electrical Characteristics Table........................................ 6 Changes from Revision M (May 2003) to Revision N (September 2016) Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1 • Deleted Ordering Information table; see POA at the end of the data sheet....................................................... 1 • Deleted Lead temperature row........................................................................................................................... 4 • Changed RθJA for D (SOIC) from 97 to 109.2 and for P (PDIP) from 85 to 51.4................................................ 5 2 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated TL7702B, TL7705B, TL7733B www.ti.com SLVS037O – SEPTEMBER 1989 – REVISED DECEMBER 2020 5 Pin Configuration and Functions REF 1 8 VCC RESIN 2 7 SENSE CT 3 6 RESET GND 4 5 RESET Not to scale Figure 5-1. D or P Package 8-Pin SOIC or PDIP Top View Pin Functions PIN NAME NO. I/O DESCRIPTION CT 3 O Timing capacitor input. The timing capacitor determines the time delay that the reset outputs remain active after the voltage at the SENSE input exceeds the positive-going threshold value. GND 4 — Ground REF 1 O Reference voltage. See Section 6.5 for reference voltage output and specification. RESET 6 O Active high reset. See Figure 6-1 for RESET function and timing. RESET 5 O Active low reset. See Figure 6-1 for RESET function and timing. RESIN 2 I Reset input. When the Reset Input is low, the RESET output goes high and the RESET goes low. When the Reset Input is high, the RESET and RESET outputs are allowed to trigger based on the SENSE voltage. SENSE 7 I Sense input. Voltage input to be supervised. See Figure 6-1 for SENSE function and timing. VCC 8 — Supply voltage. See Section 6.3 for recommended voltage input range. Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 3 TL7702B, TL7705B, TL7733B www.ti.com SLVS037O – SEPTEMBER 1989 – REVISED DECEMBER 2020 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN Supply voltage(2), VCC Input voltage, VI MAX UNIT 20 V RESIN –0.3 20 SENSE –0.3 20 V High-level output current, IOH (RESET) –30 mA Low-level output current, IOL ( RESET) 30 mA Operating virtual junction temperature, TJ Storage temperature, Tstg (1) (2) –65 150 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 2000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) 1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MAX UNIT 3.6 18 V 2 18 V VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage RESIN 0 0.8 V VI Input voltage SENSE 0 18 V IOH High-level output current RESET –20 mA IOL Low-level output current RESET 20 mA TA Operating free-air temperature RESIN TL77xxBC 4 MIN Submit Document Feedback 0 70 TL77xxBI –40 85 TL7705BQ –40 125 °C Copyright © 2020 Texas Instruments Incorporated TL7702B, TL7705B, TL7733B www.ti.com SLVS037O – SEPTEMBER 1989 – REVISED DECEMBER 2020 6.4 Thermal Information TL77xxB THERMAL METRIC(1) (2) D (SOIC) P (PDIP) 8 PINS 8 PINS UNIT 109.2 51.4 °C/W 56 40.6 °C/W RθJA Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance RθJB Junction-to-board thermal resistance 49.9 28.6 °C/W ψJT Junction-to-top characterization parameter 11.4 17.7 °C/W ψJB Junction-to-board characterization parameter 49.4 28.5 °C/W (1) (2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Maximum power dissipation is a function of TJ(max), RθJA , and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA) / RθJA. Operating at the absolute maximum TJ of 150°C can affect reliability. Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 5 TL7702B, TL7705B, TL7733B www.ti.com SLVS037O – SEPTEMBER 1989 – REVISED DECEMBER 2020 6.5 Electrical Characteristics: TL77xxBC, TL77xxBI, and TL7705BQ over operating free-air temperature range (unless otherwise noted)(1) PARAMETER TEST CONDITIONS VOH High-level output voltage, RESET IOH = –16 mA VOL Low-level output voltage, RESET IOL = 16 mA VREF Reference voltage, REF Iref = –500 µA, TA = 25°C MIN TA = 25°C TL7705B VIT– MAX V 0.4 V V 2.48 2.53 2.58 2.505 2.53 2.555 4.5 4.55 4.6 TL7733B 3.03 3.08 3.13 TL7702B 2.48 2.53 2.58 4.45 4.55 4.65 3 3.08 3.16 TA = full range(2) TL7705B TL7733B TL7702B VHYS Hysteresis, SENSE (VIT+ – VIT–) VRES Power-up reset voltage(3) II Input current UNIT VCC – 1.5 TL7702B Negative-going input threshold voltage at SENSE input TYP V 10 VCC = 3.6 V to 18 V, TA = 25°C TL7705B mV 30 TL7733B 10 IOL at RESET = 2 mA, TA = 25°C RESIN VI = 0.4 V to VCC SENSE, TL7702B VI = VREF to 18 V 1 V –10 –0.1 µA –2 IOH High-level output current, RESET VO = 18 V, see Figure 7-1 50 µA IOL Low-level output current, RESET VO = 0 V, see Figure 7-1 –50 µA ICC Supply current (1) (2) (3) VSENSE = 15 V, RESIN ≥ 2 V 1.8 3 VCC = 18 V, TA = full range(2) mA 3.5 All electrical characteristics are measured with 0.1-µF capacitors connected at REF, CT, and VCC to GND. Full range is 0°C to 70°C for the C-suffix devices, –40°C to 85°C for the I-suffix devices, and –40°C to 125°C for the Q-suffix device. This is the lowest voltage at which RESET becomes active. 6.6 Switching Characteristics: TL77xxBC, TL77xxBI, and TL7705BQ VCC = 5 V, CT open, TA = 25°C, over operating free-air temperature range (unless otherwise noted) PARAMETER 6 FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time from lowlevel to high-level output RESIN RESET See , Figure 6-1 Figure 6-2, Figure 7-1 270 500 ns tPHL Propagation delay time from highlevel to low-level output RESIN RESET See Figure 6-1, Figure 6-2, Figure 7-2 270 500 ns tw Effective pulse duration tr Rise time tf Fall time Submit Document Feedback RESIN See Figure 7-3,Figure 7-4 SENSE RESET RESET RESET RESET See Figure 6-1, Figure 7-1, Figure 7-2 See Figure 6-1, Figure 7-1, Figure 7-2 150 ns 100 75 75 150 150 200 50 ns ns Copyright © 2020 Texas Instruments Incorporated TL7702B, TL7705B, TL7733B www.ti.com SLVS037O – SEPTEMBER 1989 – REVISED DECEMBER 2020 6.7 Timing Diagrams Voltage Fault V IT+ SENSE V IT+ V IT± 0V V IH RESIN Undefined 2V 0.8 V tf tr V IL tPLH 90% 90% 90% RESET VOH 50% 10% td tf td td 90% 50% RESET 10% 10% 10% tr 10% VOL t PH L Copyright © 2016, Texas Instruments Incorporated Figure 6-1. TL7702B, TL7705B, and TL7733B Timing Diagram VCC and SENSE VIT+ V IT± V IT+ Vres VITVres 0 RESET td td Output Undefined Output Undefined 0 Copyright © 2016, Texas Instruments Incorporated Figure 6-2. VIT and VRES Timing Diagram Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 7 TL7702B, TL7705B, TL7733B www.ti.com SLVS037O – SEPTEMBER 1989 – REVISED DECEMBER 2020 6.8 Typical Characteristics 20 700 18 600 t -Deassertion Time - ns RESET tr 16 t ± AssertionTime ±ns RESET tr 14 12 RESET tf 400 300 RESET tf 200 10 8 6 500 100 RESET t f RESET tr 0 0 2 4 6 8 0 10 2 R L± Load Resistance ± kŸ Figure 6-3. Assertion Time vs Load Resistance 4 6 8 RL±Load Resistance ± kŸ 10 Figure 6-4. Deassertion Time vs Load Resistance 36 2.1 1.9 1.7 24 RESET tr 18 RESET tf 12 t- Deassertion Time ±µs t ± Assertion Time± ns 30 1.5 1.3 1.1 RESET tf and RESET tr 0.9 0.7 0.5 6 0 25 50 75 100 125 150 175 200 C L-Load Capacitance - pF Figure 6-5. Assertion Time vs Load Capacitance 8 Submit Document Feedback 0.3 0 25 50 75 100 125 150 CL - Load Capacitance - pF 175 200 Figure 6-6. Deassertion Time vs Load Capacitance Copyright © 2020 Texas Instruments Incorporated TL7702B, TL7705B, TL7733B www.ti.com SLVS037O – SEPTEMBER 1989 – REVISED DECEMBER 2020 7 Parameter Measurement Information 5V VCC DUT RESET RL (see Note 1) 15 pF (see Note 2) RESET OUTPUT CONFIGURATION Copyright © 2016, Texas Instruments Incorporated A. For IOL and IOH, RL = 10 kΩ. For all switching characteristics, RL = 511 Ω. B. This figure includes jig and probe capacitance. Figure 7-1. RESET Output Configuration 5V RL (see Note 1) RESET DUT 15 pF (see Note 2) GND RESET OUTPUT CONFIGURATION Copyright © 2016, Texas Instruments Incorporated A. For IOL and IOH, RL = 10 kΩ. For all switching characteristics, RL = 511 Ω. B. This figure includes jig and probe capacitance. Figure 7-2. RESET Output Configuration tw 5V 2.5 V 0V RESIN Figure 7-3. Input Pulse Definition RESIN tw VT + 2V VT VT - 2V SENSE Figure 7-4. Input Pulse Definition SENSE Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 9 TL7702B, TL7705B, TL7733B www.ti.com SLVS037O – SEPTEMBER 1989 – REVISED DECEMBER 2020 8 Detailed Description 8.1 Overview The TL7702B, TL7705B, and TL7733B are integrated-circuit supply-voltage supervisors designed for use as reset controllers in microcomputer and microprocessor systems. The supply-voltage supervisor monitors the supply for undervoltage conditions at the SENSE input. During power up, the RESET output becomes active (low) when VCC attains a value approaching 1 V. As VCC approaches 3 V (assuming that SENSE is above VT+), the delay-timer function activates a time delay, after which outputs RESET and RESET go inactive (high and low, respectively). When an undervoltage condition occurs during normal operation, outputs RESET and RESET go active. To ensure that a complete reset occurs, the reset outputs remain active for a time delay after the voltage at the SENSE input exceeds the positive-going threshold value. The time delay is determined by the value of the external capacitor CT : td ≈ 2.6 × 104 × CT , where CT is in farads (F) and td is in seconds (s). An external capacitor (typically 0.1 µF) must be connected to REF to reduce the influence of fast transients in the supply voltage. 8.2 Functional Block Diagram The functional block diagram is shown for illustrative purposes only; the actual circuit includes a trimming network to adjust the reference voltage and sense-comparator trip point. VCC 8 Reference Voltage 1 CT SENSE 6 3 + VX 7 R1 (see Note 1) Reference Voltage 2 ± 5 RESET RESET + R2 (see Note 1) RESIN ± 2 1 GND REF 4 Copyright © 2016, Texas Instruments Incorporated 10 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated TL7702B, TL7705B, TL7733B www.ti.com SLVS037O – SEPTEMBER 1989 – REVISED DECEMBER 2020 8.3 Feature Description 8.3.1 Wide Supply-Voltage Range The TL77xxB family operates using a wide supply voltage from 3.6 V to 18 V. 8.3.2 Adjustable Pulse Duration The CT pin enables the ability to set a user-defined time delay in order to ensure that the fault condition is recognized. The external capacitor charges based on an internal current source until the voltage at the CT pin exceeds that of the internal reference voltage. The time delay is determined by the value of the external capacitor CT : td ≈ 2.6 × 104 × CT , where CT is in farads (F) and td is in seconds (s). The current source to charge the timing capacitor varies ±15%. Reference Voltage 2 is approximately 1.8 V and varies approximately ±5%. Once the timing capacitor charges, it discharges to about 0.6 V, not completely to 0 V. 8.4 Device Functional Modes Figure 8-1 displays how the RESET and RESET output pins respond to the change in the the SENSE and RESIN input pins. When the RESIN pin is high, the RESET outputs are able to respond to a drop in the supply voltage at the SENSE pin. When the RESIN pin is low, the RESET and RESET pins are set HIGH and LOW respectively. Voltage Fault V IT+ SENSE V IT+ V IT± 0V V IH RESIN Undefined 2V 0.8 V tf tr V IL tPLH 90% 90% 90% RESET VOH 50% 10% td tf td td 90% 50% RESET 10% tr 10% 10% 10% VOL t PH L Copyright © 2016, Texas Instruments Incorporated Figure 8-1. TL77xxB RESET and RESET Response and Timing Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 11 TL7702B, TL7705B, TL7733B www.ti.com SLVS037O – SEPTEMBER 1989 – REVISED DECEMBER 2020 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information Figure 9-1 shows an application where the TL7705B device is being used to sense the voltage supply for a microcontroller that is supplied with 5 V. If the voltage supply drops below the threshold voltage, the RESET pin is pulled LOW, signaling the microcontroller to reset. 9.2 Typical Application TL7705B Copyright © 2016, Texas Instruments Incorporated Figure 9-1. Reset Controller Schematic for a Microprocessor 9.2.1 Design Requirements The external components required include the decoupling capacitor for the REF pin and the timing capacitor for the CT pin. Additionally, because the RESET output is open collector, a pullup resistor is required to ensure the correct HIGH level for the microcontroller RESET pin. 9.2.2 Detailed Design Procedure TI recommends pullup and pulldown resistors of 10 kΩ. To achieve a 2.6 ms time delay, use CT = 0.1 µF. Both outputs of the TL770xB must be terminated with similar value resistors, even when only one is being used. This prevents unwanted plateauing in either output waveform during switching, which may be interpreted as an undefined state or delay system reset 12 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated TL7702B, TL7705B, TL7733B www.ti.com SLVS037O – SEPTEMBER 1989 – REVISED DECEMBER 2020 9.2.3 Application Curve 4.65 VIT- (V) 4.6 4.55 4.5 4.45 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) D001 Figure 9-2. TL7705B Threshold Voltage vs Temperature Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 13 TL7702B, TL7705B, TL7733B www.ti.com SLVS037O – SEPTEMBER 1989 – REVISED DECEMBER 2020 10 Power Supply Recommendations System Supply VS 8 7 2 Reset Input (from system) 1 RT (see text) 0.1 µ F CT 3 10 k Ÿ VCC SENSE 5 RESET To System RESET RESIN REF 6 RESET CT To System RESET GND 4 10 k Ÿ Copyright © 2016, Texas Instruments Incorporated Figure 10-1. System Reset Controller With Undervoltage Sensing When the TL770xB SENSE terminal is used to monitor VCC, TI recommends a current-limiting resistor in series with CT. During normal operation, the timing capacitor is charged by the onboard current source to approximately VCC or an internal voltage clamp (≈7.1-V Zener), whichever is less. When the circuit then is subjected to an undervoltage condition during which VCC is rapidly slewed down, the voltage on CT exceeds that on VCC. This forward biases a secondary path internally, which falsely activates the outputs. A fault is indicated when VCC drops below V(CT), not when VSENSE falls below VT–. Adding the external resistor, RT, prevents false triggering. Its value is calculated as follows: (V(CT) – VT-) / RT (1) where • • • V(CT) = VCC or 7.1 V, whichever is less VT– = 4.55 V (nom) RT = value of series resistor required For VCC = 5 V (5 – 4.55) / RT < 1 mA (2) Therefore, RT > 450 Ω (3) Using a 20%-tolerance resistor, RT should be greater than 560 Ω. Adding this series resistor changes the duration of the reset pulse by no more than 10%. RT extends the discharge of CT, but also skews the V(CT) threshold. These effects tend to cancel one another. The precise percentage change can be derived theoretically, but the equation is complicated by this interaction and is dependent upon the duration of the supply-voltage fault condition. Both outputs of the TL770xB must be terminated with similar value resistors, even when only one is being used. This prevents unwanted plateauing in either output waveform during switching, which may be interpreted as an undefined state or delay system reset. 14 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated TL7702B, TL7705B, TL7733B www.ti.com SLVS037O – SEPTEMBER 1989 – REVISED DECEMBER 2020 11 Layout 11.1 Layout Guidelines Figure 11-1 shows an example layout for the TL7705B device. As the RESET and RESET pins are open collector outputs, place pullup and pulldown resistors on the RESET and RESET pins respectively. A capacitor must be placed on the REF pin to stabilize the reference. This can help to prevent false triggering if noise couples into the reference. 11.2 Layout Example 5V 8 1 REF 2 RESIN SENSE 7 3 CT RESET 6 4 GND RESET 5 VCC 10 k 0.1 F 0.1 F 10 k GND Figure 11-1. TL7705B Layout Example Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 15 TL7702B, TL7705B, TL7733B www.ti.com SLVS037O – SEPTEMBER 1989 – REVISED DECEMBER 2020 12 Device and Documentation Support 12.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 12-1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY TL7702B Click here Click here Click here Click here Click here TL7705B Click here Click here Click here Click here Click here TL7733B Click here Click here Click here Click here Click here 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 16 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TL7702BCD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 7702BC Samples TL7702BCDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 7702BC Samples TL7702BCDRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 7702BC Samples TL7702BCDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 7702BC Samples TL7702BCP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL7702BCP Samples TL7702BID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 7702BI Samples TL7702BIDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 7702BI Samples TL7702BIP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TL7702BIP Samples TL7705BCD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 7705BC Samples TL7705BCDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 7705BC Samples TL7705BCDRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 7705BC Samples TL7705BCDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 7705BC Samples TL7705BCP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL7705BCP Samples TL7705BID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 7705BI Samples TL7705BIDE4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 7705BI Samples TL7705BIDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 7705BI Samples TL7705BIP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TL7705BIP Samples TL7705BQD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 7705BQ Samples TL7705BQDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 7705BQ Samples TL7705BQDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 7705BQ Samples Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TL7705BQDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 7705BQ Samples TL7733BCD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 7733BC Samples TL7733BCDE4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 7733BC Samples TL7733BCDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 7733BC Samples TL7733BCDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 7733BC Samples TL7733BCDRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 7733BC Samples TL7733BCP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL7733BCP Samples TL7733BID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 7733BI Samples TL7733BIDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 7733BI Samples TL7733BIDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 7733BI Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of