TLC04CD

TLC04/MF4A-50, TLC14/MF4A-100 BUTTERWORTH FOURTH-ORDER LOW-PASS SWITCHED-CAPACITOR FILTERS SLAS021A – NOVEMBER 1986 – REVISED MARCH 1995 D D D D D D D D D OR P PACKAGE (TOP VIEW) Low Clock-to-Cutoff-Frequency Ratio Error TLC04/MF4A-50 . . . ± 0.8% TLC14/MF4A-100 . . . ± 1% Filter Cutoff Frequency Dependent Only on External-Clock Frequency Stability Minimum Filter Response Deviation Due to External Component Variations Over Time and Temperature Cutoff Frequency Range From 0.1 Hz to 30 kHz, VCC ± = ± 2.5 V 5-V to 12-V Operation Self Clocking or TTL-Compatible and CMOS-Compatible Clock Inputs Low Supply-Voltage Sensitivity Designed to be Interchangeable With National MF4-50 and MF4-100 CLKIN CLKR LS VCC – 1 8 2 7 3 6 4 5 FILTER IN VCC+ AGND FILTER OUT description The TLC04/MF4A-50 and TLC14/MF4A-100 are monolithic Butterworth low-pass switched-capacitor filters. Each is designed as a low-cost, easy-to-use device providing accurate fourth-order low-pass filter functions in circuit design configurations. Each filter features cutoff frequency stability that is dependent only on the external-clock frequency stability. The cutoff frequency is clock tunable and has a clock-to-cutoff frequency ratio of 50:1 with less than ± 0. 8% error for the TLC04/MF4A-50 and a clock-to-cutoff frequency ratio of 100:1 with less than ± 1% error for the TLC14/MF4A-100. The input clock features self-clocking or TTL- or CMOS-compatible options in conjunction with the level shift (LS) terminal. The TLC04C/MF4A-50C and TLC14C/MF4A-100C are characterized for operation from 0°C to 70°C. The TLC04I/MF4A-50I and TLC14I/MF4A-100I are characterized for operation from – 40°C to 85°C. The TLC04M/MF4A-50M and TLC14M/MF4A-100M are characterized over the full military temperature range of – 55°C to 125°C. AVAILABLE OPTIONS PACKAGE TA CLOCK-TO-CUTOFF CLOCK TO CUTOFF FREQUENCY RATIO 0°C to 70°C 50:1 100:1 TLC04CD/MF4A-50CD TLC14CD/MF4A-100CD TLC04CP/MF4A-50CP TLC14CP/MF4A-100CP – 40°C to 85°C 50:1 100:1 TLC04ID/MF4A-50ID TLC14ID/MF4A-100ID TLC04IP/MF4A-50IP TLC14IP/MF4A-100IP – 55°C to 125°C 50:1 100:1 SMALL OUTLINE (D) PLASTIC DIP (P) TLC04MP/MF4A-50MP TLC14MP/MF4A-100MP The D package is available taped and reeled. Add the suffix R to the device type (e.g., TLC04CDR/MF4A-50CDR). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TLC04/MF4A-50, TLC14/MF4A-100 BUTTERWORTH FOURTH-ORDER LOW-PASS SWITCHED-CAPACITOR FILTERS SLAS021A – NOVEMBER 1986 – REVISED MARCH 1995 functional block diagram LS CLKIN CLKR Level Shift 3 1 2 Nonoverlapping Clock Generator φ1 FILTER IN AGND 8 φ2 Butterworth Fourth-Order Low-Pass Filter 6 5 FILTER OUT Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION AGND 6 I Analog ground. The noninverting input to the operational amplifiers of the Butterworth fourth-order low-pass filter. CLKIN 1 I Clock in. CLKIN is the clock input terminal for CMOS-compatible clock or self-clocking options. For either option, LS is at VCC – . For self-clocking, a resistor is connected between CLKIN and CLKR and a capacitor is connected from CLKIN to ground. CLKR 2 I Clock R. CLKR is the clock input for a TTL-compatible clock. For a TTL clock, LS is connected to midsupply and CLKIN can be left open, but it is recommended that it be connected to either VCC+ or VCC – . FILTER IN 8 I Filter input FILTER OUT 5 O Butterworth fourth-order low-pass filter output LS 3 I Level shift. LS accommodates the various input clocking options. For CMOS-compatible clocks or self-clocking, LS is at VCC – and for TTL-compatible clocks, LS is at midsupply. VCC+ VCC – 7 I Positive supply voltage terminal 4 I Negative supply voltage terminal 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC04/MF4A-50, TLC14/MF4A-100 BUTTERWORTH FOURTH-ORDER LOW-PASS SWITCHED-CAPACITOR FILTERS SLAS021A – NOVEMBER 1986 – REVISED MARCH 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC± (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 7 V Operating free-air temperature range, TA: TLC04C/MF4A-50C, TLC14C/MF4A-100C . . . . . . 0°C to 70°C TLC04I/MF4A-50I, TLC14I/MF4A-100I . . . . . . . . – 40°C to 85°C TLC04M/MF4A-50M, TLC14M/MF4A-100M . . . – 55°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to the AGND terminal. recommended operating conditions TLC04/MF4A-50 Positive supply voltage, VCC+ Negative supply voltage, VCC– MIN MAX 2.25 6 2.25 6 V – 2.25 –6 – 2.25 –6 V 2 Low-level input voltage, VIL V 5 5 5 0.8 1.5 x 106 2 x 106 0.1 40 x 103 0.05 20 x 103 0 70 0 70 TLC04I/MF4A-50I, TLC14I/MF4A-100I – 40 85 – 40 85 TLC04M/MF4A-50M, TLC14M/MF4A-100M – 55 125 – 55 125 5 TLC04C/MF4A-50C, TLC14C/MF4A-100C Operating free-air temperature, TA 2 0.8 1.5 x 106 2 x 106 VCC± = ± 2.5 V VCC± = ± 5 V Cutoff frequency, fco (see Note 3) UNIT MAX High-level input voltage, VIH frequency fclock Clock frequency, l k (see Note 2) TLC14/MF4A-100 MIN V Hz Hz °C NOTES: 2. Above 250 kHz, the input clock duty cycle should be 50% to allow the operational amplifiers the maximum time to settle while processing analog samples. 3. The cutoff frequency is defined as the frequency where the response is 3.01 dB less than the dc gain of the filter. electrical characteristics over recommended operating free-air temperature range, VCC+ = 2.5 V, VCC– = –2.5 V, fclock ≤ 250 kHz (unless otherwise noted) filter section TLC04/MF4A-50 PARAMETER VOO TEST CONDITIONS MIN TYP‡ Output offset voltage VOM Peak output voltage IOS Short circuit output current Short-circuit MAX TLC14/MF4A-100 MIN 25 VOM+ VOM – Source Sink RL = 10 kΩ TA = 25°C, 25°C TYP‡ 50 1.8 2 1.8 2 – 1.25 – 1.7 – 1.25 – 1.7 See Note 4 – 0.5 – 0.5 4 4 MAX UNIT mV V mA ICC Supply current fclock = 250 kHz 1.2 2.25 1.2 2.25 mA ‡ All typical values are at TA = 25°C. NOTE 4: IOS(source) is measured by forcing the output to its maximum positive voltage and then shorting the output to the VCC – terminal IOS(sink) is measured by forcing the output to its maximum negative voltage and then shorting the output to the VCC+ terminal. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TLC04/MF4A-50, TLC14/MF4A-100 BUTTERWORTH FOURTH-ORDER LOW-PASS SWITCHED-CAPACITOR FILTERS SLAS021A – NOVEMBER 1986 – REVISED MARCH 1995 electrical characteristics over recommended operating free-air temperature range, VCC+ = 5 V, VCC– = –5 V, fclock ≤ 250 kHz (unless otherwise noted) filter section VOO TLC04/MF4A-50 TYP† MAX TEST CONDITIONS PARAMETER MIN Output offset voltage VOM Peak output voltage IOS Short circuit output current Short-circuit TLC14/MF4A-100 TYP† MAX UNIT 200 mV MIN 150 VOM+ VOM – Source Sink RL = 10 kΩ 3.75 4.3 3.75 4.5 – 3.75 – 4.1 – 3.75 – 4.1 TA = 25°C,, See Note 4 –2 –2 5 5 V mA ICC Supply current fclock = 250 kHz 1.8 3 1.8 3 mA kSVS Supply voltage sensitivity (see Figures 1 and 2) – 30 – 30 dB † All typical values are at TA = 25°C. NOTE 4: IOS(source) is measured by forcing the output to its maximum positive voltage and then shorting the output to the VCC – terminal. IOS(sink) is measured by forcing the output to its maximum negative voltage and then shorting the output to the VCC+ terminal. clocking section PARAMETER MIN TYP† MAX VCC+ = 10 V, VCC – = 0 VCC+ = 5 V, VCC – = 0 VCC+ = 10 V, VCC – = 0 6.1 7 8.9 3.1 3.5 4.4 1.3 3 3.8 VCC+ = 5 V, VCC – = 0 VCC+ = 10 V, VCC – = 0 VCC+ = 5 V, VCC – = 0 0.6 1.5 1.9 2.3 4 7.6 1.2 2 3.8 TEST CONDITIONS VIT IT+ Positive going input threshold voltage Positive-going VIT – Negative going input threshold voltage Negative-going Vh hys Hysteresis voltage (VIT IT+ – VIT– IT ) VOH High level output voltage High-level VCC = 10 V VCC = 5 V IO = – 10 µA VOL Low level output voltage Low-level VCC = 10 V VCC = 5 V IO = 10 µA VCC = 10 V VCC = 5 V LS at midsupply, y, TA = 25°C VCC = 10 V VCC = 5 V CLKR and CLKIN shortened to VCC – –3 –7 – 0.75 –2 VCC = 10 V VCC = 5 V CLKR and CLKIN shortened to VCC+ 3 7 0.75 2 Input leakage current IO CLKIN CLKR Output current † All typical values are at TA = 25°C. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 UNIT V V V V 4.5 1 0.5 2 2 V µA mA mA TLC04/MF4A-50, TLC14/MF4A-100 BUTTERWORTH FOURTH-ORDER LOW-PASS SWITCHED-CAPACITOR FILTERS SLAS021A – NOVEMBER 1986 – REVISED MARCH 1995 operating characteristics over recommended operating free-air temperature range, VCC+ = 2.5 V, VCC– = –2.5 V (unless otherwise noted) TLC04/MF4A-50 PARAMETER TEST CONDITIONS Maximum clock frequency, fmax See Note 2 Clock-to-cutoff-frequency ratio (fclock/fco) fclock ≤ 250 kHz, Temperature coefficient of clock-to-cutoff frequency ratio fclock ≤ 250 kHz Frequency q y response above and below cutoff frequency (see Note 5) Dynamic range (see Note 6) Stop-band frequency attentuation at 2 fco Voltage amplification, dc TA = 25°C MIN TYP† 1.5 3 49.27 50.07 MAX 50.87 TLC14/MF4A-100 MIN TYP† 1.5 3 99 100 ± 25 MAX MHz 101 ± 25 Hz/Hz ppm/°C fco = 5 kHz, fclock kHz l k = 250 kHz, TA = 25°C f = 6 kHz – 7.9 – 7.57 – 7.1 f = 4.5 kHz – 1.7 – 1.46 – 1.3 fco = 5 kHz, fclock kHz l k = 250 kHz, TA = 25°C f = 3 kHz – 7.9 – 7.42 – 7.1 f = 2.25 kHz – 1.7 –1.51 – 1.3 dB dB TA = 25°C fclock ≤ 250 kHz fclock ≤ 250 kHz, TA = 25°C UNIT 80 RS ≤ 2 kΩ 24 25 – 0.15 0 78 0.15 24 25 – 0.15 0 dB dB 0.15 dB Peak-to-peak clock feedthrough voltage 5 5 mV † All typical values are at TA = 25°C. NOTES: 2. Above 250 kHz, the input clock duty cycle should be 50% to allow the operational amplifiers the maximum time to settle while processing analog samples. 5. The frequency responses at f are referenced to a dc gain of 0 dB. 6. The dynamic range is referenced to 1.06 V rms (1.5 V peak) where the wideband noise over a 30-kHz bandwidth is typically 106 µV rms for the TLC04/MF4A-50 and 135 µV rms for the TLC14/MF4A-100. operating characteristics over recommended operating free-air temperature range, VCC+ = 5 V, VCC– = –5 V (unless otherwise noted) TLC04/MF4A-50 PARAMETER TEST CONDITIONS Maximum clock frequency, fmax See Note 2 Clock-to-cutoff-frequency ratio (fclock/fco) fclock ≤ 250 kHz, Temperature coefficient of clock-to-cutoff frequency ratio fclock ≤ 250 kHz Frequency q y response above and below cutoff frequency (see Note 5) Dynamic range (see Note 6) Stop-band frequency attentuation at 2 fco Voltage amplification, dc TA = 25°C MIN TYP† 2 4 49.58 49.98 TLC14/MF4A-100 TYP† MAX MIN 2 4 50.38 99 100 ± 15 MAX MHz 101 ± 15 Hz/Hz ppm/°C fco = 5 kHz, fclock kHz l k = 250 kHz, TA = 25°C f = 6 kHz – 7.9 – 7.57 – 7.1 f = 4.5 kHz – 1.7 – 1.44 – 1.3 fco = 5 kHz, fclock kHz l k = 250 kHz, TA = 25°C TA = 25°C f = 3 kHz – 7.9 – 7.42 – 7.1 f = 2.25 kHz – 1.7 –1.51 – 1.3 fclock ≤ 250 kHz fclock ≤ 250 kHz, UNIT dB dB 86 RS ≤ 2 kΩ 24 25 – 0.15 0 0.15 84 dB 24 25 dB – 0.15 0 0.15 dB Peak-to-peak clock feedthrough voltage TA = 25°C 7 7 mV † All typical values are at TA = 25°C. NOTES: 2. Above 250 kHz, the input clock duty cycle should be 50% to allow the operational amplifiers the maximum time to settle while processing analog samples. 5. The frequency responses at f are referenced to a dc gain of 0 dB. 6. The dynamic range is referenced to 2.82 V rms (4 V peak) where the wideband noise over a 30-kHz bandwidth is typically 142 µV rms for the TLC04/MF4A-50 and 178 µV rms for the TLC14/MF4A-100. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TLC04/MF4A-50, TLC14/MF4A-100 BUTTERWORTH FOURTH-ORDER LOW-PASS SWITCHED-CAPACITOR FILTERS SLAS021A – NOVEMBER 1986 – REVISED MARCH 1995 TYPICAL CHARACTERISTICS FILTER OUTPUT vs SUPPLY VOLTAGE VCC+ RIPPLE FREQUENCY 0 VCC+ = 5 V + 50-mV Sine Wave (0 to 40 kHz) VCC – = – 5 V Filter in at 0 V fclock = 250 kHz Filter Output – dB – 10 – 20 – 30 – 40 – 50 – 60 0 5 10 15 20 25 30 35 40 Supply Voltage VCC+ Ripple Frequency – kHz Figure 1 FILTER OUTPUT vs SUPPLY VOLTAGE VCC – RIPPLE FREQUENCY 0 VCC+ = 5 V VCC – = – 5 V + 50-mV Sine Wave (0 to 40 kHz) Filter in at 0 V fclock = 250 kHz Filter Output – dB – 10 – 20 – 30 – 40 – 50 – 60 0 5 10 15 20 25 30 35 Supply Voltage VCC – Ripple Frequency – kHz Figure 2 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 40 TLC04/MF4A-50, TLC14/MF4A-100 BUTTERWORTH FOURTH-ORDER LOW-PASS SWITCHED-CAPACITOR FILTERS SLAS021A – NOVEMBER 1986 – REVISED MARCH 1995 APPLICATION INFORMATION 5V 7 VCC+ CMOS CLKIN 5V –5 V 3 LS 1 CLKIN 2 CLKR Level Shift Nonoverlapping Clock Generator φ1 8 FILTER IN 6 AGND φ2 Butterworth Fourth-Order Low-Pass Filter 5 FILTER OUT VCC – 4 –5 V Figure 3. CMOS-Clock-Driven Dual-Supply Operation 5V 7 VCC+ TTL CLKR –5 V 3 LS 1 CLKIN 2 CLKR Level Shift 0V Nonoverlapping Clock Generator φ1 8 FILTER IN 6 AGND φ2 Butterworth Fourth-Order Low-Pass Filter 5 FILTER OUT VCC – 4 –5 V Figure 4. TTL-Clock-Driven Dual-Supply Operation POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TLC04/MF4A-50, TLC14/MF4A-100 BUTTERWORTH FOURTH-ORDER LOW-PASS SWITCHED-CAPACITOR FILTERS SLAS021A – NOVEMBER 1986 – REVISED MARCH 1995 APPLICATION INFORMATION 5V 7 VCC+ R 3 LS 1 CLKIN 2 CLKR Level Shift C Nonoverlapping Clock Generator φ1 Filter Input 8 FILTER IN 6 AGND φ2 Butterworth Fourth-Order Low-Pass Filter FILTER OUT 5 Filter Output VCC – 4 –5 V f clock + ƪǒ Ǔǒ Ǔƫ 1 V RC In V –V CC IT– –V CC IT ) V ) IT V IT– For VCC = 10 V fclock = 1 1.69 RC Figure 5. Self-Clocking Through Schmitt-Trigger Oscillator Dual-Supply Operation 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC04/MF4A-50, TLC14/MF4A-100 BUTTERWORTH FOURTH-ORDER LOW-PASS SWITCHED-CAPACITOR FILTERS SLAS021A – NOVEMBER 1986 – REVISED MARCH 1995 APPLICATION INFORMATION 10 V 7 VCC+ 3 LS 1 CLKIN 2 CLKR Level Shift 10 V CMOS CLKIN See Note A 0V –5 V TTL CLKR Nonoverlapping Clock Generator 10 kΩ 0V FILTER IN (see Note B) φ1 5 VOC 8 FILTER IN 6 AGND φ2 Butterworth Fourth-Order Low-Pass Filter FILTER OUT 5 VCC – 0.1 µF 4 10 kΩ See Note C NOTES: A. The external clock used must be of CMOS level because the clock is input to a CMOS Schmitt trigger. B. The filter input signal should be dc-biased to midsupply or ac-coupled to the terminal. C. AGND must be biased to midsupply. Figure 6. External-Clock-Driven Single-Supply Operation POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TLC04/MF4A-50, TLC14/MF4A-100 BUTTERWORTH FOURTH-ORDER LOW-PASS SWITCHED-CAPACITOR FILTERS SLAS021A – NOVEMBER 1986 – REVISED MARCH 1995 APPLICATION INFORMATION 10 V 7 VCC+ R 3 LS 1 CLKIN 2 CLKR Level Shift Nonoverlapping Clock Generator C φ1 10 kΩ 8 FILTER IN 6 AGND Butterworth Fourth-Order Low-Pass Filter φ2 FILTER OUT VCC – 4 10 kΩ 0.1 µF See Note A f clock + ƪǒ Ǔǒ Ǔƫ 1 V RC In V –V CC IT– –V CC IT ) V ) IT V IT– For VCC = 10 V fclock = 1 1.69 RC NOTE A: AGND must be biased to midsupply. Figure 7. Self Clocking Through Schmitt-Trigger Oscillator Single-Supply Operation 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TLC04/MF4A-50, TLC14/MF4A-100 BUTTERWORTH FOURTH-ORDER LOW-PASS SWITCHED-CAPACITOR FILTERS SLAS021A – NOVEMBER 1986 – REVISED MARCH 1995 APPLICATION INFORMATION 5V 7 VCC+ Clock Input 3 LS 1 CLKIN 2 CLKR Level Shift Nonverlapping Clock Generator φ1 8 FILTER IN 6 AGND 10 kΩ Butterworth Fourth-Order Low-Pass Filter φ2 FILTER OUT 5 VCC – 0.1 µF 4 –5 V Figure 8. DC Offset Adjustment POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2022 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS K0 P1 B0 W Reel Diameter Cavity A0 B0 K0 W P1 A0 Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes Q1 Q2 Q1 Q2 Q3 Q4 Q3 Q4 User Direction of Feed Pocket Quadrants *All dimensions are nominal Device TLC04IDR Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2022 TAPE AND REEL BOX DIMENSIONS Width (mm) W L H *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC04IDR SOIC D 8 2500 350.0 350.0 43.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2022 TUBE T - Tube height L - Tube length W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) TLC04CD D SOIC 8 75 505.46 6.76 3810 4 TLC04ID D SOIC 8 75 505.46 6.76 3810 4 TLC14CD D SOIC 8 75 505.46 6.76 3810 4 TLC14ID D SOIC 8 75 505.46 6.76 3810 4 TLC14IDG4 D SOIC 8 75 505.46 6.76 3810 4 Pack Materials-Page 3 IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2022, Texas Instruments Incorporated