TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F – JUNE 1999 – REVISED DECEMBER 2011
www.ti.com
FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY
OPERATIONAL AMPLIFIERS
Check for Samples: TLC080 , TLC081, TLC082, TLC083, TLC084, TLC085, TLC08xA
FEATURES
DESCRIPTION
•
•
The
first
members
of
TI’s
new BiMOS
general-purpose operational amplifier family are the
TLC08x. The BiMOS family concept is simple:
provide an upgrade path for BiFET users who are
moving away from dual-supply to single-supply
systems and demand higher ac and dc performance.
With performance rated from 4.5 V to 16 V across
commercial (0°C to 70°C) and an extended industrial
temperature range (–40°C to 125°C), BiMOS suits a
wide range of audio, automotive, industrial, and
instrumentation applications. Familiar features like
offset nulling pins, and new features like MSOP
PowerPAD™ packages and shutdown modes, enable
higher levels of performance in a variety of
applications.
1
23
•
•
•
•
•
•
•
Wide Bandwidth: 10 MHz
High Output Drive:
– IOH: 57 mA at VDD – 1.5 V
– IOL: 55 mA at 0.5 V
High Slew Rate:
– SR+: 16 V/µs
– SR–: 19 V/µs
Wide Supply Range: 4.5 V to 16 V
Supply Current: 1.9 mA/Channel
Ultralow Power Shutdown Mode:
– IDD: 125 µA/Channel
Low Input Noise Voltage: 8.5 nV√Hz
Input Offset Voltage: 60 µV
Ultra-Small Packages:
– 8- or 10-Pin MSOP (TLC080/1/2/3)
Developed in TI’s patented LBC3 BiCMOS process,
the new BiMOS amplifiers combine a very high input
impedance, low-noise CMOS front end with a
high-drive bipolar output stage, thus providing the
optimum performance features of both. AC
performance improvements over the TL08x BiFET
predecessors include a bandwidth of 10 MHz (an
increase of 300%) and voltage noise of 8.5 nV/√Hz
(an improvement of 60%). DC improvements include
an ensured VICR that includes ground, a factor of 4
reduction in input offset voltage down to 1.5 mV
(maximum) in the standard grade, and a power
supply rejection improvement of greater than 40 dB to
130 dB. Added to this list of impressive features is
the ability to drive ±50-mA loads comfortably from an
ultrasmall-footprint MSOP PowerPAD package, which
positions the TLC08x as the ideal high-performance
general-purpose operational amplifier family.
–
+
FAMILY PACKAGE TABLE
PACKAGE TYPES
DEVICE
NO. OF
CHANNELS
MSOP
PDIP
SOIC
TSSOP
SHUTDOWN
TLC080
1
8
8
8
—
Yes
TLC081
1
8
8
8
—
TLC082
2
8
8
8
—
—
TLC083
2
10
14
14
—
Yes
TLC084
4
14
14
20
—
TLC085
4
16
16
20
Yes
UNIVERSAL
EVM BOARD
Refer to the EVM
Selection Guide
(Lit# SLOU060)
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2011, Texas Instruments Incorporated
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F – JUNE 1999 – REVISED DECEMBER 2011
www.ti.com
TLC080 and TLC081 AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SMALL OUTLINE
(D) (1)
SMALL OUTLINE
(DGN) (1)
SYMBOL
PLASTIC DIP
(P)
TLC080CD
TLC080CDGN
xxTIACW
TLC080CP
TLC081CD
TLC081CDGN
xxTIACY
TLC081CP
TLC080ID
TLC080IDGN
xxTIACX
TLC080IP
TLC081ID
TLC081IDGN
xxTIACZ
TLC081IP
TLC080AID
—
—
TLC080AIP
TLC081AID
—
—
TLC081AIP
0°C to 70°C
–40°C to 125°C
(1)
This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLC080CDR).
TLC082 and TLC083 AVAILABLE OPTIONS
PACKAGED DEVICES
SMALL
OUTLINE
(D) (1)
TA
0°C to 70°C
–40°C to 125°C
(1)
(2)
MSOP
(DGN)
(1)
SYMBOL
(2)
(DGQ)
(1)
SYMBOL
(2)
PLASTIC
DIP
(N)
PLASTIC
DIP
(P)
TLC082CP
TLC082CD
TLC082CDGN
xxTIADZ
—
—
—
TLC083CD
—
—
TLC083CDGQ
xxTIAEB
TLC083CN
—
TLC082ID
TLC082IDGN
xxTIAEA
—
—
—
TLC082IP
TLC083ID
—
—
TLC083IDGQ
xxTIAEC
TLC083IN
—
TLC082AID
—
—
—
—
—
TLC082AIP
TLC083AID
—
—
—
—
TLC083AIN
—
This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLC082CDR).
xx represents the device date code.
TLC084 and TLC085 AVAILABLE OPTIONS
PACKAGED DEVICES
TA
0°C to 70°C
–40°C to 125°C
(1)
SMALL OUTLINE
(D) (1)
PLASTIC DIP
(N)
TSSOP
(PWP) (1)
TLC084CD
TLC084CN
TLC084CPWP
TLC085CD
TLC085CN
TLC085CPWP
TLC084ID
TLC084IN
TLC084IPWP
TLC085ID
TLC085IN
TLC085IPWP
TLC084AID
TLC084AIN
TLC084AIPWP
TLC085AID
TLC085AIN
TLC085AIPWP
This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLC084CDR).
space
For the most current package and ordering information, see the Package Option Addendum at the end of this
data sheet, or see the TI web site at www.ti.com.
2
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Copyright © 1999–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F – JUNE 1999 – REVISED DECEMBER 2011
www.ti.com
TLC080
D, DGN, OR P PACKAGE
(TOP VIEW)
NULL
IN
IN +
GND
1
8
2
7
3
6
4
5
TLC081
D, DGN, OR P PACKAGE
(TOP VIEW)
NULL
IN
IN +
GND
SHDN
VDD
OUT
NULL
TLC083
DGQ PACKAGE
(TOP VIEW)
1OUT
1IN
1IN+
GND
1SHDN
1
2
3
4
5
10
9
8
7
6
TLC084
PWP PACKAGE
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
2
7
3
6
4
5
1OUT
1IN
1IN +
GND
NC
VDD
OUT
NULL
8
2
7
3
6
4
5
(TOP VIEW)
(TOP VIEW)
1
14
2
13
3
12
4
11
5
10
6
9
7
8
1OUT
1IN
1IN+
VDD
2IN+
2IN
2OUT
VDD
2OUT
2IN
2IN+
NC
2SHDN
NC
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
14
2
13
3
12
4
11
5
10
6
9
7
8
4OUT
4IN
4IN+
GND
3IN+
3IN
3OUT
(TOP VIEW)
(TOP VIEW)
1OUT
1IN
1IN+
VDD
2IN+
2IN
2OUT
1/2SHDN
1
VDD
2OUT
2IN
2IN+
TLC085
PWP PACKAGE
TLC085
D OR N PACKAGE
4OUT
4IN
4IN+
GND
3IN+
3IN
3OUT
NC
NC
NC
1
TLC084
D OR N PACKAGE
(TOP VIEW)
1OUT
1IN
1IN+
VDD
2IN+
2IN
2OUT
NC
NC
NC
8
TLC083
D OR N PACKAGE
1OUT
1IN
1IN+
GND
NC
1SHDN
NC
VDD
2OUT
2IN
2IN+
2SHDN
1
TLC082
D, DGN, OR P PACKAGE
(TOP VIEW)
4OUT
4IN
4IN+
GND
3IN +
3IN
3OUT
3/4SHDN
1OUT
1IN
1IN+
VDD
2IN+
2IN
2OUT
1/2SHDN
NC
NC
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
4OUT
4IN
4IN+
GND
3IN+
3IN
3OUT
3/4SHDN
NC
NC
NC - No internal connection
TYPICAL PIN 1 INDICATORS
Pin 1
Printed or
Molded Dot
Copyright © 1999–2011, Texas Instruments Incorporated
Pin 1
Stripe
Pin 1
Bevel Edges
Pin 1
Molded ”U” Shape
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Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
3
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F – JUNE 1999 – REVISED DECEMBER 2011
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage, VDD
(2)
Continuous total power dissipation
V
See Dissipation Rating Table
0 to 70
°C
I suffix
−40 to 125
°C
150
°C
–65 to 150
°C
260
°C
Storage temperature range, Tstg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(2)
17
C suffix
Maximum junction temperature, TJ
(1)
UNIT
±VDD
Differential input voltage range, VID
Operating free-air temperature range, TA:
VALUE
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to GND .
DISSIPATION RATING TABLE
PACKAGE
θJC
(°C/W)
θJA
(°C/W)
TA ≤ 25°C
POWER RATING
D (8)
38.3
176
710 mW
D (14)
26.9
122.3
1022 mW
D (16)
25.7
114.7
1090 mW
DGN (8)
4.7
52.7
2.37 W
DGQ (10)
4.7
52.3
2.39 W
N (14, 16)
32
78
1600 mW
P (8)
41
104
1200 mW
PWP (20)
1.40
26.1
4.79 W
RECOMMENDED OPERATING CONDITIONS
Single supply
Supply voltage, VDD
Split supply
Common-mode input voltage, VICR
Shutdown on/off voltage level (1)
Operating free-air temperature, TA
(1)
4
VIH
MIN
MAX
4.5
16
±2.25
±8
GND
VDD–2
2
VIL
C-suffix
I-suffix
0.8
0
70
–40
125
UNIT
V
V
V
°C
Relative to the voltage on the GND terminal of the device.
Submit Documentation Feedback
Copyright © 1999–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F – JUNE 1999 – REVISED DECEMBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TLC080/1/2/3,
VIO
Input offset voltage
∝VIO
Temperature coefficient of
input offset voltage
TLC084/5
VDD = 5 V,
VIC = 2.5 V,
VO = 2.5 V,
TLC080/1/2/3A,
TLC084/5A
TA (1)
MIN
25°C
TYP
MAX
390
1900
Full range
3000
25°C
390
Full range
Input offset current
RS = 50 Ω
TLC08XC
VIC = 2.5 V,
TLC08XI
VO = 2.5 V,
IIB
Input bias current
RS = 50 Ω
Common-mode input voltage
RS = 50 Ω
IOH = –1 mA
IOH = –20 mA
VOH
High-level output voltage
VIC = 2.5 V
IOH = –35 mA
IOH = –50 mA
IOL = 1 mA
IOL = 20 mA
VOL
Low-level output voltage
1.9
VIC = 2.5 V
IOL = 35 mA
3
0 to 3.0
0 to 3.5
Full range
0 to 3.0
0 to 3.5
4.3
25°C
4.1
Full range
3.9
25°C
3.7
Full range
3.5
25°C
3.4
Full range
3.2
25°C
3.2
3
25°C
0.18
Full range
0.35
Full range
25°C
0.43
0.55
0.45
0.63
Full range
–40°C to
85°C
0.7
25°C
57
VOL = 0.5 V from negative rail
25°C
55
ri(d)
Differential input resistance
CIC
Common-mode input
capacitance
f = 10 kHz
zo
Closed-loop output
impedance
f = 10 kHz,
CMRR
Common-mode rejection ratio VIC = 0 to 3 V,
kSVR
Supply voltage rejection ratio
(ΔVDD /ΔVIO)
RL = 10 kΩ
AV = 10
RS = 50 Ω
VDD = 4.5 V to 16 V, VIC = VDD/2,
No load
V
0.7
VOH = 1.5 V from positive rail
VO(PP) = 3 V,
0.39
0.45
100
Large-signal differential
voltage amplification
0.25
0.35
25°C
100
AVD
(1)
3.6
25°C
Output current
V
3.8
25°C
IO
V
4
Sinking
Short-circuit output current
pA
700
25°C
Sourcing
IOS
50
100
25°C
IOL = 50 mA
pA
700
Full range
–40°C to
85°C
50
100
Full range
25°C
TLC08XC
TLC08XI
VICR
µV/°C
1.2
VDD = 5 V,
µV
1400
2000
25°C
IIO
UNIT
25°C
100
Full range
100
120
mA
mA
dB
25°C
1000
GΩ
25°C
22.9
pF
25°C
0.25
Ω
25°C
80
Full range
80
25°C
80
Full range
80
110
100
dB
dB
Full range is 0°C to 70°C for C suffix and –40°C to 125°C for I suffix. If not specified, full range is –40°C to 125°C.
Copyright © 1999–2011, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
5
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F – JUNE 1999 – REVISED DECEMBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
IDD
TEST CONDITIONS
Supply current (per channel)
VO = 2.5 V,
Supply current in shutdown
IDD(SHDN) mode (per channel) (TLC080,
TLC083, TLC085)
No load
TA (1)
MIN
MAX
1.8
2.5
25°C
Full range
3.5
25°C
SHDN ≤ 0.8 V
TYP
125
Full range
UNIT
mA
200
250
µA
OPERATING CHARACTERISTICS
at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VO(PP) = 0.8 V,
SR+
Positive slew rate at unity
gain
SR–
Negative slew rate at unity VO(PP) = 0.8 V,
gain
RL = 10 kΩ
Vn
Equivalent input noise
voltage
In
Equivalent input noise
current
THD + N
Total harmonic distortion
plus noise
t(on)
Amplifier turnon time (2)
t(off)
Amplifier turnoff time (2)
Gain-bandwidth product
ts
φm
Settling time
Phase margin
Gain margin
(1)
(2)
6
CL = 50 pF,
RL = 10 kΩ
CL = 50 pF,
TA (1)
MIN
TYP
16
25°C
10
Full range
9.5
25°C
12.5
Full range
19
10
f = 100 Hz
25°C
12
f = 1 kHz
25°C
8.5
f = 1 kHz
25°C
0.6
VO(PP) = 3 V,
AV = 1
RL = 10 kΩ and 250 Ω,
AV = 10
f = 1 kHz
AV = 100
RL = 10 kΩ
f = 10 kHz,
RL = 10 kΩ
V(STEP)PP = 1 V,
AV = −1,
CL = 10 pF,
RL = 10 kΩ
0.1%
V(STEP)PP = 1 V,
AV = –1,
CL = 47 pF,
RL = 10 kΩ
0.1%
RL = 10 kΩ,
CL = 50 pF
RL = 10 kΩ,
CL = 0 pF
RL = 10 kΩ,
CL = 50 pF
RL = 10 kΩ,
CL = 0 pF
MAX
UNIT
V/µs
V/µs
nV/√Hz
fA /√Hz
0.002
25°C
0.012
%
0.085
µs
25°C
0.15
25°C
1.3
µs
25°C
10
MHz
0.18
0.01%
0.39
25°C
0.01%
0.18
µs
0.39
25°C
25°C
32
40
2.2
3.3
°
dB
Full range is 0°C to 70°C for C suffix and –40°C to 125°C for I suffix. If not specified, full range is –40°C to 125°C.
Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the
supply current has reached half its final value.
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Copyright © 1999–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F – JUNE 1999 – REVISED DECEMBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
at specified free-air temperature, VDD = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TLC080/1/2/3,
VIO
Input offset voltage
∝VIO
Temperature coefficient of
input offset voltage
TLC084/5
VDD = 12 V,
VIC = 6 V,
VO = 6 V,
TLC080/1/2/3A,
TLC084/5A
TA (1)
MIN
25°C
TYP
MAX
390
1900
Full range
3000
25°C
390
Full range
Input offset current
RS = 50 Ω
TLC08xC
VIC = 6 V,
TLC08xI
VO = 6 V,
IIB
Input bias current
RS = 50 Ω
Common-mode input voltage
RS = 50 Ω
IOH = –1 mA
IOH = –20 mA
VOH
High-level output voltage
VIC = 6 V
IOH = –35 mA
IOH = –50 mA
IOL = 1 mA
IOL = 20 mA
VOL
Low-level output voltage
1.5
VIC = 6 V
IOL = 35 mA
3
0 to 10.5
Full range
0 to 10.0
0 to 10.5
11.1
11.2
25°C
10.8
Full range
10.7
25°C
10.6
Full range
10.3
25°C
10.3
–40°C to
85°C
10.2
25°C
10.5
0.17
Full range
0.35
Full range
25°C
0.4
Full range
–40°C to
85°C
25°C
57
VOL = 0.5 V from negative rail
25°C
55
ri(d)
Differential input resistance
CIC
Common-mode input
capacitance
f = 10 kHz
zo
Closed-loop output
impedance
f = 10 kHz,
CMRR
Common-mode rejection ratio VIC = 0 to 10 V,
kSVR
Supply voltage rejection ratio
(ΔVDD /ΔVIO)
RL = 10 kΩ
AV = 10
RS = 50 Ω
VDD = 4.5 V to 16 V, VIC = VDD/2,
No load
V
0.6
0.65
VOH = 1.5 V from positive rail
VO(PP) = 8 V,
0.52
0.6
0.45
150
Large-signal differential
voltage amplification
0.45
0.5
150
AVD
0.25
0.35
25°C
25°C
Output current
V
10.7
25°C
IO
(1)
11
Sinking
Short-circuit output current
V
11
Sourcing
IOS
pA
700
0 to 10.0
25°C
IOL = 50 mA
50
100
25°C
25°C
pA
700
Full range
Full range
50
100
Full range
25°C
TLC08xC
TLC08xI
VICR
µV/°C
1.2
VDD = 12 V,
µV
1400
2000
25°C
IIO
UNIT
25°C
120
Full range
120
140
mA
mA
dB
25°C
1000
GΩ
25°C
21.6
pF
25°C
0.25
Ω
25°C
80
Full range
80
25°C
80
Full range
80
110
100
dB
dB
Full range is 0°C to 70°C for C suffix and –40°C to 125°C for I suffix. If not specified, full range is –40°C to 125°C.
Copyright © 1999–2011, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
7
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F – JUNE 1999 – REVISED DECEMBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
at specified free-air temperature, VDD = 12 V (unless otherwise noted)
PARAMETER
IDD
TEST CONDITIONS
Supply current (per channel)
VO = 7.5 V,
Supply current in shutdown
IDD(SHDN) mode (TLC080, TLC083,
TLC085) (per channel)
No load
TA (1)
MIN
MAX
1.9
2.9
25°C
Full range
3.5
25°C
SHDN ≤ 0.8 V
TYP
125
UNIT
mA
200
Full range
250
µA
OPERATING CHARACTERISTICS
at specified free-air temperature, VDD = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VO(PP) = 2 V,
SR+
Positive slew rate at unity
gain
SR–
Negative slew rate at unity VO(PP) = 2 V,
gain
RL = 10 kΩ
Vn
Equivalent input noise
voltage
In
Equivalent input noise
current
THD + N
Total harmonic distortion
plus noise
t(on)
Amplifier turnon time (2)
t(off)
Amplifier turnoff time (2)
Gain-bandwidth product
ts
φm
Settling time
Phase margin
Gain margin
(1)
(2)
8
CL = 50 pF,
RL = 10 kΩ
CL = 50 pF,
TA (1)
MIN
TYP
16
25°C
10
Full range
9.5
25°C
12.5
Full range
19
10
f = 100 Hz
25°C
14
f = 1 kHz
25°C
8.5
f = 1 kHz
25°C
0.6
VO(PP) = 8 V,
AV = 1
RL = 10 kΩ and 250 Ω,
AV = 10
f = 1 kHz
AV = 100
RL = 10 kΩ
f = 10 kHz,
RL = 10 kΩ
V(STEP)PP = 1 V,
AV = −1,
CL = 10 pF,
RL = 10 kΩ
0.1%
V(STEP)PP = 1 V,
AV = –1,
CL = 47 pF,
RL = 10 kΩ
0.1%
RL = 10 kΩ,
CL = 50 pF
RL = 10 kΩ,
CL = 0 pF
RL = 10 kΩ,
CL = 50 pF
RL = 10 kΩ,
CL = 0 pF
MAX
UNIT
V/µs
V/µs
nV/√Hz
fA /√Hz
0.002
25°C
0.005
%
0.022
µs
25°C
0.47
25°C
2.5
µs
25°C
10
MHz
0.17
0.01%
0.22
25°C
0.01%
0.17
µs
0.29
25°C
25°C
37
42
3.1
4
°
dB
Full range is 0°C to 70°C for C suffix and –40°C to 125°C for I suffix. If not specified, full range is –40°C to 125°C.
Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the
supply current has reached half its final value.
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SLOS254F – JUNE 1999 – REVISED DECEMBER 2011
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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
Input offset voltage
vs Common-mode input voltage
1, 2
IIO
Input offset current
vs Free-air temperature
3, 4
IIB
Input bias current
vs Free-air temperature
3, 4
VOH
High-level output voltage
vs High-level output current
5, 7
VOL
Low-level output voltage
vs Low-level output current
6, 8
Zo
Output impedance
vs Frequency
9
IDD
Supply current
vs Supply voltage
10
PSRR
Power supply rejection ratio
vs Frequency
11
CMRR
Common-mode rejection ratio
vs Frequency
12
Vn
Equivalent input noise voltage
vs Frequency
13
VO(PP)
Peak-to-peak output voltage
vs Frequency
14, 15
Crosstalk
vs Frequency
16
Differential voltage gain
vs Frequency
17, 18
Phase
vs Frequency
17, 18
Phase margin
vs Load capacitance
19, 20
Gain margin
vs Load capacitance
21, 22
Gain-bandwidth product
vs Supply voltage
SR
Slew rate
vs Supply voltage
vs Free-air temperature
24
25, 26
THD + N
Total harmonic distortion plus noise
vs Frequency
27, 28
vs Peak-to-peak output voltage
29, 30
φm
23
Large-signal follower pulse response
31, 32
Small-signal follower pulse response
33
Large-signal inverting pulse response
34, 35
Small-signal inverting pulse response
36
Shutdown forward isolation
vs Frequency
37, 38
Shutdown reverse isolation
vs Frequency
39, 40
Shutdown supply current
vs Supply voltage
41
vs Free-air temperature
Shutdown pulse
Copyright © 1999–2011, Texas Instruments Incorporated
42
43, 44
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9
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F – JUNE 1999 – REVISED DECEMBER 2011
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TYPICAL CHARACTERISTICS
1500
VDD = 5 V
TA = 25° C
600
400
200
0
-200
-400
1100
900
700
500
300
100
-100
-300
-600
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
-500
0
3
4
5
6
7
8
9 10 11 12
200
150
100
IIB
50
0
IIO
-50
-100
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
TA – Free-Air Temperature – °C
Figure 1.
Figure 2.
Figure 3.
INPUT BIAS CURRENT AND
INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
5.0
0
IIO
-20
-40
-60
-80
-100
IIB
-120
VDD = 12 V
-140
1.0
VDD = 5 V
VOL – Low-Level Output Voltage – V
20
4.5
TA = 70°C
TA = 25°C
4.0
TA = 40 °C
3.5
TA = 125°C
3.0
2.5
2.0
-160
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
VDD = 5 V
0.9
0.8
0.7
TA = 125°C
0.6
TA = 70°C
TA = 25°C
0.5
0.4
0.3
TA = 40 °C
0.2
0.1
0.0
0
5
10 15 20 25 30 35 40 45 50
IOH - High-Level Output Current - mA
0
5 10 15 20 25 30 35 40 45 50
IOL – Low-Level Output Current – mA
Figure 4.
Figure 5.
Figure 6.
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
OUTPUT IMPEDANCE
vs
FREQUENCY
1000
1.0
11.5
11.0
TA = 40 °C
10.5
TA = 25°C
10.0
9.5
VDD = 12 V
0.9
0.8
TA = 125°C
0.7
TA = 70°C
0.6
TA = 25°C
0.5
0.4
0.3
TA = 40 °C
0.2
0.1
0
5
10 15 20 25 30 35 40 45 50
IOH – High-Level Output Current – mA
Figure 7.
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100
VDD = 5 V and 12 V
TA = 25°C
10
AV = 100
1
AV = 10
0.10
AV = 1
VDD = 12 V
0.0
9.0
ZO – Output Impedance – W
TA = 125°C
TA = 70°C
VOL – Low-Level Output Voltage –V
12.0
VOH – High-Level Output Voltage – V
2
VDD = 5 V
250
VICR – Common-Mode Input Voltage – V
TA – Free-Air Temperature – °C
10
1
300
VICR – Common-Mode Input Voltage – V
VOH – High-Level Output Voltage – V
IIB/IIO – Input Bias and Input Offset Current – pA
VDD = 12 V
TA = 25° C
1300
VIO – Input Offset Voltage - mV
VIO – Input Offset Voltage – mV
1000
800
INPUT BIAS CURRENT AND
INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
IIB/IIO – Input Bias and Input Offset Current – pA
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
0
5
10 15 20 25 30 35 40 45
IOL – Low-Level Output Current – mA
50
0.01
100
1k
10k
100k
1M
f – Frequency – Hz
Figure 8.
10M
Figure 9.
Copyright © 1999–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F – JUNE 1999 – REVISED DECEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS
POWER SUPPLY REJECTION
RATIO
vs
FREQUENCY
2.4
TA = 25°C
TA = 40 °C
2.0
1.8
TA = 125°C
1.6
TA = 70°C
1.4
AV = 1
SHDN = VDD
Per Channel
1.2
1.0
4
5
6
7
8
140
120
VDD = 12 V
100
80
60
40
VDD = 5 V
20
0
9 10 11 1 2 13 14 15
0
10
100k
1M
10M
100
80
60
40
20
0
100
1k
10k
100k
1M
f – Frequency – Hz
Figure 11.
Figure 12.
EQUIVALENT INPUT NOISE
VOLTAGE
vs
FREQUENCY
PEAK-TO-PEAK OUTPUT
VOLTAGE
vs
FREQUENCY
PEAK-TO-PEAK OUTPUT
VOLTAGE
vs
FREQUENCY
30
25
20
15
VDD = 12 V
10
VDD = 5 V
5
0
10
10k
VDD = 5 V and 12 V
TA = 25°C
120
Figure 10.
V O(PP) – Peak-to-Peak Output Voltage – V
Hz
Vn – Equivalent Input Noise Voltage – nV/
35
1k
140
f – Frequency – Hz
VDD – Supply Voltage – V
40
100
100
1k
10k
12
VDD = 12 V
10
8
6
VDD = 5 V
4
THD+N < = 5%
RL = 600 Ω
TA = 25°C
2
0
10k
100k
V O(PP) – Peak-to-Peak Output Voltage – V
IDD – Supply Current – mA
2.2
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
CMRR – Common-Mode Rejection Ratio – dB
PSRR – Power Supply Rejection Ratio – dB
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
f – Frequency – Hz
100k
1M
f – Frequency – Hz
Figure 13.
10M
10M
12
10
VDD = 12 V
8
6
VDD = 5 V
4
2
0
10k
THD+N < = 5%
RL= 10 kΩ
TA = 25°C
100k
1M
f – Frequency – H
Figure 14.
10M
Figure 15.
CROSSTALK
vs
FREQUENCY
0
-20
Crosstalk – dB
-40
VDD = 5 V and 12 V
AV = 1
RL = 10 kΩ
VI(PP) = 2 V
For All Channels
-60
-80
-100
-120
-140
-160
10
100
1k
10k
100k
f – Frequency – Hz
Figure 16.
Copyright © 1999–2011, Texas Instruments Incorporated
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11
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SLOS254F – JUNE 1999 – REVISED DECEMBER 2011
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TYPICAL CHARACTERISTICS
DIFFERENTIAL VOLTAGE GAIN AND
PHASE
vs
FREQUENCY
80
Gain
A VD – Different Voltage Gain – dB
60
-45
50
Phase
40
-90
30
20
-135
10
0
-10
-20
1k
VDD = ±2.5 V
RL = 10 kΩ
CL = 0 pF
TA = 25°C
10k
-180
100k
1M
10M
-225
100M
20
-135
10
0
-20
1k
VDD = ±6 V
RL = 10 kΩ
CL = 0 pF TA
= 25°C
Rnull = 0 Ω
3.5
Rnull = 20 Ω
VDD = 5 V
RL = 10 kΩ
TA = 25°C
Rnull = 50 Ω
30°
Rnull = 100 Ω
25°
20°
Rnull = 20 Ω
15°
VDD = 12 V
RL = 10 kΩ
TA = 25°C
10°
5°
2
Rnull = 50 Ω
1.5
1
VDD = 5 V
RL = 10 kΩ
TA = 25°C
Rnull = 20 Ω
100
CL – Load Capacitance – pF
CL – Load Capacitance – pF
Figure 19.
Figure 20.
Figure 21.
GAIN MARGIN
vs
LOAD CAPACITANCE
GAIN BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
SLEW RATE
vs
SUPPLY VOLTAGE
GBWP – Gain Bandwidth Product – MHz
Rnull = 0 Ω
Rnull = 100 Ω
4
3.5
3
Rnull = 50 Ω
2
Rnull = 20 Ω
1.5
VDD = 12 V
RL = 10 kΩ
TA = 25°C
10.0
22
CL = 11 pF
9.9
9.8
20
9.7
RL = 10 kΩ
9.6
9.5
9.4
RL = 600 Ω
9.3
100
CL – Load Capacitance – pF
Figure 22.
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19
Slew Rate
18
17
16
Slew Rate +
15
9.2
14
9.1
13
9.0
0
10
RL = 600 Ω and 10 kΩ
CL = 50 pF
AV = 1
21
TA = 25°C
SR – Slew Rate – V/ms
5
4.5
1
2.5
0
10
100
CL – Load Capacitance – pF
Rnull = 100 Ω
3
0.5
0°
10
100
G – Gain Margin – dB
φ m – Phase Margin
Rnull = 50 Ω
0°
10
100M
4
Rnull = 0 Ω
40°
25°
0.5
10M
GAIN MARGIN
vs
LOAD CAPACITANCE
35°
2.5
1M
PHASE MARGIN
vs
LOAD CAPACITANCE
30°
5°
-225
100k
10k
45°
10°
-180
Figure 18.
15°
-90
30
f – Frequency – Hz
35°
φ m – Phase Margin
Phase
40
Figure 17.
Rnull = 0 Ω
Rnull = 100 Ω
20°
-45
50
f – Frequency – Hz
40°
φ m – Phase Margin – dB
Gain
60
-10
PHASE MARGIN
vs
LOAD CAPACITANCE
12
0
70
Phase – °
0
70
Phase – °
A VD – Different Voltage Gain – dB
80
DIFFERENTIAL VOLTAGE GAIN AND
PHASE
vs
FREQUENCY
12
4
5
6
7 8 9 10 11 12 13 14 15 16
VDD – Supply Voltage – V
4
5
6
7 8 9 10 11 12 13 14 15 16
VDD – Supply Voltage – V
Figure 23.
Figure 24.
Copyright © 1999–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F – JUNE 1999 – REVISED DECEMBER 2011
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TYPICAL CHARACTERISTICS
SLEW RATE
vs
FREE-AIR TEMPERATURE
25
Slew Rate
Slew Rate –
20
15
Slew Rate +
10
15
Slew Rate +
10
5
VDD = 12 V
RL= 600 Ω and 10 kΩ
CL = 50 pF
AV = 1
5
Total Harmonic Distortion + Noise – %
VDD = 5 V
RL= 600 Ω and 10 kΩ
CL = 50 pF
AV = 1
SR – Slew Rate – V/ms
VDD = 5 V
VO(PP) = 2 V
RL = 10 kΩ
AV = 100
0.1
AV = 10
0.01
AV = 1
0
-55 -35 -15 5 25 45 65 85 105 125
TA – Free-Air Temperature –°C
0
-55 -35 -15 5 25 45 65 85 105 125
TA – Free-Air Temperature – °C
Figure 25.
Figure 26.
Figure 27.
TOTAL HARMONIC DISTORTION
PLUS NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION
PLUS NOISE
vs
PEAK-TO-PEAK OUTPUT VOLTAGE
TOTAL HARMONIC DISTORTION
PLUS NOISE
vs
PEAK-TO-PEAK OUTPUT VOLTAGE
10
10
Total Harmonic Distortion + Noise – %
VDD = 12 V
VO(PP) = 8 V
RL = 10 kΩ
AV = 100
0.01
AV = 10
AV = 1
0.001
100
1k
10k
100k
VDD = 5 V
AV = 1
f = 1 kHz
1
0.1
RL = 600 Ω
0.01
RL = 10 kΩ
0.001
0.0001
0.25 0.75 1.25
100k
VDD = 12 V
AV = 1
f = 1 kHz
RL = 250 Ω
0.1
RL = 600 Ω
0.01
0.001
RL = 10 kΩ
0.0001
0.5
2.5
4.5
6.5
8.5
Figure 29.
Figure 30.
LARGE SIGNAL FOLLOWER
PULSE RESPONSE
LARGE SIGNAL FOLLOWER
PULSE RESPONSE
SMALL SIGNAL FOLLOWER
PULSE RESPONSE
VDD = 5 V
RL = 600 Ω
and 10 kΩ
CL = 8 pF
TA = 25°C
0.2 0.4 0.6 0.8
1 1.2 1.4 1.6 1.8 2
VO – Output Voltage – V
VO (500 mV/Div)
VI (5 V/Div)
VO (2 V/Div)
VDD = 12 V
RL = 600 Ω
and 10 kΩ
CL = 8 pF
TA = 25°C
0
0.2 0.4 0.6 0.8
1 1.2 1.4 1.6 1.8 2
VI(100mV/Div)
VO(50mV/Div)
VDD = 5 V and 12 V
RL = 600Ω and 10 kΩ
CL = 8 pF
TA = 25°C
0
0.8 0.9 0.10
0.1 0. 2 0.3 0.4 0.5 0.6 0.7 0.
t – Time – ms
t – Time – ms
t – Time – ms
Figure 31.
Figure 32.
Figure 33.
Copyright © 1999–2011, Texas Instruments Incorporated
10.5
VO(PP) – Peak-to-Peak Output Voltage – V
Figure 28.
VI (1 V/Div)
V O – Output Voltage – V
1.75 2.25 2.75 3.25 3.75
10k
1
VO(PP) – Peak-to-Peak Output Voltage – V
f – Frequency – Hz
0
RL = 250 Ω
1k
f – Frequency– Hz
Total Harmonic Distortion + Noise – %
0.1
0.001
100
VO – Output Voltage – V
SR – Slew Rate – V/ms
1
25
20
Total Harmonic Distortion + Noise – %
TOTAL HARMONIC DISTORTION
PLUS NOISE
vs
FREQUENCY
SLEW RATE
vs
FREE-AIR TEMPERATURE
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13
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SLOS254F – JUNE 1999 – REVISED DECEMBER 2011
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TYPICAL CHARACTERISTICS
LARGE SIGNAL INVERTING
PULSE RESPONSE
LARGE SIGNAL INVERTING
PULSE RESPONSE
VI (5 V/div)
VDD = 5 V
RL = 600 Ω
and 10 kΩ
CL = 8 pF
TA = 25°C
VI (100 mV/div)
VO – Output Voltage – V
VO – Output Voltage – V
VO – Output Voltage – V
VI (2 V/div)
SMALL SIGNAL INVERTING
PULSE RESPONSE
VDD = 12 V
RL = 600 Ω
and 10 kΩ
CL = 8 pF
TA = 25°C
VDD = 5 V and 12 V
RL = 600 Ω and 10 kΩ
CL = 8 pF
TA = 25°C
VO (50 mV/Div)
VO (2 V/Div)
VO (500 mV/Div)
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
Figure 35.
Figure 36.
SHUTDOWN FORWARD
ISOLATION
vs
FREQUENCY
SHUTDOWN FORWARD
ISOLATION
vs
FREQUENCY
SHUTDOWN REVERSE
ISOLATION
vs
FREQUENCY
140
120
100
RL = 600 Ω
80
60
RL = 10 kΩ
40
1k
10k 100k
1M
f – Frequency – Hz
10M
120
100
80
RL = 600 Ω
60
RL = 10 kΩ
40
20
100
100M
1k
10k
100k
1M
10M
VDD = 5 V
CL= 0 pF
TA = 25°C
VI(PP) = 0.1, 2.5, and 5 V
120
100
80
RL = 600 Ω
60
RL = 10 kΩ
40
20
100
100M
1k
10k
100k
1M
10M
100M
f – Frequency – Hz
Figure 37.
Figure 38.
Figure 39.
SHUTDOWN REVERSE
ISOLATION
vs
FREQUENCY
SHUTDOWN SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SHUTDOWN SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
I DD(SHDN) – Shutdown Supply Current – mA
VDD = 12 V
CL= 0 pF
TA = 25°C
VI(PP) = 0.1, 8, 12 V
120
100
80
RL = 600 Ω
60
RL = 10 kΩ
40
20
1k
10k 100k
1M
f – Frequency – Hz
10M
100M
Figure 40.
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136
Shutdown On
RL = open
VIN = VDD/2
134
132
130
128
126
124
122
120
118
4
5
6
7
8 9 10 11 12 13 14 15 16
VDD – Supply Voltage – V
I DD(SHDN) – Shutdown Supply Current – mA
f – Frequency – Hz
140
100
140
VDD = 12 V
CL= 0 pF
TA = 25°C
VI(PP) = 0.1, 8, 12 V
Sutdown Reverse Isolation – dB
VDD = 5 V
CL= 0 pF
TA = 25°C
VI(PP) = 0.1, 2.5, and 5 V
100
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Figure 34.
Sutdown Forward Isolation – dB
Sutdown Forward Isolation – dB
0
1.2 1.4 1.6 1.8 2
t – Time – ms
20
Sutdown Reverse Isolation – dB
1
t – Time – ms
140
14
0.2 0.4 0.6 0.8
t – Time – ms
180
AV = 1
VIN = VDD/2
160
140
VDD = 12 V
120
VDD = 5 V
100
80
60
–55
–25
5
35
65
95
TA – Free-Air Temperature –°C
Figure 41.
125
Figure 42.
Copyright © 1999–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F – JUNE 1999 – REVISED DECEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS
SHUTDOWN PULSE
SHUTDOWN PULSE
5.5
4
Shutdown Pulse
I DD – Supply Current – mA
5.0
4.5
4.0
2
VDD = 5 V
CL= 8 pF
TA = 25°C
3.5
3.0
2.5
0
IDD RL = 10 kΩ
2.0
1.5
-2
IDD RL = 600 Ω
1.0
6
5.5
SD Off
Shutdown Pulse - V
I DD – Supply Current – mA
6.0
6
-4
0.5
SD Off
5.0
4
Shutdown Pulse
4.5
4.0
2
VDD = 12 V
CL= 8 pF
TA = 25°C
3.5
3.0
2.5
0
IDD RL = 10 kΩ
2.0
1.5
-2
IDD RL = 600 Ω
1.0
Shutdown Pulse - V
6.0
-4
0.5
0.0
0
10
20
30 40 50
t – Time – ms
60
70
80
0.0
-6
0
10
20
Figure 43.
30 40 50
t – Time – ms
60
70
-6
80
Figure 44.
PARAMETER MEASUREMENT INFORMATION
Rnull
_
+
RL
CL
Figure 45
Figure 45.
APPLICATION INFORMATION
Input Offset Voltage Null Circuit
The TLC080 and TLC081 has an input offset nulling function. Refer to Figure 46 for the diagram.
IN
OUT
N2
+
IN +
N1
100 kΩ
R1
VDD
A.
R1 = 5.6 kΩ for offset voltage adjustment of ±10 mV. R1 = 20 kΩ for offset voltage adjustment of ±3 mV.
Figure 46. Input Offset Voltage Null Circuit
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15
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F – JUNE 1999 – REVISED DECEMBER 2011
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Driving a Capacitive Load
When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the
device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 10 pF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier, as
shown in Figure 47. A minimum value of 20 Ω should work well for most applications.
RF
RG
RNULL
_
Input
Output
+
CLOAD
Figure 47. Driving a Capacitive Load
Offset Voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage:
RF
IIB–
RG
+
VI
VO
+
RS
IIB+
V
( ( ))
1
V
OO = IO +
RF
R
G
± I IB + R S
( ( ))
1+
RF
R
G
± I IB– R F
Figure 48. Output Offset Voltage Model
16
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TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F – JUNE 1999 – REVISED DECEMBER 2011
www.ti.com
High Speed CMOS Input Amplifiers
The TLC08x is a family of high-speed low-noise CMOS input operational amplifiers that has an input capacitance
of the order of 20 pF. Any resistor used in the feedback path adds a pole in the transfer function equivalent to the
input capacitance multiplied by the combination of source resistance and feedback resistance. For example, a
gain of –10, a source resistance of 1 kΩ, and a feedback resistance of 10 kΩ add an additional pole at
approximately 8 MHz. This is more apparent with CMOS amplifiers than bipolar amplifiers due to their greater
input capacitance.
This is of little consequence on slower CMOS amplifiers, as this pole normally occurs at frequencies above their
unity-gain bandwidth. However, the TLC08x with its 10-MHz bandwidth means that this pole normally occurs at
frequencies where there is on the order of 5dB gain left and the phase shift adds considerably.
The effect of this pole is the strongest with large feedback resistances at small closed loop gains. As the
feedback resistance is increased, the gain peaking increases at a lower frequency and the 180° phase shift
crossover point also moves down in frequency, decreasing the phase margin.
For the TLC08x, the maximum feedback resistor recommended is 5 kΩ; larger resistances can be used but a
capacitor in parallel with the feedback resistor is recommended to counter the effects of the input capacitance
pole.
The TLC083 with a 1-V step response has an 80% overshoot with a natural frequency of 3.5 MHz when
configured as a unity gain buffer and with a 10-kΩ feedback resistor. By adding a 10-pF capacitor in parallel with
the feedback resistor, the overshoot is reduced to 40% and eliminates the natural frequency, resulting in a much
faster settling time (see Figure 49). The 10-pF capacitor was chosen for convenience only.
2
VIN
VO – Output Voltage – V
1
0
With
CF = 10 pF
1
1.5
VI – Input Voltage – V
Load capacitance had little effect on these measurements due to the excellent output drive capability of the
TLC08x.
10 pF
10 kΩ
_
1
IN
0.5
VOUT
0
VDD = ±5 V
AV = +1
RF = 10 kΩ
RL = 600 Ω
CL = 22 pF
+
600 Ω
50 Ω
22 pF
0.5
0
0.2 0.4 0.6 0.8
t - Time - ms
1
1.2 1.4 1.6
Figure 49. 1-V Step Response
Copyright © 1999–2011, Texas Instruments Incorporated
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17
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F – JUNE 1999 – REVISED DECEMBER 2011
www.ti.com
General Configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into theFigure 50 system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see ).
RG
RF
VO
+
VI
R1
C1
f
V
O
V
I
=
(
1+
R
R
F
G
)(
1
–3dB = 2pR1C1
1
1 + sR1C1
)
Figure 50. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
C1
+
_
VI
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
R2
f
C2
RG
RF
1
–3dB = 2pRC
RG =
(
RF
1
2–
Q
)
Figure 51. 2-Pole Low-Pass Sallen-Key Filter
18
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TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F – JUNE 1999 – REVISED DECEMBER 2011
www.ti.com
Shutdown Function
Three members of the TLC08x family (TLC080/3/5) have a shutdown terminal (SHDN) for conserving battery life
in portable applications. When the shutdown terminal is tied low, the supply current is reduced to
125 µA/channel, the amplifier is disabled, and the outputs are placed in a high-impedance mode. To enable the
amplifier, the shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left
floating, care should be taken to ensure that parasitic leakage current at the shutdown terminal does not
inadvertently place the operational amplifier into shutdown. The shutdown terminal threshold is always
referenced to the voltage on the GND terminal of the device. Therefore, when operating the device with split
supply voltages (e.g. ±2.5 V), the shutdown terminal needs to be pulled to VDD– (not system ground) to disable
the operational amplifier.
The amplifier’s output with a shutdown pulse is shown in Figure 43 and Figure 44. The amplifier is powered with
a single 5-V supply and is configured as noninverting with a gain of 5. The amplifier turnon and turnoff times are
measured from the 50% point of the shutdown pulse to the 50% point of the output waveform. The times for the
single, dual, and quad are listed in the data tables.
Figure 37 through Figure 40 show the amplifiers forward and reverse isolation in shutdown. The operational
amplifier is configured as a voltage follower (AV = 1). The isolation performance is plotted across frequency using
0.1 VPP, 2.5 VPP, and 5 VPP input signals at ±2.5 V supplies and 0.1 VPP, 8 VPP, and 12 VPP input signals at ±6 V
supplies.
Circuit Layout Considerations
To achieve the levels of high performance of the TLC08x, follow proper printed-circuit board design techniques.
A general set of guidelines is given in the following.
• Ground planes – It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and output,
the ground plane can be removed to minimize the stray capacitance.
• Proper power supply decoupling – Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor
on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the
application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier.
In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distance
increases, the inductance in the connecting trace makes the capacitor less effective. The designer should
strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors.
• Sockets – Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is
the best implementation.
• Short trace runs/compact part placements – Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the
amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the
input of the amplifier.
• Surface-mount passive components – Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept
as short as possible.
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19
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TLC083, TLC084, TLC085, TLC08xA
SLOS254F – JUNE 1999 – REVISED DECEMBER 2011
www.ti.com
General PowerPAD Design Considerations
The TLC08x is available in a thermally-enhanced PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which the die is mounted [see Figure 52(a) and Figure 52(b)]. This
arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see
Figure 52(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance
can be achieved by providing a good thermal path away from the thermal pad.
DIE
Side View (a)
Thermal
Pad
DIE
Bottom View (c)
End View (b)
A.
The thermal pad is electrically isolated from all terminals in the package.
Figure 52. Views of Thermally-Enhanced DGN Package
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad must be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
Soldering the PowerPAD to the printed circuit board (PCB) is always required, even with applications
that have low power dissipation. This soldering provides the necessary thermal and mechanical connection
between the lead frame die pad and the PCB.
Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the
recommended approach.
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TLC080 , TLC081, TLC082
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SLOS254F – JUNE 1999 – REVISED DECEMBER 2011
www.ti.com
The PowerPAD must be connected to the most negative supply voltage (GND pin potential) of the device.
1. Prepare the PCB with a top side etch pattern (see the landing patterns at the end of this data sheet). There
should be etch for the leads as well as etch for the thermal pad.
2. Place five holes (dual) or nine holes (quad) in the area of the thermal pad. These holes should be 13 mils in
diameter. Keep them small so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the TLC08x IC. These additional vias may be larger than the 13-mil diameter
vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be
soldered so that wicking is not a problem.
4. Connect all holes to the internal plane that is at the same potential as the ground pin of the device.
5. When connecting these holes to this internal plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In
this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the
holes under the TLC08x PowerPAD package should make their connection to the internal ground plane with
a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes (dual) or nine holes (quad) exposed. The bottom-side solder mask should cover the five or nine holes
of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the
reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the TLC08x IC is simply placed in position and run through the solder
reflow operation as any standard surface-mount component. This results in a part that is properly installed.
For a given θJA, the maximum power dissipation is shown in Figure 53 and is calculated by the following formula:
æ T -TA ö
PD= ç MAX ÷
è θJA ø
(1)
Where:
PD =
Maximum power dissipation of TLC08x IC (watts)
TMAX =
Absolute maximum junction temperature (150°C)
TA =
Free-ambient air temperature (°C)
θJA =
θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
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TLC080 , TLC081, TLC082
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SLOS254F – JUNE 1999 – REVISED DECEMBER 2011
www.ti.com
Maximum Power Dissipation – W
7
6
5
4
3
2
PWP Package
Low-K Test PCB
θJA = 29.7°C/W
TJ = 150°C
SOT-23 Package
Low-K Test PCB
θJA = 324°C/W2
DGN Package
Low-K Test PCB
θJA = 52.3°C/W
SOIC Package
Low-K Test PCB
θJA = 176°C/W
PDIP Package
Low-K Test PCB
θJA = 104°C/W
1
0
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
TA – Free-Air Temperature – °C
A.
Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 53. Maximum Power Dissipation vs Free-Air Temperature
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the device,
especially multi-amplifier devices. Because these devices have linear output stages (Class A-B), most of the heat
dissipation is at low output voltages with high output currents.
The other key factor when dealing with power dissipation is how the devices are mounted on the PCB. The
PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a
copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other
hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the
device, θJA decreases and the heat dissipation capability increases. The currents and voltages shown in these
graphs are for the total package. For the dual or quad amplifier packages, the sum of the RMS output currents
and voltages should be used to choose the proper package.
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TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F – JUNE 1999 – REVISED DECEMBER 2011
www.ti.com
Macromodel Information
Macromodel information provided was derived using Microsim Parts™, the model generation software used with
Microsim PSpice™. The Boyle macromodel (see (1)) and subcircuit in Figure 54 are generated using the TLC08x
typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the
following key parameters can be generated to a tolerance of 20% (in most cases):
• Maximum positive output voltage swing
• Maximum negative output voltage swing
• Slew rate
• Quiescent power dissipation
• Input bias current
• Open-loop voltage amplification
• Unity-gain frequency
• Common-mode rejection ratio
• Phase margin
• DC output resistance
• AC output resistance
• Short-circuit output current limit
(1)
G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE
Journal of Solid-State Circuits, SC-9, 353 (1974).
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23
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SLOS254F – JUNE 1999 – REVISED DECEMBER 2011
www.ti.com
Figure 54. Boyle Macromodel and Subcircuit
24
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Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F – JUNE 1999 – REVISED DECEMBER 2011
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (April 2006) to Revision F
•
Page
Updated Figure 9 ................................................................................................................................................................ 10
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25
PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLC080AIDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C080AI
Samples
TLC080AIP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 125
TLC080AI
Samples
TLC080CDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
ACW
Samples
TLC080CDGNRG4
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
ACW
Samples
TLC080CDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
C080C
Samples
TLC080ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C080I
Samples
TLC080IDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
ACX
Samples
TLC080IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C080I
Samples
TLC081AID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C081AI
Samples
TLC081AIDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C081AI
Samples
TLC081AIP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 125
TLC081AI
Samples
TLC081CD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
C081C
Samples
TLC081CDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
ACY
Samples
TLC081CDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
ACY
Samples
TLC081CDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
C081C
Samples
TLC081CP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TLC081C
Samples
TLC081ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C081I
Samples
TLC081IDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
ACZ
Samples
TLC081IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C081I
Samples
TLC081IP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 125
TLC081I
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLC082AID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C082AI
Samples
TLC082AIDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C082AI
Samples
TLC082AIDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C082AI
Samples
TLC082AIP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 125
C082AI
Samples
TLC082CD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
C082C
Samples
TLC082CDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
C082C
Samples
TLC082CDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
ADZ
Samples
TLC082CDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
ADZ
Samples
TLC082CDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
C082C
Samples
TLC082CP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
C082C
Samples
TLC082ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C082I
Samples
TLC082IDGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AEA
Samples
TLC082IDGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AEA
Samples
TLC082IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C082I
Samples
TLC082IDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C082I
Samples
TLC082IP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 125
C082I
Samples
TLC083AID
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C083AI
Samples
TLC083CDGQR
ACTIVE
HVSSOP
DGQ
10
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
AEB
Samples
TLC083CDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
C083C
Samples
TLC083CN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
C083C
Samples
TLC083IDGQ
ACTIVE
HVSSOP
DGQ
10
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AEC
Samples
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLC083IN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 125
C083I
Samples
TLC084AID
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLC084AI
Samples
TLC084AIDG4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLC084AI
Samples
TLC084AIDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLC084AI
Samples
TLC084AIN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 125
TLC084AI
Samples
TLC084AIPWP
ACTIVE
HTSSOP
PWP
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLC084AI
Samples
TLC084AIPWPR
ACTIVE
HTSSOP
PWP
20
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLC084AI
Samples
TLC084CD
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC084C
Samples
TLC084CDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC084C
Samples
TLC084CN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TLC084C
Samples
TLC084CPWP
ACTIVE
HTSSOP
PWP
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
TLC084C
Samples
TLC084CPWPR
ACTIVE
HTSSOP
PWP
20
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
TLC084C
Samples
TLC084ID
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLC084I
Samples
TLC084IDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLC084I
Samples
TLC084IDRG4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLC084I
Samples
TLC084IPWP
ACTIVE
HTSSOP
PWP
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLC084I
Samples
TLC084IPWPR
ACTIVE
HTSSOP
PWP
20
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLC084I
Samples
TLC085AID
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLC085AI
Samples
TLC085AIDR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLC085AI
Samples
TLC085AIN
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 125
TLC085AI
Samples
TLC085AIPWP
ACTIVE
HTSSOP
PWP
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLC085AI
Samples
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLC085CN
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TLC085C
Samples
TLC085CPWP
ACTIVE
HTSSOP
PWP
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
TLC085C
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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