TLC1543QDBG4

TLC1542I,, TLC1542M,, TLC1542Q TLC1542C, TLC1543C, TLC1543I, TLC1543Q www.ti.com SLAS052G – MARCH 1992 – REVISED JANUARY 2006 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS • • • • • • • • • 10-Bit Resolution A/D Converter 11 Analog Input Channels Three Built-In Self-Test Modes Inherent Sample-and-Hold Function Total Unadjusted Error: ±1LSB Max On-Chip System Clock End-of-Conversion (EOC) Output Terminal Compatible With TLC542 CMOS Technology DB, DW, J, OR N PACKAGE (TOP VIEW) A0 A1 A2 A3 A4 A5 A6 A7 A8 GND DESCRIPTION In addition to a high-speed A/D converter and versatile control capability, these devices have an on-chip 14-channel multiplexer that can select any one of 11 analog inputs or any one of three internal self-test voltages. The sample-and-hold function is automatic. At the end of A/D conversion, the end-of-conversion (EOC) output goes high to indicate that conversion is complete. The converter incorporated in the devices features differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry from logic and supply noise. A switched-capacitor design allows low-error conversion over the full operating free-air temperature range. 20 2 3 19 18 4 5 17 16 6 7 15 14 8 9 13 12 10 11 VCC EOC I/O CLOCK ADDRESS DATA OUT CS REF + REF − A10 A9 FK OR FN PACKAGE (TOP VIEW) A2 A1 A0 VCC EOC The TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, and TLC1543Q are CMOS 10-bit switched-capacitor successive-approximation analog-to-digital converters. These devices have three inputs and a 3-state output [chip select (CS), input-output clock (I/O CLOCK), address input (ADDRESS), and data output (DATA OUT)] that provide a direct 4-wire interface to the serial port of a host processor. These devices allow high-speed data transfers from the host. 1 A3 A4 A5 A6 A7 4 3 2 1 20 19 18 5 6 17 16 7 15 14 9 10 11 12 13 8 I/O CLOCK ADDRESS DATA OUT CS REF + A8 GND A9 A10 REF − FEATURES Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1992–2006, Texas Instruments Incorporated TLC1542I,, TLC1542M,, TLC1542Q TLC1542C, TLC1543C, TLC1543I, TLC1543Q www.ti.com SLAS052G – MARCH 1992 – REVISED JANUARY 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OPTIONS PACKAGE SMALL OUTLINE (DB) TA 0°C to 70°C SMALL OUTLINE (DW) CHIP CARRIER (FN) PLASTIC DIP (N) TLC1542CDW TLC1542CFN TLC1542CN TLC1543CDW TLC1543CFN TLC1543CN TLC1542IDW TLC1542IFN TLC1542IN TLC1543IDB TLC1543IDW TLC1543IFN TLC1543IN TLC1543QDB TLC1543QDW TLC1543CDB -40°C to 85°C CHIP CARRIER (FK) CERAMIC DIP (J) TLC1542MFK TLC1542MJ TLC1542QFN -40°C to 125°C TLC1543QFN -55°C to 125°C FUNCTIONAL BLOCK DIAGRAM REF+ 14 REF − 13 1 A0 2 A1 Sample and Hold 3 4 A2 A3 5 6 7 A4 A5 A6 8 9 11 A7 A8 A9 10 14-Channel Analog Multiplexer 4 12 A10 10-Bit Analog-to-Digital Converter (switched capacitors) Output Data Register Input Address Register 10 10-to-1 Data Selector and Driver 16 DATA OUT 4 3 System Clock, Control Logic, and I/O Counters Self-Test Reference ADDRESS I/O CLOCK 19 EOC 17 18 15 CS TYPICAL EQUIVALENT INPUTS INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE 1 kΩ TYP A0 −A10 Ci = 60 pF TYP (equivalent input capacitance) 2 INPUT CIRCUIT IMPEDANCE DURING HOLD MODE Submit Documentation Feedback A0 −A10 5 MΩ TYP TLC1542I,, TLC1542M,, TLC1542Q TLC1542C, TLC1543C, TLC1543I, TLC1543Q www.ti.com SLAS052G – MARCH 1992 – REVISED JANUARY 2006 TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION 17 I Serial address input. A 4-bit serial address selects the desired analog input or test voltage that is to be converted next. The address data is presented with the MSB first and shifts in on the first four rising edges of I/O CLOCK. After the four address bits have been read into the address register, this input is ignored for the remainder of the current conversion period. 1-9, 11, 12 I Analog signal inputs. The 11 analog inputs are applied to these terminals and are internally multiplexed. The driving source impedance should be less than or equal to 1 kΩ. CS 15 I Chip select. A high-to-low transition on this input resets the internal counters and controls and enables DATA OUT, ADDRESS, and I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system clock. A low-to-high transition disables ADDRESS and I/O CLOCK within a setup time plus two falling edges of the internal system clock. DATA OUT 16 O The 3-state serial output for the A/D conversion result. This output is in the high-impedance state when CS is high and active when CS is low. With a valid chip select, DATA OUT is removed from the high-impedance state and is driven to the logic level corresponding to the MSB value of the previous conversion result. The next falling edge of I/O CLOCK drives this output to the logic level corresponding to the next most significant bit, and the remaining bits shift out in order with the LSB appearing on the ninth falling edge of I/O CLOCK. On the tenth falling edge of I/O CLOCK, DATA OUT is driven to a low logic level so that serial interface data transfers of more than ten clocks produce zeroes as the unused LSBs. EOC 19 O End of conversion. This output goes from a high to a low logic level on the trailing edge of the tenth I/O CLOCK and remains low until the conversion is complete and data are ready for transfer. GND 10 I The ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to this terminal. I/O CLOCK 18 I Input/output clock. This terminal receives the serial I/O CLOCK input and performs the following four functions: 1) It clocks the four input address bits into the address register on the first four rising edges of the I/O CLOCK with the multiplex address available after the fourth rising edge. 2) On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplex input begins charging the capacitor array and continues to do so until the tenth falling edge of I/O CLOCK. 3) It shifts the nine remaining bits of the previous conversion data out on DATA OUT. 4) It transfers control of the conversion to the internal state controller on the falling edge of the tenth clock. REF+ 14 I The upper reference voltage value (nominally VCC) is applied to this terminal. The maximum input voltage range is determined by the difference between the voltage applied to this terminal and the voltage applied to the REF- terminal. REF- 13 I The lower reference voltage value (nominally ground) is applied to this terminal. VCC 20 I Positive supply voltage NAME ADDRESS A0-A10 NO. DETAILED DESCRIPTION With chip select (CS) inactive (high), the ADDRESS and I/O CLOCK inputs are initially disabled and DATA OUT is in the high-impedance state. When the serial interface takes CS active (low), the conversion sequence begins with the enabling of I/O CLOCK and ADDRESS and the removal of DATA OUT from the high-impedance state. The serial interface then provides the 4-bit channel address to ADDRESS and the I/O CLOCK sequence to I/O CLOCK. During this transfer, the serial interface also receives the previous conversion result from DATA OUT. I/O CLOCK receives an input sequence that is between 10 and 16 clocks long from the host serial interface. The first four I/O clocks load the address register with the 4-bit address on ADDRESS, selecting the desired analog channel, and the next six clocks providing the control timing for sampling the analog input. There are six basic serial-interface timing modes that can be used with the device. These modes are determined by the speed of I/O CLOCK and the operation of CS as shown in Table 1. These modes are (1) a fast mode with a 10-clock transfer and CS inactive (high) between conversion cycles, (2) a fast mode with a 10-clock transfer and CS active (low) continuously, (3) a fast mode with an 11- to 16-clock transfer and CS inactive (high) between conversion cycles, (4) a fast mode with a 16-clock transfer and CS active (low) continuously, (5) a slow mode with an 11- to 16-clock transfer and CS inactive (high) between conversion cycles, and (6) a slow mode with a 16-clock transfer and CS active (low) continuously. Submit Documentation Feedback 3 TLC1542I,, TLC1542M,, TLC1542Q TLC1542C, TLC1543C, TLC1543I, TLC1543Q www.ti.com SLAS052G – MARCH 1992 – REVISED JANUARY 2006 The MSB of the previous conversion appears at DATA OUT on the falling edge of CS in mode 1, mode 3, and mode 5, on the rising edge of EOC in mode 2 and mode 4, and following the sixteenth clock falling edge in mode 6. The remaining nine bits are shifted out on the next nine falling edges of I/O CLOCK. Ten bits of data are transmitted to the host-serial interface through DATA OUT. The number of serial clock pulses used also depends on the mode of operation, but a minimum of ten clock pulses is required for conversion to begin. On the tenth clock falling edge, the EOC output goes low and returns to the high logic level when conversion is complete and the result can be read by the host. Also, on the tenth clock falling edge, the internal logic takes DATA OUT low to ensure that the remaining bit values are zero when the I/O CLOCK transfer is more than ten clocks long. Table 1 lists the operational modes with respect to the state of CS, the number of I/O serial transfer clocks that can be used, and the timing edge on which the MSB of the previous conversion appears at the output. Table 1. MODE OPERATION MODES Fast Modes Slow Modes (1) (2) (3) CS NO. OF 1/O CLOCK MSB AT DATA OUT (1) TIMING DIAGRAM Mode 1 High between conversion cycles 10 CS falling edge Figure 9 Mode 2 Low continuously 10 EOC rising edge Figure 10 Mode 3 High between conversion cycles 11 TO 16 (2) CS falling edge Figure 11 Mode 4 Low continuously 16 (2) EOC rising edge Figure 12 CS falling edge Figure 13 16th clock falling edge Figure 14 Mode 5 High between conversion cycles Mode 6 Low continuously 11 to 16 (3) 16 (3) These edges also initiate serial-interface communication. No more than 16 clocks should be used. No more than 16 clocks should be used. FAST MODES The device is in a fast mode when the serial I/O CLOCK data transfer is completed before the conversion is completed. With a 10-clock serial transfer, the device can only run in a fast mode since a conversion does not begin until the falling edge of the tenth I/O CLOCK. MODE 1: FAST MODE, CS INACTIVE (HIGH) BETWEEN CONVERSION CYCLES, 10-CLOCK TRANSFER In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer is ten clocks long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time plus two falling edges of the internal system clock. MODE 2: FAST MODE, CS ACTIVE (LOW) CONTINUOUSLY, 10-CLOCK TRANSFER In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer is ten clocks long. After the initial conversion cycle, CS is held active (low) for subsequent conversions; the rising edge of EOC then begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the previous conversion to appear immediately on this output. MODE 3: FAST MODE, CS INACTIVE (HIGH) BETWEEN CONVERSION CYCLES, 11- to 16-CLOCK TRANSFER In this mode, CS is inactive (high) between serial I/O CLOCK transfers, and each transfer can be 11 to 16 clocks long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time plus two falling edges of the internal system clock. 4 Submit Documentation Feedback TLC1542I,, TLC1542M,, TLC1542Q TLC1542C, TLC1543C, TLC1543I, TLC1543Q www.ti.com SLAS052G – MARCH 1992 – REVISED JANUARY 2006 MODE 4: FAST MODE, CS ACTIVE (LOW) CONTINUOUSLY, 16-CLOCK TRANSFER In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks long. After the initial conversion cycle, CS is held active (low) for subsequent conversions; the rising edge of EOC then begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the previous conversion to appear immediately on this output. SLOW MODES In a slow mode, the conversion is completed before the serial I/O CLOCK data transfer is completed. A slow mode requires a minimum 11-clock transfer into I/O CLOCK, and the rising edge of the eleventh clock must occur before the conversion period is complete; otherwise, the device loses synchronization with the host-serial interface and CS has to be toggled to initialize the system. The eleventh rising edge of the I/O CLOCK must occur within 9.5 µs after the tenth I/O clock falling edge. MODE 5: SLOW MODE, CS INACTIVE (HIGH) BETWEEN CONVERSION CYCLES, 11- to 16-CLOCK TRANSFER In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 11 to 16 clocks long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time plus two falling edges of the internal system clock. MODE 6: SLOW MODE, CS ACTIVE (LOW) CONTINUOUSLY, 16-CLOCK TRANSFER In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks long. After the initial conversion cycle, CS is held active (low) for subsequent conversions. The falling edge of the sixteenth I/O CLOCK then begins each sequence by removing DATA OUT from the low state, allowing the MSB of the previous conversion to appear immediately at DATA OUT. The device is then ready for the next 16-clock transfer initiated by the serial interface. ADDRESS BITS The 4-bit analog channel-select address for the next conversion cycle is presented to the ADDRESS terminal (MSB first) and is clocked into the address register on the first four leading edges of I/O CLOCK. This address selects one of 14 inputs (11 analog inputs or three internal test inputs). ANALOG INPUTS AND TEST MODES The 11 analog inputs and the three internal test inputs are selected by the 14-channel multiplexer according to the input address as shown in Tables 2 and 3. The input multiplexer is a break-before-make type to reduce input-to-input noise injection resulting from channel switching. Sampling of the analog input starts on the falling edge of the fourth I/O CLOCK, and sampling continues for six I/O CLOCK periods. The sample is held on the falling edge of the tenth I/O CLOCK. The three test inputs are applied to the multiplexer, sampled, and converted in the same manner as the external analog inputs. Submit Documentation Feedback 5 TLC1542I,, TLC1542M,, TLC1542Q TLC1542C, TLC1543C, TLC1543I, TLC1543Q www.ti.com SLAS052G – MARCH 1992 – REVISED JANUARY 2006 Table 2. ANALOG-CHANNEL-SELECT ADDRESS ANALOG INPUT SELECTED VALUE SHIFTED INTO ADDRESS INPUT BINARY HEX A0 0000 0 A1 0001 1 A2 0010 2 A3 0011 3 A4 0100 4 A5 0101 5 A6 0110 6 A7 0111 7 A8 1000 8 A9 1001 9 A10 1010 A Table 3. TEST-MODE-SELECT ADDRESS INTERNAL SELF-TEST VOLTAGE SELECTED (1) OUTPUT RESULT (HEX) (2) BINARY HEX 1011 B Vref- 1100 C 000 Vref+ 1101 D 3FF Vref+ − Vref− 2 (1) (2) VALUE SHIFTED INTO ADDRESS INPUT 200 Vref+ is the voltage applied to the REF+ input, and Vref- is the voltage applied to the REF- input. The output results shown are the ideal values and vary with the reference stability and with internal offsets. CONVERTER AND ANALOG INPUT The CMOS threshold detector in the successive-approximation conversion system determines each bit by examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the conversion process, the analog input is sampled by closing the SC switch and all ST switches simultaneously. This action charges all the capacitors to the input voltage. In the next phase of the conversion process, all ST and SC switches are opened and the threshold detector begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF-) voltage. In the switching sequence, ten capacitors are examined separately until all ten bits are identified and then the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector looks at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the REF+ voltage, and the equivalent nodes of all the other capacitors on the ladder are switched to REF-. If the voltage at the summing node is greater than the trip point of the threshold detector (approximately one-half VCC), a 0 bit is placed in the output register and the 512-weight capacitor is switched to REF-. If the voltage at the summing node is less than the trip point of the threshold detector, a 1 bit is placed in the register and the 512-weight capacitor remains connected to REF+ through the remainder of the successive-approximation process. The process is repeated for the 256-weight capacitor, the 128-weight capacitor, and so forth down the line until all bits are counted. With each step of the successive-approximation process, the initial charge is redistributed among the capacitors. The conversion process relies on charge redistribution to count and weigh the bits from MSB to LSB. 6 Submit Documentation Feedback TLC1542I,, TLC1542M,, TLC1542Q TLC1542C, TLC1543C, TLC1543I, TLC1543Q www.ti.com SLAS052G – MARCH 1992 – REVISED JANUARY 2006 SC Threshold Detector 512 Node 512 REF − 256 128 REF+ REF+ REF − ST 16 REF+ REF − ST 8 REF+ REF − ST 4 REF − ST REF+ REF − ST 2 1 REF+ REF+ REF − ST REF − ST To Output Latches 1 REF − ST ST VI Figure 1. Simplified Model of the Successive-Approximation System CHIP-SELECT OPERATION The trailing edge of CS starts all modes of operation, and CS can abort a conversion sequence in any mode. A high-to-low transition on CS within the specified time during an ongoing cycle aborts the cycle, and the device returns to the initial state (the contents of the output data register remain at the previous conversion result). Exercise care to prevent CS from being taken low close to completion of conversion because the output data can be corrupted. REFERENCE VOLTAGE INPUTS There are two reference inputs used with the device: REF+ and REF-. These voltage values establish the upper and lower limits of the analog input to produce a full-scale and zero reading respectively. The values of REF+, REF-, and the analog input should not exceed the positive supply or be lower than GND consistent with the specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to or higher than REF+ and at zero when the input signal is equal to or lower than REF-. Submit Documentation Feedback 7 TLC1542I,, TLC1542M,, TLC1542Q TLC1542C, TLC1543C, TLC1543I, TLC1543Q www.ti.com SLAS052G – MARCH 1992 – REVISED JANUARY 2006 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT VCC, see (2) Supply voltage range -0.5 V to 6.5 V VI Input voltage range -0.3 V to VCC + 0.3 V VO Output voltage range -0.3 V to VCC + 0.3 V Vref+ Positive reference voltage VCC + 0.1 V Vref- Negative reference voltage -0.1 V ±20 mA Peak input current (any input) ±30 mA Peak total input current (all inputs) TLC1542C, TLC1543C TA Operating free-air temperature range Tstg Storage temperature range, 0°C to 70°C TLC1542I, TLC1543I -40°C to 85°C TLC1542Q, TLC1543Q -40°C to 125°C TLC1542M -55°C to 125°C -65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds (1) (2) 260°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to digital ground with REF- and GND wired together (unless otherwise noted). RECOMMENDED OPERATING CONDITIONS MIN VCC Supply voltage Vref+, see (1) Positive reference voltage Vref-, see (1) 4.5 (1) 2.5 (1) 0 VIH High-level control input voltage VCC = 4.5 V to 5.5 V VIL Low-level control input voltage VCC = 4.5 V to 5.5 V tsu(A), see Figure 4 Setup time, address bits at data input before I/O CLOCK↑ th(A), see Figure 4 th(CS), see Figure 5 tsu(CS), see Figure 5 (2) and 5.5 VCC UNIT V V V VCC+0. 2 V VCC V 2 V 0.8 V 100 ns Hold time, address bits after I/O CLOCK↑ 0 ns Hold time, CS low after last I/O CLOCK↓ 0 ns 1.425 µs Setup time, CS low before clocking in first address bit Clock frequency at I/O CLOCK, see (3) 0 2.1 MHz twH(I/O) Pulse duration, I/O CLOCK high, 190 ns twL(I/O) Pulse duration, I/O CLOCK low, 190 ns tt(I/O), see Figure 6 tt(CS) (1) (2) (3) (4) 8 5 0 Differential reference voltage Analog input voltage ,see MAX VCC Negative reference voltage Vref+-Vref-, see NOM (4) and Transition time, I/O CLOCK, Transition time, ADDRESS and CS, 1 µs 10 µs Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied to REF- convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref+ - Vref-); however, the electrical specifications are no longer applicable. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed. For 11- to 16-bit transfers, after the tenth I/O CLOCK falling edge (≤ 2 V) at least 1 I/O CLOCK rising edge (≥ 2 V) must occur within 9.5 µs. This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of normal room temperature, the devices function with input clock transition time as slow as 1 µs for remote data-acquisition applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor. Submit Documentation Feedback TLC1542I,, TLC1542M,, TLC1542Q TLC1542C, TLC1543C, TLC1543I, TLC1543Q www.ti.com SLAS052G – MARCH 1992 – REVISED JANUARY 2006 RECOMMENDED OPERATING CONDITIONS (continued) MIN TLC1542C, TLC1543C TA Operating free-air temperature, NOM MAX 0 UNIT 70 TLC1542I, TLC1543I -40 85 TLC1542Q, TLC1543Q -40 125 TLC1542M -55 125 °C ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range, VCC = Vref+ = 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz (unless otherwise noted) PARAMETER MIN TYP (1) TEST CONDITIONS MAX VCC = 4.5 V, IOH = -1.6 mA VCC = 4.5 V to 5.5 V, IOH = -20 µA VCC = 4.5 V, IOL = 1.6 mA 0.4 VCC = 4.5 V to 5.5 V, IOL = 20 µA 0.1 Off-state (high-impedance-state) output current VO = VCC, CS at VCC 10 VO = 0, CS at VCC -10 IIH High-level input current VI = VCC 0.005 2.5 IIL Low-level input current VI = 0 0.005 -2.5 µA ICC Operating supply current CS at 0 V 0.8 2.5 mA Selected channel leakage current TLC1542/TLC1543 C, I, or Q Selected channel at VCC, Unselected channel at 0 V 1 Selected channel at 0 V, Unselected channel at VCC -1 Selected channel at VCC, TA= 25°C Unselected channel at 0 V, 1 Selected channel at 0 V, TA = 25°C Unselected channel at VCC, -1 Selected channel at VCC, Unselected channel at 0 V 2.5 Selected channel at 0 V, Unselected channel at VCC -2.5 Vref+ = VCC, Vref- = GND VOH High-level output voltage VOL Low-level output voltage IOZ Selected channel leakage current TLC1542M Maximum static analog reference current into REF+ Ci (1) Input capacitance 2.4 UNIT V VCC-0.1 10 Analog inputs 7 Control inputs 5 V µA µA µA µA µA pF All typical values are at VCC = 5 V, TA = 25°C. OPERATING CHARACTERISTICS over recommended operating free-air temperature range, VCC = Vref+ = 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz (unless otherwise noted) TEST CONDITIONS EL (1) (2) Linearity error, see (2)) MIN TYP (1) MAX UNIT TLC1542C, I, or Q ±0.5 LSB TLC1543C, I, or Q ±1 LSB TLC1542M ±1 LSB All typical values are at TA = 25°C. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics. Submit Documentation Feedback 9 TLC1542I,, TLC1542M,, TLC1542Q TLC1542C, TLC1543C, TLC1543I, TLC1543Q www.ti.com SLAS052G – MARCH 1992 – REVISED JANUARY 2006 OPERATING CHARACTERISTICS (continued) over recommended operating free-air temperature range, VCC = Vref+ = 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz (unless otherwise noted) TEST CONDITIONS EZS Zero-scale error, see EFS Full-scale error, see (3) Total unadjusted error, see (5) TYP (1) MAX UNIT See (4) ±1 LSB TLC1543C, I, or Q See (4) ±1 LSB TLC1542M See (4) ±1 LSB TLC1542C, I, or Q See (4) ±1 LSB TLC1543C, I, or Q See (4) ±1 LSB TLC1542M See (4) ±1 LSB TLC1542C, I, or Q ±1 LSB TLC1543C, I, or Q ±1 LSB TLC1542M ±1 LSB 21 µs TLC1542C, I, or Q (3) MIN ADDRESS = 1011 Self-test output code, see Table 3 and (6) 512 ADDRESS = 1100 0 ADDRESS = 1101 1023 tconv Conversion time See timing diagrams tc Total cycle time (access, sample, and conversion) See timing diagrams and (7) tacq Channel acquisition time (sample) See timing diagrams and (7) tv Valid time, DATA OUT remains valid after I/O CLOCK↓ See Figure 6 td(I/O-DATA) Delay time, I/O CLOCK↓ to DATA OUT valid See Figure 6 td(I/O-EOC) Delay time, tenth I/O CLOCK↓ to EOC↓ See Figure 7 td(EOC-DATA) Delay time, EOC↑ to DATA OUT (MSB) See Figure 8 100 ns tPZH, tPZL Enable time, CS↓ to DATA OUT (MSB driven) See Figure 3 1.3 µs tPHZ, tPLZ Disable time, CS↑ to DATA OUT (high impedance) See Figure 3 150 ns tr(EOC) Rise time, EOC See Figure 8 300 ns tf(EOC) Fall time, EOC See Figure 7 300 ns tr(DATA) Rise time, data bus See Figure 6 300 ns tf(DATA) Fall time, data bus See Figure 6 300 ns td(I/O-CS) Delay time, tenth I/O CLOCK↓ to CS↓ to abort conversion (see Note (8)) 9 µs (3) (4) (5) (6) (7) (8) 10 21 +10 I/O CLOCK periods 6 10 µs I/O CLOCK periods ns 70 240 ns 240 ns Zero-scale error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the difference between 1111111111 and the converted output for full-scale input voltage. Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied to REF- convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref+-Vref-); however, the electrical specifications are no longer applicable. Total unadjusted error comprises linearity, zero-scale, and full-scale errors. Both the input address and the output codes are expressed in positive logic. I/O CLOCK period = 1/(I/O CLOCK frequency) (see Figure 6) Any transitions of CS are recognized as valid only if the level is maintained for a setup time plus two falling edges of the internal clock (1.425 µs) after the transition. Submit Documentation Feedback TLC1542I,, TLC1542M,, TLC1542Q TLC1542C, TLC1543C, TLC1543I, TLC1543Q www.ti.com SLAS052G – MARCH 1992 – REVISED JANUARY 2006 PARAMETER MEASUREMENT INFORMATION VCC Test Point VCC Test Point RL = 2.18 kΩ RL = 2.18 kΩ DATA OUT EOC 12 kΩ CL = 50 pF 12 kΩ CL = 100 pF Figure 2. Load Circuits 2V CS 0.8 V tPZH, tPZL DATA OUT tPHZ, tPLZ 2.4 V 90% 0.4 V 10% Figure 3. DATA OUT Enable and Disable Voltage Waveforms Address Valid 2V 0.8 V ADDRESS th(A) tsu(A) I/O CLOCK 0.8 V Figure 4. ADDRESS Setup and Hold Time Voltage Waveforms 2V CS 0.8 V tsu(CS) th(CS) I/O CLOCK 0.8 V First Clock Last Clock 0.8 V Figure 5. I/O CLOCK Setup and Hold Time Voltage Waveforms Submit Documentation Feedback 11 TLC1542I,, TLC1542M,, TLC1542Q TLC1542C, TLC1543C, TLC1543I, TLC1543Q www.ti.com SLAS052G – MARCH 1992 – REVISED JANUARY 2006 PARAMETER MEASUREMENT INFORMATION (continued) tt(I/O) tt(I/O) I/O CLOCK 2V 2V 0.8 V 0.8 V 0.8 V I/O CLOCK Period td(I/O-DATA) tv DATA OUT 2.4 V 2.4 V 0.4 V 0.4 V tr(DATA), tf(DATA) Figure 6. I/O CLOCK and DATA OUT Voltage Waveforms I/O CLOCK 10th Clock 0.8 V td(I/O-EOC) 2.4 V 0.4 V EOC tf(EOC) Figure 7. I/O CLOCK and EOC Voltage Waveforms tr(EOC) 2.4 V EOC 0.4 V td(EOC-DATA) DATA OUT 2.4 V 0.4 V Valid MSB Figure 8. EOC and DATA OUT Voltage Waveforms 12 Submit Documentation Feedback TLC1542I,, TLC1542M,, TLC1542Q TLC1542C, TLC1543C, TLC1543I, TLC1543Q www.ti.com SLAS052G – MARCH 1992 – REVISED JANUARY 2006 PARAMETER MEASUREMENT INFORMATION (continued) TIMING DIAGRAMS CS (see Note A) I/O CLOCK 1 2 3 4 5 6 Access Cycle B A9 A8 A7 A6 B3 MSB 9 A5 B2 B1 10 1 Hi-Z State A4 A3 A2 A1 Previous Conversion Data MSB ADDRESS 8 Sample Cycle B ÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ DATA OUT 7 ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ A0 LSB B0 LSB B9 C3 EOC Shift in New Multiplexer Address; Simultaneously Shift Out Previous Conversion Value A/D Conversion Interval Initialize A. Initialize To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed. Figure 9. Timing for 10-Clock Transfer Using CS Must be High on Power Up CS (see Note A) I/O CLOCK 1 2 3 4 5 6 Access Cycle B A9 A8 A7 8 A6 A5 A4 A3 A2 Previous Conversion Data MSB 9 10 A1 A0 LSB ADDRESS B3 MSB B2 B1 1 Sample Cycle B ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎ DATA OUT 7 B0 LSB Low Level ÎÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎ B9 C3 EOC Shift in New Multiplexer Address; Simultaneously Shift Out Previous Conversion Value Initialize A. A/D Conversion Interval Initialize To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed. Figure 10. Timing for 10-Clock Transfer Not Using CS Submit Documentation Feedback 13 TLC1542I,, TLC1542M,, TLC1542Q TLC1542C, TLC1543C, TLC1543I, TLC1543Q www.ti.com SLAS052G – MARCH 1992 – REVISED JANUARY 2006 ÏÏÏ ÏÏÏ ÏÏÏ ÎÎÎ ÏÏÏ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎ PARAMETER MEASUREMENT INFORMATION (continued) See Note B CS (see Note A) I/O CLOCK 1 2 3 4 5 6 Access Cycle B DATA OUT A8 A7 B3 MSB A6 A5 A4 A3 A2 Previous Conversion Data MSB ADDRESS 8 B2 B1 9 11 10 Sample Cycle B ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ A9 7 A1 A0 Low Level LSB B0 LSB 16 1 Hi-Z B9 C3 EOC Shift in New Multiplexer Address; Simultaneously Shift Out Previous Conversion Value Initialize A/D Conversion Interval To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed. B. A low-to-high transition of CS disables ADDRESS and the I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system clock. Figure 11. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Interval Shorter Than Conversion) 14 Initialize A. Submit Documentation Feedback TLC1542I,, TLC1542M,, TLC1542Q TLC1542C, TLC1543C, TLC1543I, TLC1543Q www.ti.com SLAS052G – MARCH 1992 – REVISED JANUARY 2006 PARAMETER MEASUREMENT INFORMATION (continued) Must Be High on Power Up CS (see Note A) I/O CLOCK 1 2 3 4 5 6 Access Cycle B DATA OUT A8 A7 B3 MSB 9 B2 B1 10 14 15 A6 A5 A4 A3 A2 1 16 See Note B A1 Previous Conversion Data MSB ADDRESS 8 Sample Cycle B ÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ A9 7 Low Level A0 LSB B0 LSB ÎÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎ B9 C3 EOC Shift in New Multiplexer Address; Simultaneously Shift Out Previous Conversion Value A/D Conversion Interval Initialize Initialize A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed. B. The first I/O CLOCK must occur after the rising edge of EOC. Figure 12. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Interval Shorter Than Conversion) Submit Documentation Feedback 15 TLC1542I,, TLC1542M,, TLC1542Q TLC1542C, TLC1543C, TLC1543I, TLC1543Q www.ti.com SLAS052G – MARCH 1992 – REVISED JANUARY 2006 ÏÏÏ ÏÏÏ ÏÏÏ ÎÎ ÏÏÏ ÎÎ ÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎ Î ÎÎÎ Î ÎÎÎ Î ÏÏÏ ÎÎÎ Î ÏÏÏ ÏÏÏ ÏÏÏ PARAMETER MEASUREMENT INFORMATION (continued) CS (see Note A) I/O CLOCK 1 2 3 4 5 6 Access Cycle B A9 A8 A7 8 A6 A5 A4 A3 A2 Previous Conversion Data MSB ADDRESS B3 MSB B2 B1 9 10 B0 LSB EOC Shift in New Multiplexer Address; Simultaneously Shift Out Previous Conversion Value Initialize 11 A1 A0 LSB Low Level Hi-Z State B9 C3 A/D Conversion Interval Initialize A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed. B. The 11th rising edge of the I/O CLOCK sequence must occur before the conversion is complete to prevent losing serial interface synchronization. Figure 13. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Interval Longer Than Conversion) 16 1 16 See Note B Sample Cycle B ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎ DATA OUT 7 Submit Documentation Feedback TLC1542I,, TLC1542M,, TLC1542Q TLC1542C, TLC1543C, TLC1543I, TLC1543Q www.ti.com SLAS052G – MARCH 1992 – REVISED JANUARY 2006 PARAMETER MEASUREMENT INFORMATION (continued) Must be High on Power Up CS (see Note A) I/O CLOCK 1 2 3 4 5 6 Access Cycle B A9 A8 A7 8 9 A6 A5 A4 A3 A2 14 15 See Note B A1 Previous Conversion Data MSB 10 Sample Cycle B ÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ DATA OUT 7 A0 Low Level LSB ADDRESS B3 MSB B2 B1 B0 LSB 1 16 See Note C ÎÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎ B9 C3 EOC Shift in New Multiplexer Address; Simultaneously Shift Out Previous Conversion Value Initialize A/D Conversion Interval A. A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed. B. The 11th rising edge of the I/O CLOCK sequence must occur before the conversion is complete to prevent losing serial interface synchronization. C. C. The I/O CLOCK sequence is exactly 16 clock pulses long. Figure 14. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Interval Longer Than Conversion) Submit Documentation Feedback 17 TLC1542I,, TLC1542M,, TLC1542Q TLC1542C, TLC1543C, TLC1543I, TLC1543Q www.ti.com SLAS052G – MARCH 1992 – REVISED JANUARY 2006 APPLICATION INFORMATION 1023 1111111111 See Notes A and B 1111111110 1022 1111111101 1021 VFT = VFS − 1/2 LSB 513 1000000001 512 1000000000 VZT =VZS + 1/2 LSB 511 0111111111 VZS 0000000001 1 0000000000 0 0.0096 0.0048 2.4528 2.4576 2.4624 4.9056 4.9080 2 0.0024 0000000010 4.9104 0 4.9152 VI − Analog Input Voltage − V A. This curve is based on the assumption that Vref+ and Vref- have been adjusted so that the voltage at the transition from digital 0 to 1 (VZT) is 0.0024 V and the transition to full scale (VFT) is 4.908 V. 1 LSB = 4.8 mV. B. The full-scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (VZS) is the step whose nominal midstep value equals zero. Figure 15. Ideal Conversion Characteristics TLC1542/43 1 2 3 4 5 Analog Inputs 6 7 8 9 11 12 15 A0 CS A1 I/O CLOCK ADDRESS A2 18 17 Processor A3 A4 DATA OUT A5 EOC 16 19 A6 A7 14 A8 REF+ A9 REF− 13 5-V DC Regulator A10 GND 10 To Source Ground Figure 16. Serial Interface 18 Submit Documentation Feedback Control Circuit Step Digital Output Code VFS TLC1542I,, TLC1542M,, TLC1542Q TLC1542C, TLC1543C, TLC1543I, TLC1543Q www.ti.com SLAS052G – MARCH 1992 – REVISED JANUARY 2006 APPLICATION INFORMATION (continued) SIMPLIFIED ANALOG INPUT ANALYSIS Using the equivalent circuit in Figure 17Figure 17, the time required to charge the analog input capacitance from 0 to VS within 1/2 LSB can be derived as follows: The capacitance charging voltage is given by −t c /RtCi VC = VS 1−e ( ) where Rt = Rs + ri (1) The final voltage to 1/2 LSB is given by VC (1/2 LSB) = VS − (VS /2048) (2) Equating equation 1 to equation 2 and solving for time tc gives −t c /RtCi VS −(VS/2048) = VS 1−e ( ) and tc (1/2 LSB) = Rt × Ci × ln(2048) (3) Therefore, with the values given the time for the analog input signal to settle is tc (1/2 LSB) = (Rs + 1 kΩ) × 60 pF × ln(2048) (4) This time must be less than the converter sample time shown in the timing diagrams. Driving Source† TLC1542/3 Rs VI ri VS VC 1 kΩ MAX Ci 50 pF MAX VI = Input Voltage at A0 −A10 VS = External Driving Source Voltage Rs = Source Resistance ri = Input Resistance Ci = Equivalent Input Capacitance † Driving source requirements: • Noise and distortion for the source must be equivalent to the resolution of the converter. • Rs must be real at the input frequency. Figure 17. Equivalent Input Circuit Including the Driving Source Submit Documentation Feedback 19 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TLC1542CDW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM TLC1542C Samples TLC1542CDWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM TLC1542C Samples TLC1542CFN ACTIVE PLCC FN 20 46 RoHS & Green SN Level-1-260C-UNLIM TLC1542C Samples TLC1542CN ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type TLC1542CN Samples TLC1542IDW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM TLC1542I Samples TLC1542IDWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM TLC1542I Samples TLC1542IN ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type TLC1542IN Samples TLC1543CDB ACTIVE SSOP DB 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM P1543 Samples TLC1543CDBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM P1543 Samples TLC1543CDBRG4 ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM P1543 Samples TLC1543CDW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM TLC1543C Samples TLC1543CDWG4 ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM TLC1543C Samples TLC1543CDWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM TLC1543C Samples TLC1543CDWRG4 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM TLC1543C Samples TLC1543CFN ACTIVE PLCC FN 20 46 RoHS & Green SN Level-1-260C-UNLIM TLC1543C Samples TLC1543CFNR ACTIVE PLCC FN 20 1000 RoHS & Green SN Level-1-260C-UNLIM TLC1543C Samples TLC1543CN ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type TLC1543CN Samples TLC1543IDB ACTIVE SSOP DB 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM Y1543 Samples TLC1543IDBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM Y1543 Samples Addendum-Page 1 0 to 70 0 to 70 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TLC1543IDBRG4 ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM Y1543 Samples TLC1543IDW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM TLC1543I Samples TLC1543IDWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM TLC1543I Samples TLC1543IFN ACTIVE PLCC FN 20 46 RoHS & Green SN Level-1-260C-UNLIM TLC1543I Samples TLC1543IN ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type TLC1543IN Samples TLC1543INE4 ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type TLC1543IN Samples TLC1543QDB ACTIVE SSOP DB 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1543Q Samples TLC1543QDBG4 ACTIVE SSOP DB 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1543Q Samples TLC1543QDBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1543Q Samples TLC1543QDW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TLC1543Q Samples TLC1543QDWG4 ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TLC1543Q Samples TLC1543QDWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TLC1543Q Samples TLC1543QDWRG4 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TLC1543Q Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of