TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
D
D
D
D
D
D
D
D
Voltage-Controlled Oscillator (VCO)
Section:
– Complete Oscillator Using Only One
External Bias Resistor (RBIAS)
– Lock Frequency:
22 MHz to 50 MHz (VDD = 5 V ±5%,
TA = – 20°C to 75°C, ×1 Output)
11 MHz to 25 MHz (VDD = 5 V ±5%,
TA = – 20°C to 75°C, ×1/2 Output)
– Output Frequency . . . ×1 and ×1/2
Selectable
Phase-Frequency Detector (PFD) Section
Includes a High-Speed Edge-Triggered
Detector With Internal Charge Pump
Independent VCO, PFD Power-Down Mode
Thin Small-Outline Package (14 terminal)
CMOS Technology
Typical Applications:
– Frequency Synthesis
– Modulation/Demodulation
– Fractional Frequency Division
Application Report Available†
CMOS Input Logic Level
PW PACKAGE†
(TOP VIEW)
LOGIC VDD
SELECT
VCO OUT
FIN – A
FIN – B
PFD OUT
LOGIC GND
1
2
3
4
5
6
7
VCO VDD
BIAS
VCO IN
VCO GND
VCO INHIBIT
PFD INHIBIT
NC
14
13
12
11
10
9
8
† Available in tape and reel only and ordered as the
TLC2932IPWLE.
NC – No internal connection
description
The TLC2932 is designed for phase-locked-loop (PLL) systems and is composed of a voltage-controlled
oscillator (VCO) and an edge-triggered-type phase frequency detector (PFD). The oscillation frequency range
of the VCO is set by an external bias resistor (RBIAS). The VCO has a 1/2 frequency divider at the output stage.
The high-speed PFD with internal charge pump detects the phase difference between the reference frequency
input and signal frequency input from the external counter. Both the VCO and the PFD have inhibit functions,
which can be used as a power-down mode. The TLC2932 is suitable for use as a high-performance PLL due
to the high speed and stable oscillation capability of the device.
functional block diagram
FIN –A
FIN –B
PFD INHIBIT
4
5
9
VCO IN
Phase
Frequency
Detector
6
BIAS
PFD OUT VCO INHIBIT
SELECT
12
13
10
2
VoltageControlled
Oscillator
3
VCO OUT
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE
(PW)
– 20°C to 75°C
TLC2932IPWLE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† TLC2932 Phase-Locked-Loop Building Block With Analog Voltage-Controlled Oscillator and Phase Frequency Detector (SLAA011).
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
FIN – A
4
I
Input reference frequency f(REF IN) is applied to FIN – A.
FIN – B
5
I
Input for VCO external counter output frequency f(FIN – B). FIN – B is nominally provided from the external
counter.
LOGIC GND
7
GND for the internal logic.
LOGIC VDD
1
Power supply for the internal logic. This power supply should be separate from VCO VDD to reduce
cross-coupling between supplies.
NC
8
No internal connection.
PFD INHIBIT
9
I
PFD inhibit control. When PFD INHIBIT is high, PFD output is in the high-impedance state, see Table 3.
PFD OUT
6
O
PFD output. When the PFD INHIBIT is high, PFD output is in the high-impedance state.
13
I
Bias supply. An external resistor (RBIAS) between VCO VDD and BIAS supplies bias for adjusting the
oscillation frequency range.
SELECT
2
I
VCO output frequency select. When SELECT is high, the VCO output frequency is × 1/2 and when low, the
output frequency is × 1, see Table 1.
VCO IN
12
I
VCO control voltage input. Nominally the external loop filter output connects to VCO IN to control VCO
oscillation frequency.
VCO INHIBIT
10
I
VCO inhibit control. When VCO INHIBIT is high, VCO OUT is low (see Table 2).
VCO GND
11
VCO OUT
3
VCO VDD
14
BIAS
GND for VCO.
O
VCO output. When the VCO INHIBIT is high, VCO output is low.
Power supply for VCO. This power supply should be separated from LOGIC VDD to reduce cross-coupling
between supplies.
detailed description
VCO oscillation frequency
The VCO oscillation frequency is determined by an external resistor (RBIAS) connected between the VCO VDD
and the BIAS terminals. The oscillation frequency and range depends on this resistor value. The bias resistor
value for the minimum temperature coefficient is nominally 3.3 kΩ with 3-V at the VCO VDD terminal and
nominally 2.2 kΩ with 5-V at the VCO VDD terminal. For the lock frequency range refer to the recommended
operating conditions. Figure 1 shows the typical frequency variation and VCO control voltage.
VCO Oscillation Frequency (f osc )
VCO Oscillation Frequency Range
Bias Resistor (RBIAS)
1/2 VDD
VCO Control Voltage (VCO IN)
Figure 1. VCO Oscillation Frequency
2
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TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
VCO output frequency 1/2 divider
The TLC2932 SELECT terminal sets the fosc or 1/2 fosc VCO output frequency as shown in Table 1. The 1/2
fosc output should be used for minimum VCO output jitter.
Table 1. VCO Output 1/2 Divider Function
SELECT
VCO OUTPUT
Low
fosc
1/2 fosc
High
VCO inhibit function
The VCO has an externally controlled inhibit function which inhibits the VCO output. A high level on the VCO
INHIBIT terminal stops the VCO oscillation and powers down the VCO. The output maintains a low level during
the power-down mode, refer to Table 2.
Table 2. VCO Inhibit Function
VCO INHIBIT
VCO OSCILLATOR
VCO OUTPUT
Low
Active
Active
IDD(VCO)
Normal
High
Stopped
Low level
Power Down
PFD operation
The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phase
difference between two frequency inputs supplied to FIN–A and FIN–B as shown in Figure 2. Nominally the
reference is supplied to FIN–A, and the frequency from the external counter output is fed to FIN–B.
FIN– A
FIN– B
VOH
PFD OUT
Hi-Z
VOL
Figure 2. PFD Function Timing Chart
PFD output control
A high level on the PFD INHIBIT terminal places the PFD output in the high-impedance state and the PFD stops
phase detection as shown in Table 3. A high level on the PFD INHIBIT terminal also can be used as the
power-down mode for the PFD.
Table 3. VCO Output Control Function
PFD INHIBIT
DETECTION
PFD OUTPUT
Low
Active
Active
IDD(PFD)
Normal
High
Stopped
Hi-Z
Power Down
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3
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
schematics
VCO block schematic
RBIAS
BIAS
1/2
VCO IN
VCO
Output
Bias
Control
M
U
X
VCO OUT
SELECT
VCO INHIBIT
PFD block schematic
Charge Pump
VDD
FIN – A
PFD OUT
Detector
FIN – B
PFD INHIBIT
absolute maximum ratings†
Supply voltage (each supply), VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage range (each input), VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VDD + 0.5 V
Input current (each input), II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output current (each output), IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Continuous total power dissipation, at (or below) TA = 25°C (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . 700 mW
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 20°C to 75°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to network GND.
2. For operation above 25°C free-air temperature, derate linearly at the rate of 5.6 mW/°C.
4
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TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
recommended operating conditions
PARAMETER
VDD = 3 V
VDD = 5 V
supply see Note 3)
Supply voltage
voltage, VDD (each supply,
Input voltage, VI (inputs except VCO IN)
MIN
NOM
MAX
2.85
3
3.15
4.75
5
5.25
0
Output current, IO (each output)
VDD
±2
0
VCO control voltage at VCO IN
0.9
Lock frequency (×1 output)
VDD = 3 V
VDD = 5 V
Lock frequency (×1/2 output)
VDD = 3 V
VDD = 5 V
Bias resistor,
resistor RBIAS
VDD = 3 V
VDD = 5 V
14
VDD
21
22
50
7
10.5
11
25
2.2
3.3
4.3
1.5
2.2
3.3
UNIT
V
V
mA
V
MHz
MHz
kΩ
NOTE 3: It is recommended that the logic supply terminal (LOGIC VDD) and the VCO supply terminal (VCO VDD) should be at the same voltage
and separated from each other.
electrical characteristics over recommended operating free-air temperature range, VDD = 3 V
(unless otherwise noted)
VCO section
PARAMETER
TEST CONDITIONS
VOH
VOL
High-level output voltage
IOH = – 2 mA
IOL = 2 mA
VIT
II
Input threshold voltage at SELECT, VCO INHIBIT
Zi(VCO IN)
IDD(INH)
Input impedance
VI = VDD or GND
VCO IN = 1/2 VDD
VCO supply current (inhibit)
See Note 4
Low-level output voltage
Input current at SELECT, VCO INHIBIT
MIN
TYP
MAX
2.4
V
0.3
0.9
UNIT
1.5
V
±1
µA
10
0.01
IDD(VCO)
VCO supply current
See Note 5
5
NOTES: 4. Current into VCO VDD, when VCO INHIBIT = VDD, PFD is inhibited.
5. Current into VCO VDD, when VCO IN = 1/2 VDD, RBIAS = 3.3 kΩ, VCO INHIBIT = GND, and PFD is inhibited.
V
2.1
MΩ
1
µA
15
mA
PFD section
PARAMETER
TEST CONDITIONS
IOH = – 2 mA
IOL = 2 mA
MIN
TYP
MAX
High-level output voltage
IOZ
High-impedance-state output current
VIH
VIL
High-level input voltage at FIN–A, FIN–B
VIT
Ci
Input threshold voltage at PFD INHIBIT
Input capacitance at FIN–A, FIN–B
5
pF
Zi
IDD(Z)
Input impedance at FIN–A, FIN–B
10
MΩ
Low-level output voltage
2.7
UNIT
VOH
VOL
V
PFD INHIBIT = high,
VI = VDD or GND
V
±1
µA
2.7
V
Low-level input voltage at FIN–A, FIN–B
High-impedance-state PFD supply current
0.2
0.5
0.9
See Note 6
1.5
0.01
2.1
1
V
V
µA
IDD(PFD) PFD supply current
See Note 7
0.1
1.5
mA
NOTES: 6. Current into LOGIC VDD, when FIN–A, FIN–B = GND, PFD INHIBIT = VDD, no load, and VCO OUT is inhibited.
7. Current into LOGIC VDD, when FIN–A, FIN–B = 1 MHz (VI(PP) = 3 V, rectangular wave), NC = GND, no load, and VCO OUT is
inhibited.
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TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
operating characteristics over recommended operating free-air temperature range, VDD = 3 V
(unless otherwise noted)
VCO section
PARAMETER
fosc
ts(fosc)
TEST CONDITIONS
Operating oscillation frequency
RBIAS = 3.3 kΩ, VCO IN = 1/2 VDD
Time to stable oscillation (see Note 8)
Measured from VCO INHIBIT↓
tr
Rise time
tf
Fall time
MIN
TYP
MAX
UNIT
15
19
23
MHz
10
µs
CL = 15 pF,
See Figure 3
7
CL = 50 pF,
See Figure 3
14
CL = 15 pF,
See Figure 3
6
CL = 50 pF,
See Figure 3
10
45%
50%
14
12
ns
ns
Duty cycle at VCO OUT
RBIAS = 3.3 kΩ, VCO IN = 1/2 VDD,
55%
α(fosc)
Temperature coefficient of oscillation frequency
RBIAS = 3.3 kΩ, VCO IN = 1/2 VDD,
TA = –20°C to 75°C
0.04
%/°C
kSVS(fosc)
Supply voltage coefficient of oscillation frequency
RBIAS = 3.3 kΩ, VCO IN = 1.5 V,
VDD = 2.85 V to 3.15 V
0.02
%/mV
Jitter absolute (see Note 9)
RBIAS = 3.3 kΩ
100
ps
NOTES: 8. The time period to the stable VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.
9. The low-pass-filter (LPF) circuit is shown in Figure 28 with calculated values listed in Table 7. Jitter performance is highly dependent
on circuit layout and external device characteristics. The jitter specification was made with a carefully designed PCB with no device
socket.
PFD section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
fmax
tPLZ
Maximum operating frequency
PFD output disable time from low level
21
50
tPHZ
tPZL
PFD output disable time from high level
23
50
tPZH
tr
PFD output enable time to high level
tf
Fall time
6
PFD output enable time to low level
20
See Figures 4 and 5 and Table 4
Rise time
pF
CL = 15 pF,
POST OFFICE BOX 655303
See Figure 4
• DALLAS, TEXAS 75265
UNIT
MHz
ns
11
30
10
30
2.3
10
ns
2.1
10
ns
ns
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range, VDD = 5 V
(unless otherwise noted)
VCO section
PARAMETER
TEST CONDITIONS
VOH
VOL
High-level output voltage
IOH = – 2 mA
IOL = 2 mA
VIT
II
Input threshold voltage at SELECT, VCO INHIBIT
Zi(VCO IN)
IDD(INH)
Input impedance
VI = VDD or GND
VCO IN = 1/2 VDD
VCO supply current (inhibit)
See Note 4
Low-level output voltage
Input current at SELECT, VCO INHIBIT
MIN
TYP
MAX
4
V
0.5
1.5
UNIT
2.5
V
±1
µA
10
0.01
IDD(VCO)
VCO supply current
See Note 5
15
NOTES: 4. Current into VCO VDD, when VCO INHIBIT = VDD, and PFD is inhibited.
5. Current into VCO VDD, when VCO IN = 1/2 VDD, RBIAS = 3.3 kΩ, VCO INHIBIT = GND, and PFD is inhibited.
V
3.5
MΩ
1
µA
35
mA
PFD section
PARAMETER
TEST CONDITIONS
IOH = 2 mA
IOL = 2 mA
MIN
TYP
MAX
VOH
VOL
High-level output voltage
IOZ
High-impedance-state output current
VIH
VIL
High-level input voltage at FIN–A, FIN–B
VIT
Ci
Input threshold voltage at PFD INHIBIT
Input capacitance at FIN–A, FIN–B
5
pF
Zi
IDD(Z)
Input impedance at FIN–A, FIN–B
10
MΩ
Low-level output voltage
4.5
UNIT
V
PFD INHIBIT = high,
VI = VDD or GND
V
±1
µA
4.5
V
Low-level input voltage at FIN–A, FIN–B
High-impedance-state PFD supply current
0.2
1.5
See Note 6
2.5
0.01
1
V
3.5
V
1
µA
IDD(PFD) PFD supply current
See Note 7
0.15
3
mA
NOTES: 6. Current into LOGIC VDD, when FIN–A, FIN–B = GND, PFD INHIBIT = VDD, no load, and VCO OUT is inhibited.
7. Current into LOGIC VDD, when FIN–A, FIN–B = 1 MHz (VI(PP) = 5 V, rectangular wave), PFD INHIBIT = GND, no load, and
VCO OUT is inhibited.
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• DALLAS, TEXAS 75265
7
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
operating characteristics over recommended operating free-air temperature range, VDD = 5 V
(unless otherwise noted)
VCO section
PARAMETER
fosc
ts(fosc)
TEST CONDITIONS
Operating oscillation frequency
RBIAS = 2.2 kΩ, VCO IN = 1/2 VDD
Time to stable oscillation (see Note 8)
Measured from VCO INHIBIT↓
tr
Rise time
tf
Fall time
MIN
TYP
MAX
UNIT
30
41
52
MHz
10
µs
CL = 15 pF,
See Figure 3
5.5
CL = 50 pF,
See Figure 3
8
CL = 15 pF,
See Figure 3
5
CL = 50 pF,
See Figure 3
6
Duty cycle at VCO OUT
RBIAS = 2.2 kΩ, VCO IN = 1/2 VDD,
α(fosc)
Temperature coefficient of oscillation frequency
RBIAS = 2.2 kΩ, VCO IN = 1/2 VDD,
TA = –20°C to 75°C
kSVS(fosc)
Supply voltage coefficient of oscillation frequency
RBIAS = 2.2 kΩ, VCO IN = 2.5 V,
VDD = 4.75 V to 5.25 V
Jitter absolute (see Note 9)
RBIAS = 2.2 kΩ
45%
50%
10
10
ns
ns
55%
0.06
%/°C
0.006
%/mV
100
ps
NOTES: 8: The time period to the stable VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.
9. The LPF circuit is shown in Figure 28 with calculated values listed in Table 7. Jitter performance is highly dependent on circuit layout
and external device characteristics. The jitter specification was made with a carefully designed PCB with no device socket.
PFD section
PARAMETER
TEST CONDITIONS
fmax
tPLZ
Maximum operating frequency
tPHZ
tPZL
PFD output disable time from high level
tPZH
tr
PFD output enable time to high level
tf
Fall time
8
TYP
MAX
21
40
20
40
7.3
20
6.5
20
2.3
10
ns
1.7
10
ns
40
PFD output disable time from low level
PFD output enable time to low level
MIN
See Figures 4 and 5 and Table 4
Rise time
CL = 15 pF,
pF
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See Figure 4
• DALLAS, TEXAS 75265
UNIT
MHz
ns
ns
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
90%
90%
VCO OUT
10%
10%
tr
tf
Figure 3. VCO Output Voltage Waveform
FIN– A†
FIN– B†
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
PFD INHIBIT
VDD
50%
50%
GND
tPHZ
tr
PFD OUT
10%
GND
VOH
90%
50%
tPLZ
tf
90%
50%
GND
50%
10%
VDD
50%
VOL
tPZL
tPZH
(a) OUTPUT PULLDOWN
(see Figure 5 and Table 4)
(b) OUTPUT PULLUP
(see Figure 5 and Table 4)
† FIN–A and FIN–B are for reference phase only, not for timing.
Figure 4. PFD Output Voltage Waveform
Table 4. PFD Output Test Conditions
PARAMETER
RL
CL
tPZH
tPHZ
tr
tPZL
tPLZ
tf
S1
S2
Open
Close
VDD
Test Point
S1
1 kΩ
RL
DUT
15 pF
Close
PFD OUT
Open
CL
S2
Figure 5. PFD Output Test Conditions
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9
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
TYPICAL CHARACTERISTICS
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
VDD = 3 V
RBIAS = 2.2 kΩ
100
VDD = 5 V
RBIAS = 1.5 kΩ
– 20°C
25°C
f osc – VCO Oscillation Frequency – MHz
f osc – VCO Oscillation Frequency – MHz
40
30
75°C
20
10
– 20°C
80
25°C
60
75°C
40
20
0
0
1
2
VCO IN – VCO Control Voltage – V
3
4
1
2
3
VCO IN – VCO Control Voltage – V
0
Figure 6
Figure 7
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
80
VDD = 3 V
RBIAS = 3.3 kΩ
f osc – VCO Oscillation Frequency – MHz
f osc – VCO Oscillation Frequency – MHz
40
– 20°C
30
75°C
25°C
20
10
0
0
1
2
VCO IN – VCO Control Voltage – V
3
VDD = 5 V
RBIAS = 2.2 kΩ
– 20°C
60
75°C
25°C
40
20
0
0
Figure 8
10
5
1
2
3
4
VCO IN – VCO Control Voltage – V
Figure 9
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5
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
TYPICAL CHARACTERISTICS
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
80
VDD = 3 V
RBIAS = 4.3 kΩ
f osc – VCO Oscillation Frequency – MHz
f osc – VCO Oscillation Frequency – MHz
40
30
75°C
25°C
20
– 20°C
10
0
0
1
2
VCO IN – VCO Control Voltage – V
VDD = 5 V
RBIAS = 3.3 kΩ
60
40
25°C
20
– 20°C
0
3
75°C
0
1
2
3
4
VCO IN – VCO Control Voltage – V
Figure 10
Figure 11
VCO OSCILLATION FREQUENCY
vs
BIAS RESISTOR
VCO OSCILLATION FREQUENCY
vs
BIAS RESISTOR
30
60
VDD = 3 V
VCO IN = 1/2 VDD
TA = 25°C
f osc – VCO Oscillation Frequency – MHz
f osc – VCO Oscillation Frequency – MHz
5
25
20
15
10
2
2.5
3.5
4
3
RBIAS – Bias Resistor – kΩ
4.5
VDD = 5 V
VCO IN = 1/2 VDD
TA = 25°C
50
40
30
20
1.5
Figure 12
2
2.5
3
RBIAS – Bias Resistor – kΩ
3.5
Figure 13
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TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
TYPICAL CHARACTERISTICS
TEMPERATURE COEFFICIENT OF
OSCILLATION FREQUENCY
vs
BIAS RESISTOR
0.4
VDD = 3 V
VCO IN = 1/2 VDD
TA = – 20°C to 75°C
α (f osc) – Temperature Coefficient of Oscillation
Frequency – % / °C
α (f osc) – Temperature Coefficient of Oscillation
Frequency – % / °C
0.4
TEMPERATURE COEFFICIENT OF
OSCILLATION FREQUENCY
vs
BIAS RESISTOR
0.3
0.2
0.1
0
2
3
2.5
4
3.3 3.5
RBIAS – Bias Resistor – kΩ
VDD = 5 V
VCO IN = 1/2 VDD
TA = – 20°C to 75°C
0.3
0.2
0.1
0
1.5
4.5
VCO OSCILLATION FREQUENCY
vs
VCO SUPPLY VOLTAGE
VCO OSCILLATION FREQUENCY
vs
VCO SUPPLY VOLTAGE
48
24
RBIAS = 3.3 kΩ
VCO IN = 1.5 V
TA = 25°C
f osc – VCO Oscillation Frequency – MHz
f osc – VCO Oscillation Frequency – MHz
3.5
Figure 15
Figure 14
22
20
18
16
3.05
3
VDD – VCO Supply Voltage – V
3.15
RBIAS = 2.2 kΩ
VCO IN = 1/2 VDD
TA = 25°C
44
40
36
32
4.75
Figure 16
12
2
2.5
3
2.2
RBIAS – Bias Resistor – kΩ
5
VDD – VCO Supply Voltage – V
Figure 17
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TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
TYPICAL CHARACTERISTICS
0.05
VDD = 2.85 V to 3.15 V
VCO IN = 1/2 VDD
TA = 25°C
0.04
0.03
0.02
0.01
0
2
2.5
3
3.5
4
RBIAS – Bias Resistor – kΩ
4.5
SUPPLY VOLTAGE COEFFICIENT OF VCO
OSCILLATION FREQUENCY
vs
BIAS RESISTOR
α (f osc) – Supply Voltage Coefficient of VCO Oscillation
Frequency – % / V
α (f osc) – Supply Voltage Coefficient of VCO Oscillation
Frequency – % / V
SUPPLY VOLTAGE COEFFICIENT OF VCO
OSCILLATION FREQUENCY
vs
BIAS RESISTOR
VDD = 4.75 V to 5.25 V
VCO IN = 1/2 VDD
TA = 25°C
0.01
0.005
0
1.5
2
2.5
3
RBIAS – Bias Resistor – kΩ
Figure 18
Figure 19
RECOMMENDED LOCK FREQUENCY
(×1 OUTPUT)
vs
BIAS RESISTOR
RECOMMENDED LOCK FREQUENCY
(×1 OUTPUT)
vs
BIAS RESISTOR
60
30
VDD = 2.85 V to 3.15 V
TA = – 20°C to 75°C
Recommended Lock Frequency – MHz
Recommended Lock Frequency – MHz
3.5
25
20
15
10
2
2.5
3
3.5
4
RBIAS – Bias Resistor – kΩ
4.5
VDD = 4.75 V to 5.25 V
TA = – 20°C to 75°C
50
40
30
20
10
1.5
Figure 20
2
2.5
3
RBIAS – Bias Resistor – kΩ
3.5
Figure 21
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TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
APPLICATION INFORMATION
RECOMMENDED LOCK FREQUENCY
(×1/2 OUTPUT)
vs
BIAS RESISTOR
RECOMMENDED LOCK FREQUENCY
(×1/2 OUTPUT)
vs
BIAS RESISTOR
30
VDD = 2.85 V to 3.15 V
TA = – 20°C to 75°C
SELECT = VDD
Recommended Lock Frequency – MHz
Recommended Lock Frequency – MHz
15
12.5
10
7.5
5
2
2.5
3.5
4
3
RBIAS – Bias Resistor – kΩ
4.5
25
VDD = 4.75 V to 5.25 V
TA = – 20°C to 75°C
SELECT = VDD
20
15
10
5
1.5
Figure 23
Figure 22
14
2
2.5
3
RBIAS – Bias Resistor – kΩ
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TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
APPLICATION INFORMATION
gain of VCO and PFD
Figure 24 is a block diagram of the PLL. The
countdown N value depends on the input
frequency and the desired VCO output frequency
according to the system application requirements.
The Kp and KV values are obtained from the
operating characteristics of the device as shown
in Figure 24. Kp is defined from the phase detector
VOL and VOH specifications and the equation
shown in Figure 24(b). KV is defined from
Figures 8, 9, 10, and 11 as shown in Figure 24(c).
The parameters for the block diagram with the
units are as follows:
KV : VCO gain (rad/s/V)
Kp : PFD gain (V/rad)
Kf : LPF gain (V/V)
KN : count down divider gain (1/N)
Divider
(KN = 1/N)
PFD
(Kp)
f REF
VCO
(KV)
TLC2932
LPF
(Kf)
VOH
(a)
– 2π – π
0
π
2π
fMAX
VOH
VOL fMIN
Range of
Comparison
external counter
When a large N counter is required by the
application, there is a possibility that the PLL
response becomes slow due to the counter
response delay time. In the case of a high
frequency application, the counter delay time
should be accounted for in the overall PLL design.
VIN MIN
Kp =
VOH – VOL
4π
(b)
KV =
VIN MAX
2π(fMAX – fMIN)
VIN MAX – VIN MIN
(c)
Figure 24. Example of a PLL Block Diagram
RBIAS
The external bias resistor sets the VCO center frequency with 1/2 VDD applied to the VCO IN terminal. However,
for optimum temperature performance, a resistor value of 3.3 kΩ with a 3-V supply and a resistor value of 2.5
kΩ for a 5-V supply is recommended. For the most accurate results, a metal-film resistor is the better choice
but a carbon-compositiion resistor can be used with excellent results also. A 0.22 µF capacitor should be
connected from the BIAS terminal to ground as close to the device terminals as possible.
hold-in range
From the technical literature, the maximum hold-in range for an input frequency step for the three types of filter
configurations shown in Figure 25 is as follows:
Dw H ] 0.8
Where
ǒ Ǔ ǒ Ǔ ǒ RǓ
Kp
K
V
K ( )
f
Kf (∞) = the filter transfer function value at ω = ∞
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TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
APPLICATION INFORMATION
low-pass-filter (LPF) configurations
Many excellent references are available that include detailed design information about LPFs and should be
consulted for additional information. Lag-lead filters or active filters are often used. Examples of LPFs are shown
in Figure 25. When the active filter of Figure 25(c) is used, the reference should be applied to FIN-B because
of the amplifier inversion. Also, in practical filter implementations, C2 is used as additional filtering at the VCO
input. The value of C2 should be equal to or less than one tenth the value of C1.
C2
R1
R1
VI
VO
T1 = C1R1
C1
VI
VO
T1 = C1R1
T2 = C1R2
R2
C1
R2
C2
C1
–
VI
R1
(a) LAG FILTER
A
VO
T1 = C1R1
T2 = C1R2
(b) LAG-LEAD FILTER
(c) ACTIVE FILTER
Figure 25. LPF Examples for PLL
the passive filter
The transfer function for the lag-lead filter shown in Figure 25(b) is;
V
V
O
IN
+ 1 )1s)@ s(T1@ T2
) T2)
Where
T1
+ R1 @ C1 and T2 + R2 @ C1
Using this filter makes the closed loop PLL system a second-order type 1 system. The response curves of this
system to a unit step are shown in Figure 26.
the active filter
When using the active integrator shown in Figure 25(c), the phase detector inputs must be reversed since the
integrator adds an additional inversion. Therefore, the input reference frequency should be applied to the FIN-B
terminal and the output of the VCO divider should be applied to the input reference terminal, FIN-A.
The transfer function for the active filter shown in Figure 25(c) is:
F(s)
+ 1 )s @s @R1R2@ @C1C1
Using this filter makes the closed loop PLL system a second-order type 2 system. The response curves of this
system to a unit step are shown in Figure 27.
basic design example
The following design example presupposes that the input reference frequency and the required frequency of
the VCO are within the respective ranges of the device.
16
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APPLICATION INFORMATION
basic design example (continued)
Assume the loop has to have a 100 µs settling time (ts) with a countdown N = 8. Using the Type 1, second order
response curves of Figure 26, a value of 4.5 radians is selected for ωnts with a damping factor of 0.7. This
selection gives a good combination for settling time, accuracy, and loop gain margin. The initial parameters are
summarized in Table 5. The loop constants, KV and Kp, are calculated from the data sheet specifications and
Table 6 shows these values.
The natural loop frequency is calculated as follows:
Since
w nt s
Then
wn
+ 4.5
+ 1004.5ms + 45 k-radiansńsec
Table 5. Design Parameters
PARAMETER
SYMBOL
VALUE
UNITS
Division factor
N
8
Lockup time
t
100
µs
ωnt
4.5
rad
ζ
0.7
Radian value to selected lockup time
Damping factor
Table 6. Device Specifications
PARAMETER
SYMBOL
VCO gain
fMAX
fMIN
VALUE
UNITS
76.6
Mrad/V/s
70
MHz
20
MHz
5
V
KV
VIN MAX
VIN MIN
PFD gain
Kp
0.9
V
0.342357
V/rad
Table 7. Calculated Values
PARAMETER
Natural angular frequency
SYMBOL
VALUE
UNITS
ωn
45000
rad/sec
3.277
Mrad/sec
K = (KV • Kp)/N
Lag-lead filter
Calculated value
Nearest standard value
R1
15870
16000
Ω
Calculated value
Nearest standard value
R2
308
300
Ω
Selected value
C1
0.1
µF
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TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
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APPLICATION INFORMATION
Using the low-pass filter in Figure 25(b) and divider ratio N, the transfer function for phase and frequency are
shown in equations 1 and 2. Note that the transfer function for phase differs from the transfer function for
frequency by only the divider value N. The difference arises from the fact that the feedback for phase is unity
while the feedback for frequency is 1/N.
Hence, transfer function of Figure 24 (a) for phase is
F2(s) +
F1(s) N
@
@)
K
Kp
(T1
V
T2)
ȱȧ
ȧȧ
Ȳ
s2
ȱȧ
ȧȧ
Ȳ
ƪ
)s 1)
@
@@ )@
)
ƫ
1 s T2
Kp K
T2
V
N (T1 T2)
)
@
@)
Kp K
OUT(s)
F
REF(s)
Kp @ K
V
+ (T1
) T2)
s2
Ǹ@@
ƪ
)s@ 1)
@
@ )@
@
)
ƫ
1 s T2
K p K T2
V
N (T1 T2)
(1)
V
N (T1 T2)
and the transfer function for frequency is
F
ȳȧ
ȧȧ
ȴ
ȳȧ
ȧȧ
ȴ
) N@(T1@)VT2)
Kp K
(2)
The standard two-pole denominator is D = s2 + 2 ζ ωn s + ωn2 and comparing the coefficients of the denominator
of equation 1 and 2 with the standard two-pole denominator gives the following results.
wn +
Kp
N
(T1
K
) T2)
V
Solving for T1 + T2
T1
) T2 + KNp@@wKV2
ǒ
(3)
n
Ǔ
and by using this value for T1 + T2 in equation 3 the damping factor is
z + w2n
@
T2
) Kp @N K
V
solving for T2
T2
+ 2wz – Kp @N K
@
@
V
then by substituting for T2 in equation 3
K
Kp
2 z
V
N
T1
– w
2
K
n
N wn
p KV
+
18
)
@
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ƪ
@ ƫ
APPLICATION INFORMATION
From the circuit constants and the initial design parameters then
R2
R1
+
ȱȧ
Ȳ
+
z
N
w n * Kp K
2
Kp
wn
@
@
2 z
N
*
)
w
K
n
p@K
N
Kv
2
V
1
C1
ȳȧ
ȴ
1
C1
V
The capacitor, C1, is usually chosen between 1 µF and 0.1 µF to allow for reasonable resistor values and
physical capacitor size. In this example, C1 is chosen to be 0.1 µF and the corresponding R1 and R2 calculated
values are listed in Table 7.
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TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
APPLICATION INFORMATION
1.9
1.8
z = 0.1
1.7
z = 0.2
1.6
z = 0.3
1.5
z = 0.4
1.4
z = 0.6
z = 0.5
1.3
z = 0.7
1.2
φ 2 (t), Normalized Response
z = 0.8
1.1
1
0.9
z = 1.0
0.8
z = 1.5
0.7
0.6
z = 2.0
0.5
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
6
ωnts = 4.5
7
8
9
10
ωnt
Figure 26. Type 1 Second-Order Step Response
20
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12
13
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
APPLICATION INFORMATION
1.9
ζ = 0.1
1.8
1.7
ζ = 0.2
1.6
ζ = 0.3
1.5
ζ = 0.4
ζ = 0.5
1.4
ζ = 0.6
1.3
φ 0 (t), Normalized Output Frequency
ζ = 0.7
1.2
1.1
1
0.9
ζ = 0.8
0.8
ζ = 1.0
0.7
ζ = 2.0
0.6
0.5
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
ωnt
Figure 27. Type 2 Second-Order Step Response
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TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
APPLICATION INFORMATION
AVDD
VDD
1
2
VCO
LOGIC VDD (Digital)
SELECT
14
VCO VDD
1/2 fosc
R1†
13
BIAS
0.22 µF
REF IN
DGND
3
VCO OUT
4
FIN – A
5
FIN – B
6
PFD OUT
VCO IN
VCO GND
R3
12
11
C2
R2
C1
VCO INHIBIT 10
AGND
7
Divide
By
N
Phase
Comparator
PFD INHIBIT 9
LOGIC GND (Digital)
NC
8
DGND
S3
S4
S5
R4
R5
R6
DGND
DVDD
† RBIAS resistor
Figure 28. Evaluation and Operation Schematic
PCB layout considerations
The TLC2932 contains a high frequency analog oscillator; therefore, very careful breadboarding and
printed-circuit-board (PCB) layout is required for evaluation.
The following design recommendations benefit the TLC2932 user:
D
D
D
D
D
D
22
External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.
RF breadboarding or RF PCB techniques should be used throughout the evaluation and production
process.
Wide ground leads or a ground plane should be used on the PCB layouts to minimize parasitic inductance
and resistance. The ground plane is the better choice for noise reduction.
LOGIC VDD and VCO VDD should be separate PCB traces and connected to the best filtered supply point
available in the system to minimize supply cross-coupling.
VCO VDD to GND and LOGIC VDD to GND should be decoupled with a 0.1-µF capacitor placed as close
as possible to the appropriate device terminals.
The no-connection (NC) terminal on the package should be connected to GND.
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TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,32
0,17
0,65
14
0,13 M
8
0,15 NOM
4,70
4,30
6,70
6,10
Gage Plane
0,25
1
7
0°– 8°
0,70
0,40
A
Seating Plane
1,20 MAX
0,10
0,10 MIN
PINS **
8
14
16
20
24
28
A MAX
3,30
5,30
5,30
6,80
8,10
10,00
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064 / B 10/94
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
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