TLC352IP

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 SLCS016A − SEPTEMBER 1985 − REVISED SEPTEMBER 2002 D Single- or Dual-Supply Operation D Wide Range of Supply Voltages TLC352C, TLC352I . . . D OR P PACKAGE (TOP VIEW) 1.5 V to 18 V 1OUT 1IN− 1IN+ GND D Very Low Supply Current Drain D D D D D D D D 150 µA Typ at 5 V 65 µA Typ at 1.4 V Built-In ESD Protection High Input Impedance . . . 1012 Ω Typ Extremely Low Input Bias Current 5 pA Typ Ultrastable Low Input Offset Voltage Input Offset Voltage Change at Worst-Case Input Conditions Typically 0.23 µV/ Month, Including the First 30 Days Common-Mode Input Voltage Range Includes Ground Outputs Compatible With TTL, MOS, and CMOS Pin-Compatible With LM393 1 8 2 7 3 6 4 5 VDD 2OUT 2IN− 2IN+ symbol (each comparator) IN+ OUT IN− description This device is fabricated using LinCMOS technology and consists of two independent voltage comparators, each designed to operate from a single power supply. Operation from dual supplies is also possible if the difference between the two supplies is 1.4 V to 18 V. Each device features extremely high input impedance (typically greater than 1012 Ω), which allows direct interface to high-impedance sources. The output are n-channel open-drain configurations and can be connected to achieve positive-logic wired-AND relationships. The capability of the TLC352 to operate from 1.4-V supply makes this device ideal for low-voltage battery applications. The TLC352 has internal electrostatic discharge (ESD) protection circuits and has been classified with a 2000-V ESD rating tested under MIL-STD-883C, Method 3015. However, care should be exercised in handling this device as exposure to ESD may result in degradation of the device parametric performance. The TLC352C is characterized for operation from 0°C to 70°C. The TLC352I is characterized for operation over the industrial temperature range of − 40°C to 85°C. AVAILABLE OPTIONS PACKAGE TA VIO max AT 25°C 0°C to 70°C − 40°C to 85°C SMALL-OUTLINE (D) PLASTIC DIP (P) 5 mV TLC352CD TLC352CP 5 mV TLC352ID TLC352IP The D packages are available taped and reeled. Add R suffix to device type (e.g., TLC352 CDR). LinCMOS is a trademark of Texas Instruments Incorporated. Copyright  2002, Texas Instruments Incorporated   
  
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 SLCS016A − SEPTEMBER 1985 − REVISED SEPTEMBER 2002 equivalent schematic (each comparator) Common to All Channels VDD OUT GND IN− IN+ absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 18 V Output voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Duration of output short circuit to ground (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA TLC352C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C TLC352I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 40°C to 85°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values except differential voltages are with respect to the network ground. 2. Differential voltages are at IN+ with respect to IN −. 3. Short circuits from outputs to VDD can cause excessive heating and eventual device destruction. DISSIPATION RATING TABLE 2 PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR DERATE ABOVE TA TA = 70°C POWER RATING TA = 85°C POWER RATING D P 500 mW 500 mW 5.8 mW/°C N/A 64°C N/A 464 mW 500 mW 377 mW 500 mW POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VDD = 5 V VDD = 10 V 0 0 0 1.4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Input bias current Common-mode input voltage range Low-level output voltage Low-level output current Supply current (two comparators) IIB VICR VOL IOL IDD VID = 0.5 V, VID = − 0.5 V, VIC = VICR min, No load VOL = 0.3 V See Note 4 TEST CONDITIONS Full range 25°C 25°C Full range 25°C Full range MAX 25°C MAX 25°C Full range 25°C TA† 1 0 to 0.2 MIN 65 1.6 100 5 1 2 TYP TLC352C 200 150 200 200 0.6 0.3 6.5 5 MAX 1 0 to 0.2 MIN 70 8.5 65 1.6 100 5 1 2 TYP TLC352I − 40 0 0 1.4 16 200 150 200 200 2 1 7 5 MAX 85 8.5 3.5 µA mA mV V nA pA nA pA mV UNIT °C V V UNIT † All characteristics are measured with zero common-mode input voltage unless otherwise noted. Full range is 0°C to 70°C for TLC352C, − 40°C to 85°C for TLC352I. IMPORTANT: See Parameter Measurement Information. NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 1.25 V or below 150 mV with a 10-kΩ resistor between the output and VDD. They can be verified by applying the limit value to the input and checking for the appropriate output state. Input offset current Input offset voltage IIO VIO PARAMETER 16 3.5 MAX MIN MIN MAX TLC352I TLC352C electrical characteristics at specified free-air temperature, VDD = 1.4 V (unless otherwise noted) Operating free-air temperature, TA Common-mode input voltage, VIC Supply voltage, VDD recommended operating conditions TM
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 SLCS016A − SEPTEMBER 1985 − REVISED SEPTEMBER 2002 3 4 VID = − 1 V, VID = 1 V, Low-level output current Supply current (two comparators) IDD No load VOL = 1.5 V IOL = 4 mA VOH = 5 V VOH = 15 V See Note 5 Full range 25°C 25°C Full range 25°C Full range 25°C 6 0.15 16 150 0.4 0.3 700 400 1 6 0 to VDD − 1.5 0.15 16 150 0.1 5 1 1 TYP TLC352I 0 to VDD − 1.5 MIN Full range 0.6 0.3 6.5 5 MAX 25°C 0.1 5 1 1 TYP TLC352C 0 to VDD − 1 MIN 0 to VDD − 1 MAX 25°C MAX 25°C Full range 25°C TA† 0.4 0.3 700 400 1 2 1 7 5 MAX mA mA mV µA nA V nA pA nA pA mV UNIT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 RL connected to 5 V through 5.1 kΩ,, CL = 15 pF‡, See Note 6 650 200 TYP TTL-level input step MIN MAX TLC352C, TLC352I 100-mV input step with 5-mV overdrive TEST CONDITIONS ‡ CL includes probe and jig capacitance. NOTE 6: The response time specified is the interval between the input step function and the instant when the output crosses 1.4 V. Response time PARAMETER switching characteristics, VDD = 5 V, TA = 25°C ns UNIT † All characteristics are measured with zero common-mode input voltage unless otherwise noted. Full range is 0°C to 70°C for TLC352C, − 40°C to 85°C for TLC352I. IMPORTANT: See Parameter Measurement Information. NOTE 5: The offset voltage limits given are the maximum values required to drive the output above 4 V or below 400 mV with a 10-kΩ resistor between the output and VDD. They can be verified by applying the limit value to the input and checking for the appropriate output state. VID = 1 V, IOL VID = 1 V Low-level output voltage Common-mode input voltage range VICR VOL Input bias current IIB High-level output current Input offset current IIO VIC = VICR min, TEST CONDITIONS IOH Input offset voltage VIO PARAMETER electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) Template Release Date: 7−11−94
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 SLCS016A − SEPTEMBER 1985 − REVISED SEPTEMBER 2002 
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 SLCS016A − SEPTEMBER 1985 − REVISED SEPTEMBER 2002 PARAMETER MEASUREMENT INFORMATION The digital output stage of the TLC352 can be damaged if it is held in the linear region of the transfer curve. Conventional operational amplifier/comparator testing incorporates the use of a servo loop that is designed to force the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, the following alternative for measuring parameters such as input offset voltage, common-mode rejection, etc., are offered. To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown in Figure 1(a). With the noninverting input positive with respect to the inverting input, the output should be high. With the input polarity reversed, the output should be low. A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can be slewed as shown in Figure 1(b) for the VICR test, rather than changing the input voltages, to provide greater accuracy. A close approximation of the input offset voltage can be obtained by using a binary search method to vary the differential input voltage while monitoring the output state. When the applied input voltage differential is equal but opposite in polarity to the input offset voltage, the output changes state. 5V 1V 5.1 kΩ 5.1 kΩ + + − − Applied VIO Limit VO Applied VIO Limit VO −4V (a) VIO WITH VIC = 0 (b) VIO WITH VIC = 4 V Figure 1. Method for Verifying That Input Offset Voltage Is Within Specified Limits POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 
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 SLCS016A − SEPTEMBER 1985 − REVISED SEPTEMBER 2002 PARAMETER INFORMATION Figure 2 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the comparator into the linear region. The circuit consists of a switching-mode servo loop in which U1a generates a triangular waveform of approximately 20-mV amplitude. U1b acts as a buffer, with C2 and R4 removing any residual dc offset. The signal is then applied to the inverting input of the comparator under test, while the noninverting input is driven by the output of the integrator formed by U1c through the voltage divider formed by R9 and R10. The loop reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input exactly equals the input offset voltage. Voltage divider R9 and R10 provides a step up of the input offset voltage by a factor of 100 to make measurement easier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the reading; therefore, it is suggested that their tolerance level be 1% or lower. Measuring the extremely low values of input current requires isolation from all other sources of leakage current and compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakage can be measured with no device in the socket. Subsequently, this open-socket leakage value can be subtracted from the measurement obtained with a device in the socket to obtain the actual input current of the device. R5 1.8 kΩ, 1% VDD U1b 1/4 TLC274CN Buffer + C2 1 µF U1c 1/4 TLC274CN − DUT − R1 240 kΩ − C1 0.1 µF R6 5.1 kΩ C3 0.68 µF + R3 100 kΩ R7 1MΩ R4 47 kΩ Integrator R8 1.8 kΩ, 1% U1a 1/4 TLC274CN Triangle Generator R10 100 Ω, 1% C4 0.1 µF R9 10 kΩ, 1% R2 10 kΩ Figure 2. Circuit for Input Offset Voltage Measurement 6 VIO (X100) + POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
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 SLCS016A − SEPTEMBER 1985 − REVISED SEPTEMBER 2002 PARAMETER MEASUREMENT INFORMATION Response time is defined as the interval between the application of an input step function and the instant when the output reaches 50% of its maximum value. Response time, low-to-high-level output, is measured from the leading edge of the input pulse, while response time, high-to-low level output, is measured from the trailing edge of the input pulse. Response-time measurement at low input signal levels can be greatly affected by the input offset voltage. The offset voltage should be balanced by the adjustment at the inverting input (as shown in Figure 3) so that the circuit is just at the transition point. Then a low signal, for example 105-mV or 5-mV overdrive, causes the output to change state. VDD 1 µF 5.1 kΩ Pulse Generator DUT 50 Ω CL (see Note A) 1V Input Offset Voltage Compensation Adjustment 10 Ω 10 Turn 1 kΩ 0.1 mF −1V TEST CIRCUIT Overdrive Overdrive Input Input 100 mV 100 mV 90% 90% 50 % Low-to-HighLevel Output 10% High-to-LowLevel Output tr 50% 10% tf tPLH tPHL VOLTAGE WAVEFORMS NOTE A: CL includes probe and jig capacitance. Figure 3. Response, Rise, and Fall Times Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TLC352CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 352C Samples TLC352CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 352C Samples TLC352CP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TLC352CP Samples TLC352CPWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 P352 Samples TLC352ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 352I Samples TLC352IDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 352I Samples TLC352IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 352I Samples TLC352IDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 352I Samples TLC352IP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TLC352IP Samples TLC352IPW ACTIVE TSSOP PW 8 150 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 P352I Samples TLC352IPWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 P352I Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of