TLC3545IDGKR


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   FEATURES D 200-KSPS Sampling Rate D Built-In Conversion Clock D INL: ±1 LSB Max D D D D D D D D DNL: ±1 LSB Max SINAD = 81.5 dB, SFDR = 95 dB THD = 94 dB at 15 kHz fin, 200 KSPS SPI/DSP-Compatible Serial Interfaces With SCLK Input up to 15 MHz Single 5-V Supply Rail-to-Rail Analog Input With 500 kHz BW Two Input Options Available: − TLC3541 − Single Channel Input − TLC3545 − Single Channel, Pseudo-Differential Input (TLC3541) Optimized DSP Interface − Requires FS Input Only Low Power With Auto-Power Down − Operating Current: 3.5 mA − Auto-Powerdown Current: 5 µA Pin Compatible 12-/14-/16-Bit Family in 8-Pin SOIC and MSOP Packages APPLICATIONS D ATE System D Industrial Process Control D Measurement D Motor Control DESCRIPTION The TLC3541 and TLC3545 are a family of high performance, 14-bit, low power, miniature CMOS analog-to-digital converters (ADCs). These devices operate from a single 5-V supply. Devices are available with single, dual, or single pseudo-differential inputs. All of these devices have a chip select (CS), serial clock (SCLK), and serial data output (SDO) that provides a direct 3-wire interface to the serial port of most popular host microprocessors (SPI interface). When interfaced with a DSP, a frame sync signal (FS) is used to indicate the start of a serial data frame on either pin 1 (CS) or pin 7 (FS) for the TLC3541. The TLC3545 ADC connects to the DSP via pin 1 only (CS). The TLC3541 and TLC3545 are designed to operate with low power consumption. The power saving feature is further enhanced with an auto-power down mode. This product family features a high-speed serial link to modern host processors with an external SCLK up to 15 MHz. Both families use a built-in oscillator as the conversion clock, providing a 2.67 µs maximum conversion time. TLC3541 D OR DGK Package (TOP VIEW) CS REF GND AIN 1 8 2 7 3 6 4 5 TLC3545 D OR DGK Package (TOP VIEW) SDO FS VDD SCLK CS REF GND AIN(+) 1 8 2 7 3 6 4 5 SDO SCLK VDD AIN(−) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 
 
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 SLAS345 − DECEMBER 2001 AVAILABLE OPTIONS PACKAGED DEVICES TA −40°C to 85°C 8-MSOP (DGK) 8-SOIC (D) TLC3541IDGK (PKG Code = AMG) TLC3541ID TLC3545IDGK (PKG Code = AMM) TLC3545ID functional block diagram TLC3541 TLC3545 VDD VDD REF AIN REF S/H OSC SCLK CS FS LOW POWER SAR ADC AIN (+) SDO AIN (−) OSC Conversion Clock CONTROL LOGIC SCLK CS LOW POWER SAR ADC Conversion Clock CONTROL LOGIC GND GND 2 S/H www.ti.com SDO 

 SLAS345 − DECEMBER 2001 Terminal Functions TLC3541 single channel unipolar ADCs TERMINAL NAME NO. I/O DESCRIPTION AIN 4 I Analog input channel CS 1 I Chip select. A high-to-low transition on the CS input removes SDO from a high-impedance state within a maximum delay time. If the TLC3541 is attached to a dedicated TMS320 DSP serial port using the FS input, CS can be grounded. FS 7 I DSP frame sync input. Indication of a start of a serial data frame. A low-to-high transition removes SDO from the high-impedance state and the MSB is presented. Tie this pin to VDD if not used. GND 3 I Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND. SDO 8 O The 3-state serial data output for the A/D conversion result. SDO is kept in the high-impedance state when CS is high. The output format is MSB first. Remaining data bits are presented on the rising edge of SCLK. When FS is not active (FS = 1 at the falling edge of CS): The MSB is presented on the SDO pin on the falling edge of CS after a maximum delay time. Data is valid on each falling edge of SCLK until all data is read. When FS is active (FS = 0 at the falling edge of CS): The MSB is presented to the SDO output on the rising edge of FS. Data is valid on the falling edge SCLK and changes on the rising edge SCLK (this is typically used with an active FS from a DSP). SDO returns to the high-impedance state after the 17th rising edge on SCLK. If a 17th SCLK cycle is not presented, as is the case when using an SPI host, SDO returns to the high-impedance state on the rising edge of CS. SCLK 5 I Serial clock. This terminal receives the serial SCLK from the host processor. REF 2 I External voltage reference input VDD 6 I Positive supply voltage TLC3545 single channel pseudo-differential ADCs TERMINAL NAME NO. I/O DESCRIPTION AIN0 (+) 4 I Positive analog input for the TLC3545. AIN1 (−) 5 I Inverted analog input for the TLC3545. CS 1 I Chip select. A high-to-low transition on CS removes SDO from the high-impedance state within a maximum delay time. The CS input can be connected to a DSP frame sync (FS) output when a dedicated TMS320 DSP serial port is used. GND 3 I Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND. SDO 8 O The 3-state serial data output for the A/D conversion result. SDO is kept in the high-impedance state when CS is high and presents output data after the CS falling edge until the LSB is presented. The output format is MSB first. The remaining data bits are presented on the rising edge of SCLK. Output data is valid on each falling edge of SCLK until all data is read. SDO returns to the high-impedance state after the 17th rising edge on SCLK. If a 17th SCLK cycle is not presented, as is the case when using an SPI host, SDO returns to the high-impedance state on the rising edge of CS. SCLK 7 I Serial clock. This terminal receives the serial SCLK from the host processor. REF 2 I External voltage reference input VDD 6 I Positive supply voltage www.ti.com 3 

 SLAS345 − DECEMBER 2001 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, GND to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6.5V Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD+0.3 V Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD+0.3 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD+0.3 V Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C Operating free-air temperature range: TA (I suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions Supply voltage, VDD Frequency, SCLK Tolerable clock jitter, SCLK Aperature jitter External reference voltage input, VREF VREF input impedance External reference input current Analog input voltage VDD = 4.5 V to 5.5 V VDD = 4.5 V to 5.5 V MIN NOM 4.5 5 100 VDD = 4.5 V to 5.5 V External reference voltage input, VREF VDD = 5 V, CS = 1, VDD = 5 V, CS = 0, SCLK = 0 VDD = VREF = 4.5 V, AIN, AIN(+) CS=0, SCLK = 15 MHz SCLK = 15 MHz AIN(−) 100 4 20 0.02 www.ti.com ps V kΩ 1 0 VDD −0.2 0.2 −40 V kHz MΩ 25 2.1 TLC3541/45I UNIT ps VDD 100 Low level control input voltage, VIL 4 5.5 15000 97 High level control input voltage, VIH Operating free-air temperature, TA MAX mA V V 0.8 V 85 °C 

 SLAS345 − DECEMBER 2001 electrical characteristics over recommended operating free-air temperature range, VDD = 5 V, VREF = 4.096 V, SCLK frequency = 15 MHz (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS TYP MAX VDD = 4.5 V, VDD = 4.5 V IOH = −0.2 mA IOL = 0.8 mA Off-state output current (high-impedance-state) VO = VDD, VO = 0, CS = VDD 1 2.5 CS = VDD −1 −2.5 IIH IIL High-level input current 0.005 2.5 Low-level input current VI = VDD VI = 0 −0.005 2.5 µA ICC Operating supply current CS at 0 V, 3.5 mA ICC(PD) Power-down supply current 5 µA Input capacitance Zi Input resistance V 0.4 VDD = 4.5 V to 5.5 V For all digital inputs, 0≤ VI ≤ 0.3 V or VI ≥ VDD − 0.3 V, SCLK=VDD, VDD = 4.5 V to 5.5 V Selected analog input channel leakage current Ci 3.9 UNIT Low-level output voltage IOZ High-level output voltage MIN 3 Selected channel at VDD 1 Selected channel at 0 V −1 Analog inputs 11 14 Control Inputs 20 25 VDD = 5.5 V V µA A µA µA A pF 500 Ω MAX UNIT ac specifications (TLC3541/45) PARAMETER SINAD Signal-to-noise ratio +distortion SNR Signal-to-noise ratio TEST CONDITIONS Total harmonic distortion ENOB Effective number of bits SFDR Spurious free dynamic range TYP fI = 15 kHz at 200 KSPS fI = 15 kHz at 200 KSPS 81.5 −94 −87 TLC3545 fI = 15 kHz at 200 KSPS fI = 15 kHz at 200 KSPS −94 −89 13.2 TLC3541 fI = 15 kHz at 200 KSPS fI = 15 kHz at 200 KSPS −95 −87 TLC3545 fI = 15 kHz at 200 KSPS −95 −89 TLC3541 THD MIN Full-power bandwidth, −3 dB, analog input Full-power bandwidth, −1 dB, analog input Crosstalk 0.25 LSB dB 82 dB dB Bits dB 1 MHz 500 kHz 80 dB dc specifications (TLC3541/45) PARAMETER TEST CONDITIONS MIN INL Integral linearity error (see Note 1) −1 DNL Differential linearity error −1 EO Offset error (see Note 2) EG Gain error (see Note 2) TYP† 0.75 MAX UNIT 1 LSB 1 LSB TLC3541 −3.5 3.5 TLC3545 −1 1 TLC3541 −2 2 TLC3545 −1.8 1.8 mV mV † All typical values are at VDD = 5 V, TA = 25°C. NOTES: 1. Linear error is the maximum deviation from the best straight line through the A/D transfer characteristics. 2. Zero error is the difference between 0000h and the converted output for zero input voltage: full-scale error is the difference between ideal full-scale and the converted output for full-scale input voltage. www.ti.com 5 

 SLAS345 − DECEMBER 2001 timing requirements, VDD = 5 V, VREF = 4.096 V, SCLK frequency = 15 MHz (unless otherwise specified) MIN TYP MAX UNIT tcyc(SCLK) tw1 SCLK cycle time, VDD = 4.5 V to 5.5 V (see Note 3) 66 10000 ns Pulse duration, SCLK low 27 5000 ns tw2 th1 Pulse duration, SCLK high 27 5000 ns tsu1 th2 Setup time, CS falling edge before the first SCLK falling edge tw3 td1 Pulse duration, CS high td2 td3 Delay time, SCLK rising edge to next SDO data bit valid, VDD = VREF = 4.5 V, 20 pF Delay time, 17th SCLK rising edge to 3-stated SDO, VDD = VREF = 4.5 V, 20 pF (see Note 4) tsu3 tw4 Setup time, CS falling edge before FS rising edge (TLC3541 only) 0.5 1 SCLKs Pulse duration, FS high (TLC3541 only) 0.5 1 SCLKs tsu4 th4 Setup time, FS rising edge before SCLK falling edge (TLC3541 only) tsu5 td4 Setup time, FS falling edge before 1st SCLK falling edge (TLC3541 only) th6 tsu6 Hold time, CS low after 1st SCLK falling edge 5 ns Setup time, CS rising edge before 9th (or the last) SCLK falling edge 5 ns th7 tsu7 Hold time, FS low after 1st SCLK falling edge (TLC3541 only) 5 ns Setup time, FS rising edge before 9th (or the last) SCLK falling edge 5 ns tcyc(reset) tconv Active CS/FS cycle time, SCLK falling edges required to initialize ADC Hold time, CS high after SCLK falling edge Hold time, CS low after 16th SCLK falling edge 3 ns 15 ns 5 ns 0.5 Delay time, CS falling edge to SDO MSB valid, VDD = VREF = 4.5 V, 20 pF Hold time, FS high after SCLK falling edge (TLC3541 only) 12 17 ns 15 ns 20 ns 12.5 ns 5 ns 12 ns Delay time, FS rising edge to SDO MSB valid, (VDD = VREF = 4.5 V, 20 pF TLC3541 only) Conversion time (20 conversion clocks based on 7.5 MHz to 12 MHz OSC) SCLKs 15 1 8 1.67 2.67 ns SCLKs µs ts Sample time, 20 SCLKs, SCLK up to 15 MHz 1.33 200 µs NOTES: 3. Timing specifications given for 40/60 to 60/40 duty cycle 4. SDO goes into the high impedance state after detection of the 17th rising SCLK edge or a rising CS edge if a 17th SCLK is not presented. 6 www.ti.com 

 SLAS345 − DECEMBER 2001 TYPICAL CHARACTERISTICS FFT 0 fi = 15 kHz, VDD = VREF = 5 V, 200 KSPS Magnitude − dB −20 −40 −60 −80 −100 −120 −140 −160 0 10 20 30 40 50 60 70 80 90 100 70 80 90 100 fi − Input Frequency − kHz Figure 1 FFT 0 fi = 1.5 kHz, VDD = VREF = 5 V, 200 KSPS Magnitude − dB −20 −40 −60 −80 −100 −120 −140 −160 0 10 20 30 40 50 60 fi − Input Frequency − kHz DNL − Differential Nonlinearity − LSB Figure 2 DIFFERENTIAL NONLINEARITY 1.5 1 0.5 0 −0.5 −1 −1.5 0 5000 10000 15000 Code Figure 3 www.ti.com 7 

 SLAS345 − DECEMBER 2001 TYPICAL CHARACTERISTICS INL − Integral Nonlinearity − LSB INTEGRAL NONLINEARITY 1.5 1 0.5 0 −0.5 −1 −1.5 0 5000 10000 15000 Code Figure 4 TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY SIGNAL-TO NOISE RATIO vs INPUT FREQUENCY −80 85 THD − Total Harmonic Distortion − dB SNR − Signal-To-Noise Ration − dB VDD = VREF = 5 V 83 81 79 77 75 0 20 40 60 80 100 120 fi − Input Frequency − kHz −85 −90 −95 −100 0 20 40 60 80 100 fi − Input Frequency − kHz Figure 6 Figure 5 8 VDD = VREF = 5 V www.ti.com 120 

 SLAS345 − DECEMBER 2001 TYPICAL CHARACTERISTICS SIGNAL-TO-NOISE RATIO vs FREE-AIR TEMPERATURE TOTAL HARMONIC DISTORTION vs FREE-AIR TEMPERATURE 83.4 83.3 −84 SNR − Signal-To-Noise Ration − dB THD − Total Harmonic Distortion − dB −82 −86 fi = 100 kHz −88 −90 −92 fi = 15 kHz −94 83.1 fi = 15 kHz 83 82.9 82.8 82.7 82.6 −96 fi = 1 kHz −98 82.5 −40 25 80 TA − Free-Air Temperature − °C −40 25 80 TA − Free-Air Temperature − °C Figure 8 Figure 7 TOTAL HARMONIC DISTORTION vs REFERENCE VOLTAGE SIGNAL-TO-NOISE RATIO vs REFERENCE VOLTAGE 83.0 −97.5 fi = 1.5 kHz, 200 KSPS −98.0 SNR − Signal-To-Noise Ration − dB THD − Total Harmonic Distortion − dB fi = 1 kHz 83.2 −98.5 −99.0 −99.5 −100.0 −100.5 −101.0 4.0 4.5 5.0 VREF − Reference Voltage − V 82.8 82.6 82.4 82.2 82.0 81.8 4.0 4.5 5.0 VREF − Reference Voltage − V Figure 9 Figure 10 www.ti.com 9 

 SLAS345 − DECEMBER 2001 TYPICAL CHARACTERISTICS MINIMUM DIFFERENTIAL NONLINEARITY vs REFERENCE VOLTAGE 0.8 0.8 0.6 0.6 Minimum Differential Nonlinearity − LSB Maximum Differential Nonlinearity − LSB MAXIMUM DIFFERENTIAL NONLINEARITY vs REFERENCE VOLTAGE 0.4 0.2 −0.0 −0.2 −0.4 −0.6 −0.8 4.0 4.0 0.2 −0.0 −0.2 −0.4 −0.6 −0.8 4.0 4.0 5.0 5.0 4.5 0.4 VREF − Reference Voltage − V 4.5 VREF − Reference Voltage − V Figure 11 Figure 12 INTEGRAL NONLINEARITY vs REFERENCE VOLTAGE 0.8 Integral Nonlinearity − LSB 0.6 0.4 0.2 −0.0 −0.2 −0.4 −0.6 −0.8 4.0 4.5 VREF − Reference Voltage − V Figure 13 10 www.ti.com 5.0 5.0 5.0 

 SLAS345 − DECEMBER 2001 PRINCIPLES OF OPERATION control and timing device initialization/RESET cycle The TLC3541/45 each require one RESET cycle after power-on for initialization in order to operate properly. The RESET cycle is initiated by asserting the CS pin (pin 1) low for a minimum duration of at least one SCLK falling edge but no more than 8 SCLK falling edges in length. The RESET cycle is terminated by asserting CS high. If a valid RESET cycle is issued, the data presented on the SDO output during the following cycle is 3FC0h. This output code is useful in determining when a valid reset/initialization has occurred. The TLC3541 has separate CS and FS pins. In this case, it is also possible to initiate the RESET cycle by asserting FS low if CS is already asserted low. The RESET cycle can be terminated by either asserting CS high (as shown in the first RESET cycle in Figure 14), or by asserting FS high (as shown in the second RESET cycle in Figure 14), whichever happens first. 1 2 8 1 2 8 1 4 16 1 4 SCLK tcyc(reset) OR CS tcyc(reset) FS High for Valid Initialization FS 1−8 Falling SCLK Edges− ADC is Initialized SDO Normal Cycle−Sample and Convert ÎÎÎÎÎÎÎÎÎÎÎÎ t(PWRDWN) Normal Cycle−Sample and Convert MSB 1111−1111−0000−00−XX LSB+1 LSB SDO Data−Reset of Previous Cycle’s Sample For TLC35xx−LSB Presented on 14th Rising SCLK Edge Figure 14. TLC3541/45 Initialization Timing sampling The converter sample time is 20 SCLKs in duration, beginning on the 5th SCLK received during an active signal on the CS input (or FS input for the TLC3541.) conversion Each device completes a conversion in the following manner. The conversion is started after the 24th falling SCLK edge. The CS input can be released at this point or at any time during the remainder of the conversion cycle. The conversion takes a maximum of 2.67 µs to complete. Enough time (for conversion) should be allowed before the next falling edge on the CS input (or rising edge on the FS input for the TLC3541) so that no conversion is terminated prematurely. If the conversion cycle is terminated early, the data presented on SDO during the following cycle is 3FC0h. This predefined output code is helpful in determining if the cycle time is not long enough to complete the conversion. The same code is also used to determine if a reset cycle is valid. For all devices, the SDO data presented during a cycle is the result of the conversion of the sample taken during the previous cycle. The output data format is shown in the following table. SERIAL OUTPUT DATA FORMAT TLC3541/45 MSB [D15:D2] LSB [D1:D0] Conversion result (OD13−OD0) Don’t care www.ti.com 11 

 SLAS345 − DECEMBER 2001 PRINCIPLES OF OPERATION control and timing (continued) sampling and conversion cycle TLC3541: Control via pin 1, CS (FS = 1 at the falling edge of CS) − The falling edge of CS is the start of the cycle. Transitions on CS can occur when SCLK is high or low. The MSB may be read on the first falling SCLK edge after CS is low. Output data changes on the rising edge of SCLK. This control method is typically used for a microcontroller with an SPI interface, although it can also be used for a DSP. The microcontroller SPI interface should be programmed for CPOL = 0 (serial clock inactive low) and CPHA = 1 (data valid on the falling edge of serial clock). Control via pin 7, FS (CS is tied/held low) − The rising edge of FS is the start of the cycle. Transitions on FS can occur when SCLK is high or low. The MSB is presented on SDO after the rising edge of FS. The MSB may be read on the first falling edge of SCLK after the FS falling edge. Output data changes on the rising edge of SCLK. This is the typical configuration when the ADC is the only device on the TMS320 DSP serial port. Control via pin 1 and pin 7, CS and FS − Transitions on CS and FS can occur when SCLK is high or low. The MSB is presented after the rising edge of FS. The falling edge of FS is the start of the sampling cycle. The MSB may be read on the first falling edge of SCLK after the FS falling edge. Output data changes on the rising edge of SCLK. This is typically used for multiple devices connected to a single TMS320 DSP serial port. TLC3545: All control is provided using the CS input (pin 1) on the TLC3545. Transitions on CS can occur when SCLK is high or low. The cycle is started on the falling edge transition on the CS input. This signal can be provided by either a CS signal (when interfacing with an SPI microcontroller) or FS signal (when interfacing with a TMS320 DSP). The MSB is presented to SDO on the falling edge of the signal applied to pin 1 and may be read on the first falling SCLK edge after this input is low. Output data changes on the rising edge of SCLK. control modes control via pin 1 (CS, SPI interface) All devices are compatible with this mode of operation. A falling edge on the CS input initiates the cycle. (For the TLC3541, the FS input is tied to VDD ). The CS input remains low for the entire sampling time plus 4 SCLK decoding time (24 falling SCLK edges) and can then be released at any point during the remainder of the conversion. Enough time should be allowed before the next falling CS edge so that the conversion cycle is not terminated prematurely. The microcontroller SPI interface should be programmed for CPOL = 0 (serial clock inactive low) and CPHA = 1 (data is valid on the falling edge of serial clock). 1 2 3 4 5 6 7 12 13 14 15 16 24 1 SCLK tconv ts CS SDO Data Is the Result of the Previous Sample For TLC35xx, the LSB Is Presented on the Rising SCLK 14th Edge SDO MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 LSB+2 LSB+1 ÎÎÎÎÎ LSB LSB−1 t(PWRDWN) LSB−2 Figure 15. SPI Cycle TIming Using the CS Input (FS = 1 for TLC3541) 12 www.ti.com MSB MSB−1 

 SLAS345 − DECEMBER 2001 PRINCIPLES OF OPERATION control via pin 1 (CS, DSP interface) All devices are compatible with this mode of operation. The FS signal from a DSP is connected directly to the CS input of the ADC. A falling edge on the CS input while SCLK is high or low initiates the cycle. (For TLC3541 in this configuration, the FS input is tied to VDD.) Enough time should be allowed before the next rising CS edge so that the conversion cycle is not terminated prematurely. 1 3 2 4 5 6 7 12 13 14 15 16 24 1 SCLK ts tconv CS The CS Input Signal Is SDO Data Is the Result of the Previous Sample Generated by the FS Output For TLC35xx, the LSB Is Presented on the Rising SCLK 14th Edge From a TMS320 DSP MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 LSB+2 LSB+1 SDO ÎÎÎÎÎ LSB LSB−1 t(PWRDWN) LSB−2 MSB MSB−1 Figure 16. DSP Cycle Timing Using the CS Input (FS = 1 for TLC3541 only) control via pin 1 and pin 7 (CS and FS or FS only, DSP interface) Only TLC3541 is compatible with this mode of operation. The CS input to the ADC can be controlled via a general-purpose I/O pin from the DSP or tied to ground. The FS signal from the DSP is connected directly to the FS input of the ADC. A rising FS edge releases the MSB to the SDO output. The falling edge on the FS input while SCLK is high or low initiates the cycle. The CS input should remain low for the entire sampling time plus 4 SCLK decoding time after falling FS (24 falling SCLK edges) and can then be released at any time during the remainder of the conversion cycle. The optimum DSP interface is achieved when tying CS to ground and using only the FS input to control the ADC. 1 2 3 4 5 6 14 15 16 17 24 1 2 3 4 SCLK CS tconv ts FS SDO Data Is the Result of the Previous Sample For TLC35xx, the LSB Is Presented on the Rising SCLK 14th Edge SDO ÎÎÎ MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 LSB+1 The MSB Is Presented on the SDO Output After a Rising Edge on the FS Input. LSB ÎÎÎÎ LSB−1 LSB−2 t(PWRDWN) Î ÎÎ MSB MSB−1 MSB−2 MSB−3 The Device Will Go Into the Power Down State After the Conversion Is Complete. A Falling CS Edge or Rising FS Edge, Whichever Occurs First, Removes the Device From Power Down. Figure 17. DSP Cycle Timing Using FS Only (or Using Both CS and FS for TLC3541) www.ti.com 13 

 SLAS345 − DECEMBER 2001 PRINCIPLES OF OPERATION 1 SCLK tconv ts tcyc(SCLK) 5 2 14 16 15 1 17, 24 tw1 tsu1 t(PWRDWN) th2 tw2 CS th1 ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ td2 SDO tw3 td3 LSB MSB td1 MSB LSB−2 LSB−1 Figure 18. Critical Timing: Control Via CS Input (FS = 1 for TLC3541) tconv ts 2 1 SCLK 5 15 14 tsu5 16 t(PWRDWN) th2 th4 1 17, 24 tsu4 CS tw4 t(PWRDWN) td2 FS ÎÎÎ ÎÎÎ tsu3 SDO ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ td3 LSB MSB td4 LSB−1 LSB−2 Figure 19. Critical Timing: Control Via CS and FS Inputs (TLC3541 Only) 2 1 SCLK 8 9 1 2 tsu6 th6 tcyc(reset) Normal Cycle Begins CS Reset Cycle SDO MSB MSB MSB−1 (Output = 3FC0h) Figure 20. Critical Timing: Reset/Initialization Cycle (FS =1 for TLC3541) 14 www.ti.com ÎÎÎ ÎÎÎ MSB 

 SLAS345 − DECEMBER 2001 PRINCIPLES OF OPERATION 2 1 SCLK 8 th7 9 2 1 tsu7 th7 8 9 2 1 tsu6 tcyc(reset) CS tcyc(reset) OR Normal Cycle Begins FS ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Initialization Cycle (Reset) SDO MSB MSB ÎÎÎ ÎÎÎ MSB Figure 21. Critical Timing: Initialization Cycle (TLC3541 Only) MSB−1 detailed description The TLC3541/5 are successive approximation (SAR) ADCs utilizing a charge-redistribution DAC. Figure 22 shows a simplified version of the ADC. The sampling capacitor acquires the signal on AIN (or the AIN(+) pin for TLC3545) during the sampling period. When the conversion process starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is balanced, the conversion is complete and the ADC output code is generated. Charge Redistribution DAC AIN/ AIN(+) − Ci + Control Logic ADC Code Ci GND/ AIN(−) Figure 22. Simplified SAR Circuit www.ti.com 15 

 SLAS345 − DECEMBER 2001 PRINCIPLES OF OPERATION pseudo-differential inputs The TLC3545 operates in pseudo-differential mode. The inverted input is available on pin 5. The inverted input can tolerate a maximum input ripple of ±0.2 V. It is normally used for zero-scale offset cancellation or ground noise rejection. serial interface Output data format is binary (unipolar straight binary). binary D Zero-Scale Code = 0000h, VAIN = GND D Full-Scale Code = 3FFFh, VAIN = VREF – 1 LSB reference voltage An external reference must be applied via pin 2, VREF. The voltage level applied to this pin establishes the upper limit of the analog inputs to produce a full-scale reading. The value of VREF, and the analog input should not exceed the positive supply or be less than GND, consistent with the specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to or higher than VREF and at zero when the input signal is equal to or less than GND. auto-power down and power up Auto-power down is built into the devices in order to reduce power consumption. The wake-up time is fast enough to provide power down between each conversion cycle. The power-down state is initiated at the end of conversion and wakes up on a falling CS edge (or rising FS edge, whichever occurs first, for TLC3541 only). 16 www.ti.com 

 SLAS345 − DECEMBER 2001 APPLICATION INFORMATION 5V DSP to Single TLC3541 0.1 µF REF 0.1 µF 10 kΩ 10 kΩ VDD FS FSX0 SD0 DR0 DSP TLC3541 CLKX0 SCLK CLKR0 CS REF AIN GND 5V DSP to Single TLC3545 0.1 µF REF 0.1 µF 10 kΩ 10 kΩ FSX0 CS DR0 SD0 DSP SCLK CLKX0 CLKR0 VDD REF TLC3545 AIN(+) AIN(−) GND DSP to Multiple TLC3541s XF0 FSX0 DR0 DSP CLKX0 CLKR0 XF1 EXT REF INPUT 5V REF 0.1 µF 5V 0.1 µF 0.1 µF 10 kΩ REF AIN 10 kΩ 10 kΩ 10 kΩ VDD CS CS TLC3541 #1 FS FS SDO SDO GND SCLK SCLK VDD TLC3541 #2 REF AIN GND Figure 23. Typical ADC Interface to a TMS320 DSP www.ti.com 17 PACKAGE OPTION ADDENDUM www.ti.com 6-May-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TLC3541ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3541I Samples TLC3541IDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3541I Samples TLC3541IDGK ACTIVE VSSOP DGK 8 80 RoHS & Green Call TI | NIPDAUAG Level-1-260C-UNLIM -40 to 85 AMG Samples TLC3541IDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green Call TI | NIPDAUAG Level-1-260C-UNLIM -40 to 85 AMG Samples TLC3541IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3541I Samples TLC3541IDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3541I Samples TLC3545ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3545I Samples TLC3545IDGK ACTIVE VSSOP DGK 8 80 RoHS & Green Call TI | NIPDAUAG Level-1-260C-UNLIM -40 to 85 AMM Samples TLC3545IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3545I Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of