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TLC3548IPWG4

TLC3548IPWG4

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    TSSOP24

  • 描述:

    14 Bit Analog to Digital Converter 4, 8 Input 1 SAR 24-TSSOP

  • 数据手册
  • 价格&库存
TLC3548IPWG4 数据手册
TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 D 14-Bit Resolution D Maximum Throughput 200 KSPS D Analog Input Range 0-V to Reference D D D D D D D D D D D D D Voltage Multiple Analog Inputs: – 8 Channels for TLC3548 – 4 Channels for TLC3544 Pseudodifferential Analog Inputs SPI/DSP-Compatible Serial Interfaces With SCLK up to 25 MHz Single 5-V Analog Supply; 3-/5-V Digital Supply Low Power: – 4 mA (Internal Reference: 1.8 mA) for Normal Operation – 20 µA in Autopower-Down Built-In 4-V Reference, Conversion Clock and 8x FIFO Hardware-Controlled and Programmable Sampling Period Programmable Autochannel Sweep and Repeat Hardware Default Configuration INL: ±1 LSB Max DNL: ±1 LSB Max SINAD: 80.8 dB THD: –95 dB TLC3548 DW OR PW PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 SCLK FS SDI EOC/INT SDO DGND DVDD CS A0 A1 A2 A3 24 23 22 21 20 19 18 17 16 15 14 13 CSTART AVDD AGND BGAP REFM REFP AGND AVDD A7 A6 A5 A4 TLC3544 DW OR PW PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 SCLK FS SDI EOC/INT SDO DGND DVDD CS A0 A1 20 19 18 17 16 15 14 13 12 11 CSTART AVDD AGND BGAP REFM REFP AGND AVDD A3 A2 description The TLC3544 and TLC3548 are a family of 14-bit resolution high-performance, low-power, CMOS analog-to-digital converters (ADC). All devices operate from a single 5-V analog power supply and 3-V to 5-V digital supply. The serial interface consists of four digital inputs [chip select (CS), frame sync (FS), serial input-output clock (SCLK), serial data input (SDI)], and a 3-state serial data output (SDO). CS (works as SS, slave select), SDI, SDO, and SCLK form an SPI interface. FS, SDI, SDO, and SCLK form a DSP interface. The frame sync signal (FS) indicates the start of a serial data frame being transferred. When multiple converters connect to one serial port of a DSP, CS works as the chip select to allow the host DSP to access the individual converter. CS can be tied to ground if only one converter is used. FS must be tied to DVDD if it is not used (such as in an SPI interface). When SDI is tied to DVDD, the device is set in hardware default mode after power-on, and no software configuration is required. In the simplest case, only three wires (SDO, SCLK, and CS or FS) are needed to interface with the host. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2000 – 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 description (continued) In addition to being a high-speed ADC with versatile control capability, these devices have an on-chip analog multiplexer (MUX) that can select any analog input or one of three self-test voltages. The sample-and-hold function is automatically started after the fourth SCLK (normal sampling) or can be controlled by CSTART to extend the sampling period (extended sampling). The normal sampling period can also be programmed as short sampling (12 SCLKs) or long sampling (44 SCLKs) to accommodate the faster SCLK operation popular among high-performance signal processors. The TLC3544 and TLC3548 are designed to operate with low power consumption. The power saving feature is further enhanced with software power-down/ autopower-down modes and programmable conversion speeds. The conversion clock (internal OSC) is built in. The converter can also use an external SCLK as the conversion clock for maximum flexibility. The TLC3544 and TLC3548 have a 4-V internal reference. The converters are specified with unipolar input range of 0-V to 5-V when a 5-V external reference is used. AVAILABLE OPTIONS PACKAGED DEVICES TA 20-TSSOP (PW) 20-SOIC (DW) 24-SOIC (DW) 24-TSSOP (PW) 0°C to 70°C TLC3544CPW TLC3544CDW TLC3548CDW TLC3548CPW – 40°C to 85°C TLC3544IPW TLC3544IDW TLC3548IDW TLC3548IPW functional block diagram DVDD REFP BGAP REFM X8 A0 A1 A2 A3 A4 A5 A6 A7 X4 A0 A1 A2 A3 X X X X AVDD 4-V Reference SAR ADC Analog MUX FIFO X8 OSC SDO Command Decode Conversion Clock CFR SDI CMR (4 MSBs) SCLK CS FS Control Logic 4-Bit Counter CSTART DGND AGND 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 EOC/INT TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 equivalent input circuit VDD MUX 1.1 kΩ Max Ain VDD Ron C(sample) = 30 pF Max Digital Input REFM Diode Turn on Voltage: 35 V Equivalent Digital Input Circuit Equivalent Analog Input Circuit Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION 9 10 11 12 13 14 15 16 I Analog signal inputs. Analog input signals applied to these terminals are internally multiplexed. The driving source impedance should be less than or equal to 1 kΩ for normal sampling. For larger source impedance, use the external hardware conversion start signal CSTART (the low time of CSTART controls the sampling period) or reduce the frequency of SCLK to increase the sampling time. 14, 18 18, 22 I Analog ground return for the internal circuitry. Unless otherwise noted, all analog voltage measurements are with respect to AGND. 13, 19 17, 23 I Analog supply voltage 17 21 I Internal bandgap compensation pin. Install compensation capacitors between BGAP and AGND. 0.1 µF for external reference; 10 µF in parallel with 0.1 µF for internal reference. 8 8 I Chip select. When CS is high, SDO is in high-impedance state, SDI is ignored, and SCLK is disabled to clock data but works as conversion clock source if programmed. The falling edge of CS input resets the internal 4-bit counter, enables SDI and SCLK, and removes SDO from high-impedance state. TLC3544 TLC3548 9 10 11 12 AGND AVDD BGAP A0 A1 A2 A3 A0 A1 A2 A3 A4 A5 A6 A7 CS If FS is high at CS falling edge, CS falling edge initiates the operation cycle. CS works as slave select (SS) to provide an SPI interface. If FS is low at CS falling edge, FS rising edge initiates the operation cycle. CS can be used as chip select to allow the host to access the individual converter. CSTART 20 24 I DGND 6 6 I External sampling trigger signal, which initiates the sampling from a selected analog input channel when the device works in extended sampling mode (asynchronous sampling). A high-to-low transition starts the sampling of the analog input signal. A low-to-high transition puts the S/H in hold mode and starts the conversion. The low time of the CSTART signal controls the sampling period. CSTART signal must be long enough for proper sampling. CSTART must stay high long enough after the low-to-high transition for the conversion to finish maturely. The activation of CSTART is independent of SCLK and the level of CS and FS. However, the first CSTART cannot be issued before the rising edge of the 11th SCLK. Tie this terminal to DVDD if not used. Digital ground return for the internal circuitry DVDD 7 7 I Digital supply voltage POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 Terminal Functions (Continued) TERMINAL NO. NAME EOC(INT) I/O TLC3544 TLC3548 4 4 O DESCRIPTION End of conversion (EOC) or interrupt to host processor (INT) EOC: used in conversion mode 00 only. EOC goes from high to low at the end of the sampling and remains low until the conversion is complete and data is ready. INT: Interrupt to the host processor. The falling edge of INT indicates data is ready for output. INT is cleared by the following CS↓, FS↑, or CSTART↓. FS 2 2 I REFM 16 20 I REFP 15 19 I External positive reference input. When an external reference is used, the range of maximum input voltage is determined by the difference between the voltage applied to this terminal and to the REFM terminal. Always install decoupling capacitors (10 µF in parallel with 0.1 µF) between REFP and REFM. SCLK 1 1 I Serial clock input from the host processor to clock in the input from SDI and clock out the output via SDO. It can also be used as the conversion clock source when the external conversion clock is selected (see Table 2). When CS is low, SCLK is enabled. When CS is high, SCLK is disabled for the data transfer, but can still work as the conversion clock source. SDI 3 3 I Serial data input. The first 4 MSBs, ID[15:12], are decoded as one 4-bit command. All trailing bits, except for the CONFIGURE WRITE command, are filled with zeros. The CONFIGURE WRITE command requires additional 12-bit data. The MSB of input data, ID[15], is latched at the first falling edge of SCLK following FS falling edge, if FS starts the operation, or latched at the falling edge of first SCLK following CS falling edge when CS initiates the operation. SDO 5 5 O Frame sync input from DSP. The rising edge of FS indicates the start of a serial data frame being transferred (coming into or being sent out of the device). If FS is low at the falling edge of CS, the rising edge of FS initiates the operation cycle, resets the internal 4-bit counter, and enables SDI, SDO, and SCLK. Tie this pin to DVDD if FS is not used to initiate the operation cycle. External low reference input. Connect REFM to AGND. The remaining input data (if any) is shifted in on the rising edge of SCLK and latched on the falling edge of SCLK. The input via SDI is ignored after the 4-bit counter counts to 16 (clock edges) or a low-to-high transition of CS, whichever happens first. Refer to the timing specification for the timing requirements. Tie SDI to DVDD if using hardware default mode (refer to device initialization). The 3-state serial output for the A/D conversion result. All data bits are shifted out through SDO. SDO is in the high-impedance state when CS is high. SDO is released after a CS falling edge. The output format is MSB (OD[15]) first. When FS initiates the operation, the MSB of output via SDO, OD[15], is valid before the first falling edge of SCLK following the falling edge of FS. When CS initiates the operation, the MSB, OD[15], is valid before the first falling edge of SCLK following the CS falling edge. The remaining data bits are shifted out on the rising edge of SCLK and are valid before the falling edge of SCLK. Refer to the timing specification for the details. In a select/conversion operation, the first 14 bits are the results from the previous conversion (data). In READ FIFO operation, the data is from FIFO. In both cases, the last two bits are don’t care. In a WRITE operation, the output from SDO is ignored. SDO goes into high-impedance state at the sixteenth falling edge of SCLK after the operation cycle is initiated. SDO is in high-impedance state during conversions in modes 01, 10, and 11. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, GND to AVDD, DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 V Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.2 V to AVDD +0.2 V Analog input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA MAX Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVDD + 0.3 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C Operating free-air industrial temperature range, TA: I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1.16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 general electrical characteristics over recommended operating free-air temperature range, single-ended input, normal long sampling, 200 KSPS, AVDD = 5 V, external reference (VREFP = 4 V, VREFM = 0 V) or internal reference, SCLK frequency = 25 MHz, fixed channel at CONV mode 00, analog input signal source resistance = 25 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT Digital Input VIH High level control input voltage High-level VIL Low-level Low level control in input ut voltage DVDD = 5 V 3.8 DVDD = 3 V DVDD = 5 V 2.1 V 0.8 DVDD = 3 V IIH IIL High-level input current 0.6 VI = DVDD VI = DGND Low-level input current 0.005 –2.5 Input capacitance 2.5 µA µA 0.005 20 V 25 pF Digital output VOH VOL IOZ High-level High level digital output, out ut, VOH at 30-pF load IO = –0.2 0 2 mA Low-level output, Low level digital out ut, VOL at 30-pF load 4.2 DVDD = 3 V 2.4 V DVDD = 5 V IO = 0.8 mA IO = 50 µA 0.4 DVDD = 3 V IO = 0.8 mA IO = 50 µA 0.4 VO = DVDD VO = DGND Off state out Off-state output ut current (high-impedance state) DVDD = 5 V 0.1 V 0.1 0.02 CS = DVDD 1 µA –1 –0.02 4.5 5 5.5 V 2.7 5 5.5 V 2.8 3.6 1.2 2 SCLK ON 175 240 SCLK OFF 20 SCLK ON 175 SCLK OFF 20 Power Supply AVDD DVDD Supply voltage ICC Power su ly supply current ICC(SW) ICC(Autodown) CC(A t d ) AVDD currentAICC DVDD currentDICC Conversion clock is internal OSC, EXT. 5.5 4.5 V, EXT reference, reference AVDD = 5 5 V to 4 5V CS = DGND For all digital inputs DVDD or DGND, CS = DVDD, S ft Software power-down d power supply lcurrentt DGND AVDD = 5.5 V For all digital inputs DVDD or Autopower-down power supply DGND, AVDD = 5 5.5 V, DGND 5V current External reference C suffix Operating temperat temperature re I suffix † All typical values are at TA = 25°C. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 mA 230 0 70 –40 85 µA µA °C TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 general electrical characteristics over recommended operating free-air temperature range, single-ended input, normal long sampling, 200 KSPS, AVDD = 5 V, external reference (VREFP = 4 V, VREFM = 0 V) or internal reference, SCLK frequency = 25 MHz, fixed channel at CONV mode 00, analog input signal source resistance = 25 Ω (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS Resolution MIN TYP† MAX 14 UNIT bits Analog Input Voltage range 0 Leakage current Reference 0.01 Capacitance V 0.05 µA 30 pF 4.07 V Reference Internal reference voltage 3.85 100 Internal reference source current 1.8 Internal reference startup time VREFP VREFM 4 Internal reference temperature coefficient 2.5 20 External positive reference voltage 3 External negative reference voltage 0 External reference input impedance External reference current ppm/°C No conversion (AVDD = 5 V, CS = DVDD, SCLK = DGND) 100 Normal long sampling (AVDD = 5 V, CS = DGND, SCLK = 25 MHz, External conversion clock) 8.3 No conversion (VREFP = AVDD = 5 V, VREFM = AGND, External reference, CS = DVDD) Normal long sampling (AVDD = 5 V, CS = DGND, SCLK = 25 MHz external conversion clock at VREF = 5 V) mA ms 5 AGND V V MΩ 12.5 kΩ 1.5 µA 0.4 0.6 mA Throughput Rate f Internal oscillation frequency DVDD = 2.7 V to 5.5 V t(conv) Conversion time Conversion clock is external source, SCLK = 25 MHz (see Note 1) Acquisition time Normal short sampling Throughput rate (see Note 2) Normal long sampling, fixed channel in mode 00 or 01 6.5 MHz Internal OSC, 6.5 MHz minute 2.785 µs 2.895 µs 1.2 200 KSPS DC Accuracy—Normal Long Sampling EL ED Integral linearity error See Note 3 Differential linearity error –1 ±0.5 1 LSB –1 ±0.5 1 LSB EO Zero offset error See Note 4 –3 ±0.6 3 LSB E(g+) Gain error See Note 4 0 5 12 LSB † All typical values are at TA = 25°C. NOTES: 1. Conversion time t(conv) = (18x4 / SCLK) + 15 ns. 2. This is for a fixed channel in conversion mode 00 or 01. When switching the channels, additional multiplexer setting time is required to overcome the memory effect of the charge redistribution DAC (refer to Figure 8). 3. Linear error is the maximum deviation from the best fit straight line through the A/D transfer characteristics. 4. Zero offset error is the difference between 0000000000000 and the converted output for zero input voltage; gain error is the difference between 11111111111111 and the converted output for full-scale input voltage. The full-scale input voltage is equal to the reference voltage being used. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 general electrical characteristics over recommended operating free-air temperature range, single-ended input, normal long sampling, 200 KSPS, AVDD = 5 V, external reference (VREFP = 4V, VREFM = 0 V) or internal reference, SCLK frequency = 25 MHz, fixed channel at CONV mode 00, analog input signal source resistance = 25 Ω (unless otherwise noted) (continued) PARAMETER DC Accuracy—Normal Short Sampling EL ED Integral linearity error TEST CONDITIONS MIN SINAD Signal to noise ratio + distortion Signal-to-noise THD Total harmonic distortion SFDR Spurious free dynamic range ENOB Effective number of bits SNR Signal to noise ratio Signal-to-noise Channel-to-channel isolation (see Notes 2 and 5) Analog input bandwidth MAX ±0.8 See Note 3 UNIT LSB ±0.6 Differential linearity error EO Zero offset error E(g+) Gain error AC Accuracy—Normal Long Sampling TYP† LSB See Note 4 –3 ±0.6 3 LSB See Note 4 0 5 12 LSB 78.6 80.8 fi = 20 kHz fi = 100 kHz fi = 20 kHz dB 77.6 –95 –88 fi = 100 kHz fi = 20 kHz 90 97 89 fi = 100 kHz fi = 20 kHz 12.8 13.1 12.6 fi = 100 kHz fi = 20 kHz 79 81 78 fi = 100 kHz Fixed channel in conversion mode 00, fi = 35 kHz 100 Full power bandwidth, –1 dB 2 Full power bandwidth, –3 dB 2.5 –90 dB dB Bits dB dB MHz AC Accuracy—Normal Short Sampling SINAD Signal to noise ratio + distortion Signal-to-noise THD Total harmonic distortion SNR Signal to noise ratio Signal-to-noise ENOB Effective number of bits SFDR Spurious free dynamic range fi = 20 kHz fi = 100 kHz 78.9 fi = 20 kHz fi = 100 kHz fi = 20 kHz –95 fi = 100 kHz fi = 20 kHz 78 77.6 –88 79 12.8 fi = 100 kHz fi = 20 kHz 12.6 fi = 100 kHz 89 97 dB dB dB Bits dB Channel-to-channel isolation (see Notes 2 and 5) Fixed channel in conversion mode 00, fi = 35 kHz 100 dB Analog input bandwidth Full power bandwidth, –1 dB Full power bandwidth, –3 dB 2 2.5 MHz † All typical values are at TA = 25°C. NOTES: 2. This is for a fixed channel in conversion mode 00 or 01. When switching the channels, additional multiplexer setting time is required to overcome the memory effect of the charge redistribution DAC (refer to Figure 8). 3. Linear error is the maximum deviation from the best fit straight line through the A/D transfer characteristics. 4. Zero offset error is the difference between 0000000000000 and the converted output for zero input voltage; gain error is the difference between 11111111111111 and the converted output for full-scale input voltage. The full-scale input voltage is equal to the reference voltage being used. 5. It is measured by applying a full-scale of 35 kHz signal to other channels and determining how much the signal is attenuated in the channel of interest. The converter samples this examined channel continuously. The channel-to-channel isolation is degraded if the converter samples different channels alternately (refer to Figure 8). 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 timing requirements over recommended operating free-air temperature range, AVDD = 5 V, = 5 V, VREFP = 5 V, VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted) DVDD SCLK, SDI, SDO, EOC and INT PARAMETERS MIN DVDD = 2.7 V DVDD = 5 V TYP MAX 100 40† UNIT tc(1) (1) Cycle time of SCLK at 25-pF 25 pF load tw(1) Pulse width, SCLK high time at 25-pF load tr(1) Rise time for INT, INT EOC at 10-pF 10 pF load tf(1) Fall time for INT, INT EOC at 10-pF 10 pF load tsu(1) Setup time, new SDI valid (reaches 90% final level) before falling edge of SCLK, at 25-pF load 6 – ns th(1) Hold time, old SDI hold (reaches 10% of old data level) after falling edge of SCLK, at 25-pF load 0 – ns Delay time, new SDO valid (reaches 90% of final level) after SCLK rising edge, at 10-pF load 0 td(1) 0 10 23‡ ns 0 – ns 0 6 ns t(conv) t(conv) + 6 µs th(2) 40% DVDD = 5 V DVDD = 2.7 V Delay time, delay from sixteenth SCLK falling edge to EOC falling edge, normal sampling, at 10-pF load td(3) Delay time, delay from the sixteenth falling edge of SCLK to INT falling edge, at 10-pF load [see the (‡) double dagger note and Note 6] tc(1) 6 ns 6 DVDD = 2.7 V td(2) 60% 10 DVDD = 5 V DVDD= 5 V DVDD = 2.7 V Hold time, old SDO hold (reaches 10% of old data level) after SCLK rising edge, at 10-pF load ns 10 ns † The minimum pulse width of SCLK high is 12.5 ns. The minimum pulse width of SCLK low is 12.5 ns. ‡ Specified by design NOTE 6: For normal short sampling, td(3) is the delay from 16th falling edge of SCLK to INT falling edge. For normal long sampling, td(3) is the delay from 48th falling edge of SCLK to the falling edge of INT. Conversion time, t(conv) is equal to 18 × OSC + 15 ns when using internal OSC as conversion clock, or 72 × tc(1) + 15 ns when external SCLK is conversion clock source. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 VIH 90% 50% 10% CS VIL tc(1) tw(1) 1 SCLK 16 th(1) tsu(1) SDI Don’t Care ID15 ID1 Don’t Care ID0 td(1) th(2) SDO Hi-Z OD15 OD1 Hi-Z OD0 td(2) See Note A tr(1) EOC tf(1) OR td(3) See Note B INT tf(1) tr(1) NOTES: A. For normal long sampling, td(2) is the delay time of EOC low after the falling edge of 48th SCLK. B. For normal long sampling, td(3) is the delay time of INT low after the falling edge of 48th SCLK. – – – – The dotted line means signal may or may not exist, depending on application. It must be ignored. Normal sampling mode, CS initiates the conversion, FS must be tied to high. When CS is high, SDO is in Hi-Z; all inputs (FS, SCLK, SDI) are inactive and are ignored. Figure 1. Critical Timing for SCLK, SDI, SDO, EOC and INT 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 timing requirements over recommended operating free-air temperature range, AVDD = 5 V, DVDD = 5 V, VREFP = 5 V, VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted) (continued) CS trigger PARAMETERS MIN TYP MAX tsu(2) td(4) Setup time, CS falling edge before SCLK rising edge, at 25-pF load Delay time, delay time from 16th SCLK falling edge to CS rising edge, at 25-pF load ‡ 5 ns tw(2) Pulse width, CS high time at 25-pF load 1 tc(1) td(5) Delay time, delay from CS falling edge to MSB of SDO valid (reaches 90% final level), at 10-pF load td(6) Delay time, delay from CS rising edge to SDO 3-state, at 10-pF load td(7) 12 UNIT Delay time, time delay from CS falling edge to INT rising edge, edge at 10 10-pF pF load DVDD = 5 V DVDD = 2.7 V ns 0 0 12 30† ns 0 6 ns DVDD = 5 V 0 DVDD = 2.7 V 0 6 16† ns † Specified by design ‡ For normal short sampling, td(4) is the delay time from 16th SCLK falling edge to CS rising edge. For normal long sampling, td(4) is the delay time from 48th SCLK falling edge to CS rising edge. VIH VIL CS tsu(2) SCLK SDI SDO td(4) 1 Don’t Care Hi-Z tw(2) 16 ID1 ID0 Don’t Care OD15 OD1 OD0 Hi-Z ID15 Don’t Care td(6) td(5) OD15 OD7 Hi-Z EOC OR td(7) INT NOTE A: – – – – The dotted line means signal may or may not exist, depending on application. It must be ignored. Normal sampling mode, CS initiates the conversion, FS must be tied to high. When CS is high, SDO is in Hi-Z, all inputs (FS, SCLK, SDI) are inactive and are ignored. Parts with date code earlier than 13XXXXX have these discrepancies: (Date code is a 7 digit code next to the TI where the first digit indicates the year and the second digit is the month of production. 13, in this case, is 2001 and the month of March.) FS is not ignored even if the device is in microcontroller mode (CS triggered). FS must be tied to DVDD. Figure 2. Critical Timing for CS Trigger POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 timing requirements over recommended operating free-air temperature range, AVDD = 5 V, DVDD = 5 V, VREFP = 5 V, VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted) (continued) FS trigger PARAMETERS MIN td(8) tsu(3) Delay time, delay from CS falling edge to FS rising edge, at 25-pF load tw(3) Pulse width, FS high at 25-pF load td(9) Delay time, delay from FS rising edge to MSB of SDO valid (reaches 90% final level) at 10-pF load td(10) Delay time, delay from FS rising edge to next FS rising edge at 25-pF load td(11) Delay time, delay from FS rising edge to INT rising edge at 10-pF load TYP MAX tc(1) 0.5×tc(1)+5 1.25×tc(1) 26† 0.5 Setup time, FS rising edge before SCLK falling edge, at 25-pF load 0.25×tc(1) 0.75×tc(1) DVDD = 5 V DVDD = 2.7 V 30† Required sampling time + conversion time DVDD = 5 V UNIT tc(1) ns ns ns µs 6† 16† 0 DVDD = 2.7 V ns † Specified by design VIH VIL td(10) CS td(8) tw(3) FS tsu(3) SCLK SDI Don’t Care 16 1 ID15 ID1 ID0 Don’t Care ID15 Don’t Care td(9) SDO Hi-Z OD15 OD1 OD0 Hi-Z OD15 Don’t Care VOH EOC OR td(11) VOH INT NOTE A: – – – – The dotted line means signal may or may not exist, depending on application. It must be ignored. Normal sampling mode, FS initiates the conversion, CS can be tied to low. When CS is high, SDO is in Hi-Z, all inputs (FS, SCLK, SDI) are inactive and are ignored. Parts with date code earlier than 13XXXXX have these discrepancies: (Date code is a 7 digit code next to the TI where the first digit indicates the year and the second digit is the month of production. 13, in this case, is 2001 and the month of March.) SDO MSB (OD[15]) comes out from the falling edge of CS instead of FS rising edge in DSP mode (FS triggered). Figure 3. Critical Timing for FS Trigger 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 timing requirements over recommended operating free-air temperature range, AVDD = 5 V, DVDD = 5 V, VREFP = 5 V, VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted) (continued) CSTART trigger PARAMETERS MIN TYP MAX UNIT 0 15 21 ns td(12) Delay time, delay from CSTART rising edge to EOC falling edge, at 10-pF load tw(4) Pulse width CSTART low time: tW(L)(CSTART), at 25-pF load t(sample – ref)+0.4 Note 7 µs td(13) Delay time, delay from CSTART rising edge to CSTART falling edge, at 25-pF load t(conv) +15 Notes 7 and 8 ns td(14) Delay time, delay from CSTART rising edge to INT falling edge, at 10-pF load t(conv) +15 Notes 7 and 8 td(15) Delay time, delay from CSTART falling edge to INT rising edge, at 10-pF load 0 t(conv)+21 ns 6 µs NOTES: 7. The pulse width of CSTART must be not less than the required sampling time. The delay from CSTART rising edge to following CSTART falling edge must not be less than the required conversion time. The delay from CSTART rising edge to the INT falling edge is equal to the conversion time. 8. The maximum rate of SCLK is 25 MHz for normal long sampling and 10 MHz for normal short sampling. tw(4) td(13) CSTART t(conv) td(12) EOC td(15) OR td(14) INT Extended Sampling Figure 4. Critical Timing for Extended Sampling (CSTART Trigger) detailed description converter The converters are a successive-approximation ADC utilizing a charge redistribution DAC. Figure 5 shows a simplified block diagram of the ADC. The sampling capacitor acquires the signal on Ain during the sampling period. When the conversion process starts, the control logic directs the charge redistribution DAC to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator into a balanced condition. When balanced, the conversion is complete and the ADC output code is generated. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 detailed description (continued) Charge Redistribution DAC _ Ain + Control Logic ADC Code REFM Figure 5. Simplified Block Diagram of the Successive-Approximation System analog input range and internal test voltages TLC3548 has eight analog inputs (TLC3544 has four) and three test voltages. The inputs are selected by the analog multiplexer according to the command entered (see Table 1). The input multiplexer is a breakbefore-make type to reduce input-to-input noise injection resulting from channel switching. The TLC3544 and TLC3548 are specified for a unipolar input range of 0-V to 4-V when the internal reference is selected, and 0-V to 5-V when an external 5-V reference is used. analog input mode Two input signal modes can be selected: single-ended input and pseudodifferential input. Charge Redistribution DAC S1 Ain(+) _ Ain(–) + REFM Control Logic ADC Code When sampling, S1 is closed and S2 connects to Ain(–). During conversion, S1 is open and S2 connects to REFM. Figure 6. Simplified Pseudodifferential Input Circuit Pseudodifferential input refers to the negative input, Ain(–); its voltage is limited in magnitude to ±0.2 V. The input frequency limit of Ain(–) is the same as the positive input Ain(+). This mode is normally used for ground noise rejection or dc bias offset. When pseudodifferential mode is selected, only two analog input channel pairs are available for the TLC3544 and four channel pairs for the TLC3548, because half the inputs are used as the negative input (see Figure 7). 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 analog input mode (continued) Single Ended X8† X4‡ A0 A0 A1 A1 A2 A2 A3 A3 X A4 X A5 X A6 X A7 Analog MUX Pseudodifferential SAR ADC X8† A0(+) A1(–) A2(+) A3(–) A4(+) A5(–) A6(+) A7(–) Pair A Pair B X4‡ A0(+) Pair A A1(–) A2(+) Pair B A3(–) Pair C Analog MUX SAR ADC Pair D † TLC3548 ‡ TLC3544 Figure 7. Pin Assignment of Single-Ended Input vs Pseudodifferential Input reference voltage There is a built-in 4-V reference. If the internal reference is used, REFP is internally set to 4-V and REFM is set to 0-V. The external reference can be applied to the reference-input pins (REFP and REFM) if programmed (see Table 2). The REFM pin should connect to analog ground. REFP can be 3-V to 5-V. Install decoupling capacitors (10 µF in parallel with 0.1 µF) between REFP and REFM. Install compensation capacitors (10 µF in parallel with 0.1 µF for internal reference, 0.1 µF only for external reference) between BGAP and AGND. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 detailed description (continued) 2s Complement BTC 01111111111111 Binary USB 11111111111111 01111111111110 11111111111110 16383 01111111111101 11111111111101 16382 16381 00000000000001 10000000000001 8193 00000000000000 10000000000000 8192 11111111111111 01111111111111 8191 10000000000010 00000000000010 2 10000000000001 00000000000001 1 10000000000000 00000000000000 0 Step Digital Output Code ideal conversion characteristics VREFP = VFS = 4 V VREFM = VZS = 0 V 1.999878 V 122 µV 2.000122 V VMS = (VFS + VZS)/2 = 2 V 244 µV VFS – 1 LSB = 3.999756 V 3.999512 V 488 µV 1 LSB = 244 µV Unipolar Analog Input Voltage data format INPUT DATA FORMAT (BINARY) OUTPUT DATA FORMAT READ CONVERSION/FIFO MSB LSB MSB LSB ID[15:12] ID[11:0] OD[15:2] OD[1:0] Command Configuration data field or filled with zeros Conversion result Don’t Care 14-BIT Unipolar Straight Binary Output: (USB) Zero-scale code = VZS = 0000h, Vcode = VREFM Mid-scale code = VMS = 2000h, Vcode = VREFP/2 Full-scale code = VFS = 3FFFh, Vcode = VREFT – 1 LSB UnIpolar Input, Binary 2’s Complement Output: (BTC) Zero-scale code = VZS = 2000 h, Vcode = VREFM Mid-scale code = VMS = 0000h, Vcode = (VREFP – VREFM)/2 Full-scale code = VFS = 1FFFh, Vcode = VREFP – 1 LSB 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 detailed description (continued) operation description The converter samples the selected analog input signal, then converts the sample into digital output, according to the selected output format. The converter has four digital input pins (SDI, SCLK, CS, and FS) and one digital output pin (SDO) to communicate with the host device. SDI is a serial data input pin, SDO is a serial data output pin, and SCLK is a serial clock from the host device. This clock is used to clock the serial data transfer. It can also be used as the conversion clock source (see Table 2). CS and FS are used to start the operation. The converter has a CSTART pin for an external hardware sampling and conversion trigger, and an INT/EOC pin for interrupt purposes. device initialization After power on, the status of EOC/INT is initially high, and the input data register is set to all zeros. The device must be initialized before starting the conversion. The initialization procedure depends on the working mode. The first conversion result is ignored after power on. Hardware Default Mode: Nonprogrammed Mode, Default. After power on, two consecutive active cycles initiated by CS or FS put the device into hardware default mode if SDI is tied to DVDD. Each of these cycles must last 16 SCLKs at least. These cycles initialize the converter and load the CFR register with 800h (external reference, unipolar straight binary output code, normal long sampling, internal OSC, single-ended input, one-shot conversion mode, and EOC/INT pin as INT). No additional software configuration is required. Software Programmed Mode: Programmed. When the converter has to be configured, the host must write A000h into the converter first after power on, then perform the WRITE CFR operation to configure the device. start of operation cycle Each operation consists of several actions that the converter takes according to the command from the host. The operation cycle includes three periods: command period, sampling period, and conversion period. In the command period, the device decodes the command from the host. In the sampling period, the device samples the selected analog signal according to the command. In the conversion period, the sample of the analog signal is converted to digital format. The operation cycle starts from the command period, which is followed by one or several sampling and conversion periods (depending on the setting) and finishes at the end of the last conversion period. The operation cycle is initiated by the falling edge of CS or the rising edge of FS. CS Initiates The Operation: If FS is high at the falling edge of CS, the falling edge of CS initiates the operation. When CS is high, SDO is in the high-impedance state, the signals on SDI, and SDO are ignored, and SCLK is disabled to clock the serial data. The falling edge of CS resets the internal 4-bit counter and enables SDO, SDI, and SCLK. The MSB of the input data via SDI, ID[15], is latched at the first falling edge of SCLK following the falling edge of CS. The MSB of output data from SDO, OD[15], is valid before this SCLK falling edge. This mode works as an SPI interface when CS is used as the slave select (SS). It also can be used as a normal DSP interface if CS connects to the frame sync output of the host DSP. FS must be tied high in this mode. FS Initiates The Operation: If FS is low at the falling edge of CS, the rising edge of FS initiates the operation, resets the internal 4-bit counter, and enables SDI, SDO, and SCLK. The ID[15] is latched at the first falling edge of SCLK following the falling edge of FS. OD[15] is valid before this falling edge of SCLK. This mode is used to interface the converter with a serial port of the host DSP. The FS of the device is connected to the frame sync of the host DSP. When several devices are connected to one DSP serial port, CS is used as chip select to allow the host DSP to access each device individually. If only one converter is used, CS can be tied low. After the initiation, the remaining SDI data bits (if any) are shifted in and the remaining bits of SDO (if any) are shifted out at the rising edge of SCLK. The input data are latched at the falling edge of SCLK, and the output data are valid before this falling edge of SCLK. After the 4-bit counter reaches 16, the SDO goes to a high-impedance state. The output data from SDO is the previous conversion result in one shot conversion mode, or the contents in the top of the FIFO when the FIFO is used (refer to Figure 21). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 detailed description (continued) command period After the rising edge of FS (FS triggers the operation) or the falling edge of CS (CS triggers the operation), SDI, SDO, and SCLK are enabled. The first four SCLK clocks form the command period. The four MSBs of input data, ID[15:12], are shifted in and decoded. These bits represent one of the 4-bit commands from the host, which defines the required operation (see Table 1, Command Set). The four MSBs of output, OD[15:12], are also shifted out via SDO during this period. The commands are SELECT/CONVERSION, WRITE CFR, FIFO READ, SW POWER DOWN, and HARDWARE DEFAULT mode. The SELECT/CONVERSION command includes SELECT ANALOG INPUT and SELECT TEST commands. All cause a select/conversion operation. They select the analog signal being converted, and start the sampling/conversion process after the selection. WRITE CFR causes the configuration operation, which writes the device configuration information into the CFR register. FIFO READ reads the contents in the FIFO. SW POWER DOWN puts the device into software power-down mode to save power. Hardware default mode sets the device into the hardware default mode. After the command period, the remaining 12 bits of SDI are written into the CFR register to configure the device if the command is WRITE CFR. Otherwise, these bits are ignored. The configuration is retained in the autopower-down and software power-down state. If SCLK stops (while CS remains low) after the first eight bits are entered, the next eight bits can be entered after SCLK resumes. The data on SDI are ignored after the 4-bit counter counts to 16 (falling edge of SCLK) or the low-to-high transition of CS, whichever happens first. The remaining 12 bits of output data are shifted out from SDO if the command is SELECT/CONVERSION or FIFO READ. Otherwise, the data on SDO are ignored. In any case, SDO goes into a high-impedance state after the 4-bit counter counts to 16 (falling edge of SCLK) or the low-to-high transition of CS, whichever happens first. Table 1. Command Set (CMR) SDI Bit D[15:12] TLC3548 COMMAND TLC3544 COMMAND BINARY HEX 0000b 0h SELECT analog input channel 0 SELECT analog input channel 0 0001b 1h SELECT analog input channel 1 SELECT analog input channel 1 0010b 2h SELECT analog input channel 2 SELECT analog input channel 2 0011b 3h SELECT analog input channel 3 SELECT analog input channel 3 0100b 4h SELECT analog input channel 4 SELECT analog input channel 0 0101b 5h SELECT analog input channel 5 SELECT analog input channel 1 0110b 6h SELECT analog input channel 6 SELECT analog input channel 2 0111b 7h SELECT analog input channel 7 SELECT analog input channel 3 1000b 8h SW POWER DOWN 1001b 9h Reserved (test) 1010b Ah WRITE CFR, the last 12 bits of SDI are written into CFR. This command resets FIFO. 1011b Bh SELECT TEST, voltage = (REFP+REFM)/2 (see Notes 9 and 10) 1100b Ch SELECT TEST, voltage = REFM (see Note 11) 1101b Dh SELECT TEST, voltage = REFP (see Note 12) 1110b Eh FIFO READ, FIFO contents is shown on SDO; OD[15:2] = result, OD[1:0] = xx 1111b Fh Hardware default mode, CFR is loaded with 800h NOTES: 9. REFP is external reference if external reference is selected, or internal reference if internal reference is programmed. 10. The output code = mid-scale code + zero offset error + gain error. 11. The output code = zero scale code + zero offset error. 12. The output code = full-scale code + gain error. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 detailed description (continued) Table 2. Configuration Register (CFR) Bit Definition SDI BIT DEFINITION D11 Reference select: 0: Internal (4 V) 1: External D10 Conversion output code format select: 0: USB (unipolar straight binary) 1: Binary 2s complement D9 Sample period select for normal sampling 0: Long sampling (4X) 44 SCLKs Don’t care in extended sampling. 1: Short sampling (1X) 12 SCLKs D8 Conversion clock source select: 0: Conversion clock = Internal OSC 1: Conversion clock = SCLK/4 Input mode select: 0: Single-ended 1: Pseudodifferential. Pin configuration shown below. D7 Pin Configuration of TLC3548 Pin Configuration of TLC3544 Pin No. Single-ended Pseudodifferential polarity Pin No. Single-ended Pseudodifferential polarity 9 10 A0 A1 PLUS MINUS Pair A 9 10 A0 A1 PLUS MINUS Pair A 11 12 A2 A3 PLUS MINUS Pair B 11 12 A2 A3 PLUS MINUS Pair B 13 14 A4 A5 PLUS MINUS Pair C 15 16 A6 A7 PLUS MINUS Pair D D[6:5] Conversion mode select: 00: One shot mode 01: Repeat mode 10: Sweep mode 11: Repeat sweep mode D[4:3] [ ] Sweep auto sequence select (Note: These bits only take effect in conversion mode 10 and 11.) TLC3548 D2 D[1:0] TLC3544 Single ended(by ch) Pseudodifferential (by pair) Single ended (by ch) Pseudodifferential (by pair) 00: 0–1–2–3–4–5–6–7 01: 0–2–4–6–0–2–4–6 10: 0–0–2–2–4–4–6–6 11: 0–2–0–2–0–2–0–2 00: N/A 01: A–B–C–D–A–B–C–D 10: A–A–B–B–C–C–D–D 11: A–B–A–B–A–B–A–B 00: 0–1–2–3–0–1–2–3 01: 0–2–0–2–0–2–0–2 10: 0–0–1–1–2–2–3–3 11: 0–0–0–0–2–2–2–2 00: N/A 01: A–B–A–B–A–B–A–B 10: N/A 11: A–A–A–A–B–B–B–B EOC/INT pin function select: 0: Pin used as INT 1: Pin used as EOC ( for mode 00 only) FIFO trigger level (sweep sequence length). Don’t care in one shot mode. 00: Full (INT generated after FIFO level 7 filled) 01: 3/4 (INT generated after FIFO level 5 filled) 10: 1/2 (INT generated after FIFO level 3 filled) 11: 1/4 (INT generated after FIFO level 1 filled) sampling period The sampling period follows the command period. The selected signal is sampled during this time. The device has three different sampling modes: normal short mode, normal long mode, and extended mode. Normal Short Sampling Mode: Sampling time is controlled by SCLK. It takes 12 SCLK periods. At the end of sampling, the converter automatically starts the conversion period. After configuration, normal sampling, except FIFO READ and WRITE CFR commands, starts automatically after the fourth falling edge of SCLK that follows the falling edge of CS if CS triggers the operation, or follows the rising edge of FS if FS initiates the operation. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 sampling period (continued) Normal Long Sampling Mode: This mode is the same as normal short sampling, except that it lasts 44 SCLK periods. Extended Sampling Mode: The external trigger signal, CSTART, triggers sampling and conversion. SCLK is not used for sampling. SCLK is also not needed for conversion if the internal conversion clock is selected. The falling edge of CSTART begins the sampling of the selected analog input. The sampling continues while CSTART is low. The rising edge of CSTART ends the sampling and starts the conversion (with about 15 ns internal delay). The occurrence of CSTART is independent of the SCLK clock, CS, and FS. However, the first CSTART cannot occur before the rising edge of the 11th SCLK. In other words, the falling edge of the first CSTART can happen at or after the rising edge of the 11th SCLK, but not before. The device enters the extended sampling mode at the falling edge of CSTART and exits this mode once CSTART goes to high followed by two consecutive falling edges of CS or two consecutive rising edges of FS (such as one read data operation followed by a write CFR). The first CS or FS does not cause conversion. Extended mode is used when a fast SCLK is not suitable for sampling, or when an extended sampling period is needed to accommodate different input signal source impedance. conversion period The conversion period is the third portion of the operation cycle. It begins after the falling edge of the 16th SCLK for normal short sampling mode, or after the falling edge of the 48th SCLK for normal long sampling, or on the rising edge of CSTART (with 15 ns internal delay) for extended sampling mode. The conversion takes 18 conversion clocks plus 15 ns. The conversion clock source can be an internal oscillator, OSC, or an external clock, SCLK. The conversion clock is equal to the internal OSC if the internal clock is used, or equal to SCLK/4 when the external clock is programmed. To avoid premature termination of the conversion, enough time for the conversion must be allowed between consecutive triggers. EOC goes low at the beginning of the conversion period and goes high at the end of the conversion period. INT goes low at the end of this period. conversion mode Four different conversion modes (mode 00, 01, 10, 11) are available. The operation of each mode is slightly different, depending on how the converter samples and what host interface is used. Do not mix different types of triggers throughout the repeat or sweep operations. One Shot Mode (Mode 00): Each operation cycle performs one sampling and one conversion for the selected channel. The FIFO is not used. When EOC is selected, it is generated while the conversion period is in progress. Otherwise, INT is generated after the conversion is done. The result is output through the SDO pin during the next select/conversion operation. Repeat Mode (Mode 01): Each operation cycle performs multiple samplings and conversions for a fixed channel selected according to the 4-bit command. The results are stored in the FIFO. The number of samples to be taken is equal to the FIFO threshold programmed via D[1:0] in the CFR register. Once the threshold is reached, INT is generated, and the operation ends. If the FIFO is not read after the conversions, the data are replaced in the next operation. The operation of this mode starts with the WRITE CFR command to set conversion mode 01, then the SELECT/CONVERSION command, followed by a number of samplings and conversions of the fixed channel (triggered by CS, FS, or CSTART) until the FIFO threshold is hit. If CS or FS triggers the sampling, the data on SDI must be any one of the SELECT CHANNEL commands. This data is a dummy code for setting the converter in the conversion state. It does not change the existing channel selection set at the start of the operation until the FIFO is full. After the operation finishes, the host can read the FIFO, then reselect the channel and start the next REPEAT operation again; or immediately reselect the channel and start the next REPEAT operation (by issuing CS, FS, or CSTAR), or reconfigure the converter and then start a new operation according to the new setting. If CSTART triggers the sampling, the host can also immediately start the next REPEAT (on the current channel) after the FIFO is full. Besides, if FS initiates the operation and CSTART triggers the sampling and conversions, CS must not toggle during the conversion. This mode allows the host to set up the converter, continue monitoring a fixed input, and to get a set of samples as needed. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 conversion mode (continued) Sweep Mode (Mode 10): During each operation, all of the channels listed in the sweep sequence (D[4:3] of the CFR register) are sampled and converted at one time according to the programmed sequence. The results are stored in the FIFO. When the FIFO threshold is reached, an interrupt (INT) is generated, and the operation ends. If the FIFO threshold is reached before all of the listed channels are visited, the remaining channels are ignored. This allows the host to change the sweep sequence length. The mode 10 operation starts with the WRITE CFR command to set the sweep sequence. The following triggers (CS, FS, or CSTART, depending on the interface) start the samplings and conversions of the listed channels in sequence until the FIFO threshold is hit. If CS or FS starts the sampling, the SDI data must be any one of the SELECT commands to set the converter in the conversion state. However, this command is a dummy code. It does not change the existing conversion sequence. After the FIFO is full, the converter waits for the FIFO READ. It does nothing before the FIFO READ or the WRITE CFR command is issued. The host must read the FIFO completely or write the CFR. If CSTART triggers the samplings, the host must issue an extra SELECT/CONVERSION command (select any channel) via CS or FS after the FIFO READ or WRITE CFR. This extra period is named the arm period and is used to set the converter into the conversion state, but does not affect the existing conversion sequence. Besides, if FS initiates the operation and CSTART triggers the sampling and conversions, CS must not toggle during the conversion. Repeat Sweep Mode (Mode 11): This mode works in the same way as mode 10, except that it is not necessary to read the FIFO before the next operation after the FIFO threshold is hit. The next SWEEP can repeat immediately, but the contents in the FIFO are replaced by the new results. The host can read the FIFO completely, then issue the next SWEEP or repeat the SWEEP immediately (with the existing sweep sequence) by issuing sampling/conversion triggers (CS, FS or CSTART) or change the device setting with the WRITE CFR. The memory effect of charge redistribution DAC exists when the mux switches from one channel to another. This degrades the channel-to-channel isolation if the channel changes after each conversion. For example, in mode 10 and 11, the isolation is about 70 dB for the sweep sequence 0-1-2-3-4 (refer to Figure 8). The memory effect can be reduced by increasing the sampling time or using the sweep sequence 0-0-2-2-4-4-6-6 and ignoring the first sample of each channel. Figure 8 shows the typical isolation vs throughput rate when applying a sine signal (35 kHz, 3.5 Vp-p) on CH0 and dc on CH1 converting both channels alternately and measuring the attenuation of the sine wave in CH1. CHANNEL-TO-CHANNEL ISOLATION vs THROUGHPUT Channel-to-Channel Isoltaion – dB 100 90 80 70 60 0 50 100 150 200 Throughput – KSPS Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 operation cycle timing CS Initiates Operation 12 SCLKs for Short 44 SCLKs for Long 4 SCLKs t(setup)† SDI 18 OSC for Internal OSC† 72 SCLK for External Clock 15 ns t(convert) t(overhead) t(sample) 4-bit Command 12-bit CFR Data (Optional) SDO 14-bit Data (Previous Conversion) 2-bit Don’t Care Active CS (FS Is Tied to High) CSTAR (For Extended Sampling) occurs at or after the rising edge of eleventh SCLK t–CSL to FSL t(delay)† SDI 12 SCLKs for Short 44 SCLKs for Long 4 SCLKs t(setup)† 18 OSC for Internal OSC 72 SCLK for External Clock 15 nS t(convert) t(overhead) t(sample) 4-bit Command 12-bit CFR Data (Optional) SDO 14-bit Data (Previous Conversion) 2-bit Don’t Care FS Initiates Operation Active CS (CS Can Be Tied to Low) Active FS † Non JEDEC terms used. CSTAR (For Extended Sampling) occurs at or after the rising edge of eleventh SCLK After the operation is finished, the host has several choices. Table 3 summarizes operation options. 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 operation cycle timing (continued) Table 3. Operation Options CONVERSION IS INITIATED BY MODE CS FS CSTART 00 1. Issue new Select/Read operation to read data and start new conversion. 2. Reconfigure the device. 1. Issue new Select/Read operation to read data and start new conversion. 2. Reconfigure the device. 1. Issue new CSTART to start next conversion; old data lost. 2. Issue new Select/Read operation to read data—Issue new CSTART to start new conversion. 3. Reconfigure the device. 01 1. Read FIFO—Select Channel—Start new conversion. Channel must be selected after FIFO READ. 2. Select Channel—Start new conversion (old data lost) 3. Configure device again. 1. Read FIFO—Select Channel—Start new conversion. Channel must be selected after FIFO READ. 2. Select Channel—Start new conversion (old data lost) 3. Configure device again. 1. Read FIFO—Select channel—Start new conversion. Channel must be selected after FIFO READ. 2. Start new conversion (old data lost) with existing setting. 3. Configure device again. 10 1. Read FIFO—Start new conversion with existing setting. 2. Configure device—New conversion (old data lost) 1. Read FIFO—Start new conversion with existing setting. 2. Configure device—New conversion (old data lost) 1. Read FIFO—Arm Period—Start new conversion with existing setting 2. Configure device—Arm Period—New conversion (old data lost) 11 1. Read FIFO—Start new conversion with existing setting. 2. Start new conversion with the existing setting. 3. Configure device—Start new conversion with new setting. 1. Read FIFO—Start new conversion with existing setting 2. Start new conversion with the existing setting. 3. Configure Device—Start new conversion with new setting. 1. Read FIFO—Arm Period—Start new Conversion with existing setting 2. Start new conversion with existing setting. (old data lost) 3. Configure device—Arm Period—New conversion with new setting. operation timing diagrams The FIFO read and write CFR are nonconversion operations. The conversion operation performs one of four types of conversion: mode 00, 01, 10, and 11 Write Cycle (WRITE CFR Command): Write cycle does not generate EOC or INT, nor does it carry out any conversion. 1 2 3 4 1D14 ID13 1D12 5 6 ID11 ID10 7 12 13 14 15 1 16 CS FS SDI OR INT EOC SDO ÌÌÌ ÌÌÌ ID15 ID9 ID4 ID3 ID2 ID1 ÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌ ID0 ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌ Note: ID15 Hi-Z Signal May Not Exist. ÌÌÌÌ ÌÌ Don’t Care Figure 9. Write Cycle, FS Initiates Operation POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 operation timing diagrams (continued) 1 2 3 4 5 6 12 7 13 14 15 16 CS ÌÌÌÌ ÌÌÌÌ ÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌ FS = High SDI ID15 1D14 ID13 1D12 ID11 ID10 ID9 ID4 ID3 ID2 ID1 ID0 INT OR 1 ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌ ÌÌÌ EOC SDO Note: Hi-Z Signal May Not Exist. Don’t Care ID15 ID14 ÌÌÌÌÌ ÌÌÌÌÌ Figure 10. Write Cycle, CS Initiates Operation, FS = 1 FIFO Read Operation: When the FIFO is used, the first command after INT is generated is assumed to be the FIFO read. The first FIFO content is sent out immediately before the command is decoded. If this command is not a FIFO read, the output is terminated. Using more layers of the FIFO reduces the time taken to read multiple conversion results, because the read cycle does not generate an EOC or INT, nor does it make a data conversion. Once the FIFO is read, the entire contents in the FIFO must be read out. Otherwise, the remaining data is lost. 1 2 3 4 1D14 ID13 1D12 5 6 7 12 13 14 15 16 1 SCLK CS ÌÌÌ ÌÌÌ FS = High SDI INT ID15 ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ID15 OR EOC SDO OD15 OD14 OD13 OD12 OD11 OD10 OD9 Notes: ÌÌ ÌÌ OD4 Signal May Not Exist. OD3 ÌÌÌÌÌ ÌÌÌÌÌ Hi-Z OD2 OD[15:2] is FIFO Contents. Don’t Care Figure 11. FIFO Read Cycle, CS Initiates Operation, FS = 1 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ID14 OD15 OD14 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 conversion operation 48 SCLKs for Long Sampling 16 SCLKs for Short Sampling 1 2 3 4 CS ÌÌÌ ÌÌ ÌÌÌ ÌÌ FS in High SDI Select Channel ID15 ID14 ID13 1D12 INT 5 6 7 12 13 14 15 1 16 ÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌ ÌÌÌÌÌÌÌÌ ID15 t(SAMPLE) EOC t(conv) Previous Conversion Result OR SDO OD15 OD14 OD13 OD12 ÌÌÌ ÌÌÌ OD11 OD10 OD9 OD4 OD3 OD2 The dotted line means signal may or may not exist. ÌÌÌÌ Hi-Z OD15 SDO goes to Hi-Z After 16th SCLK OD[15:2] is the result of previous conversion. Don’t Care Figure 12. Mode 00, CS Initiates Operation 48 SCLKs for Long Sampling 16 SCLKs for Short Sampling 1 2 3 4 5 6 7 12 13 14 15 1 16 SCLK CS ÌÌÌ ÌÌÌ FS SDI ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ Select Channel ID15 1D14 INT ID13 1D12 ID15 t(SAMPLE) OR t(conv) EOC Previous Conversion Result SDO OD15 ÌÌ ÌÌ ÌÌÌÌÌ SDO Goes Through Hi-Z After 16 SCLK OD14 OD13 OD12 OD11 OD10 OD9 OD4 The dotted line means signal may or may not exist. OD[15:2] is the result of previous conversion. OD3 OD2 Hi-Z OD15 Don’t Care Figure 13. Mode 00, FS Initiates Operation POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 conversion operation (continued) Select Channel 16 SCLK Select Channel 16 SCLK t(sample) CS Tied to Low CSTART Possible Signal FS t(convert) ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ** *** SDI ** INT EOC OR SDO ÌÌ ÌÌ ** Data Lost Previous Conversion Result Hi-Z Conversion Result Hi-Z Hi-Z Possible Signal Select Channel Don’t Care Figure 14. Mode 00, CSTART Triggers Sampling/Conversion, FS Initiates Select CS FS ÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌ ÌÌÌÌÌÌ ÌÌÌ ÌÌ ÌÌ Select CH1 SDI *** ** Select Any Channel ** Select CH2 * * Select Any Channel ** ** DATA1 of CH1 DATA2 of CH1 * * DATA1 of CH2 DATA2 of CH2 Hi-Z SDO 1/4 FIFO FULL 1/4 FIFO FULL INT *** ** * Don’t Care Possible Signal –– WRITE CFR –– Select Channel –– FIFO Read MODE 01, FS Activates Conversion, FIFO Threshold = 1/4 Full Read FIFO After Threshold Is Hit Figure 15. Mode 01, FS Initiates Operations CS FS CSTART ÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌ ÌÌ Select CH1 SDI *** Select CH2 ** * Hi-Z SDO INT * ** *** ** * MODE 01, FS Initiates Select Period, CSTART Activates Conversion, FIFO Threshold = 1/4 Full, Read FIFO After Threshold Is Hit Figure 16. Mode 01, CSTART Triggers Samplings/Conversions 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 * DATA1 of CH2 DATA2 of CH2 1/4 FIFO FULL 1/4 FIFO FULL Don’t Care Possible Signal –– WRITE CFR –– Select Channel –– FIFO Read * DATA1 of CH1 DATA2 of CH1 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 conversion operation (continued) Configure Conversion From CH0 Conversion From CH3 Conversion From CH0 Conversion From CH3 CS ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌ ÌÌ ÌÌ FS SDI ** *** ** ** ** * * * ** * ** ** ** * INT Hi-Z SDO CH0 1st Sweep CH1 ** * CH0 CH3 2nd Sweep Using Existing Configuration Don’t Care *** CH2 1st FIFO Read Command = Configure Write for Mode 10, FIFO Threshold = 1/2 Full, Sweep Sequence: 0–1–2–3 COMMAND = Select Any Channel COMMAND = Read FIFO 2nd FIFO Read Read FIFO After FIFO Threshold Is Hit Figure 17. Mode 10, FS Initiates Operations CS Tied to Low FS Configure Conversion From CH0 Conversion From CH2 Conversion From CH0 Conversion From CH2 ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌ ÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌ ÌÌÌ ÌÌ Ì ÌÌ CSTART SDI *** ** * * * * ** * INT Hi-Z SDO CH0 CH0 *** CH2 CH0 2nd Sweep Using Existing Configuration Don’t Care ** * CH2 1st Sweep 2nd FIFO Read 1st FIFO Read Read FIFO After FIFO Threshold Is Hit, FS Initiates Select Period Command = Configure Write for Mode 10, FIFO Threshold = 1/2 Full, Sweep Sequence: 0–0–2–2 COMMAND = Select Any Channel COMMAND = Read FIFO Figure 18. Mode 10, CSTART Initiates Operations Configure Conversion From CH0 Conversion From CH3 Conversion From CH0 Conversion From CH3 Conversion From CH0 CS START 2nd Round SWEEP CONVERSION, the DATA of the 1st Round Are Lost ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌ ÌÌ ÌÌ ÌÌ FS=High SDI *** ** ** ** ** ** ** ** ** INT SDO ÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌ * CH0 Don’t Care *** ** * * CH1 * * CH2 CH3 ** READ the DATA of 2nd Sweep From FIFO Command = Configure Write for Mode 11, FIFO Threshold = 1/2 Full, Sweep Sequence: 0–1–2–3 START 2nd Sweep conversion immediately (NO FIFO READ) after the 1st SWEEP completed. COMMAND = Select Any Channel COMMAND = Read FIFO Figure 19. Mode 11, CS Initiates Operations POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 conversion operation (continued) Configure Conversion From CH0 Conversion From CH2 Conversion From CH0 Conversion From CH2 CS FS CSTART Ì ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌ ÌÌÌ ÌÌ ÌÌ ÌÌ *** ** SDI INT 1st SWEEP SDO * * * * CH0 CH0 CH2 CH2 ** * REPEAT 1st FIFO Read Don’t Care *** ** * CH0 2nd FIFO Read Read FIFO After 1st SWEEP Completed Command = Configure Write for Mode 11, FIFO Threshold = 1/2 Full, Sweep Sequence: 0–0–2–2 COMMAND = Select Any Channel COMMAND = Read FIFO Possible Signal Figure 20. Mode 11, CSTART Triggers Samplings/Conversions conversion clock and conversion speed The conversion clock source can be the internal OSC, or the external clock SCLK. When the external clock is used, the conversion clock is equal to SCLK/4. It takes 18 conversion clocks plus 15 ns to finish the conversion. If the external clock is selected, the conversion time (not including sampling time) is 18X(4/fSCLK)+15 ns. Table 4 shows the maximum conversion rate (including sampling time) when the analog input source resistor is 1 kΩ. Table 4. Maximum Conversion Rate DEVICE TLC3544/48 ((Rs = 1000)) SAMPLING MODE CONVERSION CLK MAX SCLK (MHz) CONVERSION TIME (us) RATE (KSPS) Short (16 SCLK) External SCLK/4 10 8.815 113.4 207.7 Long (48 SCLK) External SCLK/4 25 4.815 Short (16 SCLK) Internal 6.5 MHz 10 4.385 228 Long (48 SCLK) Internal 6.5 MHz 25 4.705 212.5 FIFO operation Serial SOD ×8 FIFO ADC 7 6 FIFO Full 5 4 3 2 0 FIFO 1/2 Full FIFO 3/4 Full FIFO 1/4 Full FIFO Threshold Pointer Figure 21. FIFO Structure 28 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 FIFO operation (continued) The device has an 8-level FIFO that can be programmed for different thresholds. An interrupt is sent to the host after the preprogrammed threshold is reached. The FIFO is used to store conversion results in mode 01, 10, and 11, from either a fixed channel or a series of channels according to a preprogrammed sweep sequence. For example, an application may require eight measurements from channel 3. In this case, if the threshold is set to full, the FIFO is filled with 8 data conversions sequentially taken from channel 3. Another application may require data from channel 0, 2, 4, and 6 in that order. The threshold is set to 1/2 full and sweep sequence is selected as 0–2–4–6–0–2–4–6. An interrupt is sent to the host as soon as all four data conversions are in the FIFO. The FIFO is reset after a power on and a WRITE CFR operation. The contents of the FIFO are retained during autopower down and software power down. Powerdown: The device has two power-down modes. AutoPower-Down Mode: The device enters the autopower-down state at the end of a conversion. In autopower-down, the power consumption reduces to about 1.8 mA when an internal reference is selected. The built-in reference is still on to allow the device to resume quickly. The resumption is fast enough for use between cycles. An active CS, FS, or CSTART resumes the device from power-down state. The power current is 20 µA when an external reference is programmed and SCLK stops. Software Power-Down Mode: Writing 8000h to the device puts the device into the software power-down state, and the entire chip (including the built-in reference) is powered down. The power current is reduced to about 20 µA if SCLK stops. Deselect CS to save power once the device is in the software power-down mode. An active CS, FS, or CSTART restores the device. There is no time delay when an external reference is selected. However, if an internal reference is used, it takes about 20 ms to warm up. The configuration register is not affected by any of the power-down modes but the sweep operation sequence must be started over again. All FIFO contents are retained in both power-down modes. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 TYPICAL CHARACTERISTICS INL – Integral Nonlinearity – LSB INTEGRAL NONLINEARITY vs DIGITAL OUTPUT CODE 1.0 Internal Reference = 4 V AVDD = 5 V, TA = 25°C 0.5 0.0 –0.5 –1.0 0 2000 4000 6000 8000 10000 12000 14000 16000 12000 14000 16000 Digital Output Code Figure 22 DNL – Differential Nonlinearity – LSB DIFFERENTIAL NONLINEARITY vs DIGITAL OUTPUT CODE 1.0 Internal Reference = 4 V AVDD = 5 V, TA = 25°C 0.5 0.0 –0.5 –1.0 0 2000 4000 6000 8000 10000 Digital Output Code Figure 23 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 TYPICAL CHARACTERISTICS INL AND DNL vs FREE-AIR TEMPERATURE ZERO OFFSET AND GAIN ERROR (LSB) vs FREE-AIR TEMPERATURE 1.0 4 Internal Reference = 4 V AVDD = 5 V 2 Zero Offset and Gain Error – LSB 0.8 INL (LSB) 0.7 0.6 DNL (LSB) 0.5 Zero Offset (LSB) 0 –2 –4 –6 –8 Gain Error (LSB) –10 –12 External Reference = 4 V AVDD = 5 V –14 0.4 –65 –35 –5 25 55 –16 –65 85 –35 –5 25 55 TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C Figure 24 85 Figure 25 FFT OF SNR vs FREQUENCY 20 External Reference = 4 V AVDD = 5 V TA = 25°C 200 KSPS Input Signal: 20 kHz, 0 dB –20 FFT of SNR – dB INL and DNL – LSB 0.9 –60 –100 –140 –180 0 10 20 30 40 50 60 70 80 90 100 f – Frequency – kHz Figure 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 TYPICAL CHARACTERISTICS SINAD vs INPUT SIGNAL FREQUENCY ENOB vs INPUT SIGNAL FREQUENCY 90 14.0 External Reference = 4 V AVDD = 5 V TA = 25°C External Reference = 4 V AVDD = 5 V TA = 25°C 13.5 ENOB – Bits SINAD – dB 85 80 75 13.0 12.5 70 12.0 0 20000 20k 40000 40k 60000 60k 80000 80k 100000 100k 0 20000 20k f – Input Signal Frequency – Hz Figure 27 80000 80k 100000 100k SFDR vs INPUT SIGNAL FREQUENCY –80 105 External Reference = 4 V AVDD = 5 V TA = 25°C External Reference = 4 V AVDD = 5 V TA = 25°C –85 100 SFDR – dB THD – dB 60000 60k Figure 28 THD vs INPUT SIGNAL FREQUENCY –90 –95 95 90 –100 1 10 20 30 40 50 60 70 80 90 98 f – Input Signal Frequency – kHz 85 0 20000 20k 40000 40k 60000 60k Figure 30 POST OFFICE BOX 655303 80000 80k f – Input Signal Frequency – Hz Figure 29 32 40000 40k f – Input Signal Frequency – Hz • DALLAS, TEXAS 75265 100000 100k TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 TYPICAL CHARACTERISTICS SUPPLY CURRENT AT SOFTWARE POWER-DOWN vs FREE-AIR TEMPERATURE ICC – Supply Current at Software Power Down– µA SUPPLY CURRENT vs FREE-AIR TEMPERATURE 4.5 4.3 4.2 4.1 4.0 3.9 –65 –35 –5 25 55 85 30 Internal Reference = 4 V AVDD = 5 V SCLK = OFF All Digital Input = DGND or DVDD 25 20 15 10 5 0 –65 TA – Free-Air Temperature – °C –35 –5 25 55 85 TA – Free-Air Temperature – °C Figure 31 Figure 32 SUPPLY CURRENT AT AUTOPOWER-DOWN vs FREE-AIR TEMPERATURE 4.0 ICC – Supply Current at Autopower-Down – µA ICC – Supply Current – mA 4.4 External Reference = 4 V AVDD = 5 V CS = DGND Internal OSC 3.5 External Reference = 4 V AVDD = 5 V SCLK = OFF All Digital Input = DGND or DVDD 3.0 2.5 2.0 1.5 –65 –35 –5 25 55 85 TA – Free-Air Temperature – °C Figure 33 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 33 TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 APPLICATION INFORMATION interface with host Figure 34 shows examples of the interface between a single converter and a host DSP (TMS320C54x DSP) or microprocessor. The C54x is set as FWID = 1 (active pulse width = 1CLK), (R/X) DATDLY = 1 (1 bit data delay), CLK(X/R)P = 0 (transmit data are clocked out at rising edge of CLK, receive data are sampled on falling edge of CLK), and FS(X/R)P = 1 (FS is active high). If multiple converters connect to the same C54x, use CS as the chip select. The host microprocessor is set as the SPI master with CPOL = 0 (active high clock), and CPHA = 1 (transmit data is clock out at rising edge of CLK, receive data are sampled at falling edge of CLK). 16 bits (or more) per transfer is required. VDD VDD 10 kΩ 10 kΩ Converter TMS320C54X FSR CS FSX FS DX SDI 10 kΩ Host Microprocessor SS DR Converter CS FS Ain MOSI SDI MISO SDO SCK SCLK Ain SDO CLKR SCLK CLKX INT/EOC IRQ IRQ Single Converter Connects to DSP INT/EOC Converter Connects to Microprocessor Figure 34. Typical Interface to Host DSP and Microprocessor sampling time analysis Figure 35 shows the equivalent analog input circuit of the converter. During the sampling, the input capacitor, Ci, has to be charged to VC, (VC = Vs ± voltage of 1/4 LSB = Vs ± [Vs/65532] for 14 bit converter). t(s) = Rt × Ci × In (65532) where Rt = Rs+ri, t(s) = Sampling time Driving Source VS RS Data Converter VI ri VC CI VI = Input Voltage at AIN VS = External Driving Source Voltage RS = Source Resistance ri = Equivalent Resistor of Mux., 1.5 kΩ CI = Input Capacitance, 30 pF Max. VC = Capacitance Charging Voltage Figure 35. Equivalent Input Circuit Including the Driving Source TMS320C54x is a trademark of Texas Instruments. 34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TLC3544CDW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLC3544 Samples TLC3544CPW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLC3544 Samples TLC3544CPWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLC3544 Samples TLC3544IDW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TLC3544I Samples TLC3544IPW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 Y3544 Samples TLC3548CDW ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLC3548 Samples TLC3548CDWR ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLC3548 Samples TLC3548CPW ACTIVE TSSOP PW 24 60 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 TLC3548 Samples TLC3548CPWR ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 TLC3548 Samples TLC3548IDW ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TLC3548I Samples TLC3548IDWR ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TLC3548I Samples TLC3548IPW ACTIVE TSSOP PW 24 60 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 Y3548 Samples TLC3548IPWR ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 Y3548 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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