TLC3702
DUAL MICROPOWER LinCMOS™ VOLTAGE COMPARATORS
SLCS013E − NOVEMBER 1986 − REVISED MARCH 2012
D Push-Pull CMOS Output Drives Capacitive
D
D
Loads Without Pullup Resistor,
IO = ± 8 mA
Very Low Power . . . 100 μW Typ at 5 V
Fast Response Time . . . tPLH = 2.7 μs Typ
With 5-mV Overdrive
Single-Supply Operation . . . 3 V to 16 V
TLC3702M . . . 4 V to 16 V
On-Chip ESD Protection
1OUT
1IN −
1IN +
GND
Texas Instruments LinCMOS™ process offers
superior analog performance to standard CMOS
processes. Along with the standard CMOS
advantages of low power without sacrificing
speed, high input impedance, and low bias
currents, the LinCMOS™ process offers
extremely stable input offset voltages with large
differential input voltages. This characteristic
makes it possible to build reliable CMOS
comparators.
8
2
7
3
6
4
5
VDD
2OUT
2IN −
2IN +
FK PACKAGE
(TOP VIEW)
NC
1OUT
NC
VDD
NC
description
NC
1IN −
NC
1IN +
NC
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
NC
GND
NC
The TLC3702 consists of two independent
micropower voltage comparators designed to
operate from a single supply and be compatible
with modern HCMOS logic systems. They are
functionally similar to the LM339 but use onetwentieth of the power for similar response times.
The push-pull CMOS output stage drives
capacitive loads directly without a powerconsuming pullup resistor to achieve the stated
response time. Eliminating the pullup resistor not
only reduces power dissipation, but also saves
board space and component cost. The output
stage is also fully compatible with TTL
requirements.
1
NC
2OUT
NC
2IN −
NC
2IN+
NC
D
D
D, JG, OR P PACKAGE
(TOP VIEW)
NC − No internal connection
symbol (each comparator)
IN +
OUT
IN −
The TLC3702C is characterized for operation over the commercial temperature range of 0°C to 70°C. The
TLC3702I is characterized for operation over the extended industrial temperature range of −40°C to 85°C. The
TLC3702M is characterized for operation over the full military temperature range of −55°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinCMOS is a trademark of Texas Instruments Incorporated.
Copyright © 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TLC3702
DUAL MICROPOWER LinCMOS™ VOLTAGE COMPARATORS
SLCS013E − NOVEMBER 1986 − REVISED MARCH 2012
AVAILABLE OPTIONS
PACKAGES
TA
VIOmax
at 25°C
0°C to 70°C
5 mV
−40°C to 85°C
5 mV
TLC3702ID
−55°C to 125°C
5 mV
TLC3702MD
SMALL OUTLINE
(D)
CERAMIC
(FK)
CERAMIC DIP
(JG)
PLASTIC DIP
(P)
TLC3702CD
—
—
TLC3702CP
—
—
TLC3702IP
TLC3702MFK
TLC3702MJG
—
The D package is available taped and reeled. Add R suffix to the device type (e.g., TLC3702CDR).
functional block diagram (each comparator)
VDD
IN+
Differential
Input
Circuits
OUT
IN−
GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 18 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to VDD
Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 mA
Output current, IO (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Total supply current into VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
Total current out of GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA: TLC3702C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
TLC3702I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
TLC3702M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package . . . . . . . . . . . . . . . . . . . . 300°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at IN+ with respect to IN −.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC3702
DUAL MICROPOWER LinCMOS™ VOLTAGE COMPARATORS
SLCS013E − NOVEMBER 1986 − REVISED MARCH 2012
DISSIPATION RATING TABLE
TA ≤ 25°C
POWER RATING
PACKAGE
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D
725 mW
5.8 mW/°C
464 mW
377 mW
145 mW
FK
1375 mW
11.0 mW/°C
880 mW
715 mW
275 mW
JG
1050 mW
8.4 mW/°C
672 mW
546 mW
210 mW
P
1000 mW
8.0 mW/°C
640 mW
520 mW
N/A
recommended operating conditions
TLC3702C
MIN
NOM
3
5
Supply voltage, VDD
Common-mode input voltage, VIC
High-level output current, IOH
− 0.2
16
V
VDD − 1.5
V
−20
mA
20
mA
70
°C
Low-level output current, IOL
Operating free-air temperature, TA
UNIT
MAX
0
electrical characteristics at specified operating free-air temperature, VDD = 5 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS†
VIO
Input offset voltage
VDD = 5 V to 10 V,
VIC = VICRmin,
min
See Note 3
IIO
Input offset current
VIC = 2.5
25V
IIB
Input bias current
VICR
Common mode input voltage range
Common-mode
CMRR
Common-mode
Common
mode rejection ratio
kSVR
Supply-voltage
Supply
voltage rejection ratio
TA
TLC3702C
MIN
25°C
TYP
MAX
1.2
5
0°C to 70°C
6.5
25°C
1
70°C
VIC = 2.5
25V
5
70°C
VIC = VICRmin
VDD = 5 V to 10 V
0 to VDD − 1
0°C to 70°C
0 to VDD − 1.5
84
70°C
84
0°C
84
25°C
85
70°C
85
0°C
85
High level output voltage
High-level
VID = 1 V,
IOH = − 4 mA
25°C
4.5
70°C
4.3
VOL
Low level output voltage
Low-level
VID = −1
1 V,
IOH = 4 mA
25°C
IDD
Supply current (both comparators)
Outputs low,
low No load
dB
dB
4.7
210
70°C
25°C
nA
V
25°C
VOH
nA
pA
0.6
25°C
mV
pA
0.3
25°C
UNIT
V
300
375
18
0°C to 70°C
40
50
mV
μA
†
All characteristics are measured with zero common-mode voltage unless otherwise noted.
NOTE 3: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TLC3702
DUAL MICROPOWER LinCMOS™ VOLTAGE COMPARATORS
SLCS013E − NOVEMBER 1986 − REVISED MARCH 2012
recommended operating conditions
TLC3702I
Supply voltage, VDD
Common-mode input voltage, VIC
High-level output current, IOH
MIN
NOM
3
5
−0.2
16
V
VDD − 1.5
V
−20
mA
20
mA
85
°C
Low-level output current, IOL
Operating free-air temperature, TA
UNIT
MAX
−40
electrical characteristics at specified operating free-air temperature, VDD = 5 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS†
TA
−40°C to 85°C
VIO
Input offset voltage
VDD = 5 V to 10 V,
VIC = VICRmin, See Note 3
IIO
Input offset current
VIC = 2.5
25V
IIB
VICR
CMRR
kSVR
Input bias current
Supply-voltage
Supply
voltage rejection ratio
MIN
25°C
TYP
MAX
1.2
5
7
25°C
1
85°C
VIC = 2.5
25V
5
85°C
25°C
−40°C to 85°C
0 to
VDD − 1.5
84
85°C
84
−40°C
83
25°C
85
85°C
85
−40°C
83
VDD = 5 V to 10 V
VOH
High level output voltage
High-level
VID = 1 V,
V
IOH = − 4 mA
VOL
Low level output voltage
Low-level
VID = −1
1 V,
V
IOH = − 4 mA
IDD
Supply current (both comparators)
Outputs low,
low
No load
25°C
4.5
85°C
4.3
25°C
210
18
All characteristics are measured with zero common-mode voltage unless otherwise noted.
NOTE 3. The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
dB
V
300
400
−40°C to 85°C
†
nA
dB
4.7
85°C
25°C
nA
V
25°C
VIC = VICRmin
mV
pA
2
0 to
VDD − 1
UNIT
pA
1
25°C
Common mode input voltage range
Common-mode
Common-mode
Common
mode rejection ratio
TLC3702I
40
65
mV
μA
TLC3702
DUAL MICROPOWER LinCMOS™ VOLTAGE COMPARATORS
SLCS013E − NOVEMBER 1986 − REVISED MARCH 2012
recommended operating conditions
TLC3702M
MIN
NOM
Supply voltage, VDD
4
5
Common-mode input voltage, VIC
High-level output current, IOH
0
16
V
VDD − 1.5
V
− 20
mA
20
mA
125
°C
Low-level output current, IOL
Operating free-air temperature, TA
UNIT
MAX
− 55
electrical characteristics at specified operating free-air temperature, VDD = 5 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS†
TA
−55°C to 125°C
VIO
Input offset voltage
VDD = 5 V to 10 V,
VIC = VICRmin, See Note 3
IIO
Input offset current
VIC = 2.5
25V
IIB
Input bias current
kSVR
Supply-voltage
Supply
voltage rejection ratio
VDD = 5 V to 10 V
VOH
High level output voltage
High-level
VID = 1 V,
V
IOH = − 4 mA
15
VOL
Low level output voltage
Low-level
VID = −1
1 V,
V
IOH = − 4 mA
IDD
Supply current (both comparators)
Outputs low,
low
No load
30
25°C
84
125°C
83
−55°C
82
25°C
85
125°C
85
− 55°C
82
4.5
4.2
25°C
nA
dB
dB
4.7
210
125°C
25°C
nA
V
0 to
VDD − 1.5
25°C
mV
pA
0 to
VDD − 1
125°C
UNIT
pA
5
125°C
VIC = VICRmin
5
1
25°C
VIC = 2.5
25V
MAX
10
125°C
Common mode input voltage range
Common-mode
Common-mode
Common
mode rejection ratio
TYP
1.2
25°C
−55°C to 125°C
CMRR
MIN
25°C
25°C
VICR
TLC3702M
V
300
500
18
−55°C to 125°C
40
90
mV
μA
†
All characteristics are measured with zero common-mode voltage unless otherwise noted.
NOTE 3. The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
TLC3702
DUAL MICROPOWER LinCMOS™ VOLTAGE COMPARATORS
SLCS013E − NOVEMBER 1986 − REVISED MARCH 2012
switching characteristics, VDD = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TLC3702C, TLC3702I
TLC3702M
MIN
tPLH
Propagation delay time, low
low-to-high-level
to high level output†
f = 10 kH
kHz,
CL = 50 pF
Overdrive = 2 mV
4.5
Overdrive = 5 mV
2.7
Overdrive = 10 mV
1.9
Overdrive = 20 mV
1.4
Overdrive = 40 mV
1.1
VI = 1.4 V step at IN+
tPHL
Propagation delay time, high
high-to-low-level
to low level output†
f = 10 kH
kHz,
CL = 50 pF
TYP
μs
1.1
Overdrive = 2 mV
4
Overdrive = 5 mV
2.3
Overdrive = 10 mV
1.5
Overdrive = 20 mV
0.95
Overdrive = 40 mV
0.65
VI = 1.4 V step at IN+
UNIT
MAX
μs
0.15
tf
Fall time
f = 10 kHz,
CL = 50 pF
Overdrive = 50 mV
50
ns
tr
Rise time
f = 10 kHz,
CL = 50 pF
Overdrive = 50 mV
125
ns
†
6
Simultaneous switching of inputs causes degradation in output response.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC3702
DUAL MICROPOWER LinCMOS™ VOLTAGE COMPARATORS
SLCS013E − NOVEMBER 1986 − REVISED MARCH 2012
PRINCIPLES OF OPERATION
LinCMOS™ process
The LinCMOS™ process is a linear polysilicon-gate CMOS process. Primarily designed for single-supply
applications, LinCMOS™ products facilitate the design of a wide range of high-performance analog functions
from operational amplifiers to complex mixed-mode converters.
While digital designers are experienced with CMOS, MOS technologies are relatively new for analog designers.
This short guide is intended to answer the most frequently asked questions related to the quality and reliability
of LinCMOS™ products. Further questions should be directed to the nearest TI field sales office.
electrostatic discharge
CMOS circuits are prone to gate oxide breakdown when exposed to high voltages even if the exposure is only
for very short periods of time. Electrostatic discharge (ESD) is one of the most common causes of damage to
CMOS devices. It can occur when a device is handled without proper consideration for environmental
electrostatic charges, e.g., during board assembly. If a circuit in which one amplifier from a dual op amp is being
used and the unused pins are left open, high voltages tend to develop. If there is no provision for ESD protection,
these voltages may eventually punch through the gate oxide and cause the device to fail. To prevent voltage
buildup, each pin is protected by internal circuitry.
Standard ESD-protection circuits safely shunt the ESD current by providing a mechanism whereby one or more
transistors break down at voltages higher than the normal operating voltages but lower than the breakdown
voltage of the input gate. This type of protection scheme is limited by leakage currents which flow through the
shunting transistors during normal operation after an ESD voltage has occurred. Although these currents are
small, on the order of tens of nanoamps, CMOS amplifiers are often specified to draw input currents as low as
tens of picoamps.
To overcome this limitation, TI design engineers developed the patented ESD-protection circuit shown in
Figure 1. This circuit can withstand several successive 2-kV ESD pulses, while reducing or eliminating leakage
currents that may be drawn through the input pins. A more detailed discussion of the operation of the TI
ESD-protection circuit is presented on the next page.
All input and output pins on LinCMOS™ and Advanced LinCMOS™ products have associated ESD-protection
circuitry that undergoes qualification testing to withstand 2000 V discharged from a 100-pF capacitor through
a 1500-Ω resistor (human body model) and 200 V from a 100-pF capacitor with no current-limiting resistor
(charged device model). These tests simulate both operator and machine handling of devices during normal
test and assembly operations.
VDD
R1
Input
To Protect Circuit
R2
Q1
Q2
D1
D2
D3
GND
Figure 1. LinCMOS™ ESD-Protection Schematic
LinCMOS and Advanced LinCMOS are trademarks of Texas Instruments Incorporated.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
TLC3702
DUAL MICROPOWER LinCMOS™ VOLTAGE COMPARATORS
SLCS013E − NOVEMBER 1986 − REVISED MARCH 2012
PRINCIPLES OF OPERATION
input protection circuit operation
Texas Instruments patented protection circuitry allows for both positive- and negative-going ESD transients.
These transients are characterized by extremely fast rise times and usually low energies, and can occur both
when the device has all pins open and when it is installed in a circuit.
positive ESD transients
Initial positive charged energy is shunted through Q1 to VSS. Q1 turns on when the voltage at the input rises
above the voltage on the VDD pin by a value equal to the VBE of Q1. The base current increases through R2
with input current as Q1 saturates. The base current through R2 forces the voltage at the drain and gate of Q2
to exceed its threshold level (VT ∼ 22 to 26 V) and turn Q2 on. The shunted input current through Q1 to VSS is
now shunted through the n-channel enhancement-type MOSFET Q2 to VSS. If the voltage on the input pin
continues to rise, the breakdown voltage of the zener diode D3 is exceeded and all remaining energy is
dissipated in R1 and D3. The breakdown voltage of D3 is designed to be 24 V to 27 V, which is well below the
gate-oxide voltage of the circuit to be protected.
negative ESD transients
The negative charged ESD transients are shunted directly through D1. Additional energy is dissipated in R1
and D2 as D2 becomes forward biased. The voltage seen by the protected circuit is −0.3 V to −1 V (the forward
voltage of D1 and D2).
circuit-design considerations
LinCMOS™ products are being used in actual circuit environments that have input voltages that exceed the
recommended common-mode input voltage range and activate the input protection circuit. Even under normal
operation, these conditions occur during circuit power up or power down, and in many cases, when the device
is being used for a signal conditioning function. The input voltages can exceed VICR and not damage the device
only if the inputs are current limited. The recommended current limit shown on most product data sheets is
±5 mA. Figure 2 and Figure 3 show typical characteristics for input voltage versus input current.
Normal operation and correct output state can be expected even when the input voltage exceeds the positive
supply voltage. Again, the input current should be externally limited even though internal positive current limiting
is achieved in the input protection circuit by the action of Q1. When Q1 is on, it saturates and limits the current
to approximately 5-mA collector current by design. When saturated, Q1 base current increases with input
current. This base current is forced into the VDD pin and into the device IDD or the VDD supply through R2
producing the current limiting effects shown in Figure 2. This internal limiting lasts only as long as the input
voltage is below the VT of Q2.
When the input voltage exceeds the negative supply voltage, normal operation is affected and output voltage
states may not be correct. Also, the isolation between channels of multiple devices (duals and quads) can be
severely affected. External current limiting must be used since this current is directly shunted by D1 and D2 and
no internal limiting is achieved. If normal output voltage states are required, an external input voltage clamp is
required (see Figure 4).
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC3702
DUAL MICROPOWER LinCMOS™ VOLTAGE COMPARATORS
SLCS013E − NOVEMBER 1986 − REVISED MARCH 2012
PRINCIPLES OF OPERATION
circuit-design considerations (continued)
INPUT CURRENT
vs
POSITIVE INPUT VOLTAGE
8
INPUT CURRENT
vs
NEGATIVE INPUT VOLTAGE
−10
TA = 25° C
−9
7
−8
I I − Input Current − mA
6
I I − Input Current − mA
TA = 25° C
5
4
3
2
−7
−6
−5
−4
−3
−2
1
−1
0
VDD
VDD + 4
VDD + 8
VDD + 12
−0
−0.3
−0.5
VI − Input Voltage − V
−0.7
−0.9
VI − Input Voltage − V
Figure 2
Figure 3
VDD
VI
RI
+
Positive Voltage Input Current Limit :
1/2
TLC3702
Vref
−
See Note A
RI +
V I * V DD * 0.3 V
5 mA
Negative Voltage Input Current Limit :
* V I * V DD * (* 0.3 V)
RI +
5 mA
NOTE A: If the correct input state is required when the negative input exceeds GND, a Schottky clamp is required.
Figure 4. Typical Input Current-Limiting Configuration for a LinCMOS™ Comparator
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
TLC3702
DUAL MICROPOWER LinCMOS™ VOLTAGE COMPARATORS
SLCS013E − NOVEMBER 1986 − REVISED MARCH 2012
PARAMETER MEASUREMENT INFORMATION
The TLC3702 contains a digital output stage which, if held in the linear region of the transfer curve, can cause
damage to the device. Conventional operational amplifier/comparator testing incorporates the use of a servo
loop which is designed to force the device output to a level within this linear region. Since the servo-loop method
of testing cannot be used, we offer the following alternatives for measuring parameters such as input offset
voltage, common-mode rejection, etc.
To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown
in Figure 5(a). With the noninverting input positive with respect to the inverting input, the output should be high.
With the input polarity reversed, the output should be low.
A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages
can be slewed to provide greater accuracy, as shown in Figure 5(b) for the VICR test. This slewing is done instead
of changing the input voltages.
A close approximation of the input offset voltage can be obtained by using a binary search method to vary the
differential input voltage while monitoring the output state. When the applied input voltage differential is equal,
but opposite in polarity, to the input offset voltage, the output changes states.
Figure 6 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the
comparator in the linear region. The circuit consists of a switching mode servo loop in which IC1a generates
a triangular waveform of approximately 20-mV amplitude. IC1b acts as a buffer, with C2 and R4 removing any
residual dc offset. The signal is then applied to the inverting input of the comparator under test, while the
noninverting input is driven by the output of the integrator formed by IC1c through the voltage divider formed
by R8 and R9. The loop reaches a stable operating point when the output of the comparator under test has a
duty cycle of exactly 50%, which can only occur when the incoming triangle wave is sliced symmetrically or when
the voltage at the noninverting input exactly equals the input offset voltage.
Voltage dividers R8 and R9 provide an increase in input offset voltage by a factor of 100 to make measurement
easier. The values of R5, R7, R8, and R9 can significantly influence the accuracy of the reading; therefore, it
is suggested that their tolerance level be one percent or lower.
Measuring the extremely low values of input current requires isolation from all other sources of leakage current
and compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board
leakage can be measured with no device in the socket. Subsequently, this open socket leakage value can be
subtracted from the measurement obtained with a device in the socket to obtain the actual input current of the
device.
5V
1V
+
Applied VIO
+
−
Limit
−
Applied VIO
VO
Limit
VO
−4V
(a) VIO WITH VIC = 0 V
(b) VIO WITH VIC = 4 V
Figure 5. Method for Verifying That Input Offset Voltage Is Within Specified Limits
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC3702
DUAL MICROPOWER LinCMOS™ VOLTAGE COMPARATORS
SLCS013E − NOVEMBER 1986 − REVISED MARCH 2012
PARAMETER MEASUREMENT INFORMATION
VDD
IC1a
1/4 TLC274CN
+
Buffer
C2
1 μF
−
DUT
−
R4
47 kΩ
R6
1 MΩ
−
R3
100 Ω
VIO
(X100)
Integrator
C4
0.1 μF
−
Triangle
Generator
R2
10 kΩ
+
R7
1.8 kΩ 1%
IC1b
1/4 TLC274CN
+
IC1c
1/4 TLC274CN
+
R1
240 kΩ
C1
0.1 μF
C3
0.68 μF
R5
1.8 kΩ 1%
R9
100 Ω 1%
R8
10 kΩ 1%
Figure 6. Circuit for Input Offset Voltage Measurement
Response time is defined as the interval between the application of an input step function and the instant when
the output reaches 50% of its maximum value. Response time for the low-to-high-level output is measured from
the leading edge of the input pulse, while response time for the high-to-low-level output is measured from the
trailing edge of the input pulse. Response time measurement at low input signal levels can be greatly affected
by the input offset voltage. The offset voltage should be balanced by the adjustment at the inverting input as
shown in Figure 7, so that the circuit is just at the transition point. A low signal, for example 105-mV or 5-mV
overdrive, causes the output to change state.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
TLC3702
DUAL MICROPOWER LinCMOS™ VOLTAGE COMPARATORS
SLCS013E − NOVEMBER 1986 − REVISED MARCH 2012
PARAMETER MEASUREMENT INFORMATION
VDD
Pulse
Generator
1 μF
50 Ω
+
DUT
1V
10 Ω
10-Turn
Potentiometer
−
1 kΩ
CL
(see Note A)
0.1 μF
−1V
TEST CIRCUIT
Overdrive
Overdrive
Input
Input
100 mV
100 mV
90%
Low-to-High
Level Output
High-to-Low
Level Output
50%
10%
90%
50%
10%
tr
tf
tPLH
tPHL
VOLTAGE WAVEFORMS
NOTE A: CL includes probe and jig capacitance.
Figure 7. Response, Rise, and Fall Times Circuit and Voltage Waveforms
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC3702
DUAL MICROPOWER LinCMOS™ VOLTAGE COMPARATORS
SLCS013E − NOVEMBER 1986 − REVISED MARCH 2012
TYPICAL CHARACTERISTICS†
Table of Graphs
FIGURE
VIO
Input offset voltage
Distribution
8
IIB
Input bias current
vs Free-air temperature
9
CMRR
Common-mode rejection ratio
vs Free-air temperature
10
kSVR
Supply-voltage rejection ratio
vs Free-air temperature
11
VOH
High level output current
High-level
vs Free
Free-air
air temperature
vs High-level output current
12
13
VOL
Low level output voltage
Low-level
vs Low
Low-level
level output current
vs Free-air temperature
14
15
tt
Transition time
vs Load capacitance
16
Supply current response
vs Time
17
Low-to-high-level output response
Low-to-high level output propagation delay time
18
High-to-low level output response
High-to-low level output propagation delay time
19
tPLH
Low-to-high level output propagation delay time
vs Supply voltage
20
tPHL
High-to-low level output propagation delay time
vs Supply voltage
21
Supply current
vs Frequency
vs Supply voltage
vs Free-air temperature
22
23
24
IDD
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
DISTRIBUTION OF INPUT
OFFSET VOLTAGE
180
Number of Units
160
140
120
100
80
60
40
20
ÉÉ
ÉÉ
ÉÉ
Ç
ÉÉ
Ç
ÉÉ
Ç
ÉÉ
Ç
ÉÉ
Ç
Ç
ÉÉ
Ç
Ç
ÉÉ
Ç
Ç
ÇÇ
É
ÉÉ
ÉÉ
Ç
Ç
ÇÉ
ÇÇ
É
ÉÉ
ÉÉ
Ç
Ç
ÇÇ
É
ÇÇ
ÇÇ
É
ÉÉ
Ç
É
ÉÉ
ÇÇÉ
ÇÇÇÇ
ÉÉ
ÇÇ
ÉÇ
ÉÉ
ÇÇ
ÉÉ
ÇÇ
0
−5
10
VDD = 5 V
VIC = 2.5 V
TA = 25° C
698 Units Tested
From 4 Wafer Lots
−4
−3
−2
−1
0
1
2
3
4
VDD = 5 V
VIC = 2.5 V
IIB − Input Bias Current − nA
200
5
1
0.1
0.01
0.001
25
VIO − Input Offset Voltage − mV
Figure 8
†
50
75
100
125
TA − Free-Air Temperature − °C
Figure 9
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
TLC3702
DUAL MICROPOWER LinCMOS™ VOLTAGE COMPARATORS
SLCS013E − NOVEMBER 1986 − REVISED MARCH 2012
TYPICAL CHARACTERISTICS†
SUPPLY VOLTAGE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
90
90
88
kSVR − Supply Voltage Rejection Ratio − dB
CMRR − Common-Mode Rejection Ratio − dB
COMMON-MODE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
VDD = 5 V
86
84
82
80
78
76
74
72
70
−75
−50
−25
0
25
50
75
100
88
VDD = 5 V to 10 V
86
84
82
80
78
76
74
72
70
−75
125
−50
−25
Figure 10
VOH− High-Input Level Output Voltage −V
VOH − High-Level Outout Voltage − V
75
100
4.9
4.85
4.8
4.75
4.7
4.65
4.6
VDD = 16 V
−0.25
−0.5
−0.75
10 V
−1
5V
−1.25
4V
−1.5
−1.75
3V
TA = 25° C
−2
−25
0
25
50
75
100
125
0
−2.5
−5
−7.5
−10 −12.5 −15 −17.5 −20
IOH − High-Level Output Current − mA
TA − Free-Air Temperature − °C
Figure 12
Figure 13
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
14
125
VDD
VDD = 5 V
IOH = − 4 mA
4.55
†
50
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
5
4.5
−75 −50
25
Figure 11
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
4.95
0
TA − Free-Air Temperature − °C
TA − Free-Air Temperature − °C
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC3702
DUAL MICROPOWER LinCMOS™ VOLTAGE COMPARATORS
SLCS013E − NOVEMBER 1986 − REVISED MARCH 2012
TYPICAL CHARACTERISTICS†
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
1.5
VOL − Low-Level Output Voltage − V
3V
VOL − Low-Level Output Voltage − mV
400
TA = 25°C
4V
1.25
5V
1
0.75
10 V
0.5
0.25
0
VDD = 16 V
0
2
4
6
8
10
12
14
16
18
350
300
250
200
150
100
50
0
−75
20
VDD = 5 V
IOL = 4 mA
−50
IOL − Low-Level Output Current − mA
−25
VDD = 5 V
TA = 25°C
IDD − Supply
Current − mA
Rise Time
150
Fall Time
100
125
VDD = 5 V
CL = 50 pF
f = 10 kHz
5
0
100
75
Output
Voltage − V
t t − Transition Time − ns
10
200
50
25
0
0
200
400
600
800
5
0
1000
t − Time
CL − Load Capacitance − pF
Figure 16
†
75
SUPPLY CURRENT RESPONSE
TO AN OUTPUT VOLTAGE TRANSITION
250
125
50
Figure 15
OUTPUT TRANSITION TIME
vs
LOAD CAPACITANCE
175
25
TA − Free-Air Temperature − °C
Figure 14
225
0
Figure 17
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
TLC3702
DUAL MICROPOWER LinCMOS™ VOLTAGE COMPARATORS
SLCS013E − NOVEMBER 1986 − REVISED MARCH 2012
TYPICAL CHARACTERISTICS
LOW-TO-HIGH-LEVEL OUTPUT RESPONSE
FOR VARIOUS INPUT OVERDRIVES
5
5
VO − Output
Voltage − V
40 mV
20 mV
10 mV
5 mV
2 mV
VO − Output
Voltage − V
40
20
10
5
2
0
0
100
100
VDD = 5 V
TA = 25°C
CL = 50 pF
0
0
1
2
3
Differential
Input
Voltage − mV
Differential
Input
Voltage − mV
HIGH-TO-LOW-LEVEL OUTPUT RESPONSE
FOR VARIOUS INPUT OVERDRIVES
4
mV
mV
mV
mV
mV
VDD = 5 V
TA = 25° C
CL = 50 pF
0
5
0
tPLH − Low-to-High-Level Output
Response Time − μs
1
Figure 18
4
5 mV
10 mV
2
20 mV
1
0
40 mV
0
2
4
6
8
10
12
14
16
t PHL − High-to-Low-Level Output Response − μs
t PLH − Low-to-High-Level Output Response − μs
Overdrive = 2 mV
3
6
5
CL = 50 pF
TA = 25°C
5
Overdrive = 2 mV
4
3
5 mV
2
10 mV
20 mV
1
40 mV
0
0
2
VDD − Supply Voltage − V
4
6
8
Figure 21
POST OFFICE BOX 655303
10
12
VDD − Supply Voltage − V
Figure 20
16
4
HIGH-TO-LOW-LEVEL
OUTPUT RESPONSE TIME
vs
SUPPLY VOLTAGE
CL = 50 pF
TA = 25°C
5
3
Figure 19
LOW-TO-HIGH-LEVEL
OUTPUT RESPONSE TIME
vs
SUPPLY VOLTAGE
6
2
tPHL − High-to-Low-Level Output
Response Time − μs
• DALLAS, TEXAS 75265
14
16
TLC3702
DUAL MICROPOWER LinCMOS™ VOLTAGE COMPARATORS
SLCS013E − NOVEMBER 1986 − REVISED MARCH 2012
TYPICAL CHARACTERISTICS†
AVERAGE SUPPLY CURRENT
(PER COMPARATOR)
vs
FREQUENCY
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
40
10000
Outputs Low
No Loads
35
VDD = 16 V
1000
VDD − Supply Current − μ A
VDD − Supply Current − μ A
TA = 25°C
CL = 50 pF
10 V
5V
100
4V
TA = − 55°C
TA = − 40°C
30
25
TA = − 25°C
20
15
TA = − 125°C
TA = 85°C
10
5
3V
10
0.01
0.1
1
10
0
100
0
1
f − Frequency − kHz
2
3
4
5
6
7
8
VDD − Supply Voltage − V
Figure 22
Figure 23
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
30
VDD = 5 V
No Load
IDD − Supply Current −μA
25
20
Outputs Low
15
10
Outputs High
5
0
−75
−50
−25
0
25
50
75
100
125
TA − Free-Air Temperature − °C
Figure 24
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
TLC3702
DUAL MICROPOWER LinCMOS™ VOLTAGE COMPARATORS
SLCS013E − NOVEMBER 1986 − REVISED MARCH 2012
APPLICATION INFORMATION
The inputs should always remain within the supply rails in order to avoid forward biasing the diodes in the
electrostatic discharge (ESD) protection structure. If either input exceeds this range, the device is not damaged
as long as the input is limited to less than 5 mA. To maintain the expected output state, the inputs must remain
within the common-mode range. For example, at 25°C with VDD = 5 V, both inputs must remain between
−0.2 V and 4 V to ensure proper device operation.
To ensure reliable operation, the supply should be decoupled with a capacitor (0.1 μF) that is positioned as close
to the device as possible.
The TLC3702 has internal ESD-protection circuits that prevent functional failures at voltages up to 2000 V as
tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in handling these devices as
exposure to ESD may result in the degradation of the device parametric performance.
Table of Applications
FIGURE
Pulse-width-modulated motor speed controller
25
Enhanced supply supervisor
26
Two-phase nonoverlapping clock generator
27
Micropower switching regulator
28
12 V
5V
EN
1/2 TLC3702
See
Note A
+
100 kΩ
+
10 kΩ
5V
SN75603
Half-H Driver
DIR
−
10 kΩ
C1
0.01 μF
(see Note B)
−
Motor
1/2 TLC3704
12 V
DIR
10 kΩ
5V
EN
10 kΩ
Motor Speed Control
Potentiometer
5V
Direction
Control
S1
SPDT
NOTES: A. The recommended minimum capacitance is 10 μF to eliminate common ground switching noise.
B. Adjust C1 for change in oscillator frequency.
Figure 25. Pulse-Width-Modulated Motor Speed Controller
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN75604
Half-H Driver
TLC3702
DUAL MICROPOWER LinCMOS™ VOLTAGE COMPARATORS
SLCS013E − NOVEMBER 1986 − REVISED MARCH 2012
APPLICATION INFORMATION
5V
VCC
12 V
12-V
Sense
3.3 kΩ
+
5V
10 kΩ
1/2 TLC3702
TL7705A
RESIN
1 kΩ
SENSE
RESET
To μP
Reset
−
REF
CT
GND
2.5 V
1 μF
1/2 TLC3702
+
V(UNREG)
(see Note A)
R1
CT
(see Note B)
To μP Interrupt
Early Power Fail
−
R2
Monitors 5 VDC Rail
Monitors 12 VDC Rail
Early Power Fail Warning
(R1 +R2)
R2
B. The value of CT determines the time delay of reset.
NOTES: A.
V (UNREG) + 2.5
Figure 26. Enhanced Supply Supervisor
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
TLC3702
DUAL MICROPOWER LinCMOS™ VOLTAGE COMPARATORS
SLCS013E − NOVEMBER 1986 − REVISED MARCH 2012
APPLICATION INFORMATION
12 V
12 V
R1
100 kΩ
(see Note B)
12 V
−
−
R2
5 kΩ
(see Note C)
1/2 TLC3702
100 kΩ
+
22 kΩ
100 kΩ
100 kΩ
1OUT
+
−
C1
0.01 μF
(see Note A)
+
R3
100 kΩ
(see Note B)
1OUT
2OUT
NOTES: A. Adjust C1 for a change in oscillator frequency where:
1/f = 1.85(100 kΩ)C1
B. Adjust R1 and R3 to change duty cycle
C. Adjust R2 to change deadtime
Figure 27. Two-Phase Nonoverlapping Clock Generator
POST OFFICE BOX 655303
1/2 TLC3702
2OUT
12 V
20
1/2 TLC3702
• DALLAS, TEXAS 75265
TLC3702
DUAL MICROPOWER LinCMOS™ VOLTAGE COMPARATORS
SLCS013E − NOVEMBER 1986 − REVISED MARCH 2012
APPLICATION INFORMATION
V + 6 V to 16 V
I
I L + 0.01 mA to 0.25 mA
V
1/2 TLC3702
+
+ 2.5
VI
1/2 TLC3702
(R1 ) R2)
R2
SK9504
(see Note C)
G S
100 kΩ
−
100 kΩ
VI
O
+
−
100 kΩ
D
+
C1
180 μF
(see Note A)
VI
47 μF
Tantalum
IN5818
100 kΩ
R1
R=6Ω
L = 1 mH
(see Note D)
VO
100 kΩ
TLC271
(see Note B)
VI
470 μF
RL
+
R2
100 kΩ
−
C2
100 pF
100 kΩ
270 kΩ
VI
LM385
2.5 V
NOTES: A. Adjust C1 for a change in oscillator frequency
B. TLC271 − Tie pin 8 to pin 7 for low bias operation
C. SK9504 − VDS = 40 V
IDS = 1 A
D. To achieve microampere current drive, the inductance of the circuit must be increased.
Figure 28. Micropower Switching Regulator
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
PACKAGE OPTION ADDENDUM
www.ti.com
7-Dec-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-9153201Q2A
ACTIVE
LCCC
FK
20
55
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629153201Q2A
TLC3702
MFKB
5962-9153201QPA
LIFEBUY
CDIP
JG
8
50
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
9153201QPA
TLC3702M
5962-9153202QPA
LIFEBUY
CDIP
JG
8
50
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629153202QPA
TLC3702CD
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
3702C
TLC3702CDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
3702C
TLC3702CDRG4
ACTIVE
SOIC
D
8
2500
TBD
Call TI
Call TI
0 to 70
TLC3702CP
LIFEBUY
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
TLC3702CP
Samples
Samples
TLC3702CPS
LIFEBUY
SO
PS
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
P3702
TLC3702CPSR
LIFEBUY
SO
PS
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
P3702
TLC3702CPWR
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
P3702
TLC3702ID
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
3702I
TLC3702IDG4
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
3702I
TLC3702IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
3702I
TLC3702IDRG4
LIFEBUY
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
3702I
TLC3702IP
LIFEBUY
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
TLC3702IP
TLC3702IPE4
LIFEBUY
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
TLC3702IP
TLC3702IPW
LIFEBUY
TSSOP
PW
8
150
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
P3702I
TLC3702IPWR
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
P3702I
TLC3702IPWRG4
ACTIVE
TSSOP
PW
8
2000
TBD
Call TI
Call TI
-40 to 85
TLC3702MD
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
3702M
TLC3702MDG4
LIFEBUY
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
3702M
TLC3702MDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
3702M
Addendum-Page 1
Samples
Samples
Samples
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
7-Dec-2023
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLC3702MDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
3702M
TLC3702MFKB
ACTIVE
LCCC
FK
20
55
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629153201Q2A
TLC3702
MFKB
TLC3702MJG
LIFEBUY
CDIP
JG
8
50
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
TLC3702MJG
TLC3702MJGB
LIFEBUY
CDIP
JG
8
50
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
9153201QPA
TLC3702M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
