TLC372MDREP

TLC372-EP LinCMOS™ DUAL DIFFERENTIAL COMPARATORS www.ti.com SGLS385 – MARCH 2007 FEATURES • • • • • • • • • • • • • • • (1) Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product Change Notification Qualification Pedigree (1) ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 100 V Using Machine Model (C = 200 pF, R = 0) Single or Dual-Supply Operation Wide Range of Supply Voltages . . .4 V to 18 V Very Low Supply Current Drain . . .150 µA Typ at 5 V Fast Response Time . . . 200 ns Typ for TTL-Level Input Step Built-in ESD Protection High Input Impedance . . . 1012Ω Typ Extremely Low Input Bias Current. . .5 pA Typ Ultrastable Low Input Offset Voltage Input Offset Voltage Change at Worst-Case Input Conditions Typically 0.23 µV/Month, Including the First 30 Days • • • Common-Mode Input Voltage Range Includes Ground Output Compatible With TTL, MOS, and CMOS Pin-Compatible With LM393 D PACKAGE (TOP VIEW) 1OUT 1IN1IN+ GND 1 8 2 7 3 6 4 5 VCC 2OUT 2IN2IN+ SYMBOL (each comparator) IN+ OUT IN - Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. DESCRIPTION/ORDERING INFORMATION This device is fabricated using LinCMOS™ technology and consists of two independent voltage comparators, each designed to operate from a single power supply. Operation from dual supplies is also possible if the difference between the two supplies is 4 V to 18 V. Each device features extremely high input impedance (typically greater than 1012Ω), allowing direct interfacing with high-impedance sources. The outputs are n-channel open-drain configurations and can be connected to achieve positive-logic wired-AND relationships. The TLC372 has internal electrostatic discharge (ESD) protection circuits and has been classified with a 2000-V ESD rating using human-body-model (HBM) testing. However, care should be exercised in handling this device as exposure to ESD may result in a degradation of the device parametric performance. The TLC372 is characterized for operation from –55°C to 125°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinCMOS is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated TLC372-EP LinCMOS™ DUAL DIFFERENTIAL COMPARATORS www.ti.com SGLS385 – MARCH 2007 ORDERING INFORMATION (1) PACKAGE (2) TA –55°C to 125°C (1) SOIC-(D) Tape and reel ORDERABLE PART NUMBER TOP-SIDE MARKING TLC372MDREP 372MEP For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. (2) EQUIVALENT SCHEMATIC (EACH COMPARATOR) Common to All Channels VDD OUT GND IN + IN − Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN (2) VDD Supply voltage VID Differential input voltage (3) VI Input voltage range VO MAX UNIT 18 V ±18 V 18 V Output voltage 18 V II Input current ±5 mA IO Output current 20 –0.3 Duration of output short circuit to ground (4) mA unlimited Continuous total power dissipation See Dissipation Rating Table TA Operating free-air temperature range –55 125 °C Tstg Storage temperature range –65 150 °C 260 °C Lead temperature 1,6 mm (1/16 in) from case for 10 s: (1) (2) (3) (4) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values except differential voltages are with respect to network ground. Differential voltages are at IN+ with respect to IN–. Short circuits from outputs to VDD can cause excessive heating and eventual device destruction. Dissipation Rating Table 2 PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR DERATE ABOVE TA TA = 70°C POWER RATING TA = 85°C POWER RATING TA = 125°C POWER RATING D 500 mW 5.8 mW/°C 64°C 464 mW 377 mW 145 mW Submit Documentation Feedback TLC372-EP LinCMOS™ DUAL DIFFERENTIAL COMPARATORS www.ti.com SGLS385 – MARCH 2007 Recommended Operating Conditions MIN VDD Supply voltage VIC Common-mode input voltage TA Operating free-air temperature MAX 4 16 VDD = 5 V 0 3.5 VDD = 10 V 0 8.5 –55 125 UNIT V V °C Electrical Characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER VIO Input offset voltage IIO Input offset current IIB Input bias current VICR Common-mode input voltage range IOH High-level output current TEST CONDITIONS VIC = VICRmin (2) TYP MAX 1 5 Full range 10 25°C 1 10 5 25°C VID = 1 V VOH = 5 V 25°C VOH = 15 V Full range VID = –1 V, IOL = 4 mA IOL Low-level output current VID = –1 V, VOL = 1.5 V IDD Supply current (two comparators) VID = 1 V, No load 20 0 to VDD– 1 0.1 25°C 400 700 6 nA nA 3 150 Full range 25°C nA V 0 to VDD– 1.5 25°C mV pA Max Full range UNIT pA Max 25°C Low-level output voltage (2) MIN 25°C VOL (1) TA (1) 16 150 Full range µA mV mA 300 400 µA All characteristics are measured with zero common-mode input voltage unless otherwise noted. Full range is –55°C to 125°C. IMPORTANT: See Parameter Measurement Information. The offset voltage limits given are the maximum values required to drive the output above 4 V or below 400 mV with a 10-kΩ resistor between the output and VDD. They can be verified by applying the limit value to the input and checking for the appropriate output state. Switching Characteristics VDD = 5 V, TA = 25°C PARAMETER Response time (1) (2) TEST CONDITIONS RL connected to 5 V through 5.1 kΩ, CL = 15 pF (1) (2) TYP 100-mV input step with 5-mV overdrive 650 TTL-level input step 200 UNIT ns CL includes probe and jig capacitance. The response time specified is the interval between the input step function and the instant when the output crosses 1.4 V. Submit Documentation Feedback 3 TLC372-EP LinCMOS™ DUAL DIFFERENTIAL COMPARATORS www.ti.com SGLS385 – MARCH 2007 PARAMETER MEASUREMENT INFORMATION The digital output stage of the TLC372 can be damaged if it is held in the linear region of the transfer curve. Conventional operational amplifier/comparator testing incorporates the use of a servo loop that is designed to force the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, the following alternatives for measuring parameters such as input offset voltage, common-mode rejection, etc., are offered. To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown in Figure 1(a). With the noninverting input positive with respect to the inverting input, the output should be high. With the input polarity reversed, the output should be low. A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can be slewed as shown in Figure 1(b) for the VICR test, rather than changing the input voltages, to provide greater accuracy. 5V 1V 5.1 kΩ + + − Applied VIO Limit 5.1 kΩ − VO Applied VIO Limit −4 V (a) VIO WITH VIC = 0 VO (b) VIO WITH VIC = 4 V Figure 1. Method for Verifying That Input Offset Voltage is Within Specified Limits A close approximation of the input offset voltage can be obtained by using a binary search method to vary the differential input voltage while monitoring the output state. When the applied input voltage differential is equal, but opposite in polarity, to the input offset voltage, the output changes states. 4 Submit Documentation Feedback TLC372-EP LinCMOS™ DUAL DIFFERENTIAL COMPARATORS www.ti.com SGLS385 – MARCH 2007 PARAMETER MEASUREMENT INFORMATION (continued) Figure 2 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the comparator into the linear region. The circuit consists of a switching-mode servo loop in which U1a generates a triangular waveform of approximately 20-mV amplitude. U1b acts as a buffer, with C2 and R4 removing any residual dc offset. The signal is then applied to the inverting input of the comparator under test, while the noninverting input is driven by the output of the integrator formed by U1c through the voltage divider formed by R9 and R10. The loop reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input exactly equals the input offset voltage. Buffer + C2 1 µF DUT − R8 1.8 kΩ, 1% − U1a 1/4 TLC274CN + Triangle Generator R3 100 kΩ R7 1 MΩ R4 47 kΩ R1 240 kΩ C1 0.1 µF R6 5.1 kΩ R2 10 kΩ C3 0.68 µF U1c 1/4 TLC274CN − U1b 1/4 TLC274C R5 1.8 kΩ, 1% + VDD VIO (X100) Integrator C4 0.1 µF R9 10 kΩ, 1% R10 100 kΩ, 1% Figure 2. Circuit for Input Offset Voltage Measurement Voltage divider R9 and R10 provides a step up of the input offset voltage by a factor of 100 to make measurement easier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the reading; therefore, it is suggested that their tolerance level be 1% or lower. Measuring the extremely low values of input current requires isolation from all other sources of leakage current and compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakage can be measured with no device in the socket. Subsequently, this open-socket leakage value can be subtracted from the measurement obtained with a device in the socket to obtain the actual input current of the device. Submit Documentation Feedback 5 TLC372-EP LinCMOS™ DUAL DIFFERENTIAL COMPARATORS www.ti.com SGLS385 – MARCH 2007 PARAMETER MEASUREMENT INFORMATION (continued) Response time is defined as the interval between the application of an input step function and the instant when the output reaches 50% of its maximum value. Response time, low-to-high-level output, is measured from the leading edge of the input pulse, while response time, high-to-low-level output, is measured from the trailing edge of the input pulse. Response-time measurement at low input signal levels can be greatly affected by the input offset voltage. The offset voltage should be balanced by the adjustment at the inverting input as shown in Figure 3, so that the circuit is just at the transition point. Then a low signal, for example 105-mV or 5-mV overdrive, causes the output to change state. VDD 5.1 kΩ Pulse Generator DUT 50 Ω CL (see Note A) 1V Input Offset Voltage Compensation Adjustment 10 Ω 10 Turn 1 kΩ - 1V 0.1 µF TEST CIRCUIT Overdrive 100 mV Overdrive Input Input 100 mV 90% Low-to-HighLevel Output 90% 50% High-to-LowLevel Output 10% tr tPLH 50% 10% tf tPHL NOTE: A. CL includes probe and jig capacitance VOLTAGE WAVEFORMS Figure 3. Response, Rise, and Fall Times Circuit and Voltage Waveforms 6 1 µF Submit Documentation Feedback TLC372-EP LinCMOS™ DUAL DIFFERENTIAL COMPARATORS www.ti.com SGLS385 – MARCH 2007 PRINCIPLES OF OPERATION LinCMOS™ Process The LinCMOS process is a linear polysilicon-gate complementary-MOS process. Primarily designed for single-supply applications, LinCMOS products facilitate the design of a wide range of high-performance analog functions, from operational amplifiers to complex mixed-mode converters. This short guide is intended to answer the most frequently asked questions related to the quality and reliability of LinCMOS products. Further questions should be directed to the nearest TI field sales office. Electrostatic Discharge (ESD) CMOS circuits are prone to gate oxide breakdown when exposed to high voltages even if the exposure is only for very short periods of time. ESD is one of the most common causes of damage to CMOS devices. It can occur when a device is handled without proper consideration for environmental electrostatic charges, e.g. during board assembly. If a circuit in which one amplifier from a dual operational amplifier is being used and the unused pins are left open, high voltages tends to develop. If there is no provision for ESD protection, these voltages may eventually punch through the gate oxide and cause the device to fail. To prevent voltage buildup, each pin is protected by internal circuitry. Standard ESD-protection circuits safely shunt the ESD current by providing a mechanism whereby one or more transistors break down at voltages higher than the normal operating voltages but lower than the breakdown voltage of the input gate. This type of protection scheme is limited by leakage currents which flow through the shunting transistors during normal operation after an ESD voltage has occurred. Although these currents are small, on the order of tens of nanoamps, CMOS amplifiers are often specified to draw input currents as low as tens of picoamps. To overcome this limitation, TI design engineers developed the patented ESD-protection circuit shown in Figure 4. This circuit can withstand several successive 1-kV ESD pulses, while reducing or eliminating leakage currents that may be drawn through the input pins. A more detailed discussion of the operation of TI's ESDprotection circuit is presented in Circuit Design Consideration. VDD R1 Input To Protected Circuit R2 Q1 Q2 D1 D2 D3 VSS Figure 4. LinCMOS™ ESD-Protection Schematic Input Protection Circuit Operation Texas Instruments patented protection circuitry allows for both positive-and negative-going ESD transients. These transients are characterized by extremely fast rise times and usually low energies, and can occur both when the device has all pins open and when it is installed in a circuit. Submit Documentation Feedback 7 TLC372-EP LinCMOS™ DUAL DIFFERENTIAL COMPARATORS www.ti.com SGLS385 – MARCH 2007 PRINCIPLES OF OPERATION (continued) Positive ESD Transients Initial positive charged energy is shunted through Q1 to VSS. Q1 turns on when the voltage at the input rises above the voltage on the VDD pin by a value equal to the VEB of Q1. The base current increases through R2 with input current as Q1 saturates. The base current through R2 forces the voltage at the drain and gate of Q2 to exceed its threshold level (VT ~ 22 V to 26 V) and turn Q2 on. The shunted input current through Q1 to VSS is now shunted through the n-channel enhancement-type MOSFET Q2 to VSS. If the voltage on the input pin continues to rise, the breakdown voltage of the zener diode D3 is exceeded, and all remaining energy is dissipated in R1 and D3. The breakdown voltage of D3 is designed to be 24 V to 27 V, which is well below the gate oxide voltage of the circuit to be protected. Negative ESD Transients The negative charged ESD transients are shunted directly through D1. Additional energy is dissipated in R1 and D2 as D2 becomes forward biased. The voltage seen by the protected circuit is –0.3 V to –1 V (the forward voltage of D1 and D2). Circuit-Design Considerations LinCMOS products are being used in actual circuit environments that have input voltages that exceed the recommended common-mode input voltage range and activate the input protection circuit. Even under normal operation, these conditions occur during circuit power up or power down, and in many cases, when the device is being used for a signal conditioning function. The input voltages can exceed VICR and not damage the device only if the inputs are current limited. The recommended current limit shown on most product data sheets is ± 5 mA. Figure 5 and Figure 6 show typical characteristics for input voltage versus input current. Normal operation and correct output state can be expected even when the input voltage exceeds the positive supply voltage. Again, the input current should be externally limited even though internal positive current limiting is achieved in the input protection circuit by the action of Q1. When Q1 is on, it saturates and limits the current to approximately 5-mA collector current by design. When saturated, Q1 base current increases with input current. This base current is forced into the VDD pin and into the device IDD or the VDD supply through R2 producing the current limiting effects shown in Figure 5. This internal limiting lasts only as long as the input voltage is below the VT of Q2. When the input voltage exceeds the negative supply voltage, normal operation is affected and output voltage states may not be correct. Also, the isolation between channels of multiple devices (duals and quads) can be severely affected. External current limiting must be used since this current is directly shunted by D1 and D2 and no internal limiting is achieved. If normal output voltage states are required, an external input voltage clamp is required (see Figure 7). 8 Submit Documentation Feedback TLC372-EP LinCMOS™ DUAL DIFFERENTIAL COMPARATORS www.ti.com SGLS385 – MARCH 2007 PRINCIPLES OF OPERATION (continued) INPUT CURRENT vs INPUT VOLTAGE 8 TA = 25°C 7 Input Current − mA 6 5 4 3 2 1 0 VDD VDD + 4 VDD + 8 VDD + 12 Input Voltage − V Figure 5. INPUT CURRENT vs INPUT VOLTAGE 10 TA = 25°C 9 Input Current − mA 8 7 6 5 4 3 2 1 0 VDD − 0.3 VDD − 0.5 VDD − 0.7 VDD − 0.9 Input Voltage − V Figure 6. Submit Documentation Feedback 9 TLC372-EP LinCMOS™ DUAL DIFFERENTIAL COMPARATORS www.ti.com SGLS385 – MARCH 2007 PRINCIPLES OF OPERATION (continued) VDD Positive Voltage Input Current LImit: RI = RI VI See Note A A. RL + Vref +VI − VDD − 0.3 V 5 mA Negative Voltage Input Current LImit: TLC372 − RI = −VI − VDD − (−0.3 V) 5 mA If the correct output state is required when the negative input exceeds VSS, a Schottky clamp is required. Figure 7. Typical Input Current-Limiting Configuration for a LinCMOS™ Comparator 10 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TLC372MDREP ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 372MEP V62/06675-01XE ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 372MEP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of