TLC372QD

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 SLCS114E − NOVEMBER 1983 − REVISED JULY 2008 D D D D D D D D 1OUT 1IN − 1IN + GND 1 8 2 7 3 6 4 5 VCC 2OUT 2IN − 2IN + TLC372M . . . FK PACKAGE (TOP VIEW) NC 1IN − NC 1IN + NC 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 NC 2OUT NC 2IN − NC NC GND NC 2IN+ NC D 150 µA Typ at 5 V Fast Response Time . . . 200 ns Typ for TTL-Level Input Step Built-in ESD Protection High Input Impedance . . . 1012 Ω Typ Extremely Low Input Bias Current 5 pA Typ Ultrastable Low Input Offset Voltage Input Offset Voltage Change at Worst-Case Input Conditions Typically 0.23 µV/Month, Including the First 30 Days Common-Mode Input Voltage Range Includes Ground Output Compatible With TTL, MOS, and CMOS Pin-Compatible With LM393 TLC372C, TLC372I, TLC372M, TLC372Q D, P, OR PW PACKAGE TLC372M . . . JG PACKAGE (TOP VIEW) NC 1OUT NC VDD NC D Single or Dual-Supply Operation D Wide Range of Supply Voltages 2 V to 18 V D Low Supply Current Drain description This device is fabricated using LinCMOS technology and consists of two independent voltage comparators, each designed to operate from a single power supply. Operation from dual supplies is also possible if the difference between the two supplies is 2 V to 18 V. Each device features extremely high input impedance (typically greater than 1012 Ω), allowing direct interfacing with high-impedance sources. The outputs are n-channel open-drain configurations and can be connected to achieve positive-logic wired-AND relationships. The TLC372 has internal electrostatic discharge (ESD) protection circuits and has been classified with a 1000-V ESD rating using human body model testing. However, care should be exercised in handling this device as exposure to ESD may result in a degradation of the device parametric performance. NC − No internal connection TLC372M U PACKAGE (TOP VIEW) NC 1OUT 1IN− 1IN+ GND 1 10 2 9 3 8 4 7 5 6 NC VCC 2OUT 2IN− 2IN+ symbol (each comparator) IN + OUT IN − The TLC372C is characterized for operation from 0°C to 70°C. The TLC372I is characterized for operation from −40°C to 85°C. The TLC372M is characterized for operation over the full military temperature range of −55°C to 125°C. The TLC372Q is characterized for operation from − 40°C to 125°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinCMOS is a trademark of Texas Instruments Incorporated. All other trademarks are the property of their respective owners. Copyright  1983−2008, Texas Instruments Incorporated   
  
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 SLCS114E − NOVEMBER 1983 − REVISED JULY 2008 equivalent schematic (each comparator) Common to All Channels VDD OUT GND IN + IN − AVAILABLE OPTIONS(1) PACKAGED DEVICES TA VIO max AT 25°C SMALL OUTLINE (D)(2) CHIP CARRIER (FK) CERAMIC DIP (JG) PLASTIC DIP (P) TSSOP (PW) CERAMIC FLAT PACK (U) — 0°C to 70°C 5 mV TLC372CD — — TLC372CP TLC372CPW −40°C to 85°C 5 mV TLC372ID — — TLC372IP — — −55°C to 125°C 5 mV TLC372MD TLC372MFK TLC372MJG TLC372MP — TLC372MU −40°C to 125°C 5 mV TLC372QD — — TLC372QP — — 1. For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. 2. The D packages are available taped and reeled. Add R suffix to device type (e.g., TLC372CDR). 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
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 SLCS114E − NOVEMBER 1983 − REVISED JULY 2008 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 18 V Output voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Duration of output short circuit to ground (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited Package thermal impedance, θJA (see Notes 6 and 7): D package . . . . . . . . . . . . . . . . . . . . . . . . . . 97.1°C/W P package . . . . . . . . . . . . . . . . . . . . . . . . . . 84.6°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W Package thermal impedance, θJC (see Notes 6 and 7): FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6°C/W JG package . . . . . . . . . . . . . . . . . . . . . . . . . 14.5°C/W U package . . . . . . . . . . . . . . . . . . . . . . . . . . 14.7°C/W Operating free-air temperature range, TA: TLC372C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C TLC372I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C TLC372M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C TLC372Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, P, or PW package . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG or U package . . . . . . . . . . . . . . . 300°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 3. All voltage values except differential voltages are with respect to network ground. 4. Differential voltages are at IN+ with respect to IN −. 5. Short circuits from outputs to VDD can cause excessive heating and eventual device destruction. 6. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. 7. The package thermal impedance is calculated in accordance with JESD 51-7 (plastic) or MIL-STD-883 Method 1012 (ceramic). recommended operating conditions TLC372C MIN Supply voltage, VDD Common-mode input voltage, VIC Operating free-air temperature, TA VDD = 5 V VDD = 10 V TLC372I TLC372M TLC372Q MAX MIN MAX MIN 3 16 4 16 4 16 0 3.5 0 3.5 0 3.5 8.5 0 8.5 0 8.5 0 8.5 70 −40 85 −55 125 −40 125 MAX MIN 3 16 0 3.5 0 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT V V °C 3 4 VID = − 1 V, VID = 1 V, Input bias current Common-mode input voltage range High-level output current Low-level output voltage Low-level output current Supply current (two comparators) IIB VICR IOH VOL IOL IDD No load VOL = 1.5 V IOL = 4 mA VOH = 5 V VOH = 15 V See Note 4 Full range 25°C 25°C Full range 25°C Full range 25°C Full range 25°C MAX 25°C MAX 25°C Full range 25°C TA† 6 150 16 150 0.1 5 1 1 TYP TLC372C 0 to VDD −1 0 to VDD −1.5 MIN 400 300 700 400 1 0.6 0.3 6.5 5 MAX 6 150 16 150 0.1 5 1 1 TYP TLC372I 0 to VDD −1 0 to VDD −1.5 MIN 400 300 700 400 1 2 1 7 5 MAX 6 0 to VDD −1 0 to VDD −1.5 MIN 150 16 150 0.1 5 1 1 TYP 400 300 700 400 3 20 10 10 5 MAX TLC372M, TLC372Q µA mA mV µA nA V nA pA nA pA mV UNIT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 RL connected to 5 V through 5.1 kΩ, CL = 15 pF ‡, See Note 5 200 TTL-level input step TYP 650 MIN 100-mV input step with 5-mV overdrive TEST CONDITIONS ‡ CL includes probe and jig capacitance. NOTE 9: The response time specified is the interval between the input step function and the instant when the output crosses 1.4 V. Response time PARAMETER switching characteristics, VDD = 5 V, TA = 25°C MAX ns UNIT † All characteristics are measured with zero common-mode input voltage unless otherwise noted. Full range is 0°C to 70°C for TLC372C, − 40°C to 85°C for TLC372I, and − 55°C to 125°C for TLC372M and − 40°C to 125°C for TLC372Q. IMPORTANT: See Parameter Measurement Information. NOTE 8: The offset voltage limits given are the maximum values required to drive the output above 4 V or below 400 mV with a 10-kΩ resistor between the output and VDD. They can be verified by applying the limit value to the input and checking for the appropriate output state. VID = − 1 V, VID = 1 V Input offset current IIO VIC = VICRmin, Input offset voltage TEST CONDITIONS VIO PARAMETER electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) Template Release Date: 7−11−94
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 SLCS114E − NOVEMBER 1983 − REVISED JULY 2008 electrical characteristics at specified free-air temperature, VDD = 5 V, TA = 25°C (unless otherwise noted) TLC372Y TEST CONDITIONS† PARAMETER VIC = VICRmin, MIN See Note 4 TYP MAX 1 5 UNIT VIO IIO Input offset voltage Input offset current 1 pA IIB Input bias current 5 pA VICR Common-mode input voltage range IOH VOL High-level output current 0 to VDD −1 VID = 1 V, VID = − 1 V, Low-level output voltage VOH = 5 V IOL = 4 mA mV V 0.1 nA 150 400 mV IOL Low-level output current VID = − 1 V, VOL = 1.5 V 6 16 mA IDD Supply current (two comparators) VID = 1 V, No load 150 300 µA † All characteristics are measured with zero common-mode input voltage unless otherwise noted. IMPORTANT: See Parameter Measurement Information. NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V or below 400 mV with a 10-kΩ resistor between the output and VDD. They can be verified by applying the limit value to the input and checking for the appropriate output state. PARAMETER MEASUREMENT INFORMATION The digital output stage of the TLC372 can be damaged if it is held in the linear region of the transfer curve. Conventional operational amplifier/comparator testing incorporates the use of a servo loop that is designed to force the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, the following alternatives for measuring parameters such as input offset voltage, common-mode rejection, etc., are offered. To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown in Figure 1(a). With the noninverting input positive with respect to the inverting input, the output should be high. With the input polarity reversed, the output should be low. A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can be slewed as shown in Figure 1(b) for the VICR test, rather than changing the input voltages, to provide greater accuracy. 5V 1V 5.1 kΩ + + − 5.1 kΩ − Applied VIO Limit VO Applied VIO Limit −4 V (a) VIO WITH VIC = 0 VO (b) VIO WITH VIC = 4 V Figure 1. Method for Verifying That Input Offset Voltage is Within Specified Limits POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 
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 SLCS114E − NOVEMBER 1983 − REVISED JULY 2008 PARAMETER MEASUREMENT INFORMATION A close approximation of the input offset voltage can be obtained by using a binary search method to vary the differential input voltage while monitoring the output state. When the applied input voltage differential is equal, but opposite in polarity, to the input offset voltage, the output changes states. Figure 2 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the comparator into the linear region. The circuit consists of a switching-mode servo loop in which U1a generates a triangular waveform of approximately 20-mV amplitude. U1b acts as a buffer, with C2 and R4 removing any residual dc offset. The signal is then applied to the inverting input of the comparator under test, while the noninverting input is driven by the output of the integrator formed by U1c through the voltage divider formed by R9 and R10. The loop reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input exactly equals the input offset voltage. Voltage divider R9 and R10 provides a step up of the input offset voltage by a factor of 100 to make measurement easier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the reading; therefore, it is suggested that their tolerance level be 1% or lower. Measuring the extremely low values of input current requires isolation from all other sources of leakage current and compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakage can be measured with no device in the socket. Subsequently, this open-socket leakage value can be subtracted from the measurement obtained with a device in the socket to obtain the actual input current of the device. + Buffer C2 1 µF DUT − R8 1.8 kΩ, 1% − U1a 1/4 TLC274CN + Triangle Generator R3 100 kΩ R7 1 MΩ R4 47 kΩ R1 240 kΩ C1 0.1 µF R6 5.1 kΩ R2 10 kΩ C3 0.68 µF U1c 1/4 TLC274CN − U1b 1/4 TLC274C R5 1.8 kΩ, 1% + VDD Integrator C4 0.1 µF R9 10 kΩ, 1% R10 100 Ω, 1% Figure 2. Circuit for Input Offset Voltage Measurement 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VIO (X100) 
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 SLCS114E − NOVEMBER 1983 − REVISED JULY 2008 PARAMETER MEASUREMENT INFORMATION Response time is defined as the interval between the application of an input step function and the instant when the output reaches 50% of its maximum value. Response time, low-to-high level output, is measured from the leading edge of the input pulse, while response time, high-to-low level output, is measured from the trailing edge of the input pulse. Response-time measurement at low input signal levels can be greatly affected by the input offset voltage. The offset voltage should be balanced by the adjustment at the inverting input as shown in Figure 3, so that the circuit is just at the transition point. Then a low signal, for example 105-mV or 5-mV overdrive, causes the output to change state. VDD 5.1 kΩ Pulse Generator DUT 50 Ω CL (see Note A) 1V Input Offset Voltage Compensation Adjustment 1 µF 10 Ω 10 Turn 1 kΩ −1 V 0.1 µF TEST CIRCUIT Overdrive 100 mV Overdrive Input Input 100 mV 90% 90% ÁÁÁ Low-to-HighLevel Output 50% High-to-LowLevel Output 10% tr 50% 10% tf tPHL tPLH VOLTAGE WAVEFORMS NOTE A: CL includes probe and jig capacitance. Figure 3. Response, Rise, and Fall Times Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 
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 SLCS114E − NOVEMBER 1983 − REVISED JULY 2008 PRINCIPLES OF OPERATION LinCMOS process The LinCMOS process is a Linear polysilicon-gate complementary-MOS process. Primarily designed for single-supply applications, LinCMOS products facilitate the design of a wide range of high-performance analog functions, from operational amplifiers to complex mixed-mode converters. While digital designers are experienced with CMOS, MOS technologies are relatively new for analog designers. This short guide is intended to answer the most frequently asked questions related to the quality and reliability of LinCMOS products. Further questions should be directed to the nearest Texas Instruments field sales office. electrostatic discharge CMOS circuits are prone to gate oxide breakdown when exposed to high voltages even if the exposure is only for very short periods of time. Electrostatic discharge (ESD) is one of the most common causes of damage to CMOS devices. It can occur when a device is handled without proper consideration for environmental electrostatic charges, e.g. during board assembly. If a circuit in which one amplifier from a dual operational amplifier is being used and the unused pins are left open, high voltages tends to develop. If there is no provision for ESD protection, these voltages may eventually punch through the gate oxide and cause the device to fail. To prevent voltage buildup, each pin is protected by internal circuitry. Standard ESD-protection circuits safely shunt the ESD current by providing a mechanism whereby one or more transistors break down at voltages higher than the normal operating voltages but lower than the breakdown voltage of the input gate. This type of protection scheme is limited by leakage currents which flow through the shunting transistors during normal operation after an ESD voltage has occurred. Although these currents are small, on the order of tens of nanoamps, CMOS amplifiers are often specified to draw input currents as low as tens of picoamps. To overcome this limitation, Texas Instruments design engineers developed the patented ESD-protection circuit shown in Figure 4. This circuit can withstand several successive 1-kV ESD pulses, while reducing or eliminating leakage currents that may be drawn through the input pins. A more detailed discussion of the operation of Texas Instruments’s ESD- protection circuit is presented on the next page. All input and output pins on LinCMOS and Advanced LinCMOS products have associated ESD-protection circuitry that undergoes qualification testing to withstand 1000 V discharged from a 100-pF capacitor through a 1500-Ω resistor (human body model) and 200 V from a 100-pF capacitor with no current-limiting resistor (charged device model). These tests simulate both operator and machine handling of devices during normal test and assembly operations. VDD R1 Input To Protected Circuit R2 Q1 Q2 D1 D2 VSS Figure 4. LinCMOS ESD-Protection Schematic Advanced LinCMOS is a trademark of Texas Instruments Incorporated. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D3 
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 SLCS114E − NOVEMBER 1983 − REVISED JULY 2008 PRINCIPLES OF OPERATION input protection circuit operation Texas Instruments’ patented protection circuitry allows for both positive-and negative-going ESD transients. These transients are characterized by extremely fast rise times and usually low energies, and can occur both when the device has all pins open and when it is installed in a circuit. positive ESD transients Initial positive charged energy is shunted through Q1 to VSS. Q1 turns on when the voltage at the input rises above the voltage on the VDD pin by a value equal to the VEB of Q1. The base current increases through R2 with input current as Q1 saturates. The base current through R2 forces the voltage at the drain and gate of Q2 to exceed its threshold level (VT ~ 22 V to 26 V) and turn Q2 on. The shunted input current through Q1 to VSS is now shunted through the n-channel enhancement-type MOSFET Q2 to VSS. If the voltage on the input pin continues to rise, the breakdown voltage of the zener diode D3 is exceeded, and all remaining energy is dissipated in R1 and D3. The breakdown voltage of D3 is designed to be 24 V to 27 V, which is well below the gate oxide voltage of the circuit to be protected. negative ESD transients The negative charged ESD transients are shunted directly through D1. Additional energy is dissipated in R1 and D2 as D2 becomes forward biased. The voltage seen by the protected circuit is −0.3 V to −1 V (the forward voltage of D1 and D2). circuit-design considerations LinCMOS products are being used in actual circuit environments that have input voltages that exceed the recommended common-mode input voltage range and activate the input protection circuit. Even under normal operation, these conditions occur during circuit power up or power down, and in many cases, when the device is being used for a signal conditioning function. The input voltages can exceed VICR and not damage the device only if the inputs are current limited. The recommended current limit shown on most product data sheets is ± 5 mA. Figure 5 and Figure 6 show typical characteristics for input voltage versus input current. Normal operation and correct output state can be expected even when the input voltage exceeds the positive supply voltage. Again, the input current should be externally limited even though internal positive current limiting is achieved in the input protection circuit by the action of Q1. When Q1 is on, it saturates and limits the current to approximately 5-mA collector current by design. When saturated, Q1 base current increases with input current. This base current is forced into the VDD pin and into the device IDD or the VDD supply through R2 producing the current limiting effects shown in Figure 5. This internal limiting lasts only as long as the input voltage is below the VT of Q2. When the input voltage exceeds the negative supply voltage, normal operation is affected and output voltage states may not be correct. Also, the isolation between channels of multiple devices (duals and quads) can be severely affected. External current limiting must be used since this current is directly shunted by D1 and D2 and no internal limiting is achieved. If normal output voltage states are required, an external input voltage clamp is required (see Figure 7). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 
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 SLCS114E − NOVEMBER 1983 − REVISED JULY 2008 PRINCIPLES OF OPERATION circuit-design considerations (continued) INPUT CURRENT vs POSITIVE INPUT VOLTAGE INPUT CURRENT vs NEGATIVE INPUT VOLTAGE 8 −10 TA = 25°C TA = 25°C −9 7 −8 Input Current (mA) Input Current (mA) 6 5 4 3 −7 −6 −5 −4 −3 2 −2 1 −1 0 VDD VDD + 4 VDD + 8 Input Voltage (V) 0 −0.3 VDD + 12 −0.5 −0.7 −0.9 Input Voltage (V) Figure 6 Figure 5 VDD Positive Voltage Input Current Limit: RI = RI VI See Note A + Vref TLC372 − RL +VI − VDD − 0.3 V 5 mA Negative Voltage Input Current Limit: RI = | − VI | − 0.3 V 5 mA NOTE A: If the correct output state is required when the negative input is less than GND, a schottky clamp is required. Figure 7. Typical Input Current-Limiting Configuration for a LinCMOS Comparator 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 5962-87658012A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 596287658012A TLC372MFKB 5962-8765801PA ACTIVE CDIP JG 8 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8765801PA TLC372M Samples 5962-9554901NXD ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 Q372M Samples 5962-9554901NXDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 Q372M Samples TLC372CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 372C Samples TLC372CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 372C Samples TLC372CDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 372C Samples TLC372CP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TLC372CP Samples TLC372CPS ACTIVE SO PS 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 P372 Samples TLC372CPSR ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 P372 Samples TLC372CPW ACTIVE TSSOP PW 8 150 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 P372 Samples TLC372CPWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 P372 Samples TLC372ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 372I Samples TLC372IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 372I Samples TLC372IDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 372I Samples TLC372IP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TLC372IP Samples TLC372MD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 372M Samples TLC372MDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 372M Samples TLC372MDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 372M Samples Addendum-Page 1 -55 to 125 Samples PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TLC372MDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 372M TLC372MFKB ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 596287658012A TLC372MFKB TLC372MJG ACTIVE CDIP JG 8 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 TLC372MJG Samples TLC372MJGB ACTIVE CDIP JG 8 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8765801PA TLC372M Samples TLC372MP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 TLC372MP Samples TLC372MUB ACTIVE CFP U 10 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 TLC372MUB Samples TLC372QD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 372Q Samples TLC372QDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 372Q Samples TLC372QDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 372Q Samples TLC372QDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 372Q Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of