TLC374MDG4

TLC374, TLC374Q, TLC374Y LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS SLCS118C – NOVEMBER 1983 – REVISED MARCH 1999 D D D D D D D D D D Single- or Dual-Supply Operation Wide Range of Supply Voltages 2 V to 18 V Very Low Supply Current Drain 0.3 mA Typ at 5 V Fast Response Time . . . 200 ns Typ for TTL-Level Input Step Built-In ESD Protection High Input Impedance . . . 1012 Ω Typ Extremely Low Input Bias Current 5 pA Typ Ultrastable Low Input Offset Voltage Input Offset Voltage Change at Worst-Case Input Conditions Typically 0.23 µV/Month, Including the First 30 Days Common-Mode Input Voltage Range Includes Ground Outputs Compatible With TTL, MOS, and CMOS Pin-Compatible With LM339 D, J, N, OR PW PACKAGE (TOP VIEW) 1OUT 2OUT VDD 2IN – 2IN + 1IN – 1IN + 14 2 13 3 12 4 11 5 10 6 9 7 8 3OUT 4OUT GND 4IN + 4IN – 3IN + 3IN – FK PACKAGE (TOP VIEW) VDD NC 2IN – NC 2IN + 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 GND NC 4IN + NC 4IN – 1IN– 1IN+ NC 3IN– 3IN+ description These quadruple differential comparators are fabricated using LinCMOS technology and consist of four independent voltage comparators designed to operate from a single power supply. Operation from dual supplies is also possible if the difference between the two supplies is 2 V to 18 V. Each device features extremely high input impedance (typically greater than 1012 Ω), allowing direct interfacing with high-impedance sources. The outputs are n-channel open-drain configurations and can be connected to achieve positive-logic wired-AND relationships. 1 2OUT 1OUT NC 3OUT 4OUT D D NC – No internal connection symbol (each comparator) IN + OUT IN – The TLC374 has internal electrostatic discharge (ESD) protection circuits and has been classified with a 1000-V ESD rating using human body model testing. However, care should be exercised in handling this device as exposure to ESD may result in degradation of the device parametric performance. The TLC374C is characterized for operation from 0°C to 70°C. The TLC374I is characterized for operation from – 40° to 85°C. The TLC374M is characterized for operation over full military temperature range of – 55°C to 125°C. The TLC374Q is characterized for operation from – 40°C to 125°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinCMOS is a trademark of Texas Instruments Incorporated. Copyright  1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TLC374, TLC374Q, TLC374Y LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS SLCS118C – NOVEMBER 1983 – REVISED MARCH 1999 AVAILABLE OPTIONS PACKAGED DEVICES SMALL OUTLINE (D) CHIP CARRIER (FK) CERAMIC DIP (J) PLASTIC DIP (N) TSSOP (PW) CHIP FORM (Y) 5 mV TLC374CD — — TLC374CN TLC374CPW TLC374Y TA VIO max AT 25°C 0°C to 70°C – 40°C to 85°C 5 mV TLC374ID — — TLC374IN — — – 55°C to 125°C 5 mV TLC374MD TLC374MFK TLC374MJ TLC374MN — — – 40°C to 125°C 5 mV TLC374QD — — TLC374QN — — The D packages are available taped and reeled. Add R suffix to device type (e.g., TLC374CDR). equivalent schematic (each comparator) Common to All Channels VDD OUT GND IN + 2 POST OFFICE BOX 655303 IN – • DALLAS, TEXAS 75265 TLC374, TLC374Q, TLC374Y LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS SLCS118C – NOVEMBER 1983 – REVISED MARCH 1999 TLC374Y chip information This chip, when properly assembled, displays characteristics similar to the TLC374C. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform. VDD (3) BONDING PAD ASSIGNMENTS (13) (12) (11) (10) (9) 1IN + (7) (6) 1IN – 2OUT (14) (8) 3IN + (7) (9) 3IN – (1) 4OUT (1) 1OUT – + (2) (8) 65 + – + (5) (4) 2IN + 2IN – (14) 3OUT – + (13) – (11) (10) 4IN + 4IN – (12) GND (2) (3) (4) (5) (6) CHIP THICKNESS: 15 TYPICAL BONDING PADS: 4 × 4 MINIMUM 90 TJMAX = 150°C TOLERANCES ARE ± 10% ALL DIMENSIONS ARE IN MILS. PIN (12) IS INTERNALLY CONNECTED TO BACKSIDE OF CHIP. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TLC374, TLC374Q, TLC374Y LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS SLCS118C – NOVEMBER 1983 – REVISED MARCH 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 18 V Output voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Duration of output short circuit to ground (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA: TLC374C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C TLC374I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C TLC374M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C TLC374Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Case temperature range for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: D, N, or PW package . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: J package . . . . . . . . . . . . . . . . . . . . . 300°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values except differential voltages are with respect to network ground. 2. Differential voltages are at IN+ with respect to IN –. 3. Short circuits from outputs to VDD can cause excessive heating and eventual device destruction. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR DERATE ABOVE TA TA = 70°C POWER RATING TA = 85°C POWER RATING TA = 125°C POWER RATING D 500 mW 7.6 mW/°C 84°C 500 mW 494 mW 190 mW FK 500 mW 11.0 mW/°C 104°C 500 mW 500 mW 269 mW J 500 mW 11.0 mW/°C 104°C 500 mW 500 mW 269 mW N 500 mW 9.2 mW/°C 95°C 500 mW 500 mW 224 mW PW 700 mW 5.6 mW/°C 448 mW — — — recommended operating conditions TLC374C MIN Supply voltage, VDD Common mode input voltage, voltage VIC Common-mode VDD = 5 V VDD = 10 V Operating free-air temperature, TA 4 POST OFFICE BOX 655303 TLC374I TLC374M TLC374Q MAX MIN MAX MIN MAX MIN 3 16 3 16 4 16 3 16 0 3.5 0 3.5 0 3.5 0 3.5 0 8.5 0 8.5 0 8.5 0 8.5 0 70 – 40 85 – 55 125 – 40 125 • DALLAS, TEXAS 75265 MAX UNIT V V °C electrical characteristics at specified free-air temperature, VDD = 5 V PARAMETER VIO Input offset voltage IIO Input offset current IIB VICR TEST CONDITIONS VIC = VICRmin min, See Note 4 TA† TLC374C MIN 25°C TYP 1 Full range VOH = 5 V VOH = 15 V VOL Low level output voltage Low-level VID = – 1 V V, IOL = 4 mA IOL Low-level output current VID = –1 V, VOL = 1.5 V IDD Supply y current (four comparators) VID = 1 V V, No load 5 1 7 1 5 5 2 25°C Full range 0 to VDD – 1.5 0 to VDD – 1.5 0 to VDD – 1.5 0.1 25°C 150 Full range 25°C 0.1 1 150 700 6 25°C 16 300 Full range 0.1 150 700 6 600 16 300 800 400 700 6 600 nA nA 1 400 nA V 1 400 mV pA 20 0 to VDD – 1 UNIT pA 10 0 to VDD – 1 25°C 5 1 1 0.6 MAX 10 0 to VDD – 1 Full range TYP 16 300 800 µA mV mA 600 800 µA † All characteristics are measured with zero common-mode input voltage unless otherwise noted. Full range is 0°C to 70°C for TLC374C, – 40°C to 85°C for TLC374I, and – 55°C to 125°C for the TLC374M, and – 40°C to 125°C for TLC374Q. MAX is 70°C for TLC374C, 85°C TLC374I, and 125°C for the TLC374M, and 125°C for TLC374Q. IMPORTANT: See Parameter Measurement Information. NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V or below 400 mV with a 10-kΩ resistor between the output and VDD. They can be verified by applying the limit value to the input and checking for the appropriate output state. switching characteristics, VDD = 5 V, TA = 25°C PARAMETER TEST CONDITIONS TLC374C, TLC374I TLC374M, TLC374Q MIN Response time RL connected to 5 V through g 5.1 kΩ, CL = 15 pF ‡, See Note 5 TYP 100-mV input step with 5-mV overdrive 650 TTL-level input step 200 ‡ CL includes probe and jig capacitance. NOTE 5: The response time specified is the interval between the input step function and the instant when the output crosses 1.4 V. UNIT MAX ns 5 TLC374, TLC374Q, TLC374Y LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS VID = 1 V 1 5 MIN SLCS118C – NOVEMBER 1983 – REVISED MARCH 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 High level output current High-level MAX 5 MAX TLC374M TYP 0.3 25°C IOH MIN 1 MAX Common-mode input voltage range MAX 6.5 25°C Input bias current TLC374I TLC374, TLC374Q, TLC374Y LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS SLCS118C – NOVEMBER 1983 – REVISED MARCH 1999 electrical characteristics at specified free-air temperature, VDD = 5 V, TA = 25°C (unless otherwise noted) PARAMETER TLC374Y TEST CONDITIONS VIC = VICRmin, MIN See Note 4 TYP MAX 1 5 UNIT VIO IIO Input offset voltage Input offset current 1 pA IIB VICR Input bias current 5 pA IOH VOL High-level output current 0.1 nA IOL IDD Low-level output current Common-mode input voltage range 0 to VDD – 1 Low-level output voltage Supply current (four comparators) VID = 1 V, VID = – 1 V, VOH = 5 V IOL = 4 mA VID = – 1 V, VID =1 V, VOL = 1.5 mV No load V 150 6 mV 400 16 300 mV mA 600 µA NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V or below 400 mV with a 10-kΩ resistor between the output and VDD. They can be verified by applying the limit value to the input and checking for the appropriate output state. switching characteristics, VDD = 5 V, TA = 25°C PARAMETER Response time TEST CONDITIONS RL connected to 5 V through g 5.1 kΩ, CL = 15 pF †, See Note 5 TLC374Y MIN TYP 100-mV input step with 5-mV overdrive 650 TTL-level input step 200 MAX † CL includes probe and jig capacitance. NOTE 4: The response time specified is the interval between the input step function and the instant when the output crosses 1.4 V. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns TLC374, TLC374Q, TLC374Y LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS SLCS118C – NOVEMBER 1983 – REVISED MARCH 1999 PARAMETER MEASUREMENT INFORMATION The digital output stage of the TLC374 can be damaged if it is held in the linear region of the transfer curve. Conventional operational amplifier/comparator testing incorporates the use of a servo loop that is designed to force the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, the following alternative for measuring parameters such as input offset voltage, common-mode rejection, etc., are offered. To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown in Figure 1(a). With the noninverting input positive with respect to the inverting input, the output should be high. With the input polarity reversed, the output should be low. A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can be slewed as shown in Figure 1(b) for the VICR test, rather than changing the input voltages, to provide greater accuracy. A close approximation of the input offset voltage can be obtained by using a binary search method to vary the differential input voltage while monitoring the output state. When the applied input voltage differential is equal, but opposite in polarity to the input offset voltage, the output changes state. 5V 1V 5.1 kΩ 5.1 kΩ Applied VIO Limit VO Applied VIO Limit VO –4 V (a) VIO WITH VIC = 0 (b) VIO WITH VIC = 4 V Figure 1. Method for Verifying That Input Offset Voltage is Within Specified Limits POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TLC374, TLC374Q, TLC374Y LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS SLCS118C – NOVEMBER 1983 – REVISED MARCH 1999 PARAMETER MEASUREMENT INFORMATION Figure 2 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the comparator into the linear region. The circuit consists of a switching-mode servo loop in which U1a generates a triangular waveform of approximately 20-mV amplitude. U1b acts as a buffer with C2 and R4 removing any residual dc offset. The signal is then applied to the inverting input of the comparator under test, while the noninverting input is driven by the output of the integrator formed by U1c through the voltage divider formed by R9 and R10. The loop reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input exactly equals the input offset voltage. Voltage divider R9 and R10 provide a step up of the input offset voltage by a factor of 100 to make measurement easier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the reading; therefore, it is suggested that their tolerance level be 1% or lower. Measuring the extremely low values of input current requires isolation from all other sources of leakage current and compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakage can be measured with no device in the socket. Subsequently, this open-socket leakage value can be subtracted from the measurement obtained with a device in the socket to obtain the actual input current of the device. VDD U1b 1/4 TLC274CN Buffer + C2 1 µF – R4 47 kΩ R1 240 kΩ + C1 0.1 µF – R6 5.1 kΩ R2 R3 10 kΩ 100 kΩ C3 0.68 µF U1c 1/4 TLC274CN – DUT R7 1 MΩ R8 1.8 kΩ, 1% U1a 1/4 TLC274CN Triangle Generator R5 1.8 kΩ, 1% R10 100 Ω, 1% + Integrator C4 0.1 µF R9 10 kΩ, 1% Figure 2. Test Circuit for Input Offset Voltage Measurement 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VIO (X100) TLC374, TLC374Q, TLC374Y LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS SLCS118C – NOVEMBER 1983 – REVISED MARCH 1999 PARAMETER MEASUREMENT INFORMATION Response time is defined as the interval between the application of an input step function and the instant when the output reaches 50% of its maximum value. Response time, low-to-high-level output, is measured from the trailing edge of the input pulse. Response-time measurement at low input signal levels can be greatly affected by the input offset voltage. The offset voltage should be balanced by the adjustment at the inverting input (as shown in Figure 3) so that the circuit is just at the transition point. Then a low signal, for example, 105-mV or 5-mV overdrive, causes the output to change state. VDD 1 µF 5.1 kΩ Pulse Generator OUT CL (see Note A) 50 Ω 1V Input Offset Voltage Compensation Adjustment 10 Ω 10 Turn 1 kΩ 0.1 µF –1 V TEST CIRCUIT Overdrive 100 mV Overdrive Input Input 100 mV 90% 50% Low-to-HighLevel Output 10% High-to-LowLevel Output 90% 50% 10% tf tr tPLH tPLH VOLTAGE WAVEFORMS NOTE A: CL includes probe and jig capacitance. Figure 3. Response, Rise, and Fall Times Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TLC374, TLC374Q, TLC374Y LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS SLCS118C – NOVEMBER 1983 – REVISED MARCH 1999 PRINCIPLES OF OPERATION LinCMOS process LinCMOS process is a linear polysilicon-gate complimentary-MOS process. Primarily designed for singlesupply applications, LinCMOS products facilitate the design of a wide range of high-performance analog functions from operational amplifiers to complex mixed-mode converters. While digital designers are experienced with CMOS, MOS technologies are relatively new for analog designers. This short guide is intended to answer the most frequently asked questions related to the quality and reliability of LinCMOS products. Further questions should be directed to the nearest TI field sales office. electrostatic discharge CMOS circuits are prone to gate oxide breakdown when exposed to high voltages even if the exposure is only for very short periods of time. Electrostatic discharge (ESD) is one of the most common causes of damage to CMOS devices. It can occur when a device is handled without proper consideration for environmental electrostatic charges, e.g. during board assembly. If a circuit in which one amplifier from a dual operational amplifier is being used and the unused pins are left open, high voltages tends to develop. If there is no provision for ESD protection, these voltages may eventually punch through the gate oxide and cause the device to fail. To prevent voltage buildup, each pin is protected by internal circuitry. Standard ESD-protection circuits safely shunt the ESD current by providing a mechanism whereby one or more transistors break down at voltages higher than normal operating voltages but lower than the breakdown voltage of the input gate. This type of protection scheme is limited by leakage currents which flow through the shunting transistors during normal operation after an ESD voltage has occurred. Although these currents are small, on the order of tens of nanoamps, CMOS amplifiers are often specified to draw input currents as low as tens of picoamps. To overcome this limitation, TI design engineers developed the patented ESD-protection circuit shown in Figure 4. This circuit can withstand several successive 1-kV ESD pulses, while reducing or eliminating leakage currents that may be drawn through the input pins. A more detailed discussion of the operation of TI’s ESD-protection circuit is presented on the next page. All input an output pins of LinCMOS and Advanced LinCMOS products have associated ESD-protection circuitry that undergoes qualification testing to withstand 1000 V discharged from a 100-pF capacitor through a 1500-Ω resistor (human body model) and 200 V from a 100-pF capacitor with no current-limiting resistor (charged device model). These tests simulate both operator and machine handling of devices during normal test and assembly operations. VDD R1 Input To Protected Circuit R2 Q1 Q2 D1 D2 D3 VSS Figure 4. LinCMOS ESD-Protection Schematic 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC374, TLC374Q, TLC374Y LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS SLCS118C – NOVEMBER 1983 – REVISED MARCH 1999 PRINCIPLES OF OPERATION Input protection circuit operation Texas Instruments patented protection circuitry allows for both positive- and negative-going ESD transients. These transients are characterized by extremely fast rise times and usually low energies, and can occur both when the device has all pins open and when it is installed in a circuit. positive ESD transients Initial positive charged energy is shunted through Q1 to VSS. Q1 turns on when the voltage at the input rises above the voltage on VDD by a value equal to the VEB of Q1. The base current increases through R2 with input current as Q1 saturates. The base current through R2 as Q1 saturates forces the voltage at the drain and gate of Q2 to exceed its threshold level (VT ∼ 22 to 26 V) and turn on Q2. The shunted input current through Q1 to VSS is now shunted through the n-channel enhancement-type MOSFET Q2 to VSS. If the voltage on the input pin continues to rise, the breakdown voltage of d3 is exceeded and all remaining energy is dissipated in R1 and D3. The breakdown voltage of D3 is designed to be 24 V to 27 V, which is well below the gate oxide voltage of the circuit to be protected. negative ESD transients The negative charged ESD transients are shunted directly through D1. Additional energy is dissipated in R1 and D2 as D2 becomes forward-biased. The voltage seen by the protected circuit is – 0.3 V to – 1 V (the forward voltage of D1 and D2). circuit-design considerations LinCMOS products are being used in actual circuits environments that have input voltages that exceed the recommended common-mode input voltage range and activate the input protection circuit. Even under normal operation, these conditions occur during circuit power up or power down, and in many cases, when the device is being used for a signal conditioning function. The input voltages can exceed VICR and not damage the device only if the inputs are current limited. The recommended current limit shown on most product data sheets is ± 5 mA. Figures 5 and 6 show typical characteristics for input voltage vs input current. Normal operation and correct output state can be expected even when the input voltage exceeds the positive supply voltage. The input current should be externally limited even through internal positive current limiting is achieved in the input protection circuit by the action of Q1. When Q1 is on, it saturates and limits the current to approximately 5-mA collector current by design. When saturated, Q1 base current increases with input current. This current is forced into the VDD pin and into the device IDD or the VDD supply through R2 producing the current limiting effects shown in Figure 5. This internal limiting lasts only as long as the input voltage is below the VT of Q2. When the input voltage exceeds the negative supply voltage, normal operation is affected and output voltage states may not be correct. Also, the isolation between channels of multiple devices (duals and quads) can be severely affected. External current limiting must be used since this current is directly shunted by D1 and D2, and no internal limiting is achieved. If normal output voltage states are required, an external input voltage clamp is required (see Figure 7). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TLC374, TLC374Q, TLC374Y LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS SLCS118C – NOVEMBER 1983 – REVISED MARCH 1999 PRINCIPLES OF OPERATION INPUT CURRENT vs INPUT VOLTAGE† INPUT CURRENT vs INPUT VOLTAGE† 8 10 TA = 25°C 9 7 TA = 25°C IIII – Input Current – mA IIII – Input Current – mA 8 6 5 4 3 7 6 5 4 3 2 2 1 1 0 VDD VDD + 4 VDD + 8 VI – Input Voltage – V 0 VDD– 0.3 VDD + 12 † The dashed line identifies an area of operation where some degradation of parametric performance may be experienced. VDD – 0.5 VDD – 0.7 VI – Input Voltage – V VDD – 0.9 † The dashed line identifies an area of operation where some degradation of parametric performance may be experienced. Figure 5 Figure 6 VDD RL VI + VREF 1/4 TLC374 – See Note A RL Positive Voltage Input Current Limit: +VI – VDD – 0.3 V RI = 5 mA Negative Voltage Input Current Limit: –VI – VDD – (0.3 V) RI = 5 mA NOTE A: If the correct output state is required when the negative input exceeds VSS, a Schotty clamp is required. Figure 7. Typical Input Current-Limiting Configuration for a LinCMOS Comparator 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 5962-87659012A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 596287659012A TLC374MFKB 5962-8765901CA ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8765901CA TLC374MJB Samples TLC374CD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLC374C Samples TLC374CDG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLC374C Samples TLC374CDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLC374C Samples TLC374CN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TLC374CN Samples TLC374CN-A ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TLC374CN_A Samples TLC374CNS ACTIVE SO NS 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLC374 Samples TLC374CPW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 P374 Samples TLC374CPWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 P374 Samples TLC374ID ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TLC374I Samples TLC374IDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TLC374I Samples TLC374IN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TLC374IN Samples TLC374MD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 TLC374M Samples TLC374MDG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM TLC374M Samples TLC374MFKB ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 596287659012A TLC374MFKB TLC374MJ ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 TLC374MJ Samples TLC374MJB ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8765901CA TLC374MJB Samples Addendum-Page 1 Samples Samples PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of