TLC5510IPWG4

TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003 D D features D D D D D Analog Input Range – TLC5510 . . . 2 V Full Scale – TLC5510A . . . 4 V Full Scale 8-Bit Resolution Integral Linearity Error ± 0.75 LSB Max (25°C) ± 1 LSB Max (– 20°C to 75°C) Differential Linearity Error ± 0.5 LSB Max (25°C) ± 0.75 LSB Max (– 20°C to 75°C) Maximum Conversion Rate 20 Mega-Samples per Second (MSPS) Max D 5-V Single-Supply Operation Low Power Consumption TLC5510 . . . 127.5 mW Typ TLC5510A . . . 150 mW Typ (includes reference resistor dissipation) TLC5510 is Interchangeable With Sony CXD1175 applications D D D D D Digital TV Medical Imaging Video Conferencing High-Speed Data Conversion QAM Demodulators PW OR NS PACKAGE† (TOP VIEW) description The TLC5510 and TLC5510A are CMOS, 8-bit, 20 MSPS analog-to-digital converters (ADCs) that utilize a semiflash architecture. The TLC5510 and TLC5510A operate with a single 5-V supply and typically consume only 130 mW of power. Included is an internal sample-and-hold circuit, parallel outputs with high-impedance mode, and internal reference resistors. OE DGND D1(LSB) D2 D3 D4 D5 D6 D7 D8(MSB) VDDD CLK The semiflash architecture reduces power consumption and die size compared to flash converters. By implementing the conversion in a 2-step process, the number of comparators is significantly reduced. The latency of the data output valid is 2.5 clocks. 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 DGND REFB REFBS AGND AGND ANALOG IN VDDA REFT REFTS VDDA VDDA VDDD † Available in tape and reel only and ordered as the shown in the Available Options table below. The TLC5510 uses the three internal reference resistors to create a standard, 2-V, full-scale conversion range using VDDA. Only external jumpers are required to implement this option and eliminates the need for external reference resistors. The TLC5510A uses only the center internal resistor section with an externally applied 4-V reference such that a 4-V input signal can be used. Differential linearity is 0.5 LSB at 25°C and a maximum of 0.75 LSB over the full operating temperature range. Typical dynamic specifications include a differential gain of 1% and differential phase of 0.7 degrees. The TLC5510 and TLC5510A are characterized for operation from –20°C to 75°C. AVAILABLE OPTIONS PACKAGE TA – 20°C to 75°C TSSOP (PW) FULL SCALE MAXIMUM FULL-SCALE INPUT VOLTAGE SOP (NS) (TAPE AND REEL ONLY) TLC5510IPW TLC5510INSLE 2V – TLC5510AINSLE 4V Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  1994 – 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003 functional block diagram Resistor Reference Divider OE REFB 270 Ω NOM Lower Sampling Comparators (4-Bit) REFT REFBS Lower Encoder (4-Bit) D1(LSB) D2 Lower Data Latch 80 Ω NOM D3 AGND D4 Lower Sampling Comparators (4-Bit) AGND Lower Encoder (4-Bit) VDDA D5 320 Ω NOM REFTS ANALOG IN CLK D6 Upper Data Latch Upper Sampling Comparators (4-Bit) D7 Upper Encoder (4-Bit) D8(MSB) Clock Generator schematics of inputs and outputs EQUIVALENT OF ANALOG INPUT EQUIVALENT OF EACH DIGITAL INPUT VDDA AGND VDDD D1 – D8 OE, CLK ANALOG IN 2 VDDD EQUIVALENT OF EACH DIGITAL OUTPUT DGND POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGND TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003 Terminal Functions TERMINAL NAME AGND NO. I/O 20, 21 DESCRIPTION Analog ground ANALOG IN 19 I Analog input CLK 12 I Clock input DGND 2, 24 D1 – D8 3 – 10 O Digital data out. D1 = LSB, D8 = MSB 1 I Output enable. When OE = low, data is enabled. When OE = high, D1 – D8 is in high-impedance state. OE VDDA VDDD 14, 15, 18 REFB 23 REFBS 22 REFT 17 REFTS 16 Digital ground Analog supply voltage 11, 13 Digital supply voltage I Reference voltage in bottom Reference voltage in bottom. When using the TLC5510 internal voltage divider to generate a nominal 2-V reference, REFBS is shorted to REFB (see Figure 3). When using the TLC5510A, REFBS is connected to ground. I Reference voltage in top Reference voltage in top. When using the TLC5510 internal voltage divider to generate a nominal 2-V reference, REFTS is shorted to REFT (see Figure 3). When using the TLC5510A, REFTS is connected to VDDA. absolute maximum ratings† Supply voltage, VDDA, VDDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Reference voltage input range, VREFT, VREFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to VDDA Analog input voltage range, VI(ANLG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to VDDA Digital input voltage range, VI(DGTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to VDDD Digital output voltage range, VO(DGTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to VDDD Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 20°C to 75°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions Supply voltage MIN NOM MAX VDDA – AGND VDDD – AGND 4.75 5 5.25 4.75 5 5.25 AGND – DGND – 100 0 100 Reference input voltage (top), Vref(T)‡ TLC5510A Reference input voltage (bottom), Vref(B)‡ TLC5510A Analog input voltage range, VI(ANLG) VREFB+2 0 VREFB 4 High-level input voltage, VIH Low-level input voltage, VIL 4 VREFT– 4 VREFT UNIT V mV V V V V 1 V Pulse duration, clock high, tw(H) (see Figure 1) 25 ns Pulse duration, clock low, tw(L) (see Figure 1) 25 ns ‡ The reference voltage levels for the TLC5510 are derived through an internal resistor divider between VDDA and ground and therefore are not derived from a separate external voltage source (see the electrical characteristics and text). For the 4 V input range of the TLC5510A, the reference voltage is externally applied across the center divider resistor. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003 electrical characteristics at VDD = 5 V, VREFT = 2.5 V, VREFB = 0.5 V, f(CLK) = 20 MHz, TA = 25°C (unless otherwise noted) digital I/O TEST CONDITIONS† PARAMETER MIN TYP MAX IIH IIL High-level input current Low-level input current VDD = MAX, VDD = MAX, VIH = VDD VIL = 0 5 IOH IOL High-level output current OE = GND, Low-level output current OE = GND, VDD = MIN, VDD = MIN, VOH = VDD – 0.5 V VOL = 0.4 V IOZH High-level high-impedance-state output leakage current OE = VDD, VDD = MAX VOH = VDD 16 IOZL Low-level high-impedance-state output leakage current OE = VDD, VDD = MIN VOL = 0 16 5 – 1.5 UNIT µA mA 2.5 µA † Conditions marked MIN or MAX are as stated in recommended operating conditions. power TEST CONDITIONS† PARAMETER IDD Supply current Ireff Reference voltage current MIN f(CLK) = 20 MHz, National Television System Committee (NTSC) ramp wave input, reference resistor dissipation is separate TLC5510 TLC5510A Vref = REFT – REFB = 2 V Vref = REFT – REFB = 4 V TYP MAX UNIT 18 27 mA 5.2 7.5 10.5 mA 10.4 15 21 mA † Conditions marked MIN or MAX are as stated in recommended operating conditions. static performance TEST CONDITIONS† PARAMETER Self-bias (1), at REFB Short REFB to REFBS, REFBS Short REFT to REFTS Self-bias (3), at REFT Short REFB to AGND, Short REFT to REFTS Rref Reference voltage resistor Between REFT and REFB Ci Analog input capacitance VI(ANLG) = 1.5 V + 0.07 Vrms TA = 25°C f(CLK) = 20 MHz,, VI = 0.5 V to 2.5 V TA = – 20°C to 75°C Self-bias (2), REFT – REFB TLC5510 Integral nonlinearity (INL) EFS Full-scale error 0.65 1.9 2.02 2.15 2.18 2.29 2.4 190 270 350 16 ± 0.75 ± 0.75 V Ω ±1 TLC5510A TLC5510 f(CLK) = 20 MHz,, VI = 0.5 V to 2.5 V TA = 25°C TA = – 20°C to 75°C ± 0.3 f(CLK) = 20 MHz,, VI = 0 to 4 V TA = 25°C TA = – 20°C to 75°C ± 0.3 TLC5510 UNIT pF ± 0.4 ± 0.4 ±1 ± 0.5 LSB ± 0.75 ± 0.5 ± 0.75 – 18 – 43 – 68 mV TLC5510A Vref = REFT – REFB = 2 V Vref= REFT – REFB = 4 V – 36 – 86 – 136 mV TLC5510 Vref = REFT – REFB = 2 V – 20 0 20 mV – 40 0 40 mV TLC5510A Vref = REFT – REFB = 4 V † Conditions marked MIN or MAX are as stated in recommended operating conditions. 4 MAX 0.61 TA = 25°C TA = – 20°C to 75°C TLC5510A Zero scale error Zero-scale TYP f(CLK) = 20 MHz,, VI = 0 to 4 V Differential nonlinearity (DNL) EZS MIN 0.57 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003 operating characteristics at VDD = 5 V, VREFT = 2.5 V, VREFB = 0.5 V, f(CLK) = 20 MHz, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS TLC5510 MIN TYP VI(ANLG) = 0.5 V – 2.5 V VI(ANLG) = 0 V – 4 V fconv Maximum conversion rate BW Analog input bandwidth At – 1 dB 14 td(D) Digital output delay time CL ≤ 10 pF (see Note 1 and Figure 1) 18 Differential gain NTSC 40 Institute of Radio Engineers (IRE) g ( ) modulation wave, fconv = 14.3 MSPS TLC5510A Differential phase tAJ td(s) Aperture jitter time ten Enable time, OE↓ to valid data tdis Disable time, OE↑ to high impedance fI = 1 1-kHz kHz ramp MSPS 20 MSPS MHz 30 ns 1% degrees 30 ps 4 ns CL = 10 pF 5 ns CL = 10 pF 7 ns Sampling delay time Input tone = 1 MHz TA = 25°C Full range 45 Input tone = 3 MHz TA = 25°C Full range 45 Input tone = 6 MHz TA = 25°C Full range 43 Input tone = 10 MHz TA = 25°C Full range 39 43 46 dB 42 39 TA = 25°C Full range Signal to noise ratio Signal-to-noise UNIT 20 0.7 Spurious free dynamic range (SFDR) SNR MAX 46 dB 44 NOTE 1: CL includes probe and jig capacitance. tw(H) tw(L) CLK (clock) td(s) ANALOG IN (input signal) D1 – D8 (output data) N+1 N N+2 N+4 N+3 N–3 N–2 N–1 N N+1 td(D) Figure 1. I/O Timing Diagram POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003 PRINCIPLES OF OPERATION functional description The TLC5510 and TLC5510A are semiflash ADCs featuring two lower comparator blocks of four bits each. As shown in Figure 2, input voltage VI(1) is sampled with the falling edge of CLK1 to the upper comparators block and the lower comparators block(A), S(1). The upper comparators block finalizes the upper data UD(1) with the rising edge of CLK2, and simultaneously, the lower reference voltage generates the voltage RV(1) corresponding to the upper data. The lower comparators block (A) finalizes the lower data LD(1) with the rising edge of CLK3. UD(1) and LD(1) are combined and output as OUT(1) with the rising edge of CLK4. As shown in Figure 2, the output data is delayed 2.5 clocks from the analog input voltage sampling point. Input voltage VI(2) is sampled with the falling edge of CLK2. UD(2) is finalized with the rising edge of CLK3, and LD(2) is finalized with the rising edge of CLK4 at the lower comparators block(B). OUT(2) data appears with the rising edge of CLK5. VI(1) VI(2) VI(3) VI(4) ANALOG IN (sampling points) CLK1 CLK2 CLK3 CLK4 CLK5 CLK (clock) Upper Comparators Block S(1) C(1) S(2) C(2) S(3) C(3) C(4) Upper Data UD(0) UD(1) UD(2) UD(3) Lower Reference Voltage RV(0) RV(1) RV(2) RV(3) S(1) Lower Comparators Block (A) H(1) Lower Comparators Block (B) Lower Data (B) D1 – D8 (data output) C(1) S(3) H(3) LD(– 1) Lower Data (A) H(0) C(0) S(2) LD(– 2) OUT(– 2) POST OFFICE BOX 655303 C(3) LD(1) H(2) C(2) LD(0) OUT(–1) S(4) H(4) LD(2) OUT(0) Figure 2. Internal Functional Timing Diagram 6 S(4) • DALLAS, TEXAS 75265 OUT(1) TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003 PRINCIPLES OF OPERATION internal referencing TLC5510 The three internal resistors shown with VDDA can generate a 2-V reference voltage. These resistors are brought out on VDDA, REFTS, REFT, REFB, REFBS, and AGND. To use the internally generated reference voltage, terminal connections should be made as shown in Figure 3. This connection provides the standard video 2-V reference for the nominal digital output. TLC5510 VDDA (analog supply) REFTS 18 R1 320 Ω NOM 16 17 REFT REFB Rref 270 Ω NOM 23 22 REFBS AGND R2 80 Ω NOM 21 Figure 3. External Connections for a 2-V Analog Input Span Using the Internal-Reference Resistor Divider TLC5510A For an analog input span of 4 V, 4 V is supplied to REFT, and REFB is grounded and terminal connections should be made as shown in Figure 4. This connection provides the 4-V reference for the nominal zero to full-scale digital output with a 4 Vpp analog input at ANALOG IN. TLC5510A 18 VDDA (analog supply) R1 320 Ω NOM 16 REFTS 4V 17 REFT REFB Rref 270 Ω NOM 23 REFBS 22 R2 80 Ω NOM 21 AGND Figure 4. External Connections for 4-V Analog Input Span POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003 PRINCIPLES OF OPERATION functional operation The output code change with input voltage is shown in Table 1. Table 1. Functional Operation DIGITAL OUTPUT CODE INPUT SIGNAL VOLTAGE STEP Vref(B) 255 0 0 0 0 0 0 0 0 • • • • • • • • • • MSB LSB • • • • • • • • • • • 128 0 1 1 1 1 1 1 1 • 127 1 0 0 0 0 0 0 0 • • • • • • • • • • • • • • • • • • • • Vref(T) 0 1 1 1 1 1 1 1 1 APPLICATION INFORMATION The following notes are design recommendations that should be used with the device. D D D D D D 8 External analog and digital circuitry should be physically separated and shielded as much as possible to reduce system noise. RF breadboarding or printed-circuit-board (PCB) techniques should be used throughout the evaluation and production process. Breadboards should be copper clad for bench evaluation. Since AGND and DGND are connected internally, the ground lead in must be kept as noise free as possible. A good method to use is twisted-pair cables for the supply lines to minimize noise pickup. An analog and digital ground plane should be used on PCB layouts when additional logic devices are used. The AGND and DGND terminals of the device should be tied to the analog ground plane. VDDA to AGND and VDDD to DGND should be decoupled with 1-µF and 0.01-µF capacitors, respectively, and placed as close as possible to the affected device terminals. A ceramic-chip capacitor is recommended for the 0.01-µF capacitor. Care should be exercised to ensure a solid noise-free ground connection for the analog and digital ground terminals. VDDA, AGND, and ANALOG IN should be shielded from the higher frequency terminals, CLK and D0–D7. When possible, AGND traces should be placed on both sides of the ANALOG IN traces on the PCB for shielding. In testing or application of the device, the resistance of the driving source connected to the analog input should be 10 Ω or less within the analog frequency range of interest. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003 APPLICATION INFORMATION DVDD 5V C12 TLC5510 AVDD 5V 13 VREF ADJ FB3 14 C8 FB2 R5 FB7 Video Input J1 C1 16 17 18 C11 C6 FB1 R4 VDDA VDDD VDDA D8 (MSB) 12 Clock 11 10 C11 REFTS D7 REFT D6 VDDA D5 ANALOG IN D4 AGND D3 AGND D2 9 8 C9 R3 D1 CLK C7 JP1 JP2 C3 TP1 Q1 15 VDDD R2 19 R1 C5 C2 20 D3 21 C4 –5V D2 JP3 JP4 22 TP3 C10 23 24 REFBS D1 (LSB) REFB DGND DGND OE 7 6 5 4 3 2 1 Output Enable NOTE A: Shorting JP1 and JP3 allows adjustment of the reference voltage by R5 using temperature-compensating diodes D2 and D3 which compensate for D1 and Q1 variations. By shorting JP2 and JP4, the internal divider generates a nominal 2-V reference. LOCATION DESCRIPTION C1, C3 – C4, C6 – C12 0.1-µF capacitor C2 10-pF capacitor C5 47-µF capacitor FB1, FB2, FB3, FB7 Q1 Ferrite bead 2N3414 or equivalent R1, R3 75-Ω resistor R2 500-Ω resistor R4 10-kΩ resistor, clamp voltage adjust R5 300-Ω resistor, reference-voltage fine adjust Figure 5. TLC5510 Evaluation and Test Schematic POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003 APPLICATION INFORMATION DVDD 5V C4 TLC5510A AVDD 5V 13 VREF ADJ FB3 14 C8 FB2 R5 15 J1 C1 16 C3 TP1 Q1 17 C11 R4 VDDA VDDD VDDA D8 (MSB) 12 Clock 11 10 C11 REFTS D7 REFT D6 VDDA D5 ANALOG IN D4 AGND D3 AGND D2 9 8 C9 R3 D1 CLK C7 FB7 Video Input VDDD 18 FB1 C6 R2 19 R1 C5 C2 20 21 –5V 22 23 24 REFBS D1 (LSB) REFB DGND DGND OE 7 6 5 4 3 2 1 NOTE A: R5 allows adjustment of the reference voltage to 4 V. R4 adjusts for the desired Q1 quiescent operating point. DESCRIPTION LOCATION C1, C3 – C4, C6 – C11 0.1-µF capacitor C2 10-pF capacitor C5 47-µF capacitor FB1, FB2, FB3, FB7 Q1 Ferrite bead 2N3414 or equivalent R1, R3 75-Ω resistor R2 500-Ω resistor R4 10-kΩ resistor, clamp voltage adjust R5 300-Ω resistor, reference-voltage fine adjust Figure 6. TLC5510A Evaluation and Test Schematic 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Output Enable TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003 APPLICATION INFORMATION AVDD 5V 4.7 µF + 1 kΩ 0.1 µF 10 kΩ POT CLOCK 1 kΩ 4.7 µF TLC5510 THS3001 49.9 Ω AVSS – 5V 4.7 µF 49.9 Ω + _ CLOCK ANALOG IN 100 pF 681 Ω 0.1 µF 681 Ω + FB1† 4.7 µF + FB3 + 4.7 µF 4.7 µF + 0.1 µF + 0.1 µF + 4.7 µF VDDA VDDA VDDA 0.1 µF OE D1 D2 D3 D4 D5 D6 D7 D8 DVDD 5V 4.7 µF REFTS 0.1 µF VDDD VDDD REFT 4.7 µF + To Processor 0.1 µF 0.1 µF REFBS 0.1 µF REFB DGND DGND 4.7 µF AGND AGND † FB – Ferrite Bead Figure 7. TLC5510 Application Schematic POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003 APPLICATION INFORMATION AV DD +5V 0.1µF + 6.8µF CLOCK 698Ω 0.1µF TLC5510A 50Ω 49.9Ω OPA690 59Ω 698Ω OE CLOCK ANALOG IN 100pF D1 D2 D3 D4 D5 D6 D7 D8 402Ω 402Ω 0.1µF FB1† + FB3 + 4.7µF 0.1µF + 4.7µF 0.1µF + VDDA VDDA VDDA 4.7µF 4.7µF DVDD +5V 0.1µF 4.7µF VREF 4V 4.7µF REFTS REFT REFBS REFB VDDD VDDD 0.1µF DGND DGND AGND AGND † FB — Ferrite Bead Figure 8. TLC5510A Application Schematic 12 To Processor POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0.1µF 4.7µF PACKAGE OPTION ADDENDUM www.ti.com 29-Sep-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) (Requires Login) TLC5510AINS ACTIVE SO NS 24 34 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC5510AINSG4 ACTIVE SO NS 24 34 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC5510AINSLE OBSOLETE SO NS 24 TLC5510AINSR ACTIVE SO NS 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC5510AINSRG4 ACTIVE SO NS 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC5510INS ACTIVE SO NS 24 34 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC5510INSG4 ACTIVE SO NS 24 34 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC5510INSLE OBSOLETE SO NS 24 TLC5510INSR ACTIVE SO NS 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC5510INSRG4 ACTIVE SO NS 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC5510IPW ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC5510IPWG4 ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC5510IPWR ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC5510IPWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TBD TBD (1) Call TI Call TI Call TI Call TI The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 29-Sep-2011 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLC5510AINSR Package Package Pins Type Drawing SO SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) NS 24 2000 330.0 24.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.2 15.4 2.5 12.0 24.0 Q1 TLC5510INSR SO NS 24 2000 330.0 24.4 8.2 15.4 2.5 12.0 24.0 Q1 TLC5510IPWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC5510AINSR SO NS 24 2000 367.0 367.0 45.0 TLC5510INSR SO NS 24 2000 367.0 367.0 45.0 TLC5510IPWR TSSOP PW 24 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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