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TLC5916-Q1, TLC5917-Q1
SLVS814A – JANUARY 2008 – REVISED MAY 2015
TLC591x-Q1 8-Bit Constant-Current LED Sink Drivers
1 Features
2 Applications
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1
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Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 1C
– Device CDM ESD Classification Level C4
Eight Constant-Current Output Channels
Output Current Adjusted Through External
Resistor
Constant Output Current Range: 5 mA to 120 mA
Constant Output Current Invariant to Load Voltage
Change
Open Load, Short Load, and Overtemperature
Detection
256-Step Programmable Global Current Gain
Excellent Output Current Accuracy:
– Between Channels: < ±3% (Maximum)
– Between ICs: < ±6% (Maximum)
Fast Response of Output Current
30-MHz Clock Frequency
Schmitt Trigger Input
3.3-V or 5-V Supply Voltage
Thermal Shutdown for Overtemperature
Protection
General LED Lighting Applications
LED Display Systems
LED Signage
Automotive LED Lighting
White Goods
Gaming Machines and Entertainment
3 Description
The TLC591x-Q1 Constant-Current LED Sink Drivers
is designed to work alone or cascaded. Because
each output is independently controlled, they can be
programmed to be on or off by the user. The high
LED voltage (VLED) allows for the use of one LED
per output or multiple LEDs on a single string. With
independently controlled outputs supplied with
constant current, the LEDs can be combined in
parallel to create higher currents on a single string.
The constant sink current for all channels is set
through a single external resistor. This allows
different LED drivers in the same application to sink
various
currents
which
provides
optional
implementation of multicolor LEDs. An additional
advantage of the independent outputs is the ability to
leave unused channels floating. The flexibility of the
TLC591x-Q1 LED driver is ideal for applications such
as (but not limited to): automotive LED lighting, 7segment displays, scrolling single-color displays,
gaming machines, white goods, video billboards, and
video panels.
Device Information(1)
PART NUMBER
TLC591x-Q1
PACKAGE
SOIC (16)
BODY SIZE (NOM)
9.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Single Implementation of TLC591x-Q1 Device
SDI
CLK
CLK
LE
LE
OE
OE
TLC5916/TLC5917-Q1
Controller
SDI
OUT7
VDD: 3.0V to 5.5V
OUT0
VLED
VDD
SDO
To Controller if Error
Detection Used
R-EXT
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLC5916-Q1, TLC5917-Q1
SLVS814A – JANUARY 2008 – REVISED MAY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
8
9
1
1
1
2
3
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Electrical Characteristics: VDD = 3 V ....................... 6
Electrical Characteristics: VDD = 5.5 V .................... 7
Timing Requirements ................................................ 8
Switching Characteristics: VDD = 3 V....................... 9
Switching Characteristics: VDD = 5.5 V.................. 10
Typical Characteristics .......................................... 11
Parameter Measurement Information ................ 12
Detailed Description ............................................ 15
9.1
9.2
9.3
9.4
9.5
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
15
15
15
17
21
10 Application and Implementation........................ 24
10.1 Application Information.......................................... 24
10.2 Typical Applications .............................................. 25
11 Power Supply Recommendations ..................... 28
12 Layout................................................................... 28
12.1 Layout Guidelines ................................................. 28
12.2 Layout Example .................................................... 28
13 Device and Documentation Support ................. 29
13.1
13.2
13.3
13.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
29
29
29
29
14 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
Changes from Original (January 2008) to Revision A
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
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Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: TLC5916-Q1 TLC5917-Q1
TLC5916-Q1, TLC5917-Q1
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SLVS814A – JANUARY 2008 – REVISED MAY 2015
5 Device Comparison Table
OVERTEMPERATURE
DETECTION
OPEN-LOAD
DETECTION
SHORT TO GND
DETECTION
TLC5916-Q1
X
X
X
TLC5917-Q1
X
X
X
DEVICE (1)
(1)
SHORT TO VLED
DETECTION
X
The device has one error register for all these conditions (1 error bit per channel).
6 Pin Configuration and Functions
D Package
16-Pin SOIC
Top View
GND
SDI
CLK
LE(ED1)
OUT0
OUT1
OUT2
OUT3
1
16
2
15
3
14
4
5
13
6
11
7
10
8
9
12
VDD
R-EXT
SDO
OE(ED2)
OUT7
OUT6
OUT5
OUT4
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
CLK
3
I
Clock input for data shift on rising edge
GND
1
—
Ground for control logic and current sink
LE(ED1)
4
I
Data strobe input. Serial data is transferred to the respective latch when LE(ED1) is high. The data is
latched when LE(ED1) goes low. Also, LE(ED1) is a control signal input for an Error Detection mode
and Current Adjust mode (See Timing Diagram). LE(ED1) has an internal pulldown.
OE(ED2)
13
I
Output enable. When OE(ED2) is active (low), the output drivers are enabled; when OE(ED2) is high,
all output drivers are turned OFF (blanked). Also, OE(ED2) is a control signal input for an Error
Detection mode and Current Adjust mode (See Timing Diagram). OE(ED2) has an internal pullup.
OUT0 to
OUT7
5 to 12
O
Constant-current outputs
R-EXT
15
I
Input used to connect an external resistor for setting up all output currents
SDI
2
I
Serial-data input to the Shift register
SDO
14
O
Serial-data output to the following SDI of next driver IC or to the microcontroller
VDD
16
I
Supply voltage
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Product Folder Links: TLC5916-Q1 TLC5917-Q1
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
VDD (2)
VI
(3)
(1)
Supply voltage
MIN
MAX
UNIT
0
7
V
V
Input voltage
–0.4
VDD + 0.4
VO (4)
Output voltage
–0.5
20
V
fclk
Clock frequency
25
MHz
IOUT
Output current
120
mA
IGND
GND terminal current
960
mA
TA
Operating free-air temperature
–40
125
°C
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–55
150
°C
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND.
Absolute negative voltage on these terminals must not go below 0 V.
Absolute maximum voltage is 7 V for 200 ms.
7.2 ESD Ratings
VALUE
(1)
±1500
Other pins
±1000
Corner pins (GND, OUT3, VDD,
and OUT4)
±1000
Human body model (HBM), per AEC Q100-002
V(ESD)
Electrostatic discharge
Charged device model (CDM), per
AEC Q100-011
Machine Model
(1)
UNIT
V
±150
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
MIN
VDD
Supply voltage
VO
Supply voltage to output pins
3
OUT0–OUT7
VO ≥ 0.6 V
NOM
MAX
UNIT
5.5
V
17
V
5
IO
Output current
DC test circuit
IOH
High-level output current source
SDO shorted to GND
–1
mA
IOL
Low-level output current sink
SDO shorted to VCC
1
mA
VIH
High-level input voltage
CLK, OE(ED2), LE(ED1), and SDI
VIL
4
Low-level input voltage
Submit Documentation Feedback
VO ≥ 1 V
120
CLK, OE(ED2), LE(ED1), and SDI
mA
0.7 × VDD
VDD
V
0
0.3 ×
VDD
V
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: TLC5916-Q1 TLC5917-Q1
TLC5916-Q1, TLC5917-Q1
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SLVS814A – JANUARY 2008 – REVISED MAY 2015
7.4 Thermal Information
TLC591x-Q1
THERMAL METRIC (1)
D (SOIC)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
86.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
47.7
°C/W
RθJB
Junction-to-board thermal resistance
43.9
°C/W
ψJT
Junction-to-top characterization parameter
11.9
°C/W
ψJB
Junction-to-board characterization parameter
43.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: TLC5916-Q1 TLC5917-Q1
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7.5 Electrical Characteristics: VDD = 3 V
VDD = 3 V, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VDD
Input voltage
VO
Supply voltage to the output pins
MIN
TYP (1)
3
VO ≥ 0.6 V
IO
Output current
IOH
High-level output current, source
IOL
Low-level output current, sink
VIH
High-level input voltage
VIL
Low-level input voltage
MAX
5.5
V
17
V
5
VO ≥ 1 V
120
–1
mA
0.7 × VDD
VDD
V
GND
0.3 × VDD
V
TJ = 25°C
0.5
Output leakage current
VOH = 17 V
VOH
High-level output voltage
SDO, IOL = –1 mA
VOL
Low-level output voltage
SDO, IOH = 1 mA
Output current 1
VOUT = 0.6 V, Rext = 720 Ω,
CG = 0.992
Output current error, die-die
IOL = 26 mA, VO = 0.6 V, Rext = 720 Ω,
TJ = 25°C
±3%
±6%
Output current skew, channel-tochannel
IOL = 26 mA, VO = 0.6 V, Rext = 720 Ω,
TJ = 25°C
±1.5%
±3%
Output current 2
VO = 0.8 V, Rext = 360 Ω, CG = 0.992
Output current error, die-die
IOL = 52 mA, VO = 0.8 V, Rext = 360 Ω,
TJ = 25°C
±2%
±6%
Output current skew, channel-tochannel
IOL = 52 mA, VO = 0.8 V, Rext = 360 Ω,
TJ = 25°C
±1.5%
±3%
IO(2)
IOUT vs
VOUT
TJ = 125°C
2
VDD – 0.4
26
Pullup resistance
OE(ED2)
500
kΩ
Pulldown resistance
LE(ED1)
500
kΩ
(2)
Restart temperature hysteresis
IOUT,Th1
Threshold current for open error
detection
IOUT,target = 26 mA
0.5 ×
Itarget%
IOUT,Th2
Threshold current for open error
detection
IOUT,target = 52 mA
0.5 ×
Itarget%
IOUT,Th3
Threshold current for open error
detection
IOUT,target = 104 mA
0.5 ×
Itarget%
IOUT,Th
Threshold current for open error
detection
IOUT,target = 5 mA to 120 mA
0.5 ×
Itarget%
VOUT,TTh
Trigger threshold voltage for
short-error detection (TLC5917Q1 only)
IOUT,target = 5 mA to 120 mA
2.44
VOUT,RTh
Return threshold voltage for
short-error detection (TLC5917Q1 only)
IOUT,target = 5 mA to 120 mA
2.2
6
%/V
±1
Overtemperature shutdown
(2)
mA
±0.1
VDD = 3 V to 5.5 V,
IO = 26 mA/120 mA
Thys
(1)
V
mA
52
Tsd
IDD
μA
V
0.4
VO = 1 V to 3 V, IO = 26 mA
Output current vs
output voltage regulation
mA
mA
1
Ileak
IO(1)
UNIT
Supply current
150
175
200
15
2.7
°C
°C
3.1
V
V
Rext = Open
5
10
Rext = 720 Ω
8
14
Rext = 360 Ω
11
18
Rext = 180 Ω
16
22
mA
Typical values represent the likely parametric nominal values determined at the time of characterization. Typical values depend on the
application and configuration and may vary over time. Typical values are not ensured on production material.
Specified by design
Submit Documentation Feedback
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TLC5916-Q1, TLC5917-Q1
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SLVS814A – JANUARY 2008 – REVISED MAY 2015
7.6 Electrical Characteristics: VDD = 5.5 V
VDD = 5.5 V, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VDD
Input Voltage
VO
Supply voltage to the output pins
MIN
TYP (1)
3
VO ≥ 0.6 V
IO
Output current
IOH
High-level output current, source
IOL
Low-level output current, sink
VIH
High-level input voltage
VIL
Low-level input voltage
MAX
5.5
V
17
V
5
VO ≥ 1 V
120
–1
mA
0.7 × VDD
VDD
V
GND
0.3 × VDD
V
TJ = 25°C
0.5
Output leakage current
VOH = 17 V
VOH
High-level output voltage
SDO, IOL = –1 mA
VOL
Low-level output voltage
SDO, IOH = 1 mA
Output current 1
VOUT = 0.6 V, Rext = 720 Ω,
CG = 0.992
Output current error, die-die
IOL = 26 mA, VO = 0.6 V, Rext = 720 Ω,
TJ = 25°C
±3%
±6%
Output current skew, channel-tochannel
IOL = 26 mA, VO = 0.6 V, Rext = 720 Ω,
TJ = 25°C
±1.5%
±3%
Output current 2
VO = 0.8 V, Rext = 360 Ω, CG = 0.992
Output current error, die-die
IOL = 52 mA, VO = 0.8 V, Rext = 360 Ω,
TJ = 25°C
±2%
±6%
Output current skew, channel-tochannel
IOL = 52 mA, VO = 0.8 V, Rext = 360 Ω,
TJ = 25°C
±1.5%
±3%
IO(2)
IOUT vs
VOUT
TJ = 125°C
2
VDD – 0.4
26
%/V
±1
Pullup resistance
OE(ED2),
500
kΩ
Pulldown resistance
LE(ED1),
500
kΩ
(2)
Overtemperature shutdown
Restart temperature hysteresis
IOUT,Th1
Threshold current for open error
detection
IOUT,target = 26 mA
0.5 ×
Itarget%
IOUT,Th2
Threshold current for open error
detection
IOUT,target = 52 mA
0.5 ×
Itarget%
IOUT,Th3
Threshold current for open error
detection
IOUT,target = 104 mA
0.5 ×
Itarget%
IOUT,Th
Threshold current for open error
detection
IOUT,target = 5 mA to 120 mA
0.5 ×
Itarget%
VOUT,TTh
Trigger threshold voltage for
short-error detection (TLC5917Q1 only)
IOUT,target = 5 mA to 120 mA
2.44
VOUT,RTh
Return threshold voltage for
short-error detection (TLC5917Q1 only)
IOUT,target = 5 mA to 120 mA
2.2
(2)
mA
±0.1
VDD = 3 V to 5.5 V,
IO = 26 mA/120 mA
Thys
(1)
V
mA
52
Tsd
IDD
μA
V
0.4
VO = 1 V to 3 V , IO = 26 mA
Output current vs
output voltage regulation
mA
mA
1
Ileak
IO(1)
UNIT
Supply current
150
175
200
15
2.7
°C
°C
3.1
V
V
Rext = Open
6
10
Rext = 720 Ω
11
14
Rext = 360 Ω
13
18
Rext = 180 Ω
19
24
mA
Typical values represent the likely parametric nominal values determined at the time of characterization. Typical values depend on the
application and configuration and may vary over time. Typical values are not ensured on production material.
Specified by design
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7.7 Timing Requirements
VDD = 3 V to 5.5 V (unless otherwise noted)
MIN
NOM
MAX
UNIT
tw(L)
LE(ED1) pulse duration
Normal mode
20
ns
tw(CLK)
CLK pulse duration
Normal mode
20
ns
Normal mode, IOUT < 60 mA
675
Normal mode, IOUT > 60 mA
800
tw(OE)
OE(ED2) pulse duration
tsu(D)
Setup time for SDI
Normal mode
3
ns
th(D)
Hold time for SDI
Normal mode
2
ns
tsu(L)
Setup time for LE(ED1)
Normal mode
15
ns
th(L)
Hold time for LE(ED1)
Normal mode
15
ns
tw(CLK)
CLK pulse duration
Error Detection mode
20
ns
tw(ED2)
OE(ED2) pulse duration
Error Detection mode
2000
ns
tsu(ED1)
Setup time for LE(ED1)
Error Detection mode
4
ns
th(ED1)
Hold time for LE(ED1)
Error Detection mode
10
ns
tsu(ED2)
Setup time for OE(ED2)
Error Detection mode
8.5
ns
th(ED2)
Hold time for OE(ED2)
Error Detection mode
10
ns
fCLK
Clock frequency
Cascade operation
8
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ns
30
MHz
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SLVS814A – JANUARY 2008 – REVISED MAY 2015
7.8 Switching Characteristics: VDD = 3 V
VDD = 3 V, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP (1)
MAX
UNIT
tPLH1
Low-to-high propagation delay time, CLK to OUTn
40
65
95
ns
tPLH2
Low-to-high propagation delay time, LE(ED1) to OUTn
40
65
95
ns
tPLH3
Low-to-high propagation delay time, OE(ED2) to OUTn
40
65
95
ns
tPLH4
Low-to-high propagation delay time, CLK to SDO
12
20
30
ns
tPHL1
High-to-low propagation delay time, CLK to OUTn
300
365
ns
tPHL2
High-to-low propagation delay time, LE(ED1) to OUTn
300
365
ns
tPHL3
High-to-low propagation delay time, OE(ED2) to OUTn
300
365
ns
tPHL4
High-to-low propagation delay time, CLK to SDO
12
20
30
ns
tw(CLK)
Pulse duration, CLK
20
ns
tw(L)
Pulse duration, LE(ED1)
20
ns
tw(OE)
Pulse duration, OE(ED2)
tw(ED2)
Pulse duration, OE(ED2) in Error Detection mode
th(ED1,ED2)
Hold time, LE(ED1) and OE(ED2)
th(D)
Hold time, SDI
tsu(D,ED1)
Setup time, SDI, LE(ED1)
tsu(ED2)
Setup time, OE(ED2)
th(L)
Hold time, LE(ED1), Normal mode
15
ns
tsu(L)
Setup time, LE(ED1), Normal mode
15
tr
Rise time, CLK (2)
500
ns
tf
Fall time, CLK (2)
500
ns
tor
Rise time, outputs (off)
85
105
ns
tor
Rise time, outputs (off), TJ = 25°C
83
100
ns
tof
Rise time, outputs (on)
280
370
ns
tof
Rise time, outputs (on), TJ = 25°C
170
225
ns
fCLK
Clock frequency
30
MHz
(1)
(2)
VIH = VDD, VIL = GND,
Rext = 360 Ω, VL = 4 V,
RL = 44 Ω, CL = 10 pF,
CG = 0.992
500
ns
2
μs
10
ns
2
ns
4
ns
8.5
ns
40
100
Cascade operation
ns
Typical values represent the likely parametric nominal values determined at the time of characterization. Typical values depend on the
application and configuration and may vary over time. Typical values are not ensured on production material.
If the devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer between two
cascaded devices.
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7.9 Switching Characteristics: VDD = 5.5 V
VDD = 5.5 V, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP (1)
MAX
UNIT
tPLH1
Low-to-high propagation delay time, CLK to OUTn
40
65
95
ns
tPLH2
Low-to-high propagation delay time, LE(ED1) to OUTn
40
65
95
ns
tPLH3
Low-to-high propagation delay time, OE(ED2) to OUTn
40
65
95
ns
tPLH4
Low-to-high propagation delay time, CLK to SDO
8
20
30
ns
tPHL1
High-to-low propagation delay time, CLK to OUTn
300
365
ns
tPHL2
High-to-low propagation delay time, LE(ED1) to OUTn
300
365
ns
tPHL3
High-to-low propagation delay time, OE(ED2) to OUTn
300
365
ns
tPHL4
High-to-low propagation delay time, CLK to SDO
20
30
ns
tw(CLK)
Pulse duration, CLK
20
ns
tw(L)
Pulse duration, LE(ED1)
20
ns
tw(OE)
Pulse duration, OE(ED2)
tw(ED2)
Pulse duration, OE(ED2) in Error Detection mode
th(D,ED1,ED2)
Hold time, SDI, LE(ED1), and OE(ED2)
th(D)
Hold time, SDI
tsu(D,ED1)
Setup time, SDI, LE(ED1)
tsu(ED2)
Setup time, OE(ED2)
th(L)
Hold time, LE(ED1), Normal mode
15
ns
tsu(L)
Setup time, LE(ED1), Normal mode
15
tr
Rise time, CLK (2)
500
ns
tf
Fall time, CLK (2)
500
ns
tor
Rise time, outputs (off)
85
105
ns
tor
Rise time, outputs (off), TJ = 25°C
83
100
ns
tof
Rise time, outputs (on)
280
370
ns
tof
Rise time, outputs (on), TJ = 25°C
170
225
ns
fCLK
Clock frequency
30
MHz
(1)
(2)
10
8
VIH = VDD, VIL = GND,
Rext = 360 Ω, VL = 4 V,
RL = 44 Ω, CL = 10 pF,
CG = 0.992
500
ns
2
μs
10
ns
2
ns
4
ns
8.5
ns
40
100
Cascade operation
ns
Typical values represent the likely parametric nominal values determined at the time of characterization. Typical values depend on the
application and configuration and may vary over time. Typical values are not ensured on production material.
If the devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer between two
cascaded devices.
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7.10 Typical Characteristics
Turn on only one channel
Channel 1
LE = 5 V (active)
OE = GND (active)
OE
CLK
OUTn
OUT1
Figure 1. Response Time, CLK to OUTn
Figure 2. Response Time, OE to OUT1
Turn on only one channel
Channel 8
OE
OUT7
Figure 3. Response Time, OE to OUT7
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8 Parameter Measurement Information
IDD
VDD
OE(ED2)
IIH, IIL
IOUT
OUT0
CLK
LE(ED1)
OUT7
SDI
VIH, VIL
R-EXT
GND
SDO
Iref
Figure 4. Test Circuit for Electrical Characteristics
IDD
IOUT
VDD
VIH, VIL
OE(ED2)
CLK
LE(ED1)
Function
Generator
OUT0
OUT7
RL
CL
SDI
Logic Input
Waveform
VIH = 5 V
VIL = 0V
R-EXT
Iref
GND
SDO
CL
VL
Figure 5. Test Circuit for Switching Characteristics
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Parameter Measurement Information (continued)
tw(CLK)
50%
CLK
50%
tsu(D)
SDI
50%
50%
th(D)
50%
50%
tPLH4, tPHL4
50%
SDO
tw(L)
50%
LE(ED1)
tsu(L)
th(L)
OE(ED2)
LOW
tPLH2, tPHL2
Output off
OUTn
50%
Output on
tPLH1, tPHL1
tw(OE)
OE(ED2)
HIGH
50%
50%
tPLH3
tPHL3
Output off
80%
80%
OUTn
50%
50%
20%
tof
20%
tor
Figure 6. Normal Mode Timing Waveforms
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Parameter Measurement Information (continued)
tw(CLK)
50%
CLK
tsu(ED2)
OE(ED2)
th(ED2)
50%
tsu(ED1)
LE(ED1)
th(ED1)
50%
2 CLK
Figure 7. Switching to Special Mode Timing Waveforms
CLK
OE(ED2)
50%
50%
tw(ED2)
Figure 8. Reading Error Status Code Timing Waveforms
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9 Detailed Description
9.1 Overview
The TLC591x-Q1 is designed for LED displays and LED lighting applications with constant-current control and
open-load, shorted-load, and overtemperature detection. The TLC591x-Q1 contains an 8-bit shift register and
data latches, which convert serial input data into parallel output format. At the output stage, eight regulated
current ports are designed to provide uniform and constant current for driving LEDs within a wide range of VF
variations. Used in system design for LED display applications, for example, LED panels, the TLC591x-Q1
device provides great flexibility and device performance. Users can adjust the output current from 5 mA to 120
mA through an external resistor, R-EXT, which gives flexibility in controlling the light intensity of LEDs. The
devices are designed for up to 17 V at the output port. The high clock frequency, 30 MHz, also satisfies the
system requirements of high-volume data transmission.
9.2 Functional Block Diagram
OUT0
OUT1
OUT6
OUT7
I/O Regulator
R-EXT
8
OE(ED2)
Output Driver and
Error Detection
Control
Logic
8
8
VDD
8-Bit Output
Latch
LE(ED1)
Configuration
Latches
8
CLK
8
8-Bit Shift
Register
SDI
SDO
8
9.3 Feature Description
9.3.1 Open-Circuit Detection Principle
The LED Open-Circuit Detection compares the effective current level Iout with the open load detection threshold
current IOUT,Th. If IOUT is below the IOUT,Th threshold, the TLC591x-Q1 detects an open-load condition. This error
status can be read as an error status code in the Special mode. For open-circuit error detection, a channel must
be on.
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Feature Description (continued)
Table 1. Open-Circuit Detection
STATE OF OUTPUT PORT
CONDITION OF OUTPUT
CURRENT
ERROR STATUS CODE
MEANING
Off
IOUT = 0 mA
0
Detection not possible
0
Open circuit
Channel n error status bit 1
Normal
IOUT < IOUT,Th
On
(1)
(1)
IOUT ≥ IOUT,Th (1)
IOUT,Th = 0.5 × IOUT,target (typical)
9.3.2 Short-Circuit Detection Principle (TLC5917-Q1 Only)
The LED short-circuit detection compares the effective voltage level (VOUT) with the shorted-load detection
threshold voltages VOUT,TTh and VOUT,RTh. If VOUT is above the VOUT,TTh threshold, the TLC5917-Q1 detects an
shorted-load condition. If VOUT is below the VOUT,RTh threshold, no error is detected and the error bit is reset. This
error status can be read as an error status code in the Special mode. For short-circuit error detection, a channel
must be on.
Table 2. Shorted-Load Detection
STATE OF OUTPUT PORT
CONDITION OF OUTPUT
VOLTAGE
ERROR STATUS CODE
MEANING
Off
On
IOUT = 0 mA
0
Detection not possible
VOUT ≥ VOUT,TTh
0
Short circuit
VOUT < VOUT,RTh
1
Normal
Minimum
Return
Threshold
Minimum
Trigger
Threshold
2.2 V
2.5 V
Maximum
Trigger
Threshold
No Fault
Short Fault
3.1 V
VOUT,RTh
VOUT,TTh
VOUT
Figure 9. Short-Circuit Detection Principle
9.3.3 Overtemperature Detection and Shutdown
TLC591x-Q1 is equipped with a global overtemperature sensor and eight individual, channel-specific,
overtemperature sensors.
• When the global sensor reaches the trip temperature, all output channels are shutdown, and the error status
is stored in the internal Error Status register of every channel. After shutdown, the channels automatically
restart after cooling down, if the control signal (output latch) remains on. The stored error status is not reset
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after cooling down and can be read out as the error status code in the Special mode.
When one of the channel-specific sensors reaches trip temperature, only the affected output channel is shut
down, and the error status is stored only in the internal Error Status register of the affected channel. After
shutdown, the channel automatically restarts after cooling down, if the control signal (output latch) remains
on. The stored error status is not reset after cooling down and can be read out as error status code in the
Special mode.
For channel-specific overtemperature error detection, a channel must be on.
The error status code is reset when TLC591x-Q1 returns to Normal mode.
Table 3. Overtemperature Detection (1)
STATE OF OUTPUT PORT
(1)
CONDITION
ERROR STATUS CODE
MEANING
Off
IOUT = 0 mA
0
On
On → all channels
Off
Tj < Tj,trip global
1
Normal
Tj > Tj,trip global
All error status bits = 0
Global overtemperature
On
On → Off
Tj < Tj,trip channel n
1
Normal
Tj > Tj,trip channel n
Channel n error status bit = 0
Channel n overtemperature
The global shutdown threshold temperature is approximately 170°C.
9.4 Device Functional Modes
The TLC591x-Q1 provides a Special Mode in which two functions are included: Error Detection and Current Gain
Control. There are two operation modes and three phases: Normal Mode phase, Mode Switching transition
phase, and Special Mode phase. The signal on the multiple function pin OE(ED2) is monitored to determine the
mode. When an one-clock-wide pulse appears on OE(ED2), the device enters the Mode Switching phase. At this
time, the voltage level on LE(ED1) determines the mode to which the TLC591x-Q1 switches. In the Normal Mode
phase, the serial data can be transferred into TLC591x-Q1 via the pin SDI, shifted in the shift register, and
transferred out via the pin SDO. LE(ED1) can latch the serial data in the shift register to the output latch.
OE(ED2) enables the output drivers to sink current.
In the Special Mode phase, the low-voltage-level signal OE(ED2) can enable output channels and detect the
status of the output current, to determine if the driving current level is sufficient. The detected Error Status is
loaded into the 8-bit shift register and shifted out via the pin SDO, synchronous to the CLK signal. The system
controller can read the error status and determine whether or not the LEDs are properly lit.
In the Special Mode phase, the TLC591x-Q1 allows users to adjust the output current level by setting a runtimeprogrammable Configuration Code. The code is sent into the TLC591x-Q1 via SDI. The positive pulse of
LE(ED1) latches the code in the shift register into a built-in 8-bit configuration latch, instead of the output latch.
The code affects the voltage at the terminal R-EXT and controls the output-current regulator. The output current
can be finely adjusted by a gain ranging from 1/12 to 127/128 in 256 steps. Therefore, the current skew between
ICs can be compensated within less than 1%. This feature is suitable for white balancing in LED color display
panels.
Table 4. Truth Table in Normal Mode
CLK
LE(ED1)
OE(ED2)
SDI
OUT0...OUT7
SDO
↑
H
L
Dn
Dn...Dn – 7
Dn – 7
↑
L
L
Dn + 1
No change
Dn – 6
↑
H
L
Dn + 2
Dn + 2...Dn – 5
Dn – 5
↓
X
L
Dn + 3
Dn + 2...Dn – 5
Dn – 5
↓
X
H
Dn + 3
Off
Dn – 5
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The signal sequence shown in Figure 11 makes the TLC591x-Q1 enter Current Adjust and Error Detection
mode.
0
1
2
3
4
5
6
7
CLK
OE(ED2)
1
LE(ED1)
0
SDI
off
OUT0
on
off
OUT1
on
off
OUT2
on
off
OUT3
on
off
OUT7
on
Don't care
SDO
Figure 10. Normal Mode
1
2
3
4
5
OE(ED2)
1
0
1
1
1
LE(ED1)
0
0
0
1
0
CLK
Figure 11. Switching to Special Mode
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In the Current Adjust mode, sending the positive pulse of LE(ED1), the content of the Shift register (a current
adjust code) is written to the 8-bit configuration latch (see Figure 12).
0
1
2
6
3
7
CLK
OE(ED2)
1
LE(ED1)
0
8-bit Configuration Code
SDI
Figure 12. Writing Configuration Code
When the TLC591x-Q1 is in the Error Detection mode, the signal sequence shown in Figure 13 enables a
system controller to read error status codes through SDO.
1
2
3
CLK
>2 µs
OE(ED2)
1
LE(ED1)
0
SDO
Error Status Code
Figure 13. Reading Error Status Code
The signal sequence shown in Figure 14 makes TLC591x-Q1 resume the Normal mode. Switching to Normal
mode resets all internal Error Status registers. OE(ED2) always enables the output port, whether the TLC591xQ1 enters Current Adjust mode or not.
1
2
3
4
5
OE(ED2)
1
0
1
1
1
LE(ED1)
0
0
0
0
0
CLK
Figure 14. Switching to Normal Mode
9.4.1 Operation Mode Switching
In order to switch between its two modes, TLC591x-Q1 monitors the signal OE(ED2). When an one-clock-wide
pulse of OE(ED2) appears, TLC591x-Q1 enters the two-clock-period transition phase, the Mode Switching
phase. After power on, the default operation mode is the Normal Mode (see Figure 15).
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Switching to Special Mode
1
2
3
Switching to Normal Mode
4
5
1
CLK
2
3
4
5
CLK
OE(ED2)
1
0
1
1
1
OE(ED2)
1
0
1
1
1
LE(ED1)
0
0
0
1
0
LE(ED1)
0
0
0
0
0
Actual Mode
Phase (Normal or Special)
Mode
Switching
Actual Mode
Phase (Normal or Special)
Special
Mode
Mode
Switching
Normal
Mode
Figure 15. Mode Switching
As shown in Figure 15, once a one-clock-wide short pulse (101) of OE(ED2) appears, TTLC591x-Q1 enters the
Mode Switching phase. At the fourth rising edge of CLK, if LE(ED1) is sampled as voltage high, TLC591x-Q1
switches to Special mode; otherwise, it switches to Normal mode. The signal LE(ED1) between the third and the
fifth rising edges of CLK cannot latch any data. Its level is used only to determine into which mode to switch.
However, the short pulse of OE(ED2) can still enable the output ports. During mode switching, the serial data
can still be transferred through SDI and shifted out from SDO.
NOTE
1. The signal sequence for the mode switching may be used frequently to ensure that TLC591xQ1 is in the proper mode.
2. The 1 and 0 on the LE(ED1) signal are sampled at the rising edge of CLK. The X means its
level does not affect the result of mode switching mechanism.
3. After power on, the default operation mode is Normal mode.
9.4.1.1 Normal Mode Phase
Serial data is transferred into TLC591x-Q1 via SDI, shifted in the Shift register, and output via SDO. LE(ED1) can
latch the serial data in the Shift register to the Output Latch. OE(ED2) enables the output drivers to sink current.
These functions differ only as described in Operation Mode Switching, in which case, a short pulse triggers
TLC591x-Q1 to switch the operation mode. However, as long as LE(ED1) is high in the Mode Switching phase,
TLC591x-Q1 remains in the Normal mode, as if no mode switching occurred.
9.4.1.2 Special Mode Phase
In the Special mode, as long as OE(ED2) is not low, the serial data is shifted to the Shift register via SDI and
shifted out via SDO, as in the Normal mode. However, there are two differences between Special mode and
Normal mode, as shown in the following sections.
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9.5 Programming
9.5.1 Reading Error Status Code in Special Mode
When OE(ED2) is pulled low while in Special mode, error detection and load error status codes are loaded into
the Shift register, in addition to enabling output ports to sink current. Figure 16 shows the timing sequence for
error detection. The 0 and 1 signal levels are sampled at the rising edge of each CLK. At least three zeros must
be sampled at the voltage low signal OE(ED2). Immediately after the second zero is sampled, the data input
source of the Shift register changes to the 8-bit parallel Error Status Code register, instead of from the serial data
on SDI. Normally, the error status codes are generated at least 2 μs after the falling edge of OE(ED2). The
occurrence of the third or later zero saves the detected error status codes into the Shift register. Therefore, when
OE(ED2) is low, the serial data cannot be shifted into TLC591x-Q1 via SDI. When OE(ED2) is pulled high, the
data input source of the Shift register is changed back to SDI. At the same time, the output ports are disabled
and the error detection is completed. Then, the error status codes saved in the Shift register can be shifted out
via SDO bit by bit along with CLK, as well as the new serial data can be shifted into TLC591x-Q1 via SDI.
While in Special mode, the TLC591x-Q1 cannot simultaneously transfer serial data and detect LED load error
status.
1
2
3
CLK
>2 µs
OE(ED2)
1
0
0
0
0
0
1
1
1
1
LE(ED1)
0
0
0
0
0
0
0
0
0
0
Error Status Code
SDO
Bit 7
Data source of
shift register
Error Detection
SDI
Bit 6
Bit 5
Bit 4
SDI
Figure 16. Reading Error Status Code
9.5.2 Writing Configuration Code in Special Mode
When in Special mode, the active high signal LE(ED1) latches the serial data in the Shift register to the
Configuration Latch, instead of the Output Latch. The latched serial data is used as the Configuration Code.
The code is stored until power off or the Configuration Latch is rewritten. As shown in Figure 17, the timing for
writing the Configuration Code is the same as the timing in the Normal Mode to latching output channel data.
Both the Configuration Code and Error Status Code are transferred in the common 8-bit Shift register. Users
must pay attention to the sequence of error detection and current adjustment to avoid the Configuration Code
being overwritten by Error Status Code.
0
1
2
3
6
7
CLK
OE(ED2)
1
LE(ED1)
0
8-bit Configuration Code
SDI
Figure 17. Writing Configuration Code
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Programming (continued)
9.5.3 8-Bit Configuration Code and Current Gain
Bit definition of the Configuration Code in the Configuration Latch is shown in Table 5.
Table 5. Bit Definition of 8-Bit Configuration Code
Meaning
Default
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
CM
HC
CC0
CC1
CC2
CC3
CC4
CC5
1
1
1
1
1
1
1
1
Bit 7 is first sent into TLC591x-Q1 via SDI. Bits 1 to 7 {HC, CC[0:5]} determine the voltage gain (VG) that affects
the voltage at R-EXT and indirectly affects the reference current, Iref, flowing through the external resistor at REXT. Bit 0 is the Current Multiplier (CM) that determines the ratio IOUT,target/Iref. Each combination of VG and CM
gives a specific Current Gain (CG).
• VG: the relationship between {HC,CC[0:5]} and the voltage gain is calculated as shown below:
VG = (1 + HC) × (1 + D/64) / 4
D = CC0 × 25 + CC1 × 24 + CC2 × 23 + CC3 × 22 + CC4 × 21 + CC5 × 20
Where HC is 1 or 0, and D is the binary value of CC[0:5]. So, the VG could be regarded as a floating-point
number with 1-bit exponent HC and 6-bit mantissa CC[0:5]. {HC,CC[0:5]} divides the programmable voltage
gain VG into 128 steps and two sub-bands:
Low-voltage subband (HC = 0): VG = 1/4 ~ 127/256, linearly divided into 64 steps
High-voltage subband (HC = 1): VG = 1/2 ~ 127/128, linearly divided into 64 steps
• CM: In addition to determining the ratio IOUT,target/Iref, CM limits the output current range.
High Current Multiplier (CM = 1): IOUT,target/Iref = 15, suitable for output current range IOUT = 10 mA to 120 mA.
Low Current Multiplier (CM = 0): IOUT,target/Iref = 5, suitable for output current range IOUT = 5 mA to 40 mA
• CG: The total Current Gain is defined as the following.
VR-EXT = 1.26 V × VG
Iref = VR-EXT/Rext, if the external resistor, Rext, is connected to ground.
IOUT,target = Iref × 15 × 3CM – 1 = 1.26 V/Rext × VG × 15 × 3CM – 1 = (1.26 V/Rext × 15) × CG
CG = VG × 3CM – 1
Therefore, CG = 1/12 to 127/128, and it is divided into 256 steps.
Examples
• Configuration Code {CM, HC, CC[0:5]} = {1,1,111111}
VG = 127/128 = 0.992 and CG = VG × 30 = VG = 0.992
• Configuration Code = {1,1,000000}
VG = (1 + 1) × (1 + 0/64)/4 = 1/2 = 0.5, and CG = 0.5
• Configuration Code = {0,0,000000}
VG = (1 + 0) × (1 + 0/64)/4 = 1/4, and CG = (1/4) × 3–1 = 1/12
After power on, the default value of the Configuration Code {CM, HC, CC[0:5]} is {1,1,111111}. Therefore,
VG = CG = 0.992. The relationship between the Configuration Code and the Current Gain is shown in Figure 18.
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1.00
CM = 0 (Low Current Multiplier)
Current Gain (CG)
0.75
HC = 1 (High
Voltage SubBand)
0.50
HC = 0 (Low
Voltage SubBand)
HC = 0 (Low
Voltage SubBand)
HC = 1 (High
Voltage SubBand)
0.25
CM = 1 (High Current Multiplier)
0.00
Configuration Code (CM, HC, CC[0:5]) in Binary Format
Figure 18. Current Gain vs Configuration Code
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Constant Current
In LED display applications, the TLC591x-Q1 provides nearly no current variations from channel to channel and
from IC to IC. While IOUT ≤ 100 mA, the maximum current skew between channels is less than ±3% and between
ICs is less than ±6%.
10.1.2 Adjusting Output Current
The TLC591x-Q1 scales up the reference current, Iref, set by the external resistor Rext to sink a current, Iout, at
each output port. Use the following formulas to calculate the target output current
IOUT,target in the saturation region:
Iref = VR-EXT/Rext, if another end of the external resistor Rext is connected to groundVR-EXT = 1.26 V × VG
IOUT,target = Iref × 15 × 3CM – 1
(1)
(2)
where
•
•
Rext is the resistance of the external resistor connected to the R-EXT terminal.
VR-EXT is the voltage of R-EXT, which is controlled by the programmable voltage gain (VG), which is defined by
the Configuration Code.
(3)
The Current Multiplier (CM) determines that the ratio IOUT,target/Iref is 15 or 5. After power on, the default value of
VG is 127/128 = 0.992, and the default value of CM is 1, so that the ratio IOUT,target/Iref = 15. Based on the default
VG and CM.
VR-EXT = 1.26 V × 127/128 = 1.25 V
IOUT,target = (1.25 V/Rext) × 15
(4)
(5)
Therefore, the default current is approximately 52 mA at 360 Ω and 26 mA at 720 Ω. The default relationship
after power on between IOUT,target and Rext is shown in Figure 19.
140
IOUT – mA
120
100
80
40
0
0 500
1000
1500
2000
2500
3000
3500 4000
Rext – Ω
Figure 19. Default Relationship Curve Between IOUT,target and Rext After Power Up
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10.2 Typical Applications
10.2.1 Single Implementation of TLC591x-Q1 Device
The TLC5917/TLC5917-Q1 Constant-Current LED Sink Drivers is designed to work alone or cascaded. Figure 20
shows implementation of a single TLC591x-Q1 device.
SDI
CLK
CLK
LE
LE
OE
OE
TLC5916/TLC5917-Q1
Controller
SDI
OUT7
VDD: 3.0V to 5.5V
OUT0
VLED
VDD
To Controller if Error
Detection Used
SDO
R-EXT
GND
Figure 20. Single Implementation of TLC591x-Q1 Device
10.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 6. The purpose of this design procedure is to
calculate the power dissipation in the device and the operating junction temperature.
Table 6. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Number of LED strings
8
Number of LEDs per string
3
LED Current (mA)
20
Forward voltage of each LED (V)
3.5
Junction-to-ambient thermal
resistance (°C/W)
86.9
Ambient temperature of application
(°C)
115
VDD (V)
5
IDD (mA)
10
Max operating junction temperature
(°C)
150
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10.2.1.2 Detailed Design Procedure
Use the following equations to determine the design parameters.
TJ = TA + RθJA × PD_TOT
where
•
•
•
•
TJ is the junction temperature
TA is the ambient temperature
RθJA is the junction-to-ambient thermal resistance
PD_TOT is the total power dissipation in the IC.
PD_TOT = PD_CS + IDD × VDD
(6)
where
•
•
•
PD_CS
PD_CS is the power dissipation in the LED current sinks.
IDD is the IC supply current.
VDD is the IC supply voltage.
= IO × VO × nCH
(7)
where
• IO is the LED current
• VO is the voltage at the output pin
• nCH is the number of LED strings.
VO = VLED – (nLED × VF)
(8)
where
•
•
•
VLED is the voltage applied to the LED string
nLED is the number of LEDs in the string
VF is the forward voltage of each LED.
(9)
VO must not be too high as this causes excess power dissipation inside the current sink. However, VO also must
not be too low as this does not allow the full LED current Figure 21.
With VLED = 12 V:
VO = 12 V – (3 × 3.5 V) = 1.5 V
PD_CS = 20 mA × 1.5 V × 8 = 0.24 W
(10)
(11)
Using PD_CS, calculate:
PD_TOT = PD_CS + IDD × VDD = 0.24 W + 0.01 A × 5 V = 0.29 W
(12)
Using PD_TOT, calculate:
TJ = TA + RθJA × PD_TOT = 115°C + 86.9°C/W × 0.29 W = 140°C
(13)
This design example demonstrates how to calculate power dissipation in the IC and ensure that the junction
temperature is kept below 150°C.
NOTE
This design example assumes that all channels have the same electrical parameters
(nLED, IO, VF, VLED). If the parameters are unique for each channel, then the power
dissipation must be calculated for each current sink separately. Then, add each result
together to calculate the total power dissipation in the current sinks.
26
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SLVS814A – JANUARY 2008 – REVISED MAY 2015
10.2.1.3 Application Curve
150
Temperature = 25°C
IO = 120 mA
125
Output Current (mA)
IO = 100 mA
100
IO = 80 mA
75
IO = 60 mA
50
IO = 40 mA
IO = 20 mA
25
IO = 5 mA
0
0
0.5
1
1.5
2
2.5
3
Output Voltage (V)
Figure 21. Output Current vs Output Voltage
10.2.2 Cascading Implementation of TLC591x-Q1 Device
The TLC5917/TLC5917-Q1 Constant-Current LED Sink Drivers is designed to work alone or cascaded. Figure 22
shows a cascaded driver implementation.
VLED
R-EXT
GND
OUT7
VDD
SDO
720
R-EXT
GND
OE
TLC5916/TLC5917-Q1
SDI
720
LE
CLK
GND
SDO
CLK
R-EXT
OUT0
OUT7
TLC5916/TLC5917-Q1
SDI
720
LE
SDO
VDD
OE
OUT0
OUT7
VDD
OE
CLK
SDI
LE
TLC5916/TLC5917-Q1
OUT0
VDD: 3.0V to 5.5V
SDI
Controller
CLK
LE
OE
Read back
Multiple Cascaded Drivers
26mA Application
Figure 22. Cascading Implementation of TLC591x-Q1 Device
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11 Power Supply Recommendations
The device is designed to operate from a VDD supply between 3 V and 5.5 V. The LED supply voltage is
determined by the number of LEDs in each string and the forward voltage of the LEDs (should be ≤ 17 V in total).
12 Layout
12.1 Layout Guidelines
The traces that carry current from the LED cathodes to the OUTx pins must be wide enough to support the
default current (up to 120 mA).
The SDI, CLK, LE (ED1), OE (ED2), and SDO pins are to be connected to the microcontroller.
There are several ways to achieve this, including the following methods:
• Traces may be routed underneath the package on the top layer.
• The signal may travel through a via to another layer.
To uC
To uC
VDD
To uC
To uC
To uC
12.2 Layout Example
GND
GND
GND
CLK
LE (ED1)
OUT0
OUT1
OUT2
GND
TLC5916/TLC5917-Q1
SDI
VDD
GND
OUT3
R-EXT
SDO
OE (ED2)
OUT7
OUT6
OUT5
OUT4
GND
VLED
Figure 23. Recommended Layout Example
28
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TLC5916-Q1, TLC5917-Q1
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SLVS814A – JANUARY 2008 – REVISED MAY 2015
13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 7. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TLC5916-Q1
Click here
Click here
Click here
Click here
Click here
TLC5917-Q1
Click here
Click here
Click here
Click here
Click here
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLC5916QDRQ1
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLC5916Q
TLC5917QDRQ1
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLC5917Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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