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TLC59210
SCLS711A – MARCH 2009 – REVISED NOVEMBER 2015
TLC59210 8-BIT DMOS Sink Driver With Latch
1 Features
3 Description
•
•
•
The TLC59210 is an 8-bit flip-flop driver for LED and
solenoid with Schmitt-trigger buffers. Each channel
can sink up to 200mA and support an output voltage
up to 30V. The TLC59210 is designed for VCC and
operation from 3.3V to 5.5V.
1
•
•
•
•
•
•
DMOS Process
High Voltage Output (Vds = 30 V)
Output Current on Each Channel
(Ids Max = 200 mA)
Latch-Up Performance Exceeds 250 mA Per
JEDEC Standard JESD-17
ESD Protection Exceeds JESD 22
– 2000-V Human Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged Device Model (C101)
LED Driver Application
Output Clamp Diodes (Parasitic)
Control Pins of CLR and CLK Inputs
Clock Input up to 1 MHz
Each output channel is controlled by a positive-edgetriggered D-type flip-flops with a direct clear (CLR)
input. Information at the data (D) input meeting the
setup time requirements is transferred to the Y output
on the positive-going edge of the clock (CLK) pulse.
Clock triggering occurs at a particular voltage level
and is not directly related to the transition time of the
positive-going pulse. When CLK is at either the high
or low level, the D input has no effect at the output.
The TLC59210 is characterized for operation from
–40°C to 85°C.
Device Information(1)
2 Applications
•
•
•
PART NUMBER
Lamp and Display (LED)
Hammer
Relay
TLC59210
PACKAGE
BODY SIZE (NOM)
PDIP (20)
24.33 mm × 6.35 mm
TSSOP (20)
6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
VLED
3.3V or 5V
RSET
TLC59210
µC
CLK
VDD
CLR
Y1
D1
Y8
D8
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLC59210
SCLS711A – MARCH 2009 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
7
1
1
1
2
3
4
Absolute Maximum Ratings ..................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics: VCC = 4.5 V to 5.5 V ........ 5
Electrical Characteristics: VCC = 3 V to 3.6 V ........... 5
Timing Requirements: VCC = 4.5 V to 5.5 V ............. 6
Timing Requirements: VCC = 3 V to 3.6 V ................ 6
Switching Characteristics: VCC = 4.5 V to 5.5 V ....... 6
Switching Characteristics: VCC = 3 V to 3.6 V ........ 6
Typical Characteristics ............................................ 7
Parameter Measurement Information .................. 8
8
Detailed Description .............................................. 9
8.1
8.2
8.3
8.4
9
Overview ................................................................... 9
Functional Block Diagram ......................................... 9
Feature Description................................................. 10
Device Functional Modes........................................ 10
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application ................................................. 11
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 13
12 Device and Documentation Support ................. 14
12.1
12.2
12.3
12.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
14
14
14
14
13 Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
Changes from Original (March 2009) to Revision A
•
2
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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SCLS711A – MARCH 2009 – REVISED NOVEMBER 2015
5 Pin Configuration and Functions
N or PW Package
20 Pin PDIP or TSSOP
(Top View)
CLR
D1
D2
D3
D4
D5
D6
D7
D8
CLK
1
20
VCC
2
19
3
18
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
GND
4
17
5
16
6
15
7
14
8
13
9
12
10
11
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
CLR
I
Direct Clear. When Low, all outputs are off
2
D1
I
Data Input 1
3
D2
I
Data Input 2
4
D3
I
Data Input 3
5
D4
I
Data Input 4
6
D5
I
Data Input 5
7
D6
I
Data Input 6
8
D7
I
Data Input 7
9
D8
I
Data Input 8
10
CLK
I
Clock input. A Rising Edge transfers information at the data input (D) to the output (Y).
11
GND
GND
12
Y8
Output
Data Output 8
13
Y7
Output
Data Output 7
14
Y6
Output
Data Output 6
15
Y5
Output
Data Output 5
16
Y4
Output
Data Output 4
17
Y3
Output
Data Output 3
18
Y2
Output
Data Output 2
19
Y1
Output
Data Output 1
20
VCC
Power
Supply for Device
Ground
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SCLS711A – MARCH 2009 – REVISED NOVEMBER 2015
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6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage
D
Input voltage
Vds
Output voltage
H output
Ids
Output current
1 bit for output low,
IIK
Input clamp current
VI < 0 V
Tstg
(1)
MIN
MAX
–0.5
7
V
–0.5
7
V
–0.5
32
V
VCC = 3 V to 3.6 V
100
VCC = 4.5 V to 5.5 V
200
UNIT
mA
–20
mA
Operating free-air temperature
–40
85
°C
Storage temperature
–65
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
(3)
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
Machine Model (A115-A), per ANSI/ESDA/JEDEC Standard JESD-17 (3)
±200
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 200-V MM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX
3
5.5
V
High-level input voltage
VCC × 0.7
VCC
V
VIL
Low-level input voltage
0
VCC × 0.3
V
Vds
Output voltage
30
V
VCC
Supply voltage
VIH
Ids
N package,
VCC = 4.5 V to 5.5 V
Duty cycle < 42%
200
Duty cycle < 100%
130
PW package,
VCC = 4.5 V to 5.5 V
Duty cycle < 24%
200
Output current
TA
Duty cycle < 100%
UNIT
mA
95
Operating free-air temperature
–40
85
°C
6.4 Thermal Information
TLC59210
THERMAL METRIC
(1)
N (PDIP)
PW (TSSOP)
20 PINS
20 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
53.6
94.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
41.2
28.3
°C/W
RθJB
Junction-to-board thermal resistance
34.6
45.7
°C/W
ψJT
Junction-to-top characterization parameter
22.3
1.6
°C/W
ψJB
Junction-to-board characterization parameter
34.4
45.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics: VCC = 4.5 V to 5.5 V
over recommended operating free-air temperature range, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VT+
Positive-going input threshold
D, CLR, CLK
VT–
Negative-going input threshold
D, CLR, CLK
1.5
VHYS
Hysteresis
D, CLR, CLK
0.5
IIH
High-level input current
VCC = 5.5 V, VI = 5.5 V
IIL
Low-level input current
VCC = 5.5 V, VI = 0 V
IOZ
Leakage current
Vds= 30 V
Ioff
Leakage current
VI = 0 to 5 V, VO = 0 to 30 V, VCC = 0
ICC
Supply current
VI = 0 to 5 V, VO = 0 to 30 V, VCC = 0
VOL
Low-level output voltage
rON
ON-state resistance
Ci
Input capacitance
TYP
MAX
3.5
UNIT
V
V
2
V
0
1
μA
0
–1
μA
5
μA
0
5
μA
Output = all OFF
0
5
Output = all ON
0
5
VCC = 4.5 V, IO = 100 mA
0.2
0.35
VCC = 4.5 V, IO = 200 mA
0.5
0.7
V
VCC = 4.5 V, IO = 100 mA
2
3.5
Ω
VI = VCC or GND
5
μA
V
pF
6.6 Electrical Characteristics: VCC = 3 V to 3.6 V
over recommended operating free-air temperature range, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.52
V
VT+
Positive-going input threshold
D, CLR, CLK
VT–
Negative-going input threshold
D, CLR, CLK
0.9
VHYS
Hysteresis
D, CLR, CLK
0.33
1.32
V
IIH
High-level input current
VCC = 3.6 V, VI = 3.6 V
0
1
μA
IIL
Low-level input current
VCC = 3.6 V, VI = 0 V
0
–1
μA
IOZ
Leakage current
VO= 30 V
5
μA
Ioff
Leakage current
VCC = 0 V, VI = 0 to 3.6 V, VO = 0 to 30 V
μA
V
0
5
Output = all OFF
0
5
Output = all ON
0
5
ICC
Supply current
VCC = 3.6 V, VI = 0 to 3.6 V, VO = 0
to 30 V
VOL
Low-level output voltage
VCC = 3 V, IO = 100 mA
0.35
0.7
V
rON
ON-state resistance
VCC = 3 V, IO = 100 mA
3.5
7
Ω
Ci
Input capacitance
VI = VCC or GND
5
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μA
pF
5
TLC59210
SCLS711A – MARCH 2009 – REVISED NOVEMBER 2015
www.ti.com
6.7 Timing Requirements: VCC = 4.5 V to 5.5 V
over recommended operating free-air temperature range, O/C to Y (unless otherwise noted)
MIN
NOM
MAX
UNIT
tsu
Setup time, CLK↑
VDD = 4.5 V
10
ns
th
Hold time, CLK↑
VDD = 4.5 V
10
ns
tw
Pulse width, CLK, CLR
VDD = 4.5 V
30
ns
6.8 Timing Requirements: VCC = 3 V to 3.6 V
over recommended operating free-air temperature range, O/C to Y (unless otherwise noted)
MIN
NOM
MAX
UNIT
tsu
Setup time, CLK↑
VDD = 3 V
10
ns
th
Hold time, CLK↑
VDD = 3 V
10
ns
tw
Pulse width, CLK, CLR
VDD = 3 V
30
ns
6.9 Switching Characteristics: VCC = 4.5 V to 5.5 V
over recommended operating free-air temperature range, TA = –40°C to 85°C (unless otherwise noted), see Figure 5
PARAMETER
TEST CONDITIONS
tTLH
Output = low to high
tTHL
Output = high to low
tPLH
Output = low to high
tPHL
Output = high to low
tPHLR
CLR–Y
TA = 25°C
TA = –40°C to 85°C
TA = 25°C
TA = –40°C to 85°C
TA = 25°C
TA = –40°C to 85°C
TA = 25°C
TA = –40°C to 85°C
TA = 25°C
TA = –40°C to 85°C
LOAD CAPACITANCE
MIN
TYP
MAX
CL = 30 pF, RL = 240 Ω,
24-V pullup
180
230
CL = 30 pF, RL = 240 Ω,
24-V pullup
300
CL = 30 pF, RL = 240 Ω,
24-V pullup
320
CL = 30 pF, RL = 240 Ω,
24-V pullup
320
CL = 30 pF, RL = 240 Ω,
24-V pullup
320
260
450
500
480
550
480
550
480
550
UNIT
ns
ns
ns
ns
ns
6.10 Switching Characteristics: VCC = 3 V to 3.6 V
over recommended operating free-air temperature range, TA = –40°C to 85°C (unless otherwise noted), see Figure 5
PARAMETER
TEST CONDITIONS
tTLH
Output = low to
high
tTHL
Output = high to
low
tPLH
Output = low to
high
tPHL
Output = high to
low
tPHLR
CLR–Y
LOAD CAPACITANCE
TA = 25°C
T A= –40°C to 85°C
TA = 25°C
T A= –40°C to 85°C
TA = 25°C
T A= –40°C to 85°C
TA = 25°C
T A= –40°C to 85°C
TA = 25°C
6
T A= –40°C to 85°C
TYP
MAX
CL = 30 pF, RL = 240
Ω,
24-V pullup
300
450
CL = 30 pF, RL = 240
Ω,
24-V pullup
300
CL = 30 pF, RL = 240
Ω,
24-V pullup
500
CL = 30 pF, RL = 240
Ω,
24-V pullup
500
CL = 30 pF, RL = 240
Ω,
24-V pullup
500
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MIN
500
UNIT
ns
450
500
ns
700
850
ns
700
850
ns
700
850
ns
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3.6
360
3.4
340
3.2
320
3
300
VOL (mV)
rON (Ω)
6.11 Typical Characteristics
2.8
2.6
280
260
2.4
240
2.2
220
2
200
3
3.2
3.4
3.6
3.8
Vcc (V)
4
4.2
4.4
4.6
3
3.2
3.4
3.6
D001
IO = 100mA
3.8
Vcc (V)
4
4.2
4.4
4.6
D002
IO = 100mA
Figure 1. rON vs VCC Conditions IO= 100mA
Figure 2. VOL vs VCC Conditions IO = 100mA
500
300
480
280
tPLH, tPHL, tPHLR (ns)
460
tTLH (ns)
260
240
220
440
420
400
380
360
200
340
180
3.2
3.4
3.6
CL = 30 pF
3.8
4
4.2
Vcc (V)
4.4
4.6
4.8
5
320
3.2
3.4
3.6
D003
RL = 240 Ω, 24-V Pullup
CL = 30 pF
Figure 3. tTLH vs VCC
3.8
4
4.2
Vcc (V)
4.4
4.6
4.8
5
D004
RL = 240 Ω, 24-V Pullup
Figure 4. Propagation Delay vs VCC
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7 Parameter Measurement Information
24 V
RL = 240 Ω
Test
Y
CL= 30 pF
LOAD CIRCUIT
FOR O/D OUTPUT
5V
50%
tsu
D
50%
th
GND
tf
tr
90%
50%
10%
tw
5V
90%
50%
50%
CLK
10%
GND
tPHL
tPLH
90%
90%
50%
10%
50%
10%
tTHL
VCC
Y
GND
tTLH
VOLTAGE WAVEFORMS
A.
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output
control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the
output control.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns,
and tf ≤ 3 ns.
D.
The outputs are measured one at a time with one transition per measurement.
E.
tPLH and tPHL are the same as tpd.
Figure 5. Test Circuit and Voltage Waveforms
8
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8 Detailed Description
8.1 Overview
The TLC59210 is an 8-bit flip-flop driver for LED and solenoid with Schmitt-trigger buffers. Each output channel is
controlled by a positive-edge-triggered D-type flip-flops with a direct clear (CLR) input. Information at the data (D)
input meeting the setup time requirements is transferred to the Y output on the positive-going edge of the clock
(CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of
the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.
8.2 Functional Block Diagram
D
Y
CLK
CLR
GND
Figure 6. Output Schematic
Y2
Y1
19
Y3
18
Y4
Y5
16
17
Y6
15
Y8
Y7
13
14
12
CLK
10
D
D
D
D
D
D
D
D
CK
CK
CK
CK
CK
CK
CK
CK
R
R
R
R
R
R
R
R
CLR
1
2
D1
3
D2
4
D3
5
D4
6
D5
7
D6
8
9
11
D7
D8
GND
This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12.
Figure 7. Logic Symbol
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8.3 Feature Description
The TLC59210 features the ability to independently control 8 Sinking Outputs (Y). At each CLK pulse the output
can be latched high or low depending on the input state (D). The CLR function allows for all outputs to be set
high.
8.4 Device Functional Modes
Table 1. Function Table
(Each Latch) (1)
INPUTS
CLR
CLK
D
L
X
X
H*
H
↑
L
H*
H
↑
H
L
H
L
X
Y0
H
↓
X
Y0
(1)
10
OUTPUT
Y
L: Low-level, H: High-level, H*: with
pullup resistor, X: Irrelevant, ↑:
Rising edge,↓: Falling edge, Z :
High-impedance (OFF)
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
In an LED display application, TLC59210 is used to drive the current sink for 8 LEDs in parallel. LED display
patterns can be created by providing different bit patterns. Each LED can be duty cycled by either duty cycling
the LED supply or the control bit.
9.1.1 Setting LED Current
The LED current is primarily dependent on the supply voltage, the forward voltage of the LED, and the series
resistor (RSET). In many applications the supply voltage and LED forward voltage cannot be adjusted. Hence,
RSET is utilized to adjust the LED current.
9.1.2 PWM Brightness Dimming
The perceived brightness of the LEDs can be adjusted by use of PWM dimming. For example, an LED driven at
50% duty cycle will appear less bright than it would at 100% duty cycle.
9.2 Typical Application
VLED
Character
Generator Circuit
and
LED Power Circuit
CLK
CLR
8-Bit Sink Current Driver
TLC59210
Parallel Data Bus
Figure 8. Typical Application Schematic
9.2.1 Design Requirements
For an LED display application, a parallel data bus used to provide the input control for TLS59210. A character
generator circuit and LED power circuit are used to generate the bit pattern written into the TLC59210 to provide
the power control for the entire LED array. The LED power circuit controls the total current into the array and can
also power cycle the LED array. For simple implementation, LED power circuit could be eliminated. The VLEDcan
be connected directly to the resistor and LED string.
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Typical Application (continued)
9.2.2 Detailed Design Procedure
The combination of LED Supply voltage (VLED), the LED forward voltage (VF), and external resistor sets the
maximum LED current (IDS) that would appear with a 100% duty cycle.
IDS= (VLED - VF)/RSET
(1)
The maximum total power dissipation and maximum current through each channel of TLC59210 is determined by
the number of the LEDs that are on at one time, the LED duty cycle, and the ambient temperature. The following
graphs show how the maximum channel current may be limited by the total power dissipation.
9.2.3 Application Curves
N=1
N = 1–3
200
200
N=2
Maximum Output Current, Ids (mA)
Maximum Output Current, Ids (mA)
N=3
N=4
160
N=8
120
N=7
N=6
N=5
80
TA = 85°C
N = Number of outputs
conducting
simultaneously
40
N=5
160
N=6
N=7
120
N=8
80
TA = 85°C
N = Number of outputs
conducting
simultaneously
40
0
0
0
10
20
30
40 50 60
Duty Cycle (%)
70
80
90
0
100
Figure 9. Maximum Output Current vs Duty Cycle
(TSSOP (PW) Package)
12
N=4
10
20
30
40 50 60
Duty Cycle (%)
70
80
90
100
Figure 10. Maximum Output Current vs Duty Cycle
(DIP (N) Package)
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10 Power Supply Recommendations
TLC59210 operates from a VCC range of 3 V to 5.5 V. The system will also require a power supply for the LEDs.
The supply voltage of the LEDs must be greater than the forward voltage of the LED plus the VOL of the
channel, but not greater than 30V.
11 Layout
11.1 Layout Guidelines
The traces carrying power through the LEDs should be wide enough to handle the necessary current. All LED
current passes through the device and into the ground node. There must be a strong connection between the
device ground and the circuit board ground.
11.2 Layout Example
To µC
To µC
To µC
To µC
To µC
To µC
To µC
To µC
To µC
To µC
CLK
D8
D7
D6
D5
D4
D3
D2
D1
CLR
GND
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
VCC
To Device
Power Suply
Via to GND
To LED
Power Supply
Figure 11. Layout Example
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Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: TLC59210
13
TLC59210
SCLS711A – MARCH 2009 – REVISED NOVEMBER 2015
www.ti.com
12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14
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Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: TLC59210
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLC59210IN
ACTIVE
PDIP
N
20
20
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
TLC59210IPWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLC59210IN
Y59210
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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