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TLC5925
SLVS765B – OCTOBER 2008 – REVISED SEPTEMBER 2015
TLC5925 Low-Power 16-Channel Constant-Current LED Sink Driver
1 Features
3 Description
•
•
The TLC5925 is designed for LED displays and LED
lighting applications. The TLC5925 contains a 16-bit
shift register and data latches, which convert serial
input data into parallel output format. At the TLC5925
output stage, 16 regulated-current ports provide
uniform and constant current for driving LEDs within a
wide range of VF variations. Used in system design
for LED display applications (such as, LED panels),
the TLC5925 provides great flexibility and device
performance. Users can adjust the output current
from 3 mA to 45 mA through an external resistor,
Rext, which gives flexibility in controlling the light
intensity of LEDs. TLC5925 is designed for up to
17 V at the output port. The high clock frequency, 30
MHz, also satisfies the system requirements of highvolume data transmission.
1
•
•
•
•
•
•
•
•
•
16 Constant-Current Output Channels
Constant Output Current Invariant to Load Voltage
Change
Excellent Output Current Accuracy:
– Between Channels: < ±4% (Max)
– Between ICs: < ±6% (Max)
Constant Output Current Range:
3 mA to 45 mA
Output Current Adjusted By External Resistor
Fast Response of Output Current, OE (Min):
100 ns
30-MHz Clock Frequency
Schmitt-Trigger Inputs
3.3-V to 5-V Supply Voltage
Thermal Shutdown for Overtemperature
Protection
ESD Performance: 1-kV HBM
The serial data is transferred into TLC5925 via SDI,
shifted in the shift register, and transferred out via
SDO. LE can latch the serial data in the shift register
to the output latch. OE enables the output drivers to
sink current.
2 Applications
•
•
•
•
•
Gaming Machine and Entertainment
General LED Applications
LED Display Systems
Signs LED Lighting
White Goods
Device Information
PART NUMBER
TLC5925
(1)
PACKAGE
BODY SIZE (NOM)
SSOP (24)
8.65 mm × 3.90 mm
SOIC (24)
15.40 mm × 7.50 mm
TSSOP (24)
7.80 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLC5925
SLVS765B – OCTOBER 2008 – REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
7
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Electrical Characteristics: VDD = 3 V......................... 5
Electrical Characteristics: VDD = 5.5 V..................... 6
Power Dissipation and Thermal Impedance ............. 6
Timing Requirements ................................................ 7
Switching Characteristics: VDD = 3 V........................ 7
Switching Characteristics: VDD = 5.5 V................... 8
Typical Characteristics ............................................ 9
Parameter Measurement Information ................ 10
8
Detailed Description ............................................ 12
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
12
12
13
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application ................................................. 15
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 16
11.1 Layout Guidelines ................................................. 16
11.2 Layout Example .................................................... 17
12 Device and Documentation Support ................. 18
12.1
12.2
12.3
12.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
13 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (March 2013) to Revision B
•
2
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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SLVS765B – OCTOBER 2008 – REVISED SEPTEMBER 2015
5 Pin Configuration and Functions
DBQ, DW, or PWP Package
24-Pin SSOP, SOIC, or TSSOP
Top View
GND
1
24
VDD
SDI
2
23
R-EXT
CLK
3
22
SDO
LE
4
21
OE
OUT0
5
20
OUT15
OUT1
6
19
OUT14
OUT2
7
18
OUT13
OUT3
8
17
OUT12
OUT4
9
16
OUT11
OUT5
10
15
OUT10
OUT6
11
14
OUT9
OUT7
12
13
OUT8
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
CLK
3
I
Clock input for data shift on rising edge
GND
1
—
Ground for control logic and current sink
LE
4
I
Data strobe input
Serial data is transferred to the respective latch when LE is high.
The data is latched when LE goes low.
LE has an internal pull-down resistor.
OE
21
I
Output enable
When OE is active (low), the output drivers are enabled.
When OE is high, all output drivers are turned OFF (blanked).
OE has an internal pullup resistor.
OUT0
5
OUT1
6
OUT2
7
OUT3
8
O
Constant-current outputs
OUT4
9
OUT5
10
OUT6
11
OUT7
12
OUT8
13
OUT9
14
OUT10
15
OUT11
16
OUT12
17
OUT13
18
OUT14
19
OUT15
20
R-EXT
23
I
Input used to connect an external resistor (Rext) for setting output currents
SDI
2
I
Serial-data input to the Shift register
SDO
22
O
Serial-data output to the following SDI of next driver IC or to the microcontroller
VDD
24
I
Supply voltage
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
0
7
V
Input voltage
–0.4
VDD + 0.4
V
Output voltage
–0.5
20
V
45
mA
750
mA
125
°C
–40
150
°C
–55
150
°C
VDD
Supply voltage
VI
VO
IOUT
Output current
IGND
GND terminal current
TA
Free-air operating temperature range
–40
TJ
Operating junction temperature range
Tstg
Storage temperature range
(1)
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101
(2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VDD
Supply voltage
VO
Output voltage
MIN
MAX
3
5.5
V
17
V
OUT0 to OUT15
VO ≥ 0.6 V
3
UNIT
IO
Output current
DC test circuit
IOH
High-level output current
SDO
IOL
Low-level output current
SDO
VIH
High-level input voltage
CLK, OE, LE, and SDI
0.7 × VDD
VDD
V
VIL
Low-level input voltage
CLK, OE, LE, and SDI
GND
0.3 × VDD
V
tR
Rise Time
CLK
500
ns
tF
Fall Time
CLK
500
ns
4
VO ≥ 1 V
45
–1
mA
1
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mA
mA
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6.4 Thermal Information
TLC5925
DBQ
(SSOP)
DW
(SOIC)
PW
(TSSOP)
24 PINS
24 PINS
24 PINS
Mounted on JEDEC 1-layer board (JESD 51-3), No airflow
99.8
80.5
118.8
°C/W
Mounted on JEDEC 4-layer board (JESD 51-7), No airflow
61
45.5
87.9
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
52.9
45.0
44.9
°C/W
RθJB
Junction-to-board thermal resistance
41.5
44.8
52.9
°C/W
ψJT
Junction-to-top characterization parameter
16.4
21.7
6.7
°C/W
ψJB
Junction-to-board characterization parameter
41.2
44.4
52.5
°C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
°C/W
THERMAL METRIC
RθJA
(1)
Junction-toambient thermal
resistance
(1)
UNIT
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics: VDD = 3 V
VDD = 3 V, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
UNIT
Input voltage
VO
Output voltage
IO
Output current
IOH
High-level output current, source
IOL
Low-level output current, sink
VIH
High-level input voltage
0.7 × VDD
VDD
VIL
Low-level input voltage
GND
0.3 × VDD
Ileak
Output leakage current
VOH = 17 V
VOH
High-level output voltage
SDO, IOL = –1 mA
VOL
Low-level output voltage
SDO, IOH = 1 mA
Output current 1
VOUT = 0.6 V, Rext = 1680 Ω
Output current error, die-die
IOL = 13 mA, VO = 0.6 V, Rext = 1680 Ω,
TJ = 25°C
±3%
±6%
Output current error, channel-tochannel
IOL = 13 mA, VO = 0.6 V, Rext = 1680 Ω,
TJ = 25°C
±1.5%
±4%
Output current 2
VO = 0.8 V, Rext = 840 Ω
Output current error, die-die
IOL = 26 mA, VO = 0.8 V, Rext = 840 Ω,
TJ = 25°C
±3%
±6%
Output current error, channel-tochannel
IOL = 26 mA, VO = 0.8 V, Rext = 840 Ω,
TJ = 25°C
±1.5%
±4%
Output current vs
output voltage regulation
VO = 1 V to 3 V, IO = 13 mA
Pullup resistance
OE
500
kΩ
Pulldown resistance
LE
500
kΩ
IO(1)
IO(2)
IOUT vs
VOUT
3
MAX
VDD
VO ≥ 0.6 V
-1
Restart temperature hysteresis
TJ = 25°C
TJ = 125°C
CIN
(1)
Supply current
Input capacitance
2
VDD – 0.4
13
μA
26
mA
±0.1
%/V
±1
175
V
mA
200
°C
°C
7
10
Rext = 1680 Ω
9
12
Rext = 840 Ω
11
13
VI = VDD or GND, CLK, SDI, SDO, OE
V
V
0.4
15
Rext = Open
IDD
0.5
150
mA
mA
1
(1)
Overtemperature shutdown
V
45
VDD = 3.0 V to 5.5 V, IO = 13 mA to 45 mA
Thys
V
17
3
VO ≥ 1 V
Tsd
5.5
10
mA
pF
Specified by design
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6.6
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Electrical Characteristics: VDD = 5.5 V
VDD = 5.5 V, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER
VDD
Input voltage
VO
Output voltage
TEST CONDITIONS
MIN
TYP
3
VO ≥ 0.6 V
MAX
5.5
V
17
V
3
IO
Output current
IOH
High-level output current, source
IOL
Low-level output current, sink
VIH
High-level input voltage
0.7 × VDD
VDD
VIL
Low-level input voltage
GND
03 × VDD
Ileak
Output leakage current
VOH = 17 V
VOH
High-level output voltage
SDO, IOL = –1 mA
VOL
Low-level output voltage
SDO, IOH = 1 mA
Output current 1
VOUT = 0.6 V, Rext = 1680 Ω
Output current error, die-die
IOL = 13 mA, VO = 0.6 V, Rext = 1680 Ω,
TJ = 25°C
±3$
±6$
Output current error, channel-tochannel
IOL = 13 mA, VO = 0.6 V, Rext = 1680 Ω,
TJ = 25°C
±1.5$
±4$
Output current 2
VO = 0.8 V, Rext = 840 Ω
Output current error, die-die
IOL = 26 mA, VO = 0.8 V, Rext = 840 Ω,
TJ = 25°C
±3%
±6%
Output current error, channel-tochannel
IOL = 26 mA, VO = 0.8 V, Rext = 840 Ω,
TJ = 25°C
±1.5%
±4%
Output current vs
output voltage regulation
VO = 1 V to 3 V , IO = 26 mA
Pullup resistance
OE
500
Pulldown resistance
LE
500
IO(1)
IO(2)
IOUT vs
VOUT
VO ≥ 1 V
45
-1
TJ = 25°C
0.5
TJ = 125°C
2
VDD – 0.4
Overtemperature shutdown
13
Thys
Restart temperature hysteresis
IDD
Supply current
CIN
(1)
Input capacitance
%/V
±1
175
kΩ
kΩ
200
15
°C
°C
9
11
Rext = 1680 Ω
12
14
Rext = 840 Ω
14
16
VI = VDD or GND, CLK, SDI, SDO, OE
V
mA
±0.1
Rext = Open
μA
mA
26
150
V
V
0.4
(1)
Tsd
mA
mA
1
VDD = 3.0 V to 5.5 V, IO = 13 mA to 45 mA
UNIT
10
mA
pF
Specified by design
6.7 Power Dissipation and Thermal Impedance
MIN
PD
6
Power dissipation
Mounted on JEDEC 4-layer board (JESD 51-7),
No airflow, TA = 25°C, TJ = 125°C
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MAX
DBQ package
1.6
DW package
2.2
PW package
1.1
UNIT
W
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6.8 Timing Requirements
VDD = 3 V to 5.5 V (unless otherwise noted)
MIN
MAX
UNIT
tw(L)
LE pulse duration
15
ns
tw(CLK)
CLK pulse duration
15
ns
tw(OE)
OE pulse duration
300
ns
tsu(D)
Setup time for SDI
3
ns
th(D)
Hold time for SDI
2
ns
tsu(L)
Setup time for LE
5
ns
th(L)
Hold time for LE
5
ns
fCLK
Clock frequency, Cascade operation
30
MHz
6.9 Switching Characteristics: VDD = 3 V
VDD = 3 V, TJ = –40°C to 125°C (unless otherwise noted)
MIN
TYP
MAX
tPLH1
Low-to-high propagation delay time, CLK to OUTn
PARAMETER
TEST CONDITIONS
30
45
60
UNIT
ns
tPLH2
Low-to-high propagation delay time, LE to OUTn
30
45
60
ns
tPLH3
Low-to-high propagation delay time, OE to OUTn
30
45
60
ns
tPLH4
Low-to-high propagation delay time, CLK to SDO
30
40
ns
tPHL1
High-to-low propagation delay time, CLK to OUTn
40
65
100
ns
tPHL2
High-to-low propagation delay time, LE to OUTn
40
65
100
ns
tPHL3
High-to-low propagation delay time, OE to OUTn
40
65
100
ns
tPHL4
High-to-low propagation delay time, CLK to SDO
30
40
ns
tw(CLK)
Pulse duration, CLK
tw(L)
Pulse duration LE
tw(OE)
Pulse duration, OE
th(D)
tsu(D)
15
ns
15
ns
300
ns
Hold time, SDI
2
ns
Setup time, SDI
3
ns
th(L)
Hold time, LE
5
ns
tsu(L)
Setup time, LE
tr
Rise time, CLK
tf
Fall time, CLK
tor
Rise time, outputs (off)
35
tof
Rise time, outputs (on)
15
fCLK
Clock frequency
(1)
VIH = VDD, VIL = GND,
Rext = 840 Ω, VL = 4 V,
RL = 88 Ω, CL = 10 pF
5
ns
(1)
500
ns
500
ns
50
70
ns
50
120
ns
30
MHz
(1)
Cascade operation
If the devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer between two
cascaded devices.
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6.10 Switching Characteristics: VDD = 5.5 V
VDD = 5.5 V, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH1
Low-to-high propagation delay time, CLK to OUTn
20
35
55
ns
tPLH2
Low-to-high propagation delay time, LE to OUTn
20
35
55
ns
tPLH3
Low-to-high propagation delay time, OE to OUTn
20
35
55
ns
tPLH4
Low-to-high propagation delay time, CLK to SDO
20
30
ns
tPHL1
High-to-low propagation delay time, CLK to OUTn
15
28
42
ns
tPHL2
High-to-low propagation delay time, LE to OUTn
15
28
42
ns
tPHL3
High-to-low propagation delay time, OE to OUTn
15
28
42
ns
tPHL4
High-to-low propagation delay time, CLK to SDO
20
30
ns
tw(CLK)
Pulse duration, CLK
tw(L)
Pulse duration LE
tw(OE)
Pulse duration, OE
th(D)
Hold time, SDI
tsu(D)
10
ns
10
ns
200
ns
2
ns
Setup time, SDI
3
ns
th(L)
Hold time, LE
5
ns
tsu(L)
Setup time, LE
tr
Rise time, CLK
tf
Fall time, CLK
tor
Rise time, outputs (off)
25
tof
Rise time, outputs (on)
7
fCLK
Clock frequency
(1)
8
VIH = VDD, VIL = GND,
Rext = 840 Ω, VL = 4 V,
RL = 88 Ω, CL = 10 pF
5
ns
(1)
500
ns
500
ns
45
65
ns
12
20
ns
30
MHz
(1)
Cascade operation
If the devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer between two
cascaded devices.
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0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
CLK
OE
1
LE
0
SDI
off
OUT0
on
off
OUT1
on
off
OUT2
on
off
OUT3
on
off
OUT15
on
SDO
Don't care
Figure 1. Timing Diagram
6.11 Typical Characteristics
50
Temperature = 25°C
IO = 45 mA
IO = 38 mA
Output Current (mA)
40
IO = 31 mA
30
IO = 24 mA
20
IO = 17 mA
IO = 10 mA
10
IO = 3 mA
0
0
0.5
1
1.5
2
2.5
3
Output Voltage (V)
Figure 2. Output Current vs Output Voltage
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7 Parameter Measurement Information
IDD
VDD
OE
IIH, IIL
IOUT
OUT0
CLK
LE
OUT15
SDI
VIH, VIL
R-EXT
GND
SDO
Iref
Figure 3. Test Circuit for Electrical Characteristics
IDD
IOUT
VDD
VIH, VIL
OE
CLK
LE
Function
Generator
OUT0
OUT15
RL
CL
SDI
Logic input
waveform
VIH = VDD
VIL = 0V
R-EXT
GND
SDO
Iref
CL
VL
Figure 4. Test Circuit for Switching Characteristics
10
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Parameter Measurement Information (continued)
tw(CLK)
CLK
50%
tsu(D)
SDI
50%
50%
th(D)
50%
50%
tPLH4, tPHL4
50%
SDO
tw(L)
50%
LE
tsu(L)
th(L)
OE Low
OE
LOW
tPLH2, tPHL2
Output off
OUTn
50%
Output on
tPLH1, tPHL1
tw(OE)
HIGH
50%
OE Pulsed
OE
50%
tPLH3
tPHL3
Output off
90%
OUTn
90%
50%
50%
10%
tof
10%
tor
Figure 5. Normal Mode Timing Waveforms
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8 Detailed Description
8.1 Overview
The TLC5925 is a 16-channel LED driver designed for LED displays and LED lighting applications. The TLC5925
contains a 16-bit shift register and data latches, which convert serial input data into parallel output format. At the
TLC5925 output stage, 16 regulated-current ports provide uniform and constant current for driving LEDs within a
wide range of VF variations. Used in system design for LED display applications (for example, LED panels), the
TLC5925 provides great flexibility and device performance. Users can adjust the output current from 3 mA to 45
mA through an external resistor, REXT, which gives flexibility in controlling the light intensity of LEDs. TLC59025
is designed for up to 17 V at the output port. The high clock frequency, 30 MHz, also satisfies the system
requirements of high-volume data transmission.
8.2 Functional Block Diagram
OUT0
R-EXT
OUT1
OUT14 OUT15
I/O REGULATOR
VDD
8
OUTPUT DRIVER
OE
CONTROL
LOGIC
16
16
16-BIT OUTPUT
LATCH
LE
CONFIGURATION
LATCHES
16
CLK
8
SDI
16-BIT SHIFT
REGISTER
SDO
16
8.3 Feature Description
8.3.1 Constant Current
In LED display applications, TLC5925 provides nearly no current variations from channel to channel and from IC
to IC. While IOUT ≤ 45 mA, the maximum current skew between channels is less than ±5% and between ICs is
less than ±6%.
12
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8.4 Device Functional Modes
The table below lists the functional modes for the TLC5925.
Table 1. Truth Table in Normal Operation
CLK
LE
OE
SDI
OUT0...OUT15...OUT15
SDO
↑
H
L
Dn
Dn...Dn – 7...Dn – 15
Dn – 15
↑
L
L
Dn + 1
No change
Dn – 14
↑
H
L
Dn + 2
Dn + 2...Dn – 5...Dn – 13
Dn – 13
↓
X
L
Dn + 3
Dn + 2...Dn – 5...Dn – 13
Dn – 13
↓
X
H
Dn + 3
off
Dn – 13
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Turning on the LEDs
To turn on an LED connected to one of the outputs of the device, the output must be pulled low. To do this, the
SDI signal must let the device know which outputs should be activated. Using the rising edge of CLK, the logic
level of the SDI signal latches the desired state of each output into the shift register. Once this is complete, the
LE signal must be toggled from low to high then back to low. Once /OE is pulled down, the corresponding
outputs will be pulled low and the LEDs will be turned on. The below diagram shows outputs 0, 3, 4, 5, 10, 13,
and 15 being activated.
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
CLK
OE
1
LE
0
SDI
off
OUT0
on
off
OUT1
on
off
OUT2
on
off
OUT3
on
off
OUT15
on
SDO
Don't care
Figure 6. Timing Diagram
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Application Information (continued)
9.1.2 Propagation Delay Times
Figure 7. CLK to OUT7
Figure 8. OE to OUT1
Figure 9. OE to OUT7
9.2 Typical Application
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Typical Application (continued)
9.2.1 Design Requirements
For the following design procedure, the input voltage (VDD) is between 3 V and 5.5 V.
9.2.2 Detailed Design Procedure
9.2.2.1 Adjusting Output Current
TLC5925 sets IOUT based on the external resistor Rext. Users can follow the below formulas to calculate the
target output current IOUT,target in the saturation region:
IOUT,target = (1.21 V / Rext) × 18, where Rext is the external resistance connected between R-EXT and GND.
Therefore, the default current is approximately 26 mA at 840 Ω and 13 mA at 1680 Ω.
9.2.3 Application Curve
IOUT – mA
The default relationship after power on between IOUT,target and Rext is shown in Figure 10.
45
40
35
30
25
20
15
10
5
0
0
500
1000
1500
2000
Rext – 8W
2500
3000
3500
4000
Figure 10. Default Relationship Curve Between IOUT,target and Rext After Power Up
10 Power Supply Recommendations
The TLC5925 is designed to operate with a VDD range between 3 V and 5.5 V.
11 Layout
11.1 Layout Guidelines
The SDI, CLK, SDO, LE, and OE signals should all be kept from potential noise sources.
All traces carrying power through the LEDs should be wide enough to handle necessary currents.
All LED current passes through the device and into the ground node. There must be a strong connection
between the device ground and the circuit board ground.
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11.2 Layout Example
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12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLC5925IDBQR
ACTIVE
SSOP
DBQ
24
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLC5925I
TLC5925IDWR
ACTIVE
SOIC
DW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLC5925I
TLC5925IDWRG4
ACTIVE
SOIC
DW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLC5925I
TLC5925IPWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
Y5925
TLC5925IPWRG4
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
Y5925
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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