TLC5943
www.ti.com
SBVS101 – DECEMBER 2007
16-Channel, 16-Bit PWM LED Driver with
7-Bit Global Brightness Control
•
FEATURES
1
• 16 Channels, Constant Current Sink Output
• 50-mA Capability (Constant Current Sink)
• 16-Bit (65,536 Steps) Grayscale Control with
Enhanced Spectrum (ES) PWM
• 7-Bit (128 Steps) Global Brightness Control for
All Channels with Sink Current
• LED Power-Supply Voltage up to 17 V
• VCC = 3.0 V to 5.5 V
• Constant Current Accuracy:
– Channel-to-Channel = ±1.5%
– Device-to-Device = ±3%
• CMOS Level I/O
• 30-MHz Data Transfer Rate
• 33-MHz Grayscale Control Clock
• Auto Display Repeat
• Auto Data Refresh
• Continuous Base LED Open Detection (LOD):
– Detect LED opening and LED short to GND
during display
• Thermal Shutdown (TSD):
– Automatic shutdown at high temperature
conditions
– Restart under normal temperature
23
VLED
SCLK
BCSEL
•
•
•
Monochrome, Multicolor, Full-Color LED
Displays
LED Signboards
Display Backlighting
DESCRIPTION
The TLC5943 is a 16-channel, constant current sink
driver. Each channel is individually adjustable with
65,536 enhanced spectrum pulse-width modulated
(PWM) steps controlled by grayscale (GS) data. All
output drivers are adjustable with 128 constant sink
current steps at same value controlled by brightness
control (BC) data. Both GS data and BC data are
writable via a serial interface port. The maximum
current value of all 16 channels can be set by a
single external resistor.
VLED
¼
¼
¼
¼
¼
¼
OUT15
OUT0
SIN
SOUT
SCLK
XERR
SCLK
XERR
BCSEL
VCC VCC
VCC
XLAT
BLANK
VCC
VCC
GSCLK
XTEST
IREF
RIREF
OUT15
SOUT
GSCLK
FLAGS
READ
¼
SIN
BLANK
GSCLK
VLED
¼
XLAT
BLANK
XERR
READ
APPLICATIONS
BCSEL
XLAT
Controller
•
VLED
OUT0
DATA
•
Readable Error Information:
– LED Open Detection (LOD)
– Thermal Error Flag (TEF)
Noise Reduction:
– 4-channel grouped delay to prevent inrush
current
Operating Temperature: –40°C to +85°C
XTEST
IREF
TLC5943
IC1
GND
RIREF
TLC5943
ICn
GND
5
XTEST pin must be connected to VCC or GND.
Typical Application Circuit (Multiple Daisy-Chained TLC5943s)
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
TLC5943
www.ti.com
SBVS101 – DECEMBER 2007
DESCRIPTION, CONTINUED
The TLC5943 has two error detection circuits for LED open detection (LOD) and a thermal error flag (TEF). LOD
detects a broken or disconnected LED and shorted LED to GND during the display period. TEF indicates an
over-temperature condition; when a TEF is set, all output drivers are turned off. When the TEF is cleared, all
output drivers are restarted.
blank
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1)
PRODUCT
PACKAGE-LEAD
TLC5943
HTSSOP-28 PowerPAD™
5 mm × 5 mm QFN-32
TLC5943
(1)
ORDERING NUMBER
TRANSPORT MEDIA,
QUANTITY
TLC5943PWPR
Tape and Reel, 2000
TLC5943PWP
Tube, 50
TLC5943RHBR
Tape and Reel, 3000
TLC5943RHBT
Tape and Reel, 250
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1) (2)
Over operating free-air temperature range, unless otherwise noted.
PARAMETER
TLC5943
VCC
Supply voltage, VCC
IOUT
Output current (dc): OUT0 to OUT15
VIN
Input voltage range:
SIN, SCLK, XLAT, BLANK, GSCLK, BCSEL, IREF
VOUT
Output voltage range
TJ(max)
Maximum operating junction temperature
TSTG
Storage temperature range
ESD rating
(1)
(2)
2
SOUT, XERR
OUT0 to OUT15
Human body model (HBM)
Charged device model (CDM)
UNIT
–0.3 to +6.0
V
60
mA
–0.3 to VCC + 0.3
V
–0.3 to VCC + 0.3
V
–0.3 to +18
V
+150
°C
–55 to +150
°C
2
kV
500
V
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
All voltage values are with respect to network ground terminal.
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SBVS101 – DECEMBER 2007
RECOMMENDED OPERATING CONDITIONS
At TA= –40°C to +85°C, unless otherwise noted.
TLC5943
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
DC Characteristics: VCC = 3 V to 5.5 V
VCC
Supply voltage
VO
Voltage applied to output
3.0
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
IOL
Low-level output current
IOLC
Constant output sink current
TA
Operating free-air temperature
TJ
Operating junction
temperature
5.5
V
17
V
0.7 × VCC
VCC
V
GND
0.3 × VCC
OUT0 to OUT15
V
SOUT
–1
mA
SOUT
1
mA
XERR
5
mA
OUT0 to OUT15
50
mA
–40
+85
°C
–40
+125
°C
AC Characteristics: VCC = 3 V to 5.5 V
fCLK (sclk)
Data shift clock frequency
fCLK (gsclk)
Grayscale control clock
frequency
TWH0 / TWL0
TWH1
Pulse duration
SCLK
30
MHz
GSCLK
33
MHz
SCLK, GSCLK
10
ns
XLAT, BLANK
30
ns
TSU0
SIN–SCLK↑
6
ns
TSU1
XLAT↑–SCLK↑
100
ns
TSU2
BLANK↓–GSCLK↑
10
ns
TSU3
BCSEL–SCLK↑
10
ns
TSU4
BCSEL–XLAT↑
30
ns
TSU5
XLAT↓–SCLK↑
15
ns
TSU6
XLAT↑–BLANK↓
20
ns
TH0
SIN–SCLK↑
3
ns
TH1
XLAT↑–SCLK↑
30
ns
BCSEL–SCLK↓
10
ns
BCSEL–XLAT↑
100
ns
TH2
Setup time
Hold time
TH3
DISSIPATION RATINGS
(1)
(2)
(3)
PACKAGE
OPERATING FACTOR
ABOVE TA = +25°C
TA < +25°C
POWER RATING
TA = +70°C
POWER RATING
TA = +85°C
POWER RATING
HTSSOP-28 with
PowerPAD soldered (1)
31.67 mW/°C
3958 mW
2533 mW
2058 mW
HTSSOP-28 with
PowerPAD not soldered (2)
16.21 mW/°C
2026 mW
1296 mW
1053 mW
QFN-32 (3)
27.86 mW/°C
3482 mW
2228 mW
1811 mW
With PowerPAD soldered onto copper area on printed circuit board (PCB); 2 oz. copper. For more information, see SLMA002 (available
for download at www.ti.com).
With PowerPAD not soldered onto copper area on PCB.
The package thermal impedance is calculated in accordance with JESD51-5.
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SBVS101 – DECEMBER 2007
ELECTRICAL CHARACTERISTICS
At VCC = 3.0 V to 5.5 V, and TA = –40°C to +85°C. Typical values at VCC = 3.3 V and TA = +25°C, unless otherwise noted.
TLC5943
PARAMETER
VOH
TEST CONDITIONS
High-level output voltage
VOL
Low-level output voltage
IIN
IOH = –1 mA at SOUT
IOL = 1 mA at SOUT
MAX
UNIT
VCC – 0.4
TYP
VCC
V
0
0.4
V
0.4
V
1
µA
IOL = 5 mA at XERR
VIN = VCC or GND at SIN, SCLK, GSCLK, XLAT,
BLANK, BCSEL
Input current
MIN
–1
ICC1
SIN/SCLK/GSCLK/XLAT/BCSEL = low, BLANK = high,
GSn = FFFFh, BCn = 7Fh, VOUTn = 1 V, RIREF = 10 kΩ
1
3
mA
ICC2
SIN/SCLK/GSCLK/XLAT/BCSEL = low, BLANK = high,
GSn = FFFFh, BCn = 7Fh, VOUTn = 1 V, RIREF = 2 kΩ
4
8
mA
SCLK/GSCLK = 30 MHz, SIN = 15MHz,
XLAT/BCSEL/BLANK = low,
GSn = FFFFh, BCn = 7Fh, Auto Repeat on,
VOUTn = 1 V, RIREF = 2 kΩ (1)
14
30
mA
SCLK/GSCLK = 30 MHz, SIN = 15MHz,
XLAT/BCSEL/BLANK = low,
GSn = FFFFh, BCn = 7Fh, Auto Repeat on,
VOUTn = 1 V, RIREF = 1 kΩ (1)
27
50
mA
49
55
mA
Supply current (VCC)
ICC3
ICC4
IO(LC)
Constant output current
All OUTn = ON, BCn = 7Fh, VOUTn = 1 V,
VOUTfix = 1 V, RIREF = 1 kΩ
IO(LKG1)
Leakage output current
BLANK = high, RIREF = 1 kΩ, VOUTn = 17 V,
At OUT0 to OUT15
0.1
µA
IO(LKG2)
Leakage output current
No error condition, VXERR = 5.5 V, at XERR
1
µA
ΔIO(LC)
Constant current error
(pin-to-pin) (1)
All OUTn = ON, BCn = 7Fh, VOUTn = 1 V,
VOUTfix = 1 V, RIREF = 1 kΩ, at OUT0 to OUT15
±1.5
±4
%
ΔIO(LC1)
Constant current error
(device-to-device) (2)
All OUTn = ON, BCn = 7Fh, VOUTn = 1 V,
VOUTfix = 1 V, RIREF = 1 kΩ
±3
±9
%
ΔIO(LC2)
Line regulation (3)
All OUTn = ON, BCn = 7Fh, VOUTn = 1 V,
VOUTfix = 1 V, RIREF = 1 kΩ, at OUT0 to OUT15
±1
±4
%/V
ΔIO(LC3)
Load regulation (4)
All OUTn = ON, DCn = 7Fh, VOUTn = 1 V to 3 V,
VOUTfix = 1 V, RIREF = 1 kΩ, at OUT0 to OUT15
±1
±3
%/V
T(TEF)
Thermal error flag threshold
Junction temperature (5)
+150
+162
+175
°C
T(HYS)
Thermal error hysteresis
Junction temperature (5)
+5
+10
+20
°C
VLOD
LED open detection threshold
All OUTn = ON
VIREF
Reference voltage output
RIREF = 1 kΩ
(1)
43
0.2
0.3
0.4
V
1.16
1.20
1.24
V
The deviation of each output from the average of OUT0–OUT15 constant current. Deviation is calculated by the formula:
IOUTn
D (%) =
-1
´ 100
(IOUT0 + IOUT1 + ... + IOUT15)
(2)
16
.
The deviation of the OUT0–OUT15 constant current average from the ideal constant current value.
Deviation is calculated by the following formula:
(IOUT0 + IOUT1 + ... IOUT14 + IOUT15)
- (Ideal Output Current)
16
D (%) =
´ 100
Ideal Output Current
Ideal current is calculated by the formula:
IOUT(IDEAL) = 41 ´
(3)
1.20
RIREF
Line regulation is calculated by this equation:
D (%/V) =
(IOUTn at VCC = 5.5 V) - (IOUTn at VCC = 3.0 V)
(4)
(IOUTn at VOUTn = 3 V) - (IOUTn at VOUTn = 1 V)
100
´
(IOUTn at VOUTn = 1 V)
4
5.5 V - 3 V
Load regulation is calculated by the equation:
D (%/V) =
(5)
100
´
(IOUTn at VCC = 3.0 V)
3V-1V
Not tested. Specified by design.
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TLC5943
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SBVS101 – DECEMBER 2007
SWITCHING CHARACTERISTICS
At VCC = 3.0 V to 5.5 V, TA = –40°C to +85°C, CL = 15 pF, RL = 82 Ω, RIREF = 1 kΩ, and VLED = 5.0 V. Typical values at
VCC = 3.3 V and TA = +25°C, unless otherwise noted.
TLC5943
PARAMETER
tR0
Rise time
tR1
tF0
TEST CONDITIONS
MIN
TYP
SOUT
16
OUTn, BC = 7Fh
10
SOUT
tF1
Fall time
XERR, CL = 100 pF, RL = 1 kΩ, VXERR = 5 V
tD0
SCLK↑ to SOUT
tD1
BLANK↑ to OUT0 sink current off
tD2
GSCLK↑ to OUT0/4/8/12
Propagation delay time
tD3
30
16
OUTn, BC = 7Fh
tF2
MAX
10
30
UNIT
ns
ns
100
ns
25
ns
20
40
ns
5
18
40
ns
GSCLK↑ to OUT1/5/9/13
20
42
73
ns
tD4
GSCLK↑ to OUT2/6/10/14
35
66
106
ns
tD5
GSCLK↑ to OUT3/7/11/15
50
90
140
ns
10
ns
tON_ERR
(1)
Output on-time error (1)
GSn = 0001h, GSCLK = 33 MHz
–20
Output on-time error is calculated by the following formula: TON_ERR (ns) = tOUTON – TGSCLK. tOUTON is the actual on-time of the constant
current driver. TGSCLK is the period of GSCLK.
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SBVS101 – DECEMBER 2007
FUNCTIONAL BLOCK DIAGRAM
VCC
16
LED Open Detection Data Latch
(16 LOD)
gsclk33
VCC
16
LSB
MSB
SIN
Grayscale Shift Register
(16 Bits x 16 Channels)
SOUT
0
SCLK
255
256
LSB
MSB
First Grayscale Data Latch
(16 Bits x 16 Channels)
0
255
256
LSB
MSB
Second Grayscale Data Latch
(16 Bits x 16 Channels)
BCSEL
0
255
LSB
MSB
Brightness Control (7 Bits) / Auto
Repeat Enable (1 Bit) Shift Register
0
LSB
XLAT
7
MSB
8
0
LSB
rptena
MSB
0
GS Counter/
Auto Repeat/
Refresh
GSCLK
7
7
Second Brightness Control (7 Bits)
Data Latch
bclat2
gsclk33
gslat2
xlatbuf
256
loderr
First Brightness Control (7 Bits) / Auto
Repeat Enable (1 Bit) Data Latch
6
1
16-Bit ES PWM Timing Control
16
XERR
XERR
Control
blankbuf
16
Constant Current Driver with 7-Bit
(128 Steps) Global Current Control
Reference
Current
Control
IREF
blankbuf
Output Switching Delay
(4-Channel Unit)
tderr
BLANK
xlatbuf
16
7
16
XTEST
Thermal
Detection
LED Open Detection
(LOD, 16 Channels)
GND
GND
¼
OUT0
6
OUT1
OUT14
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OUT15
Copyright © 2007, Texas Instruments Incorporated
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SBVS101 – DECEMBER 2007
DEVICE INFORMATION
PWP PACKAGE
(Top View)
GSCLK
SIN
5
24
BCSEL
6
OUT0
7
16
OUT10
SOUT
IREF
26
15
OUT9
23
XERR
VCC
27
14
OUT8
22
OUT15
NC
28
13
NC
12
NC
Thermal
Pad
19
OUT12
BLANK
31
10
OUT6
OUT4
11
18
OUT11
XLAT
32
9
OUT5
OUT5
12
17
OUT10
OUT6
13
16
OUT9
OUT7
14
15
OUT8
8
10
OUT4
OUT3
7
OUT7
OUT3
11
6
30
OUT2
GND
5
OUT13
OUT1
20
4
9
OUT0
29
3
NC
BCSEL
OUT14
2
21
SIN
OUT2
25
1
8
XTEST
SCLK
OUT1
Thermal
Pad
OUT11
25
17
4
OUT12
SCLK
18
XTEST
OUT13
26
19
3
OUT14
XLAT
20
IREF
OUT15
27
21
2
XERR
BLANK
22
VCC
SOUT
28
23
1
GSCLK
GND
24
RHB PACKAGE
(Top View)
NC = No internal connection.
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SBVS101 – DECEMBER 2007
TERMINAL FUNCTIONS
TERMINAL
NAME
SIN
PWP
RHB
I/O
5
2
I
Serial data input for grayscale and brightness control data. Schmitt buffer input.
DESCRIPTION
SCLK
4
1
I
Serial data shift clock for GS shift register and BC shift register. Schmitt buffer input. The shift
register is selected by BCSEL. Data present on the SIN pin are shifted into the shift register
selected by BCSEL with the rising edge of the SCLK pin. Data in the selected shift register are
shifted to the MSB side by 1-bit synchronizing to the rising edge of SCLK. The MSB data of the
selected register appears on SOUT.
XLAT
3
32
I
Data in the Grayscale and Brightness shift register are moved to the respective first data latch
with a low-to-high transition of this pin.
BCSEL
6
3
I
Shift register and data latch select. Schmitt buffer input. When BCSEL is low, Grayscale shift
register and first data latch are selected. When BCSEL is high, Brightness Control shift register
and first data latch are selected. BCSEL should not be changed while SCLK is high.
GSCLK
25
24
I
Reference clock for Grayscale PWM control. Schmitt buffer input. If BLANK is low, then each
rising edge of GSCLK increments the grayscale counter for PWM control.
Blank (all constant current outputs off). Schmitt buffer input. When BLANK is high, all constant
current outputs (OUT0 through OUT15) are forced off, the Grayscale counter is reset to '0', and
the Grayscale PWM timing controller is initialized. When BLANK is low, all constant current
outputs are controlled by the Grayscale PWM timing controller.
BLANK
2
31
I
IREF
27
26
I/O
Constant current value setting. OUT0 through OUT15 sink constant current is set to desired
value by connecting an external resistor between IREF and GND.
SOUT
24
23
O
Serial data output. This output is connected to Grayscale/Status Information shift register or
Brightness Control shift register. The connected register is selected by BCSEL.
XERR
23
22
O
Error output. Open-drain output. XERR goes low when LOD or TEF is detected.
OUT0
7
4
O
Constant current output.
OUT1
8
5
O
Constant current output
OUT2
9
6
O
Constant current output
OUT3
10
7
O
Constant current output
OUT4
11
8
O
Constant current output
OUT5
12
9
O
Constant current output
OUT6
13
10
O
Constant current output
OUT7
14
11
O
Constant current output
OUT8
15
14
O
Constant current output
OUT9
16
15
O
Constant current output
OUT10
17
16
O
Constant current output
OUT11
18
17
O
Constant current output
OUT12
19
18
O
Constant current output
OUT13
20
19
O
Constant current output
OUT14
21
20
O
Constant current output
OUT15
22
21
O
Constant current output
VCC
28
27
—
Power-supply voltage
GND
1
30
—
Power ground
XTEST
26
25
I
—
12, 13,
28, 29
—
NC
8
Factory test pin. XTEST must be connected to VCC or GND.
No internal connection
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SBVS101 – DECEMBER 2007
PARAMETER MEASUREMENT INFORMATION
PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
VCC
INPUT
SOUT
GND
GND
Figure 1. SIN, SCLK, XLAT, BCSEL, BLANK, GSCLK
Figure 2. SOUT
XERR
OUTn
GND
GND
Figure 3. XERR
Figure 4. OUT0 Through OUT15
TEST CIRCUITS
RL
VCC
VCC
VCC
OUTn
IREF
(1)
RIREF
VLED
GND
(1)
CL includes measurement probe and jig
capacitance.
Figure 5. Rise Time and Fall Time Test Circuit for OUTn
(1)
CL includes measurement probe and jig
capacitance.
Figure 6. Rise Time and Fall Time Test Circuit for SOUT
VCC
VCC
XERR
IREF
VXERR
RIREF
OUTn
¼
GND
(1)
OUT0
¼
RL
VCC
CL
CL
GND
(1)
VCC
SOUT
VCC
CL
GND OUT15
VOUTn
VOUTFIX
(1)
CL includes measurement probe and jig
capacitance.
Figure 7. Rise Time and Fall Time Test Circuit for XERR
Figure 8. Constant Current Test Circuit for OUTn
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SBVS101 – DECEMBER 2007
TIMING DIAGRAMS
TWH0, TWH1, TWL0
VCC
INPUT
(1)
50%
GND
TWL
TWH
TSU0, TSU1, TSU2, TSU3, TSU4, TSU5, TSU6, TH0, TH1, TH2, TH3
VCC
CLOCK
INPUT
(1)
50%
GND
TSU
TH
VCC
DATA/CONTROL
INPUT
(1)
50%
GND
(1)
Input pulse rise and fall time is 1 ns to 3 ns.
Figure 9. Input Timing
tR0, tR1, tF0, tF1, tD0, tD1, tD2, tD3, tD4, tD5:
VCC
INPUT
(1)
50%
GND
tD
VOH or VOUTnH
90%
(2)
OUTPUT
50%
10%
VOL or VOUTnL
tR or tF
(1)
Input pulse rise and fall time is 1 ns to 3 ns.
(2)
Input pulse high level is VCC and low level is GND.
Figure 10. Output Timing
10
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SBVS101 – DECEMBER 2007
BCSEL
TSU4
TSU3
SIN
GS0
0A
GS15
15B
GS15
14B
GS15
13B
GS15
12B
TH3
GS0
3B
GS15
11B
TH0
TSU0
GS0
2B
GS0
0B
GS0
1B
TWH0
TH1
TSU1
SCLK
1
2
3
4
5
253
254
255
256
TH2
TWL0
TWH0
GSCLK
65,534 65,535 65,536 65,537 65,538
TWL0
TGSCLK
TWH1
XLAT
TSU6
TWH1
BLANK
TSU2
Latched Data
for Grayscale
(Internal)
SOUT
Previous Data
GS15
15A
tD0
GS15 GS15
14A
13A
GS15
12A
GS15
11A
GS15
10A
GS0
3A
GS0
2A
GS0
1A
GS0
0A
Latest Data
GS15
15B
LOD
15
LOD
13
LOD
14
LOD
12
LOD
11
tR0/tF0
LOD
10
LOD
9
tD1
Turning off outputs with the BLANK signal (all GS data are greater than 0300h):
OUT
0, 4, 8, 12
OFF
ON
(VOUTnH)
(VOUTnL)
tD2
OUT OFF
1, 5, 9, 13 ON
If GS data = FFFFh (65535d)
tF1
tD3
tR1
OUT OFF
2, 6, 10, 14 ON
tD4
OUT OFF
3, 7, 11, 15 ON
tD5
Turning off outputs with GSCLK (all GS data are set to 0001h):
OUT
0, 4, 8, 12
OFF
ON
tD2
OUT OFF
1, 5, 9, 13 ON
tD3
OUT OFF
2, 6, 10, 14 ON
tD4
OUT OFF
3, 7, 11, 15 ON
tD5
tOUTON
tOUTON
tOUTON
tOUTON
tON_ERR = tOUTON - TGSCLK
Figure 11. Grayscale Data Write and Constant Current Output Timing
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SBVS101 – DECEMBER 2007
BCSEL
TSU4
TH3
TSU3
SIN
BC
7B
N/A
BC
6B
BC
5B
BC
4B
BC
3B
BC
2B
BC
1B
BC
7C
BC
0B
BC
6C
BC
5C
BC
4C
BC
3C
BC
2C
BC
1C
BC
0C
TH0
TSU0
TH2
TSU1
TWH0
SCLK
1
2
3
4
5
7
6
TWL0
1
8
2
3
4
5
7
6
8
TH1
TWH1
XLAT
Latched Data
for Brightness Control
(Internal)
Previous Data
New BC Data
tD0
BC
7A
SOUT
BC
6A
BC
5A
BC
4A
BC
3A
BC
2A
BC
1A
BC
7B
BC
0A
BC
6B
BC
5B
BC
4B
BC
3B
BC
2B
BC
1B
BC
7C
BC
0B
tR0/tF0
Figure 12. Brightness Control Data Write Timing
BCSEL
Low ('L') level
The SCLK falling edge must be prior to the XLAT rising edge in case SID is read.
SIN
GS0
0A
GS0
1A
255
256
GS15
15B
GS15
14B
GS15
13B
GS15
12B
GS15
11B
1
2
3
4
5
TSU1
GS15
2B
GS15
1B
14
15
13
GS15
0B
GS14
15B
16
GS14
14B
17
GS14
12B
GS14
13B
18
19
20
GS0
0B
GS0
1B
254
255
256
SCLK
TH1 TWH1 TSU5
XLAT
tD0
SOUT
GS0
0
GS15
15A
LOD
15
LOD
14
LOD
13
LOD
12
LOD
3
LOD
2
LOD
1
LOD
0
256
255
254
253
244
243
242
241
TEF
GS14
14A
GS14
13A
GS0
1A
GS0
0A
239
238
2
1
GS15
15B
SID are entered in the GS shift register at the first rising edge of SCLK after XLAT goes low.
The SID readout consists of the saved LOD result at the 33rd GSCLK rising edge in the previous display period
and the TEF data after the previous TEF data readout.
Figure 13. Status Information Data Read Timing
12
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SBVS101 – DECEMBER 2007
TYPICAL CHARACTERISTICS
At VCC = 3.3 V and TA = +25°C, unless otherwise noted.
REFERENCE RESISTOR vs
OUTPUT CURRENT
10000
POWER DISSIPATION RATE
vs FREE-AIR TEMPERATURE
4000
Power Dissipation Rate (mW)
Reference Resistor (W)
9840
4920
3280
2460
1968
1640
1406
1230
1093
TLC5943PWP
PowerPAD Soldered
TLC5943RHB
3000
2000
TLC5943PWP
PowerPAD Not Soldered
1000
984
0
1000
0
30
20
10
40
50
-40
-20
Output Current (mA)
60
Figure 15.
OUTPUT CURRENT vs
OUTPUT VOLTAGE
OUTPUT CURRENT vs
OUTPUT VOLTAGE
55
53
40
IO = 30 mA
30
IO = 20 mA
20
IO = 10 mA
10
0
2.0
2.5
TA = +85°C
51
50
49
TA = -40°C
TA = +25°C
48
46
45
0
3.0
0.5
1.5
1.0
2.0
Output Voltage (V)
Output Voltage (V)
Figure 16.
Figure 17.
ΔIOLC vs
AMBIENT TEMPERATURE
ΔIOLC vs
OUTPUT CURRENT
5
IO = 50 mA
BC = 7Fh
3
3
2
2
1
0
3.0
1
0
-1
-1
-2
-2
-3
2.5
TA = +25°C
BC = 7Fh
4
DIOLC (%)
DIOLC (%)
1.5
1.0
0.5
52
47
IO = 5 mA
0
4
100
IO = 50 mA
BC = 7Fh
54
IO = 50 mA
Output Current (mA)
Output Current (mA)
Figure 14.
IO = 40 mA
5
80
60
40
Free-Air Temperature (°C)
TA = +25°C
BC = 7Fh
50
20
0
-3
VCC = 3.3 V
-4
VCC = 3.3 V
-4
VCC = 5 V
-5
VCC = 5 V
-5
-40
-20
0
20
40
60
80
100
0
10
20
30
Ambient Temperature (°C)
Output Current (mA)
Figure 18.
Figure 19.
40
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SBVS101 – DECEMBER 2007
TYPICAL CHARACTERISTICS (continued)
At VCC = 3.3 V and TA = +25°C, unless otherwise noted.
BRIGHTNESS CONTROL LINEARITY
BRIGHTNESS CONTROL LINEARITY
60
60
TA = +25°C
IOLCMax = 50 mA
50
IOLCMax = 50 mA
Output Current (mA)
Output Current (mA)
50
40
30
20
IOLCMax = 30 mA
10
40
30
20
TA = -40°C
TA = +25°C
10
IOLCMax = 5 mA
TA = +85°C
0
0
0
20
40
60
80
100
120
0
140
20
40
60
80
100
Brightness Control Data (dec)
Brightness Control Data (dec)
Figure 20.
Figure 21.
120
140
CONSTANT CURRENT OUTPUT
VOLTAGE WAVEFORM
CH1-GSCLK
(30 MHz)
CH1 (2 V/div)
CH2 (2 V/div)
CH3 (2 V/div)
CH2-OUT0
(GSData = 0x001h)
IOLCMax = 50 mA, BC = 7Fh
TA = +25°C,RL = 82 W
CL = 15 pF, VLED = 5 V
CH3-OUT15
(GSData = 0x001h)
Time (25 ns/div)
Figure 22.
14
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SBVS101 – DECEMBER 2007
DETAILED DESCRIPTION
Setting for the Maximum Constant Sink Current Value
On the TLC5943, the maximum constant current sink value for each channel, IOLCMax, is determined by an
external resistor, RIREF, placed between the IREF and GND pins. The RIREF resistor value is calculated with
Equation 1:
RIREF (kW) =
VIREF (V)
´ 41
IOLCMax (mA)
(1)
Where:
•
VIREF = the internal reference voltage on the IREF pin (typically 1.20 V)
IOLCMax is the largest current for all outputs. Each output sinks the IOLCMax current when it is turned on and the
brightness control data are set to the maximum value of 7Fh (127d). The sink current for each output can be
reduced by lowering the brightness control data.
RIREF must be between 984 Ω (typ) and 9.84 kΩ (typ) in order to keep IOLCMax between 5 mA and 50 mA. The
output may become unstable when IOLCMax is set lower than 5 mA. However, output currents lower than 5 mA
can be achieved by setting IOLCMax to 5 mA or higher, and then using brightness control to lower the output
current.
Figure 14 in the Typical Characteristics and Table 1 show the characteristics of the constant sink current versus
the external resistor, RIREF.
Table 1. Maximum Constant Current Output versus
External Resistor Value
IOLCMax (mA, Typical)
RIREF (Ω)
50
984
45
1093
40
1230
35
1406
30
1640
25
1968
20
2460
15
3280
10
4920
5
9840
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SBVS101 – DECEMBER 2007
Brightness Control (BC) Function
The TLC5943 is able to adjust the output current of all channels (OUT0 to OUT15). This function is called
brightness control (BC). The BC function allows users to adjust the global brightness of LEDs connected to the
outputs OUT0 to OUT15. All channel output currents can be adjusted in 128 steps from 0% to 100% of the
maximum output current, IOLCMax. The brightness control data are entered into the TLC5943 via the serial
interface.
Equation 2 determines the sink current for each output (OUTn):
IOUTn (mA) = IOLCMax (mA) ´ ( BCn )
127d
(2)
Where:
•
•
IOLCMax = the maximum channel current for each channel determined by RIREF
BCn = the programmed brightness control value for OUTn (BCn = 0 to 127d)
When the IC is powered on, the data in the Brightness Control Shift Register and data latch 1 and 2 are not set
to any default values. Therefore, BC data must be written to the BC latch 1 and 2 before turning on the constant
current output.
Table 2 summarizes the BC data versus current ratio and set current value.
Table 2. BC Data versus Current Ratio and Set Current Value
16
BC DATA
(Binary)
BC DATA
(Decimal)
BC DATA
(Hex)
SET CURRENT
RATIO TO
MAX CURRENT (%)
OUTPUT CURRENT
(mA, Typical)
AT IOLCMax = 50 mA
OUTPUT CURRENT
(mA, Typical)
AT IOLCMax = 5 mA
000 0000
0
00
0.0
0.0
0.00
000 0001
1
01
0.8
0.4
0.04
000 0010
2
02
1.6
0.8
0.08
... ...
... ...
... ...
... ...
... ...
... ...
111 1101
125
7D
98.4
49.2
4.92
111 1110
126
7E
99.2
49.6
4.96
111 1111
127
7F
100.0
50.0
5.00
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SBVS101 – DECEMBER 2007
Grayscale (GS) Function (Enhanced Spectrum PWM Operation)
The TLC5943 has an enhanced spectrum pulse-width modulation (ES PWM) function. In this PWM control, the
total display period is divided to 128 display segments. Total display period means the timing from the first
grayscale clock (GSCLK) input to the 65,536th grayscale clock input after BLANK goes low. Each display period
has 512 grayscale as a maximum. The driver (OUTn) on time changes depending on the 16-bit grayscale data.
Refer to Table 3 for sequence information and Figure 23 for timing information.
Table 3. ES PWM Drive Turn-On Time Length
GS DATA (Dec)
GS DATA (Hex)
OUTn DRIVER OPERATION
0
0000h
No turn on
1
0001h
Turns on during 1GSCLK period in first display period
2
0002h
Turns on during 1GSCLK period in first and 65th display periods
3
0003h
Turns on during 1GSCLK period in first, 65th, and 33rd display periods
4
0004h
Turns on during 1GSCLK period in first, 65th, 33rd, and 97th display periods
5
0005h
Turns on during 1GSCLK period in first, 65th, 33rd, 97th, and 17th display periods
6
0006h
Turns on during 1GSCLK period in first, 65th, 33rd, 97th, 17th, and 81st display
periods
---
---
The number of display periods in which OUTn turns on during 1GSCLK is
increased by GS data increasing in the following order.
The display period order in which OUTn turns on :
1>65>33>97>17>81>49>113>9>73>41>105>25>89>57>121>5>69>37>101>21>
85>53>117>13>77>45>109>29>93>61>125>3>67>35>99>19>83>51>115>11>
75>43>107>27>91>59>123>7>71>39>103>23>87>55>119>15>79>47>111>31>
95>63>127>2>66>34>98>18>82>50>114>10>74>42>106>26>90>58>122>6>70>
38>102>22>86>54>118>14>78>46>110>30>94>62>126>4>68>36>100>20>84>
52>116>12>76>44>108>28>92>60>124>8>72>40>104>24>88>56>120>16>80>
48>112>32>96>64>128.
127
007Fh
Turns on during 1GSCLK period in first through 127th display period. No turn on in
128th display period only.
128
0080h
Turns on during 1GSCLK period in all (1 through 128th) display periods.
129
0081h
Turns on during 2GSCLK periods in first display period and 1GSCLK period in
other display periods.
---
---
255
00FFh
Turns on during 2GSCLKs period in 1 through 127th display period and turns on
1GSCLK period in 128th display period only.
256
0100h
Turns on during 2GSCLK periods in all (1 through 128th) display periods.
257
0101h
Turns on during 3GSCLK periods in first display period and 2GSCLK periods in
other display periods.
---
---
Display period in which OUTn turn-on time increases by GS data, increasing as
does above operation
65478
FEFFh
Turns on during 511 GSCLK period in 1 through 127th display period and turns on
510 GSCLK period in 128th display period only.
65279
FF00h
Turns on during 511 GSCLK period in all (1 through 128th) display periods.
65280
FF01h
Turns on during 512 GSCLK period in first display period + 511 GSCLK period in
second through 128th display period.
---
---
65534
FFFEh
Turns on during 512 GSCLK period in first through 63rd and 65th through 127th
display period, and turns on 511 GSCLK period in 64th and 128th display periods.
65535
FFFFh
Turns on during 512 GSCLK period in first through 127th display periods, and turns
on 511 GSCLK period in 128th display period only.
The number of display periods in which OUTn turns on during 2GSCLKs increases
by GS data as when GS is 130 through 254.
Display period in which OUTn turn-on time increases by GS data, increasing as
does above operation
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SBVS101 – DECEMBER 2007
Constant Current Driver ON/OFF Tming in ES-PWM
BLANK
1 2 3
512 514
511 513
16,383 16,385 16,387 32,767 32,769 32,771
49,151 49,153 49,155 65,024 65,026
65,535
16,382 16,384 16,386
32,766 32,768 32,770
49,150 49,152 49,154
65,023 65,025
65,534 65,536
GSCLK
32nd
Period
33rd
Period
¼
¼
2nd
Period
64th 65th
Period Period
¼
OUTn
1st Period
96th
Period
97th
Period
¼
Voltage level = High ('H')
127th
Period
128th Period
1st Period
OFF
ON
Voltage level = Low ('L’)
(GSDATA = 000h)
T = GSCLK ´ 1d
OUTn
OFF
ON
(GSDATA = 001h)
T = GSCLK ´ 1d
OUTn
ON
(GSDATA = 002h)
OUTn
If Auto Repeat
is enabled
T = GSCLK ´ 1d
OFF
OFF
T = GSCLK ´ 1d
T = GSCLK ´ 1d
T = GSCLK ´ 1d
ON
(GSDATA = 003h)
T = GSCLK ´ 1d
T = GSCLK ´ 1d
T = GSCLK ´ 1d
OUTn
T = GSCLK ´ 1d
OFF
ON
¼
¼
(GSDATA = 004h)
T = GSCLK ´ 1d
T = GSCLK ´ 1d
T = GSCLK ´ 1d
T = GSCLK ´ 1d
T = GSCLK ´ 1d
OUTn
OFF
ON
¼
¼
(GSDATA = 0041h)
T = GSCLK ´ 1d
OUTn
OFF
T = GSCLK ´ 1d
T = GSCLK ´ 1d
T = GSCLK
´ 1d
T = GSCLK
´ 2d
T = GSCLK ´ 1d
T = GSCLK ´ 1d
T = GSCLK ´ 1d
T = GSCLK ´ 1d
T = GSCLK
´ 1d
T = GSCLK
´ 2d
T = GSCLK ´ 1d
T = GSCLK ´ 1d
T = GSCLK ´ 1d
T = GSCLK
´ 1d
ON
(GSDATA = 0081h)
OUTn
T = GSCLK ´ 1d
ON
(GSDATA = 0080h)
OUTn
T = GSCLK ´ 1d
OFF
OFF
T = GSCLK
´ 2d
ON
T = GSCLK ´ 511d
OUTn
T = GSCLK ´ 511d
in 2nd through 128th Periods
OFF
ON
(GSDATA = FFC0h)
OUTn
¼
¼
(GSDATA = 0082h)
T = GSCLK ´ 511d
in 2nd through 128th Periods
T = GSCLK ´ 512d
OFF
ON
¼
¼
(GSDATA = FFC1h)
OUTn
T = GSCLK ´ 512d
T = GSCLK ´ 512d in 2nd through 63rd and 65th through 127th Periods;
T = GSCLK ´ 511d in 64th Period
T = GSCLK ´ 511d
T = GSCLK ´ 512d
T = GSCLK ´ 512d in 2nd through 127th Periods
T = GSCLK ´ 511d
OFF
ON
(GSDATA = FFFEh)
OUTn
OFF
ON
(GSDATA = FFFFh)
Figure 23. PWM Operation Timing
18
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When the IC powers on, the data in the Grayscale Shift Register and latch 1/2 are not set to any default value.
Therefore, grayscale data must be written to the Grayscale latch before turning on the constant current output.
Additionally, BLANK should be high when the device turns on, to prevent the outputs from turning on before the
proper grayscale and brightness control values can be written. All constant current outputs are always off when
BLANK is high. Equation 3 determines each output (OUTn) total on time (tOUTON):
tOUTON (ns) = TGSCLK (ns) ´ GSn
(3)
Where:
•
•
TGSCLK = the period of GSCLK
GSn = the programmed grayscale value for OUTn (GSn = 0 to 65,535d)
Table 4 summarizes the GS data versus OUTn on duty and on time.
Table 4. GS Data versus OUTn Total On Duty
GS DATA (Decimal)
GS DATA (Hex)
ON-TIME DUTY (%)
GS DATA (Decimal)
GS DATA (Hex)
ON-TIME DUTY (%)
0
1
0
0
32768
8000
50.001
1
0.002
32769
8001
50.002
2
2
0.003
32770
8002
50.004
3
3
0.005
32771
8003
50.005
---
---
---
---
---
---
8191
1FFF
12.499
40959
9FFF
62.499
8192
2000
12.5
40960
A000
62.501
8193
2001
12.502
40961
A001
62.502
---
---
---
---
---
---
16381
3FFD
24.996
49149
BFFD
74.997
16382
3FFE
24.997
49150
C000
74.998
16383
3FFF
24.999
49151
C001
75
16384
4000
25
49152
C002
75.001
16385
4001
25.002
49153
C003
75.003
16386
4002
25.003
49154
C004
75.004
16387
4003
25.005
49155
C005
75.006
---
---
---
---
---
---
24575
5FFF
37.499
57343
DFFF
87.5
24576
6000
37.501
57344
E000
87.501
24577
6001
37.502
57345
E001
87.503
---
---
32765
7FFD
49.996
65533
FFFD
99.997
32766
7FFE
49.998
65534
FFFE
99.998
32767
7FFF
49.999
65535
FFFF
100
---
---
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SBVS101 – DECEMBER 2007
Auto Display Repeat Function
This function can repeat the total display period without a BLANK signal as long as GSCLK is input as Figure 24
shows. This function can be switched on or off by the data of bit 7 in the first latch of the Brightness Control.
When bit 7 is '1', Auto Repeat is enabled and the entire display period repeats without a BLANK signal. When bit
7 is '0', Auto Repeat is disabled and the entire display period executes only one time after the falling edge of
BLANK.
BLANK
1 2 3 4 5
65,534 65,536
65,535 1 2 3 4 5
¼65,533
65,534 65,536
65,535 1 2 3 4 5 6 7 8 9 10
¼ 65,533
1 2
65,534 65,536
65,535 1 2
¼
GSCLK
Brightness
1st Latch
Bit 7
Bit 7 = ‘1’
(Auto Repeat On)
Bit 7 = ‘0’
(Auto Repeat Off)
1st of 128
display period
Display period repeated
by Auto Refresh function
OFF
OUTn
(GSData = FFFFh)
2nd of 128
display period
3rd of 128
display period
OUTn is forced off
when BLANK goes high
1st of 128
display period
OUTn is not
turned on until
next BLANK
falling edge
ON
Figure 24. Auto Repeat Display Function Timing
20
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Auto Data Refresh Function
This function allows users to input Grayscale (GS) data or Brightness Control (BC) data any time without
synchronizing the input to the BLANK signal. If GS data or BC data are input during a display period, the input
data are held in the first latch for each data register. Data are then transferred to the second latch when the
65,536th GSCLK occurs. The second latch data are used for the next display period. Figure 25 through
Figure 27 show the timing.
However, when the high level signal of BLANK occurs before the 65,536th GSCLK, then the first latch data
upload to the second latch immediately. Also, when the XLAT rising edge inputs while BLANK is at a high level,
then the selected shift register data are transferred to the first and second latch at the same time. Bit 7 data of
BC update immediately whenever the data are written into the first latch.
SIN
GS0
4A
GS0
3A
GS0
2A
GS0
1B
251 252
253
254
255
GS0
0A
BC
7A
BC
6A
BC
5A
BC
4A
BC
3A
BC
2A
BC
1A
2
3
4
5
6
7
BC
0A
GS15
15B
GS15
14B
GS15
13B
GS15
12B
1
2
3
4
SCLK
BCSEL
256
1
Low level ('L') = Grayscale Register is selected
8
High level ('H') = Brightness Register is selected
XLAT
65,536
65,535
1 2
3
4
5
6
7
8
GSCLK
BLANK
Low level ('L')
GS Shift Register
(Internal)
Latest Grayscale Data
GSData
1st Latch (Internal)
Previous Grayscale Data
Latest Grayscale Data
GSData
2nd Latch (Internal)
BC Shift Register
(Internal)
Previous Grayscale Data
Latest Grayscale Data
Previous Brightness Data
Latest Brightness Data
BCData
1st Latch (Internal)
Previous Brightness Data
BCData
2nd Latch (Internal)
Previous Brightness Data (Bit 0-Bit 6)
OFF
OUTn
Latest Brightness Data
Latest Brightness Data (Bit 0-Bit 6)
PWM/Brightness Controlled by Previous Data
PWM/Brightness Controlled by Latest Data
ON
SOUT
GS0
4
GS0
3
GS0
2
GS0
1
GS0
0
GS15
15A
BC
7
BC
6
BC
5
BC
4
BC
3
BC
2
BC
1
BC
0
BC
7A
GS15
15A
GS15
14A
GS15
13A
GS15
12A
GS15
11A
If there is no BLANK input when Auto Repeat is enabled.
Figure 25. Auto Refresh Data Function Timing 1
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SBVS101 – DECEMBER 2007
SIN
GS0
4A
GS0
3A
GS0
2A
GS0
1B
251 252
253
254
255
GS0
0A
BC
7A
BC
6A
BC
5A
BC
4A
BC
3A
BC
2A
BC
1A
2
3
4
5
6
7
BC
0A
GS15
15B
GS15
14B
GS15
13B
GS15
12B
1
2
3
4
SCLK
BCSEL
256
1
Low level ('L') = Grayscale Register is selected
8
High level ('H') = Brightness Register is selected
XLAT
1 2
3
4
5
6
7
8
GSCLK
BLANK
Low level ('L')
GS Shift Register
(Internal)
GSData
1st Latch (Internal)
Latest Grayscale Data
Previous Grayscale Data
Latest Grayscale Data
GSData
2nd Latch (Internal)
BC Shift Register
(Internal)
Previous Grayscale Data
Latest Grayscale Data
Previous Brightness Data
Latest Brightness Data
BCData
1st Latch (Internal)
Previous Brightness Data
BCData
2nd Latch (Internal)
Previous Brightness Data (Bit 0-Bit 6)
OFF
OUTn
Latest Brightness Data
Latest Brightness Data (Bit 0-Bit 6)
PWM/Brightness Controlled by Previous Data
PWM/Brightness Controlled by Latest Data
ON
SOUT
GS0
4
GS0
3
GS0
2
GS0
1
GS0
0
GS15
15A
BC
7
BC
6
BC
5
BC
4
BC
3
BC
2
BC
1
BC
0
BC
7A
GS15
15A
GS15
14A
GS15
13A
GS15
12A
GS15
11A
When the BLANK input occurs after XLAT.
Figure 26. Auto Refresh Data Function Timing 2
22
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SIN
SBVS101 – DECEMBER 2007
GS0
4A
GS0
3A
GS0
2A
GS0
1B
251 252
253
254
255
GS0
0A
BC
7A
BC
6A
BC
5A
BC
4A
BC
3A
BC
2A
BC
1A
2
3
4
5
6
7
BC
0A
GS15
15B
GS15
14B
GS15
13B
GS15
12B
1
2
3
4
SCLK
BCSEL
256
1
8
High level ('H') = Brightness Register is selected
Low level ('L') = Grayscale Register is selected
XLAT
1 2
3
4
5
6
7
8
GSCLK
BLANK
Low level ('L')
GS Shift Register
(Internal)
Latest Grayscale Data
GSData
1st Latch (Internal)
Previous Grayscale Data
Latest Grayscale Data
GSData
2nd Latch (Internal)
Previous Grayscale Data
Latest Grayscale Data
BC Shift Register
(Internal)
Previous Brightness Data
Latest Brightness Data
BCData
1st Latch (Internal)
Previous Brightness Data
Latest Brightness Data
BCData
2nd Latch (Internal)
Previous Brightness Data (Bit 0-Bit 6)
Latest Brightness Data (Bit 0-Bit 6)
OFF
OUTn
PWM/Brightness Controlled by Previous Data
PWM/Brightness Controlled by Latest Data
ON
SOUT
GS0
4
GS0
3
GS0
2
GS0
1
GS0
0
GS15
15A
BC
7
BC
6
BC
5
BC
4
BC
3
BC
2
BC
1
BC
0
BC GS15
7A 15A
BC
7A
GS15
15A
GS15
14A
GS15
13A
GS15
12A
GS15
11A
When the BLANK input occurs with XLAT.
Figure 27. Auto Refresh Data Function Timing 3
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SBVS101 – DECEMBER 2007
Grayscale (GS) Shift Register and Data Latch
The Grayscale (GS) Shift Register and data latch 1 and 2 are each 256 bits in length, and set the PWM timing
for each constant current driver. See Table 4 for the ON time duty of each GS data bit. Figure 28 shows the shift
register and latch configuration. Refer to Figure 11 for the timing diagram for writing data into the GS shift
register and latch.
The driver on time is controlled by the data in the GS second data latch. GS data can be set into the latch by the
rising edge of XLAT with BCSEL = low after writing data into the GS shift register with SIN and GSCLK with
BCSEL = low. A BCSEL level change occurs during SCLK = low, and after 100 ns from the rising edge of XLAT.
When the device powers up, the data in the GS shift register and latches are not set to any default value.
Therefore, GS data must be written to the GS latch before turning on the constant current output. Also, BLANK
should be at a high level when powering on the device, because the constant current may be turned on as well.
All constant current output is off when BLANK is at a high level.
GS Data for OUT15
GS Data for OUT0
MSB
255
240
239
16
15
LSB
0
GS Data
for Bit 15
of OUT15
GS Data
for Bit 0
of OUT15
GS Data
for Bit 15
of OUT14
GS Data
for Bit 0
of OUT1
GS Data
for Bit 15
of OUT0
GS Data
for Bit 0
of OUT0
¼
¼
¼
SIN with
BCSEL = low
SCLK with
BCSEL = low
Grayscale Shift Register (16 Bits x 16 Channels)
¼
¼
GS Data for OUT14
GS Data for OUT15
MSB
255
GS Data
for Bit 15
of OUT15
¼
240
239
GS Data
for Bit 0
of OUT15
GS Data
for Bit 15
of OUT14
¼
¼ GS Data for OUT1
¼
GS Data for OUT0
LSB
0
16
15
GS Data
for Bit 0
of OUT1
GS Data
for Bit 15
of OUT0
¼
GS Data
for Bit 0
of OUT0
XLAT with
BCSEL = low
Grayscale Data Latch 1 (16 Bits x 16 Channels)
¼
¼
GS Data for OUT14
GS Data for OUT15
MSB
255
GS Data
for Bit 15
of OUT15
¼
240
239
GS Data
for Bit 0
of OUT15
GS Data
for Bit 15
of OUT14
¼
¼ GS Data for OUT1
¼
GS Data for OUT0
16
15
GS Data
for Bit 0
of OUT1
GS Data
for Bit 15
of OUT0
LSB
0
¼
GS Data
for Bit 0
of OUT0
65,536th GSCLK
when Auto Repeat is
enabled or Blank
with BCSEL = low
Grayscale Data Latch 2 (16 Bits x 16 Channels)
256 Bits
To PWM Timing Control Block
Figure 28. Grayscale Shift Register and Data Latch Configuration
24
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SBVS101 – DECEMBER 2007
Brightness Control (BC) Shift Register and Data Latch
The Brightness Control (BC) data shift register and the first latch are each 8 bits long; the second latch is 7 bits
long. The lower 7 bits in the latch are used to adjust the constant current value for all channels of the constant
current driver. The MSB of the first latch is used for the auto repeat mode setting. Table 5 shows the ratio of
setting the current value against the maximum current value for each BC data point. Figure 29 shows the shift
register and latch configuration for BC data. Figure 12 shows the timing for writing data.
The driver constant current value is controlled by the data in the second BC data latch. BC data can be set into
the latch at the rising edge of XLAT with BCSEL = high after writing the data into the BC Shift Register by SIN
and SCLK with BCSEL = high. A BCSEL level change occurs during SCLK = low and after 100 ns from the rising
edge of XLAT. When powered up, the data in the BC Shift Register and latches are not set to any default value.
Therefore, brightness data must be written to the BC latch before turning on the constant current output.
Table 5. BC Data vs Current Ratio
SOUT
BC Data (Dec)
BC Data (Lower 7 Bits; Hex)
Ratio of Setting Current Value Against MAX Value (%)
0
0
0
1
1
0.8
2
2
1.6
2.4
3
3
---
---
---
125
7D
98.4
126
7E
99.2
127
7F
100
MSB
7
6
5
4
3
2
1
LSB
0
Auto-Repeat
1 = Repeat
BC Data
for Bit 6
BC Data
for Bit 5
BC Data
for Bit 4
BC Data
for Bit 3
BC Data
for Bit 2
BC Data
for Bit 1
BC Data
for Bit 0
Brightness/Auto Repeat Control Shift Register (8 Bits)
MSB
7
6
5
4
3
2
1
LSB
0
Auto-Repeat
1 = Repeat
BC Data
for Bit 6
BC Data
for Bit 5
BC Data
for Bit 4
BC Data
for Bit 3
BC Data
for Bit 2
BC Data
for Bit 1
BC Data
for Bit 0
Shift
Data
SIN with
BCSEL = high
Shift
Clock
SCLK with
BCSEL = high
Latch
Signal
XLAT rising edge with
BCSEL = high
Brightness/Auto Repeat Control Data Latch 1 (8 Bits)
MSB
6
5
4
3
2
1
LSB
0
BC Data
for Bit 6
BC Data
for Bit 5
BC Data
for Bit 4
BC Data
for Bit 3
BC Data
for Bit 2
BC Data
for Bit 1
BC Data
for Bit 0
Latch
Signal
65,536th GSCLK when
Auto Repeat is enabled
or BLANK with BCSEL = high
Brightness Control Data Latch 2 (7 Bits)
1 Bit
To PWM Control Block
7 Bits
To Constant Current Driver
Figure 29. Brightness Control Shift Register and Latch Configuration
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SBVS101 – DECEMBER 2007
Status Information Data (SID)
Status information data (SID) are 17-bit, read-only data. Both the LED open detection (LOD) error and the
thermal error flag (TEF) are shifted out onto the SOUT pin with each rising edge of the shift clock, SCLK. The 16
LOD bits for each channel and the TEF bit are written into the 17 most significant bits of the Grayscale Shift
Register at the rising edge of the first SCLK after XLAT goes low. As a result, the previous data in the 17 most
significant bits are lost at the same time. No data are loaded into the other 175 bits. Figure 30 shows the bit
assignments. Figure 13 illustrates the read timing for the status information data.
Status Information Data (SID) Configuration
LOD Data of OUT15 to OUT0
TEF (1 Bit)
MSB
16
15
¼
2
1
OUT15
LOD Data
OUT14
LOD Data
¼
OUT1
LOD Data
OUT0
LOD Data
LSB
0
TEF Data
The 16 LOD bits for each channel and the TEF bit overwrite
the most significant 17 bits of the Grayscale Shift Register at the
rising edge of the first SCLK after XLAT goes low.
¼
GS Data for OUT15
MSB
255
SOUT
254
GS Data for OUT14-OUT1
241
OUT15-Bit15 OUT15-Bit1
(LOD-OUT15) (LOD-OUT14)
¼
240
239
OUT15-Bit1 OUT15-Bit0 OUT14-Bit15
(LOD-OUT1) (LOD-OUT0)
(TEF)
¼
GS Data for OUT0
16
15
OUT1-Bit0
OUT0-Bit15
LSB
0
¼
OUT0-Bit0
SIN
SCLK
(BCSEL = low)
Grayscale Shift Register (16 Bits ´ 16 Channels)
Figure 30. Status Information Data Configuration
The LOD data update at the rising edge of the 33rd GSCLK pulse after BLANK goes low; the LOD data are
retained until the next 33rd GSCLK. LOD data are only checked for outputs that are turned on during the rising
edge of the 33rd GSCLK pulse. A '1' in an LOD bit indicates an open LED or short LED to GND condition for the
corresponding channel. A '0' indicates normal operation. LOD shows a '0' even if the LED is open or shorted to
GND when the grayscale data are less than 1000h (4096d). Therefore, grayscale data must be greater than
1001h (4097d) to correctly receive LOD data.
The TEF bit indicates that the IC temperature is too high. The flag also indicates that the IC has turned off all
drivers to avoid damage by overheating the device. A '1' in the TEF bit means that the IC temperature has
exceeded the detect temperature threshold (T(TEF)) and the driver is turned off. A '0' in the TEF bit indicates
normal operating temperature conditions. The IC automatically turns the drivers back on when the IC
temperature decreases to less than T(TEF) –T(HYS). When the IC powers on, LOD data do not show correct values.
Therefore, LOD data must be read from the 33rd GSCLK pulse input after BLANK goes low. Table 6 shows a
truth table for both LOD and TEF.
Table 6. LOD and TEF Truth Table
CONDITION
26
SID DATA
LED OPEN DETECTION (LODn)
THERMAL ERROR FLAG (TEF)
0
LED is connected (VOUTn > VLOD)
Device temperature is low (temp ≤ T(TEF) –T(HYS))
1
LED is open or shorted to GND (VOUTn ≤ VLOD)
Device temperature is high (temp > T(TEF))
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Noise Reduction
Large surge currents may flow through the IC and the printed circuit board (PCB) on which the device is mounted
if all 16 LED channels turn on simultaneously at the start of each grayscale cycle. These large current surges
could introduce detrimental noise and electromagnetic interference (EMI) into other circuits. The TLC5943 turns
on the LED channels in a series delay to provide a circuit soft-start feature. The output current sinks are grouped
into four groups of four channels each. The first group is OUT0,4,8,12; the second group is OUT1,5,9,13; the
third group is OUT2,6,10,14; and the fourth group is OUT3,7,11,15. Each group is turns on sequentially with a
small delay between groups; see Figure 11. Both turn-on and turn-off are delayed.
Continuous Base LED Open Detection
When the 33rd GSCLK goes high in the first display period after a BLANK falling edge, the LED open detection
(LOD) circuit checks the voltage of each constant current output (OUT0 through OUT15 = OUTn) that is turned
on to detect open LEDs and short LEDs to GND. Then, if the voltage of OUTn is less than the LED open
detection threshold (VLOD = 0.3 VTYP), it sets '1' as the error flag to the LOD error bit that corresponds with the
error channel in the Status Information Data (SID) register. Also, the XERR pin level moves from Hi-Z at the
same time. As a result, GS data should be over 1001h (4097d) to get the LOD result. The OUTn channel that
has the detected LOD error is forced off to avoid an increase in the VCC supply current. OUTn turns on at the first
GSCLK after a BLANK falling edge again. LOD data are kept until the next 33rd rising edge of GSCLK in the first
display period after a BLANK falling edge. LOD is always '0' when grayscale data are less than 1001h (4097d).
XERR is forced to a Hi-Z state while BLANK is high. When powered up, LOD data are not set to any default
value. Therefore, SID data must be used after OUTn turns on with over 1001h GS data. Figure 31 shows the
LED Open Detection timing.
BLANK
1 2 3 4
30 31 32 33 34 35
65,534 65,536
65,533 65,535
1 2 3
30 31 32 33 34 35
GSCLK
1st GSCLK Period
OUTn is turned off by Auto Off
function if LOD error is detected
OFF
OUTn
(Data = FFFFh)
ON
VOUTn
GND
SID Register Value
(Internal)
Old LED open detection data
If no LOD error is detected
If the OUTn voltage (VOUT) is less than VLOD (0.3 V, typ) at the rising edge of the 33rd
GSCLK after the falling edge of BLANK, the LOD sets the SID bit corresponding
to the output channel in which LED is open or shorted to GND equal to ‘1.
New LED open detection data
If no LOD error is detected
'Hi-Z’
XERR
Low
('L')
This LED Open Detection (LOD) data are
kept until the next 33rd rising edge of
GSCLK after BLANK goes low.
Depends on LOD data
Depends on previous
If LOD error is detected
LOD data
Figure 31. LED Open Detection (LOD) Timing
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SBVS101 – DECEMBER 2007
Auto Output Off
If the active OUTn channel is not connected to an LED or if LED is shorted to GND, then VCC consumption
current increases. In order to avoid this event, the device has an auto output off function. This function turns off
channel OUTn with a detected LED opening or LED shorting to GND at the 33rd GSCLK after BLANK goes low
automatically. VCC current can be saved by this function. OUTn is controlled normally again after BLANK goes
low. Figure 32 illustrates the auto output off function.
VCC
Dissipation
Current
BLANK
1 2 3 4
30 31 32 33 34 35
65,534 65,536
65,533 65,535
1 2 3
30 31 32 33 34 35
GSCLK
If LOD error is detected
OFF
Voltage of
OUTn
ON
VOUTn
If no LOD error is detected
GND
SID Register Value
(Internal)
ON Signal of OUTn
(Internal)
(GS data = FFFFh)
Old LED open detection data
'ON'
New LED open detection data
Remain 'On' (if no
LOD error detected)
'OFF'
'ON'
Remain 'On'
(if no LOD error detected)
'OFF'
Turn 'Off' (OUTn is turned off
by Auto Off function if LOD error
is detected)
Turn 'Off' (OUTn is turned off
by Auto Off function if LOD error
is detected)
Figure 32. Auto Output Off Function
28
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SBVS101 – DECEMBER 2007
Thermal Shutdown and Thermal Error Flag
The Thermal Shutdown (TSD) function turns off all of the constant current outputs on the IC immediately when
the junction temperature (TJ) exceeds the threshold (T(TEF) = +162°C, typ) and sets the thermal error flag (TEF)
to '1'. The XERR pin goes low at the same time. The XERR pin level and the TEF level are kept until the first
SCLK falling edge after an XLAT falling edge of grayscale data. Then if TJ is still greater than T(TEF), TEF
continues at '1' while XERR remains low. If TJ becomes less than T(TEF) –T(HYS), TEF is set to '0' and XERR
becomes Hi-Z. XERR is not forced to a Hi-Z state while BLANK is high. Therefore, the error type TEF or LOD
can be distinguished from the BLANK signal control. OUTn is turned on at the first GSCLK after the BLANK
falling edge if TJ becomes less than T(TEF) – T(HYS) at the BLANK rising edge.
When the IC powers on, TEF may be set and all output is forced off. Therefore, an XLAT pulse and a BLANK
rising edge should be input once to turn on the output. Figure 33 illustrates the TEF/TSD/XERR timing sequence.
BLANK
XLAT
SCLK
65,534 65,536
65,533 65,535
1 2 3 4
1 2 3
GSCLK
IC Junction
Temperature (TJ)
TJ < T(TEF)
TJ ³ T(TEF)
TJ < T(TEF) - T(HYS)
TJ ³ T(TEF)
'1'
TEF
(Internal)
'0'
'0'
'Hi-Z’
Low
('L')
XERR
OFF
OUTn
OFF
ON
Figure 33. TEF/TSD/XERR timing
POWER DISSIPATION CALCULATION
The device power dissipation must be below the power dissipation rate of the device package (illustrated in
Figure 15) to ensure correct operation. Equation 4 calculates the power dissipation of the device:
PD = (VCC ´ ICC) + VOUT ´ IMAX ´ N ´
BCn
´ dPWM
127d
(4)
Where:
•
•
•
•
•
•
•
VCC = device supply voltage
ICC = device supply current
VOUT = OUTn voltage when driving LED current
IMAX = LED current adjusted by R(IREF) resistor
BCn = maximum BC value for OUTn
N = number of OUTn driving LED at the same time
dPWM = duty ratio defined by BLANK pin or GS PWM value
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PACKAGE OPTION ADDENDUM
www.ti.com
19-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLC5943PWP
ACTIVE
HTSSOP
PWP
28
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TLC5943
Samples
TLC5943PWPR
ACTIVE
HTSSOP
PWP
28
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TLC5943
Samples
TLC5943RHBR
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TLC
5943
Samples
TLC5943RHBT
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TLC
5943
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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