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TLC5955
SBVS237 – MARCH 2014
TLC5955 48-Channel, 16-Bit, PWM LED Driver with DC, BC, LED Open-Short Detection,
and Internal Current Setting
1 Features
3 Description
•
•
The TLC5955 is a 48-channel, constant-current sink
driver. Each channel has an individually-adjustable,
pulse width modulation (PWM), grayscale (GS)
brightness control with 65,536 steps and 128 steps of
constant-current dot correction (DC). DC adjusts
brightness deviation between channels. All channels
have a 128-step global brightness control (BC). BC
adjusts brightness deviation between the R, G, B
color group. The eight-step maximum current control
(MC) selects the maximum output current range for
all channels of each color group. GS, DC, BC, and
MC data are accessible with a serial interface port.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
48 Constant-Current Sink Output Channels
Sink Current Capability with Maximum MC, DC,
and BC Data:
– 23.9 mA (VCC ≤ 3.6 V, MC = 5)
– 31.9 mA (VCC > 3.6 V, MC = 7)
Grayscale (GS) Control:
– 16-Bit (65,536 Steps) with Enhanced Spectrum
or Conventional PWM
Maximum Current (MC) Control:
– 3 Bits (8 Steps) with a 3-mA to 30-mA Range
– 3 MC Sets for Each Color Group
Dot Correction (DC) Control:
– 7 Bits (128 Steps) with a 26.2% to 100%
Range
Global Brightness Control (BC):
– 7 Bits (128 Steps) with a 10% to 100% Range
– 3 BC Sets for Each Color Group
LED Power-Supply Voltage: Up to 10 V
VCC: 3.0 V to 5.5 V
Constant-Current Accuracy:
– Channel-to-Channel: ±2% (typ), ±5% (max)
– Device-to-Device: ±2% (typ), ±4% (max)
Data Transfer Rate: 25 MHz
Grayscale Control Clock: 33 MHz
Auto Display Repeat
Display Timing Reset
Auto Data Refresh (GS and DC Only)
LED Open Detection (LOD)
LED Short Detection (LSD)
UVLO Sets Default Data
Delay Switching to Prevent Inrush Current
Operating Temperature: –40°C to +85°C
2 Applications
•
•
•
The TLC5955 has two error flags: LED open
detection (LOD) and LED short detection (LSD). The
error detection results can be read with a serial
interface port.
Device Information
ORDER NUMBER
PACKAGE
BODY SIZE
TLC5955DCA
HTSSOP (56)
14,0 mm × 6,1 mm
TLC5955RTQ
QFN (56)
8,0 mm × 8,0 mm
Application Circuit
VLED
+
GND
Input Serial Data
x48
OUTR0
Shift Clock
SCLK
Data Latch
LAT
GS Clock
OUTB15
SIN
Output Serial Data
SOUT
VCC
TLC5955
VCC
GSCLK
GND
GND
GND
LED Video Displays
Variable Message Signs (VMS)
Illumination
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLC5955
SBVS237 – MARCH 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Terminal Configurations and Functions..............
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
8.1
8.2
8.3
8.4
1
1
1
2
3
6
9
15
16
17
28
Applications and Implementation ...................... 38
9.1 Application Information............................................ 38
9.2 Typical Application .................................................. 38
Absolute Maximum Ratings ..................................... 6
Handling Ratings....................................................... 6
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 7
Electrical Characteristics........................................... 8
Switching Characteristics .......................................... 9
Typical Characteristics ............................................ 10
10 Power Supply Recommendations ..................... 41
11 Layout................................................................... 41
11.1 Layout Guidelines ................................................. 41
11.2 Layout Example .................................................... 42
12 Device and Documentation Support ................. 43
12.1
12.2
12.3
12.4
12.5
Parameter Measurement Information ................ 12
7.1 Terminal-Equivalent Input and Output Schematic
Diagrams.................................................................. 12
7.2 Test Circuits ............................................................ 12
7.3 Timing Diagrams ..................................................... 13
8
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Device Support......................................................
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
43
43
43
43
43
13 Mechanical, Packaging, and Orderable
Information ........................................................... 43
Detailed Description ............................................ 15
4 Revision History
2
DATE
REVISION
NOTES
March 2014
*
Initial release.
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SBVS237 – MARCH 2014
5 Terminal Configurations and Functions
DCA Package
HTSSOP-56
(Top View)
SIN
1
56
GND
SCLK
2
55
GSCLK
LAT
3
54
VCC
OUTB4
4
53
OUTB8
OUTR4
5
52
OUTR8
OUTG4
6
51
OUTG8
OUTB0
7
50
OUTB12
OUTR0
8
49
OUTR12
OUTG0
9
48
OUTG12
OUTB5
10
47
OUTB9
OUTR5
11
46
OUTR9
OUTG5
12
45
OUTG9
OUTB1
13
44
OUTB13
OUTR1
14
43
OUTR13
OUTG1
15
42
OUTG13
OUTB2
16
41
OUTB14
OUTR2
17
40
OUTR14
OUTG2
18
39
OUTG14
OUTB6
19
38
OUTB10
OUTR6
20
37
OUTR10
OUTG6
21
36
OUTG10
OUTB3
22
35
OUTB15
OUTR3
23
34
OUTR15
OUTG3
24
33
OUTG15
OUTB7
25
32
OUTB11
OUTR7
26
31
OUTR11
OUTG7
27
30
OUTG11
SOUT
28
29
GND
Thermal Pad
(Solder Side)
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4
OUTG6
OUTR6
OUTB6
OUTG2
OUTR2
OUTB2
OUTG1
OUTR1
OUTB1
OUTG5
OUTR5
OUTB5
OUTG0
OUTR0
56
55
54
53
52
51
50
49
48
47
46
45
44
43
RTQ Package
QFN-56
(Top View)
OUTB3
1
42
OUTB0
OUTR3
2
41
OUTG4
OUTG3
3
40
OUTR4
OUTB7
4
39
OUTB4
OUTR7
5
38
LAT
OUTG7
6
37
SCLK
SOUT
7
36
SIN
GND
8
35
GND
OUTG11
9
34
GSCLK
OUTR11
10
33
VCC
OUTB11
11
32
OUTB8
OUTG15
12
31
OUTR8
OUTR15
13
30
OUTG8
OUTB15
14
29
OUTB12
17
18
19
20
21
22
23
24
25
26
27
OUTR10
OUTB10
OUTG14
OUTR14
OUTB14
OUTG13
OUTR13
OUTB13
OUTG9
OUTR9
OUTB9
OUTG12
OUTR12
16
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28
15
OUTG10
Thermal Pad
(Solder Side)
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SBVS237 – MARCH 2014
Terminal Functions
TERMINAL
NAME
GND
GSCLK
DCA NUMBER
RTQ NUMBER
I/O
29, 56
8, 35
—
55
34
DESCRIPTION
Power ground
I
Reference clock for the grayscale (GS) pulse width modulation (PWM) control for all outputs.
Each GSCLK rising edge increments the grayscale counter for PWM control. When the LAT
signal is input for a GS data write with the timing reset mode enabled, all constant-current
outputs (OUTX0-OUTX15, where X = R, G, or B) are forced off, the grayscale counter is
reset to 0, and the grayscale PWM timing controller is initialized.
3
38
I
The LAT rising edge either latches the data from the common shift register into the GS data
latch when the MSB of the common shift register is 0 or latches the data into the control
data latch when the MSB of the common shift register is 1. When the display timing reset bit
(TMGRST) in the control data latch is 1, the grayscale counter initialized at the LAT signal is
input for a grayscale data write. Dot correction (DC) data in the control data latch are copied
to DC data latch at the same time.
OUTB0 to
OUTB15
4, 7, 10, 13, 16, 19,
22, 25, 32, 35, 38,
41, 44, 47, 50, 53
1, 4, 11, 14, 17, 20,
23, 26, 29, 32, 39,
42, 45, 48, 51, 54
O
Constant-current outputs for the blue color group.
Multiple outputs can be configured in parallel to increase the constant-current capability.
Different voltages can be applied to each output.
OUTG0 to
OUTG15
6, 9, 12, 15, 18, 21,
24, 27, 30, 33, 36,
39, 42, 45, 48, 51
3, 6, 9, 12, 15, 18,
21, 24, 27, 30, 41,
44, 47, 50, 53, 56
O
Constant-current outputs for the green color group.
Multiple outputs can be configured in parallel to increase the constant-current capability.
Different voltages can be applied to each output.
OUTR0 to
OUTR15
5, 8, 11, 14, 17, 20,
23, 26, 31, 34, 37,
40, 43, 46, 49, 52
2, 5, 10, 13, 16, 19,
22, 25, 28, 31, 40,
43, 46, 49, 52, 55
O
Constant-current outputs for the red color group.
Multiple outputs can be configured in parallel to increase the constant-current capability.
Different voltages can be applied to each output.
SCLK
2
37
I
Serial data shift clock.
Data present on SIN are shifted to the LSB of the common shift register with the SCLK
rising edge. Data in the shift register are shifted toward the MSB at each SCLK rising edge.
The MSB data of the common shift register appears on SOUT.
SIN
1
36
I
Serial data input for the 769-bit common shift register.
LAT
SOUT
28
7
O
This bit is the serial data output of the 769-bit common shift register.
LED open detection (LOD) and LED short detection (LSD) can be read out with SOUT in the
form of status information data (SID) after the LAT falling edge is input for a GS data write.
SOUT is connected to the MSB of the 769-bit common shift register. Data are clocked out at
the SCLK rising edge.
VCC
54
33
—
Power-supply voltage
—
The thermal pad is not connected to GND internally.
The thermal pad must be connected to GND via the PCB.
Thermal pad
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6 Specifications
6.1 Absolute Maximum Ratings (1)
Over operating free-air temperature range, unless otherwise noted.
VCC
VIN
Input range
Voltage (2)
VOUT
Output range
TJ (max)
(1)
(2)
MIN
MAX
UNIT
–0.3
+6.0
V
SIN, SCLK, LAT, GSCLK
–0.3
VCC + 0.3
V
SOUT
–0.3
VCC + 0.3
V
OUTR0 to OUTR15, OUTG0 to
OUTG15, OUTB0 to OUTB15
–0.3
+11
V
+150
°C
Supply
Maximum operating junction temperature
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
All voltages are with respect to device ground terminal.
6.2 Handling Ratings
TSTG
VESD (1)
(1)
(2)
(3)
6
Storage temperature range
Human body model (HBM) ESD stress voltage (2)
Charged device model (CDM) ESD stress voltage
(3)
MIN
MAX
UNIT
–55
+150
°C
4000
V
2000
V
Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in
to the device.
Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 4000-V HBM allows
safe manufacturing with a standard ESD control process.
Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 2000-V CDM allows safe
manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
DC CHARACTERISTICS
VCC
Supply voltage
VO
Voltage applied to output
OUTX0 to OUTX15 (1)
3.0
VIH
High-level input voltage
SIN, SCLK, LAT, GSCLK
VIL
Low-level input voltage
SIN, SCLK, LAT, GSCLK
IOH
High-level output current
SOUT
IOL
Low-level output current
SOUT
OUTX0 to OUTX15
5.5
V
10
V
0.7 × VCC
VCC
V
GND
0.3 × VCC
(1)
, 3 V ≤ VCC ≤ 3.6 V
V
–2
mA
2
mA
23.9
mA
31.9
mA
IOLC
Constant output sink current
TA
Operating free-air temperature
range
–40
+85
°C
TJ
Operating junction temperature
range
–40
+125
°C
OUTX0 to OUTX15 (1), 3.6 V < VCC ≤ 5.5 V
AC CHARACTERISTICS
fCLK (SCLK)
Data shift clock frequency
SCLK
25
MHz
fCLK (GSCLK)
Grayscale control clock frequency
GSCLK
33
MHz
tWH0
SCLK
10
ns
tWL0
SCLK
10
ns
tWH1
GSCLK
10
ns
tWL1
Pulse duration
GSCLK
10
ns
tWH2
LAT
30
ns
tSU0
SIN to SCLK↑
5
ns
tSU1
LAT↓ to SCLK↑ (auto data refresh is
disabled (2))
30
ns
LAT↑ for GS data written to GSCLK↑ when
display time reset mode is disabled
50
ns
LAT↑ for GS data written to GSCLK↑ when
display time reset mode is enabled
70
ns
SCLK↑ to SIN
2
ns
SCLK↑ to LAT↑
5
ns
Setup time
tSU2
tSU3
tH0
Hold time
tH1
(1)
(2)
X = R, G, or B.
When auto data refresh is enabled, the first SCLK rising edge after the LAT signal input must be input after the first GSCLK is input.
6.4 Thermal Information
THERMAL METRIC (1)
DCA (HTSSOP)
RTQ (QFN)
56 TERMINALS
56 TERMINALS
θJA
Junction-to-ambient thermal resistance
32.2
27.9
θJCtop
Junction-to-case (top) thermal resistance
16.8
14.9
θJB
Junction-to-board thermal resistance
16.1
6.5
ψJT
Junction-to-top characterization parameter
0.8
0.3
ψJB
Junction-to-board characterization parameter
16.0
6.4
θJCbot
Junction-to-case (bottom) thermal resistance
0.9
2.0
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
At TA = –40°C to +85°C and VCC = 3 V to 5.5 V, unless otherwise noted. Typical values at TA = +25°C and VCC = 3.3 V.
PARAMETER
CONDITION
VOH
High-level output voltage
(SOUT)
IOH = –2 mA
VOL
Low-level output voltage
(SOUT)
IOL = 2 mA
IIN
Input current
(SIN, SCLK, LAT, GSCLK)
VIN = VCC or GND
MIN
TYP
VCC – 0.4
–1
MAX
UNIT
VCC
V
0.4
V
1
μA
ICC0
SIN, SCLK, and LAT = GND, all OUTXn = off,
GSCLK = GND, GSXn = 0000h, DCXn and BCX = 7Fh,
VOUTXn = 0.8 V, MCX = 0 (3.2-mA target) (1) (2)
15
20
mA
ICC1
SIN, SCLK, and LAT = GND, all OUTXn = off,
GSCLK = GND, GSXn = 0000h, DCXn and BCX = 7Fh,
VOUTXn = 0.8 V, MCX = 4 (19.1-mA target)
16
22
mA
ICC2
SIN, SCLK, and LAT = GND, auto display repeat
enabled, GSCLK = 33 MHz, GSXn = FFFFh, DCXn and
BCX = 7Fh, VOUTXn = 0.8 V, MCX = 4 (19.1-mA target)
18
26
mA
ICC3
VCC = 5.0 V, SIN, SCLK, and LAT = GND, auto display
repeat enabled, GSCLK = 33 MHz, GSXn = FFFFh,
DCXn and BCX = 7Fh, VOUTXn = 0.8 V, MCX = 7
(31.9-mA target)
20
29
mA
Supply current (VCC)
IOLC0
Constant output sink current
(OUTX0 to OUTX15)
IOLC1
IOLKG0
17.4
19.1
20.8
mA
VCC = 5.0 V, all OUTXn = on, DCXn and BCX = 7Fh,
VOUTXn = VOUTfix = 0.8 V, MCX = 7
29.1
31.9
34.7
mA
0.1
μA
TJ = +25°C
All OUTn = off,
VOUTXn = VOUTfix = 10 V,
MCX = 7
Output leakage current
(OUTX0 to OUTX15)
IOLKG1
All OUTXn = on, DCXn and BCX = 7Fh,
VOUTXn = VOUTfix = 0.8 V, MCX = 4
IOLKG2
0.2
μA
0.3
0.8
μA
TJ = +85°C
TJ = +125°C
ΔIOLC0
Constant-current error
(channel-to-channel, OUTX0 to
OUTX15) (3)
All OUTXn = on, DCXn and BCX = 7Fh,
VOUTXn = VOUTfix = 0.8 V, MCX = 4
±2%
±5%
ΔIOLC1
Constant-current error
(device-to-device, OUTX0 to
OUTX15) (4)
All OUTXn = on, DCXn and BCX = 7Fh,
VOUTXn = VOUTfix = 0.8 V, MCX = 4
±2%
±4%
ΔIOLC2
Line regulation
(OUTx0 to OUTx15) (5)
VCC = 3.0 V to 5.5 V, all OUTXn = on,
DCXn and BCX = 7Fh, VOUTXn = VOUTfix = 0.8 V,
MCX = 4
±0.1
±1
(1)
(2)
(3)
%/V
X = R, G, or B. For example, MCX = MCR, MCG, and MCG.
n = 0 to 15.
The deviation of each output from the OUTX0 to OUTX15 constant-current average of the same color group. Deviation is calculated by
the formula:
IOLCXn
D (%) =
-1
(IOLCX0 + IOLCX1 + ... + IOLCX14 + IOLCX15)
´ 100
16
(4)
where X = R, G, or B; n = 0 to 15.
Deviation of the OUTX0 to OUTX15 constant-current average from the ideal constant-current value.
Deviation is calculated by the formula:
(IOLCX0 + IOLCX1 + ... IOLCX14 + IOLCX15)
D (%) =
16
- (Ideal Output Current)
´ 100
Ideal Output Current
(5)
where X = R, G, or B; n = 0 to 15.
Ideal current is the target current when MC is 4.
Line regulation is calculated by the formula:
D (%/V) =
(IOLCXn at VCC = 5.5 V) - (IOLCXn at VCC = 3.0 V)
(IOLCXn at VCC = 3.0 V)
´
100
5.5 V - 3.0 V
where X = R, G, or B; n = 0 to 15.
8
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Electrical Characteristics (continued)
At TA = –40°C to +85°C and VCC = 3 V to 5.5 V, unless otherwise noted. Typical values at TA = +25°C and VCC = 3.3 V.
PARAMETER
CONDITION
MIN
ΔIOLC3
Load regulation
(OUTx0 to OUTx15) (6)
All OUTXn = on, DCXn and BCX = 7Fh,
VOUTXn = 0.8 V to 3.0 V, VOUTfix = 0.8 V, MCX = 4
VLOD
LED open-detection threshold
All OUTXn = on
VLSD0
VLSD1
(6)
LED short-detection threshold
TYP
MAX
UNIT
±0.1
±1
%/V
0.25
0.30
0.35
V
All OUTXn = on, LSDVLT = 0
0.65 × VCC
0.70 × VCC
0.75 × VCC
V
All OUTXn = on, LSDVLT = 1
0.85 × VCC
0.90 × VCC
0.95 × VCC
V
Load regulation is calculated by the equation:
D (%/V) =
(IOLCXn at VOUTXn = 3 V) - (IOLCXn at VOUTXn = 0.8 V)
IOLCXn at VOUTXn = 0.8 V
´
100
3 V - 0.8 V
where X = R, G, or B; n = 0 to 15.
6.6 Switching Characteristics
At TA = –40°C to +85°C, VCC = 3 V to 5.5 V, CL = 15 pF, RL = 120 Ω, MCX = 7, and VLED = 4.5 V, unless otherwise noted.
Typical values at TA = +25°C and VCC = 3.3 V.
PARAMETER
tR0
Rise time
tR1
tF0
Fall time
tF1
tD0
TEST CONDITIONS
MIN
SOUT
OUTXn, VCC = 3.6 V, DCXn, and BCX = 7Fh, TA = +25°C (1)
TYP
MAX
3
5
30
SOUT
3
OUTXn, VCC = 3.6 V, DCXn, and BCX = 7Fh, TA = +25°C
40
SCLK↑ to SOUT↑↓
20
UNIT
ns
ns
5
ns
ns
30
ns
tD1
GSCLK↑ to OUTX4 and
OUTX11 on or off
40
ns
tD2
GSCLK↑ to OUTX0 and
OUTX15 on or off
43
ns
tD3
GSCLK↑ to OUTX5 and
OUTX10 on or off
46
ns
GSCLK↑ to OUTX1 and
OUTX14 on or off
49
ns
GSCLK↑ to OUTX2 and
OUTX13 on or off
52
ns
tD6
GSCLK↑ to OUTX6 and
OUTX9 on or off
55
ns
tD7
GSCLK↑ to OUTX3 and
OUTX12 on or off
58
ns
tD8
GSCLK↑ to OUTX7 and
OUTX8 on or off
61
ns
tD4
Propagation delay
tD5
tON_ERR
(1)
(2)
Output on-time error (2)
VCC = 3.6 V, GSCLK = 33 MHz, DCXn
and BCX = 7Fh, TA = +25°C
tOUTON – tGSCLK, VCC = 3.6 V to 5.5 V, GSXn = 0001h,
GSCLK = 33 MHz, DCXn and BCX = 7Fh
–20
20
ns
X = R, G, or B; n = 0 to 15.
Output on-time error (tON_ERR) is calculated by the formula: tON_ERR = tOUT_ON – tGSCLK. tOUTON is the actual on-time of the constantcurrent driver. tGSCLK is the GSCLK period.
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6.7 Typical Characteristics
At TA = +25°C and VCC = 5.0 V, unless otherwise noted.
40
30
25
20
DC = 0h
DC = 10h
DC = 20h
DC = 30h
DC = 40h
DC = 50h
DC = 60h
DC = 70h
DC = 7Fh
35
Output Current (mA)
35
Output Current (mA)
40
MC = 0
MC = 1
MC = 2
MC = 3
MC = 4
MC = 5
MC = 6
MC = 7
15
10
5
30
25
20
15
10
5
0
0
0
0.5
1
1.5
2
2.5
3
Output Voltage (V)
0
BCX = DCXn = 7Fh
2
2.5
35
25
20
34
Output Current (mA)
30
15
10
33
32
31
TTA=±40C
A = ±40C
30
5
C
TTA=25°
A = 25C
C
TTA=85°
A = 85C
29
0
0
0.5
1
1.5
2
2.5
0
3
Output Voltage (V)
0.6
0.8
1
Output Voltage (V)
C004
Figure 4. Output Current vs Output Voltage (Temperature
Changing)
5
4
4
Constant-Current Error (%)
5
3
2
1
0
±1
±2
±3
±4
10
15
20
Output Current (mA)
25
30
3
2
1
0
±1
±2
±3
±4
Max
Min
±5
BCX = DCXn = 7Fh
0.4
BCX = DCXn = 7Fh
Figure 3. Output Current vs Output Voltage
(BCX Changing)
5
0.2
C003
BCX = DCXn = 7Fh
0
3
C002
Figure 2. Output Current vs Output Voltage
(DCXn Changing)
BC = 0h
BC = 10h
BC = 20h
BC = 30h
BC = 40h
BC = 50h
BC = 60h
BC = 70h
BC = 7Fh
35
Output Current (mA)
1.5
BCX = DCXn = 7Fh
40
Constant-Current Error (%)
1
Output Voltage (V)
Figure 1. Output Current vs Output Voltage
(MCX Changing)
Max
Min
±5
35
±40
±20
VOUTXn = 0.8 V
0
20
40
60
Ambient Temperature (C)
C005
MCX = 4
Figure 5. Constant-Current Error vs Output Current
(Channel-to-Channel in Each Color Group)
10
0.5
C001
BCX = DCXn = 7Fh
80
100
C006
VOUTXn = 0.8 V
Figure 6. Constant-Current Error vs Ambient Temperature
(Channel-to-Channel in Each Color Group)
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Typical Characteristics (continued)
At TA = +25°C and VCC = 5.0 V, unless otherwise noted.
35
25
20
15
10
5
25
20
15
10
5
0
0
0
16
32
48
64
80
96
112
128
DC Data (Decimal)
BCX = 7Fh
0
VOUTXn = 0.8 V
30
30
Supply Current (mA)
35
25
20
15
10
5
15
20
25
30
Output Current (mA)
BCX = DCXn = 7Fh
GSCLK = 33 MHz
SIN = 12.5 MHz
VOUT = 0.8 V
80
96
112
128
C008
VOUTXn = 0.8 V
25
20
15
10
5
VCC = 3.3 V
VCC = 5 V
0
64
Figure 8. Global Brightness Control (BC) Linearity
35
10
48
DCXn = 7Fh
40
5
32
BC Data (Decimal)
40
0
16
C007
Figure 7. Dot Correction (DC) Linearity
Supply Current (mA)
MCX = 0
MCX = 1
MCX = 2
MCX = 3
MCX = 4
MCX = 5
MCX = 6
MCX = 7
30
Output Current (mA)
30
Output Current (mA)
35
MCX = 0
MCX = 1
MCX = 2
MCX = 3
MCX = 4
MCX = 5
MCX = 6
MCX = 7
VCC = 3.3 V
VCC = 5 V
0
35
±40
0
±20
SCLK = 25 MHz
GSXn = FFFFh
20
40
60
80
Ambient Temperature (C)
C009
MCX = 4
SCLK = 25 MHz
GSXn = FFFFh
Figure 9. Supply Current vs Output Current
BCX = DCXn = 7Fh
GSCLK = 33 MHz
100
C010
SIN = 12.5 MHz
VOUT = 0.8 V
Figure 10. Supply Current vs Ambient Temperature
Ch1: GSCLK (5 V/div)
Ch2: OUTR4 (2 V/div)
Ch3: OUTGO (2 V/div)
Ch4: OUTB5 (2 V/div)
Time (20 ns/div)
MCX = 7
VLED = 4.5 V
BCX = DCXn = 7Fh
RL = 120 Ω
GSCLK = 33 MHz
GSXn = 0001h
Figure 11. Constant-Current Output Voltage Waveform
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7 Parameter Measurement Information
7.1 Terminal-Equivalent Input and Output Schematic Diagrams
VCC
VCC
INPUT
SOUT
GND
GND
Figure 12. SIN, SCLK, LAT, GSCLK
Figure 13. SOUT
OUTXn
(1)
GND
(1) X = R, G, or B; n = 0 to 15.
Figure 14. OUTX0 Through OUTX15
7.2 Test Circuits
RL
VCC
VCC
OUTXn
VCC
(1)
VLED
(2)
CL
GND
SOUT
VCC
GND
CL
(1)
(1) X = R, G, or B; n = 0 to 15.
(1) CL includes measurement probe and jig capacitance.
(2) CL includes measurement probe and jig capacitance.
Figure 16. Rise Time and Fall Time Test Circuit
for SOUT
Figure 15. Rise Time and Fall Time Test Circuit
for OUTXn
VCC
OUTR0
¼
VCC
OUTXn
(1)
¼
GND
OUTB15
VOUTfix
VOUTXn(1)
(1) X = R, G, or B; n = 0 to 15.
Figure 17. Constant-Current Test Circuit for OUTXn
12
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7.3 Timing Diagrams
tWH0, tWL0, tWH1, tWL1, tWH2:
VCC
Input
(1)
50%
GND
tWH
tWL
tSU0, tSU1, tSU2, tSU3, tH0, tH1:
VCC
Clock Input
(1)
50%
GND
tSU
tH
VCC
Data and Control Input
(1)
50%
GND
(1)
Input pulse rise and fall time is 1 ns to 3 ns.
Figure 18. Input Timing
tR0, tR1, tF0, tF1, tD0, tD1, tD2, tD3, tD4, tD5, tD6, tD7, tD8:
VCC
Input
(1)
50%
GND
tD
VOH or VOUTXnH
90%
Output
(2)
50%
10%
(2)
VOL or VOUTXnL
tR or tF
(1)
Input pulse rise and fall time is 1 ns to 3 ns.
(2)
X = R, G, or B; n = 0 to 15.
Figure 19. Output Timing
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Timing Diagrams (continued)
GS Data Write
SIN
R0
0A
Low
B15
15B
B15
14B
GS Data Write
B15
13B
R0
3B
B15
12B
R0
2B
R0
0B
R0
1B
tH0
tSU0
Low
tH1
tWH0
B15
15C
B15
14C
B15
13C
B15
12C
B15
11C
B15
10C
tSU1
SCLK
1
2
4
3
5
766
767
769
768
1
tWL0
2
4
3
5
tWH1
tGSCLK
7
6
GSCLK
65534
65536
65538
65537
65535
1
3
2
4
tWH2
5
6
tWL1
LAT
tSU2, tSU3
Grayscale Data
In GS Data Latch
(Internal)
New Data
Old Data
tD0
SOUT
Low
LOD
B15
LOD
G15
LOD
R15
LOD
B14
R0
3A
R0
2A
R0
1A
R0
0A
Low
LOD
B15
LOD
R15
LOD
G15
LOD
B14
LOD
G14
LOD
R14
LOD
B13
tR0, tF0
Display Timing Reset Enabled, Auto Display Repeat Disabled, All GS Data Are FFFFh
OUTR4, OUTR11,
OUTG4, OUTG11,
OUTB4, OUTB11
Off
OUTR0, OUTR15,
OUTG0, OUTG15,
OUTB0, OUTB15
Off
OUTR5, OUTR10,
OUTG5, OUTG10,
OUTB5, OUTB10
Off
OUTR1, OUTR14,
OUTG1, OUTG14,
OUTB1, OUTB14
Off
OUTR2, OUTR13,
OUTG2, OUTG13,
OUTB2, OUTB13
Off
OUTR6, OUTR9,
OUTG6, OUTG9,
OUTB6, OUTB9
Off
OUTR3, OUTR12,
OUTG3, OUTG12,
OUTB3, OUTB12
Off
OUTR7, OUTR8,
OUTG7, OUTG8,
OUTB7, OUTB8
Off
On
(VOUTXnH)
tF1
tR1
(VOUTXnL)
tD1
On
tD2
On
tD3
On
tD4
On
tD5
On
tD6
On
tD7
On
tD8
Figure 20. Data Input, Output, and Constant Output Timing
14
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8 Detailed Description
8.1 Overview
The TLC5955 is 48-channel, 30-mA, constant-current LED driver that can control LED on-time with pulse width
modulation (PWM) in 65,536 steps for grayscale (GS) control. A maximum of 281 trillion colors can be generated
with red, green, and blue LEDs connected to the constant-current outputs.
The device has a 128-step, 7-bit, output current control function called dot correction (DC) that can control each
constant-current output. Inherently, LED lamps have different intensities resulting from manufacturing differences.
The DC function can reduce the inherent differences in intensity and improve LED lamp brightness uniformity.
The device also has a 128-step, 7-bit, output current control function called global brightness control (BC) that
can control each color group output. The BC function can adjust the red, green, and blue LED intensity for true
white with constant-current control. The device contributes higher image quality to LED displays with fine white
balance tuning by using these GS, DC, and BC functions.
The display controller can locate LED lamp failures via the device because the controller can detect LED lamp
failures with the LED open detection (LOD) and LED short detection (LSD) functions and the reliability of the
display can be improved by the LOD, LSD function.
The device maximum constant-current output value can be set by internal register data instead of the general
method of using an external resistor setting. Thus, any failure modes that occur from the external resistor can be
eliminated and one resistor can be eliminated.
The device constant-current output can drive approximately 19 mA at a 0.25-V output voltage and a +25°C
ambient temperature. This voltage is called knee voltage. This 0.25-V, low-knee voltage can contribute to the
design of a lower-power display system. The total number of LED drivers on one LED display panel can be
reduced because 48 LED lamps can be driven by one LED driver. Therefore, designing fine-pitch LED displays is
simplified.
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8.2 Functional Block Diagram
LSB
lodisdlat
VCC
MSB
96-Bit LOD, LSD Data Latch
0
95
96
LSB
MSB
SIN
769-Bit Common Shift Register
0
SCLK
SOUT
Bit 768
768
latgs
768
LSB
MSB
768-Bit Grayscale (GS) Data Latch
0
767
379
371
LSB
MSB
371-Bit Control Data Latch
(DC, MC, BC, FC)
LAT
0
LSB
UVLO
8-Bit Write
Command
Decoder
370
336
lat2nd
GSCLK
16-Bit GS
Counter
0
35
MC, BC, FC Bits
335
1
3
48-Channel,
16-Bit ES, Conventional PWM Timing
336
48
8-Set, 6-Channel Grouped
Switching Delay
30
48
Reference
Current Control
with 3-Bit MC and
7-Bit BC for Each
Color
48-Channel Constant Sink Current Driver
with 7-Bit DC
1
LED Open Detection (LOD)
LED Short Detection (LSD)
GND
OUTR0
16
768
MSB
336-Bit DC Data Latch
lodisdlat
latgs
8
OUTG0
OUTB0
96
OUTR15 OUTG15 OUTB15
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8.3 Feature Description
8.3.1 Output Current Calculation
The output current value controlled by MC, DC, and BC can be calculated by Equation 1.
IOUTn (mA) = IOLCMax (mA) ´ 0.262 + 0.738 ´
DCXn
BCX
´ 0.10 + 0.90 ´
127
127
where:
•
•
•
•
•
IOLCMax = the maximum constant-current value for all OUTXn for each color group programmed by MC data,
DCXn = the dot correction value for each channel (0h to 7Fh),
BCX = the global brightness control value (0h to 7Fh),
X = R, G, or B for the red, green, or blue color group, and
n = 0 to 15.
(1)
Each output sinks the IOLCMax current when they turn on and the dot correction (DC) data and the global
brightness control (BC) data are set to the maximum value of 7Fh (127d). Each output sink current can be
reduced by lowering the DC and BC values.
When IOUT is set lower than 1 mA by both MC and BC or BC only, the output may be unstable. Output currents
lower than 1 mA can be achieved by setting IOUT to 1 mA with MC and BC or BC only and then using DC to
lower the output current.
8.3.2 Register and Data Latch Configuration
The TLC5955 has one common shift register and three data latches: the grayscale (GS) data latch, the control
data latch, and the dot correction (DC) data latch. The common shift register is 769 bits long, the GS data latch is
768 bits long, the control data latch is 371 bits long, and the DC data latch is 336 bits long.
If the common shift register MSB is 0, the least significant 768 bits from the common shift register are latched
into the GS data latch. If the MSB is 1, and bits 767 to 760 are 96h (10010110b), the data are latched into the
control data latch. Refer to Figure 21 for the common shift register, GS data latch, control data latch, and DC
data latch configurations.
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Feature Description (continued)
Common Shift Register (769 Bits)
LSB
MSB
SOUT
Latch
Select
Bit
Common Common Common
Data Bit Data Bit Data Bit
767
766
765
768
767
766
765
Common Common
Data Bit Data Bit
764
763
764
Common
Data Bit
5
763
5
3
4
2
1
0
768 Bits
Grayscale (GS) Data Latch (768 Bits)
752
48
47
32
31
16
15
LSB
0
OUTB15
Bit 0
OUTR1
Bit 0
OUTB0
Bit 15
OUTB0
Bit 0
OUTG0
Bit 15
OUTG0
Bit 0
OUTR0
Bit 15
OUTR0
Bit 0
MSB
767
SIN
SCLK
Lower 768 Bits
Bits 767:0
OUTB15
Bit 15
Common Common Common Common Common
Data Bit Data Bit Data Bit Data Bit Data Bit
4
3
2
1
0
GS data for OUTB15
GS data for OUTG0
GS data for OUTB0
GS data for OUTR0
768 Bits
The latch pulse
comes from LAT
when the MSB of
the common shift
register is 0 and the
RFRESH bit is 0.
When the REFRESH
bit is 1, the latch
pulse is input at the
65536th GS clock
after the LAT input.
To Grayscale Timing Control Circuit
Bits 335:0
Bits 344:336
9–Bit
Previous
MC data
RESET
from
UVLO
Bits
Bits
Bits
344:342 341:339 338:336
Bits 370:345
LatMC
Control Data
Latch (371 Bits)
Bits 767:760
MSB
LSB
767 --- 760
8-Bit Command
Decoder
LAT
(96h)
MSB - 366
365:359
370:366
FUNC
Bits 4:0
FC, 5 Bits
BRIGHT
Bits 6:0,
OUTBn
358:352
351:345
BRIGHT
Bits 6:0,
OUTGn
BRIGHT
Bits 6:0,
OUTRn
BC, 21 Bits
344:342
Max
Current
OUTBn
341:339 338:336 335:329
Max
Current
OUTGn
Max
Current
OUTRn
MC, 9 Bits
LSB
6:0
328:322
DOTCOR DOTCOR
Bits 6:0, Bits 6:0,
OUTB15 OUTG15
DOTCOR
Bits 6:0,
OUTR0
DC, 336 Bits
336 Bits
335:329
LSB
6:0
335:322
DOTCOR DOTCOR
Bits 6:0, Bits 6:0,
OUTB15 OUTG15
DOTCOR
Bits 6:0,
OUTR0
DC, 336 Bits
The latch pulse
comes from LAT
DC Data Latch (336 Bits) when the MSB of
5 Bits
To Control Logic
9 Bits
21 Bits
To BC Circuit
To Output Current
Reference Circuit
336 Bits
the common shift
register is 1.
To Dot Correction Circuit
Figure 21. Common Shift Register and Data Latches Configuration
8.3.2.1 769-Bit Common Shift Register
The 769-bit common shift register is used to shift data from the SIN terminal into the TLC5955. The data shifted
into the register are used for GS, DC, maximum output current, global BC functions, and function control data
write operations. The common shift register LSB is connected to SIN and the MSB is connected to SOUT. On
each SCLK rising edge, the data on SIN are shifted into the LSB and all 769 bits are shifted towards the MSB.
The register MSB is always connected to SOUT. When the device is powered up, the data in the 769-bit
common shift register are random.
18
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Feature Description (continued)
8.3.2.2 Grayscale (GS) Data Latch
The GS data latch is 768 bits long, and sets the PWM timing for each constant-current output. The on-time of all
constant-current outputs is controlled by the data in this data latch. The 768-bit GS data in the common shift
register are copied to the data latch at a LAT rising edge when the common shift resister MSB is 0.
When the device is powered up, the data are random and all constant-current outputs are forced off. However,
no outputs turn on until GS data are written to the GS data latch even if a GSCLK is input. The data bit
assignment is shown in Table 1. Refer to Figure 22 for a GS data write timing diagram.
Table 1. Grayscale Data Latch Bit Description
GS DATA
LATCH BIT
NUMBER
BIT NAME
DEFAULT
VALUE
CONTROLLED
CHANNEL
GS DATA
LATCH BIT
NUMBER
DEFAULT
VALUE
BIT NAME
CONTROLLED
CHANNEL
15-0
GSR0[15:0]
Bits[15:0] for OUTR0
399-384
GSR8[15:0]
Bits[15:0] for OUTR8
31-16
GSG0[15:0]
Bits[15:0] for OUTG0
415-400
GSG8[15:0]
Bits[15:0] for OUTG8
47-32
GSB0[15:0]
Bits[15:0] for OUTB0
431-416
GSB8[15:0]
Bits[15:0] for OUTB8
63-48
GSR1[15:0]
Bits[15:0] for OUTR1
447-432
GSR9[15:0]
Bits[15:0] for OUTR9
79-64
GSG1[15:0]
Bits[15:0] for OUTG1
463-448
GSG9[15:0]
Bits[15:0] for OUTG9
95-80
GSB1[15:0]
Bits[15:0] for OUTB1
479-464
GSB9[15:0]
Bits[15:0] for OUTB9
111-96
GSR2[15:0]
Bits[15:0] for OUTR2
495-480
GSR10[15:0]
Bits[15:0] for OUTR10
127-112
GSG2[15:0]
Bits[15:0] for OUTG2
511-496
GSG10[15:0]
Bits[15:0] for OUTG10
143-128
GSB2[15:0]
Bits[15:0] for OUTB2
527-512
GSB10[15:0]
Bits[15:0] for OUTB10
159-144
GSR3[15:0]
Bits[15:0] for OUTR3
543-528
GSR11[15:0]
Bits[15:0] for OUTR11
175-160
GSG3[15:0]
Bits[15:0] for OUTG3
559-544
GSG11[15:0]
191-176
GSB3[15:0]
Bits[15:0] for OUTB3
575-560
GSB11[15:0]
207-192
GSR4[15:0]
Bits[15:0] for OUTR4
591-576
GSR12[15:0]
223-208
GSG4[15:0]
Bits[15:0] for OUTG4
607-592
GSG12[15:0]
239-224
GSB4[15:0]
Bits[15:0] for OUTB4
623-608
GSB12[15:0]
Bits[15:0] for OUTB12
255-240
GSR5[15:0]
Bits[15:0] for OUTR5
639-624
GSR13[15:0]
Bits[15:0] for OUTR13
271-256
GSG5[15:0]
Bits[15:0] for OUTG5
655-640
GSG13[15:0]
Bits[15:0] for OUTG13
287-272
GSB5[15:0]
Bits[15:0] for OUTB5
671-656
GSB13[15:0]
Bits[15:0] for OUTB13
303-288
GSR6[15:0]
Bits[15:0] for OUTR6
687-672
GSR14[15:0]
Bits[15:0] for OUTR14
319-304
GSG6[15:0]
Bits[15:0] for OUTG6
703-688
GSG14[15:0]
Bits[15:0] for OUTG14
335-320
GSB6[15:0]
Bits[15:0] for OUTB6
719-704
GSB14[15:0]
Bits[15:0] for OUTB14
351-336
GSR7[15:0]
Bits[15:0] for OUTR7
735-720
GSR15[15:0]
Bits[15:0] for OUTR15
367-352
GSG7[15:0]
Bits[15:0] for OUTG7
751-736
GSG15[15:0]
Bits[15:0] for OUTG15
383-368
GSB7[15:0]
Bits[15:0] for OUTB7
767-752
GSB15[15:0]
Bits[15:0] for OUTB15
N/A
(no default
value)
Bits[15:0] for OUTG11
N/A
(no default
value)
Bits[15:0] for OUTB11
Bits[15:0] for OUTR12
Bits[15:0] for OUTG12
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R0
0A
SIN
B15
15B
Low
B15
14B
B15
13B
3
4
R0
3B
R0
2B
R0
1B
R0
0B
B15
15C
Low
B15
14C
B15
13C
B15
12C
B15
11C
3
4
5
SCLK
1
2
766
767
768
769
1
2
6
LAT
Common Shift Register LSB
(Internal)
R0
0A
Low
B15
15B
B15
14B
R0
3B
R0
2B
R0
1B
R0
0B
Low
B15
15C
B15
14C
B15
13C
B15
12C
Common Shift Register LSB+1
(Internal)
R0
1A
R0
0A
Low
B15
15B
R0
4B
R0
3B
R0
2B
R0
1B
R0
0B
Low
B15
15C
B15
14C
B15
13C
Common Shift Register MSB–2
(Internal)
B15
14A
LOD
G15
LOD
R15
LOD
B14
LOD
G14
R0
0A
Low
B15
15B
B15
14B
LOD
G15A
LOD LOD LOD LOD LOD
R15A B14A G14A R14A B13A
Common Shift Register MSB–1
(Internal)
B15
15A
LOD
B15
LOD
G15
LOD
R15
LOD
B14
R0
1A
R0
0A
Low
B15
15B
LOD
B15A
LOD LOD LOD LOD LOD
G15A R15A B14A G14A R14A
LOD
B15
LOD
G15
LOD
R15
R0
2A
R0
1A
R0
0A
Common Shift Register MSB
(Internal)
Low
Grayscale Data Latch
(Internal)
DC, MC, BC, FC Data
336-Bit DC Data Latch
(Internal)
SOUT
Control data are not changed.
Same data are copied from the DC data latch in the control data latch.
DC Data
L
LOD
B15
LOD
G15
LOD LOD LOD LOD LOD
B15A G15A R15A B14A G14A
GS Data
GS Data
Control Data Latch
(DC, MC, BC, FC)
(Internal)
Low
LOD
R15
R0
2A
R0
1A
R0
0A
Low
LOD LOD LOD LOD LOD
B15A G15A R15A B14A G14A
Figure 22. Grayscale Data Write Timing Diagram (RFRESH = 0)
8.3.2.3 Control Data Latch
The control data latch is 371 bits long. The data latch contains dot correction (DC) data, maximum current (MC)
data, global brightness control (BC) data, and function control (FC) data. The DC for each constant-current
output are controlled by the data in the DC data latch. The control data in the data latch are updated with the
lower 371 bits of the common shift register at the LAT rising edge when the common shift register MSB is 1. The
336 bits of DC data are copied from the control data latch when the 65,536th GSCLK is input with RFRESH set
to 1 in the control data latch after the GS data are written or the LAT rising edge for GS data writes is input when
the RFRESH bit is 0.
When the device is powered up, the data in the control data latch (except the MC bits) are random. Therefore,
DC, BC, and FC data must be written to the control data latch before turning on the constant-current outputs.
Furthermore, MC data should be set appropriately for the application. Refer to Figure 23 for a control data write
timing diagram.
20
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SIN
DCR0
0A
H
H
L
L
H
DCR0
3B
DCR0
2B
DCR0
0B
DCR0
1B
H
L
H
L
H
L
DC, MC, BC, FC data writes are selected when the MSB[1:9] bits are 96h (HLLHLHHL).
DC, MC, BC, FC are selected
when the MSB is high.
SCLK
1
2
3
4
5
766
767
768
1
769
2
3
4
5
6
LAT
Common Shift Register LSB
(Bit 0, Internal)
DCR0
0A
H
H
L
L
DCR0
3B
DCR0
2B
DCR0
1B
DCR0
0B
H
H
L
L
H
Common Shift Register LSB +1
(Bit 1, Internal)
DCR0
1A
DCR0
0A
H
H
L
DCR0
4B
DCR0
3B
DCR0
2B
DCR1
1B
DCR0
0B
H
H
L
L
Common Shift Register
(Bit 336, Internal)
MCR
0A
DCB0
6A
DCB0
5A
DCB0
4A
DCB0
3A
MCG
0B
MCR
2B
MCR
1B
MCR
0B
DCB0
6B
DCB0
5B
DCB0
4B
DCB0
3B
DCB0
2B
Common Shift Register
(Bit 344, Internal)
MCB
2A
MCB
1A
MCB
0A
MCG MCB
2A
1A
BCR
2B
BCR
1B
BCR
0B
MCB
2B
MCB
1B
MCB
0B
MCG
2B
MCG
1B
MCG
0B
Common Shift Register MSB–1
(Bit 767, Internal)
H
L
L
H
L
DCR0
1A
DCR0
0A
H
H
L
L
H
L
H
Common Shift Register MSB
(Bit 768, Internal)
H
H
L
L
H
DCR0
2A
DCR0
1A
DCR0
0A
H
H
L
L
H
L
GS Data Latch
(Internal)
On and off control data are not changed.
DC data in the data latch are updated when the MSB of the common shift register
is 1 and the write command bit (bits 767 :760) is 96h (10010110b).
DC Data in Control Data Latch
(Internal)
New DC Data
Old DC Data
The 336-bit DC data are not updated at this time. DC data in the control data latch
are copied to the 336-bit DC data latch when the GS data are copied from common
shift register to the GS data latch.
336-Bit DC Data Latch
(Internal)
DC Data are Not Changed
DC Data
The 9-bit MC data (bits 344:336) in the data latch are not updated at this time
because the previous MC data (MCB2A to MCR0A) are written.
MC Data Latch
(Internal)
MC data are updated when the same data are written twice with the write command
data (96h). MCB2B to MCR0B data must be the same as MCB2A to MCR0A.
New MC Data
Old MC Data
BC Data Latch
(Internal)
New BC Data
Old BC Data
BC and FC data in the data latch are updated when the MSB of the common shift
register is 1 and write command bit (bits 767 :760) is 96h10010110b.
FC Data Latch
(Internal)
SOUT
New FC Data
Old FC Data
H
H
L
L
H
DCR0
2
DCR0
1
DCR0
0
H
H
L
L
H
L
Figure 23. Control Data Write Timing Diagram for DC, MC, BC, and FC
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Dot Correction (DC) Data Latch
DC data are 336 bits long; the data for each constant-current output are controlled by seven bits. Each constantcurrent output DC is controlled by the DC data latch. Each DC value individually adjusts the output current for
each constant-current output. As explained in the Dot Correction (DC) Function section, the DC values are used
to adjust the output current from 26.2% to 100% of the current value set by MC and BC data. When the device is
powered on, the data in the DC data latch are random.
The DC data bit assignment is shown in Table 2. See Table 9 for a summary of the DC data value versus set
current value.
Table 2. Dot Correction Data Bit Description
CONTROL
DATA LATCH
BIT NUMBER
BIT NAME
DEFAULT
VALUE
CONTROLLED
CHANNEL
CONTROL
DATA LATCH
BIT NUMBER
BIT NAME
CONTROLLED
CHANNEL
DEFAULT
VALUE
6-0
DCR0[6:0]
DC bits[6:0] for OUTR0
174-168
DCR8[6:0]
DC bits[6:0] for OUTR8
13-7
DCG0[6:0]
DC bits[6:0] for OUTG0
181-175
DCG8[6:0]
DC bits[6:0] for OUTG8
20-14
DCB0[6:0]
DC bits[6:0] for OUTB0
188-182
DCB8[6:0]
DC bits[6:0] for OUTB8
27-21
DCR1[6:0]
DC bits[6:0] for OUTR1
195-189
DCR9[6:0]
DC bits[6:0] for OUTR9
34-28
DCG1[6:0]
DC bits[6:0] for OUTG1
202-196
DCG9[6:0]
DC bits[6:0] for OUTG9
41-35
DCB1[6:0]
DC bits[6:0] for OUTB1
209-203
DCB9[6:0]
DC bits[6:0] for OUTB9
48-42
DCR2[6:0]
DC bits[6:0] for OUTR2
216-210
DCR10[6:0]
DC bits[6:0] for OUTR10
55-49
DCG2[6:0]
DC bits[6:0] for OUTG2
223-217
DCG10[6:0]
DC bits[6:0] for OUTG10
62-56
DCB2[6:0]
DC bits[6:0] for OUTB2
230-224
DCB10[6:0]
DC bits[6:0] for OUTB10
69-63
DCR3[6:0]
DC bits[6:0] for OUTR3
237-231
DCR11[6:0]
DC bits[6:0] for OUTR11
76-70
DCG3[6:0]
DC bits[6:0] for OUTG3
244-238
DCG11[6:0]
83-77
DCB3[6:0]
DC bits[6:0] for OUTB3
251-245
DCB11[6:0]
90-84
DCR4[6:0]
DC bits[6:0] for OUTR4
258-252
DCR12[6:0]
N/A
(no default
value)
DC bits[6:0] for OUTG11
N/A
(no default
value)
DC bits[6:0] for OUTB11
DC bits[6:0] for OUTR12
97-91
DCG4[6:0]
DC bits[6:0] for OUTG4
265-259
DCG12[6:0]
104-98
DCB4[6:0]
DC bits[6:0] for OUTB4
272-266
DCB12[6:0]
DC bits[6:0] for OUTG12
DC bits[6:0] for OUTB12
111-105
DCR5[6:0]
DC bits[6:0] for OUTR5
279-273
DCR13[6:0]
DC bits[6:0] for OUTR13
118-112
DCG5[6:0]
DC bits[6:0] for OUTG5
286-280
DCG13[6:0]
DC bits[6:0] for OUTG13
125-119
DCB5[6:0]
DC bits[6:0] for OUTB5
293-287
DCB13[6:0]
DC bits[6:0] for OUTB13
132-126
DCR6[6:0]
DC bits[6:0] for OUTR6
300-294
DCR14[6:0]
DC bits[6:0] for OUTR14
139-133
DCG6[6:0]
DC bits[6:0] for OUTG6
307-301
DCG14[6:0]
DC bits[6:0] for OUTG14
146-140
DCB6[6:0]
DC bits[6:0] for OUTB6
314-308
DCB14[6:0]
DC bits[6:0] for OUTB14
153-147
DCR7[6:0]
DC bits[6:0] for OUTR7
321-315
DCR15[6:0]
DC bits[6:0] for OUTR15
160-154
DCG7[6:0]
DC bits[6:0] for OUTG7
328-322
DCG15[6:0]
DC bits[6:0] for OUTG15
167-161
DCB7[6:0]
DC bits[6:0] for OUTB7
335-329
DCB15[6:0]
DC bits[6:0] for OUTB15
8.3.2.5
Maximum Current (MC) Data Latch
The maximum output current per channel, IOLCMax, is programmed by MC data and can be set with the serial
interface. IOLCMax is the largest current for each output. Each output sinks the IOLCMax current when they turn on
with DC and BC data set to the maximum value of 7Fh (127d). MC data must have the same data continuously
written twice in order to change the data. When the device is powered on, the MC data are set to 0.
The MC data bit assignment is shown in Table 3. See Table 8 for a summary of the MC data value for each color
group versus the set current value.
Table 3. Maximum Current Data Bit Assignment in the Control Data Latch
CONTROL DATA
LATCH BIT
NUMBER
22
CONTROLLED CHANNEL
BIT NAME
DEFAULT VALUE
338-336
MCR[2:0]
0
MC bits[2:0] for red color group channels (OUTR0 to OUTR15)
341-339
MCG[2:0]
0
MC bits[2:0] for green color group channels (OUTG0 to OUTG15)
344-342
MCB[2:0]
0
MC bits[2:0] for blue color group channels (OUTB0 to OUTB15)
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8.3.2.6 Global Brightness Control (BC) Data Latch
Global BC data are seven bits long. The global brightness for all outputs is controlled by the data in the control
data latch. The data are used to adjust the constant-current values for the 48-channel constant-current outputs.
As explained in the Global Brightness Control (BC) Function section, the BC values are used to adjust the output
current from 10% to 100% of the maximum value. When the device is powered on, the BC data are random.
The global BC data bit assignment in the control data latch is shown in Table 4. See Table 10 for a summary of
the BC data value versus set current value.
Table 4. Global Brightness Control Data Bit Assignment in the Control Data Latch
CONTROL DATA
LATCH BIT
NUMBER
CONTROLLED CHANNEL
BIT NAME
351-345
BCR[6:0]
358-352
BCG[6:0]
365-359
BCB[6:0]
DEFAULT VALUE
BC bits[6:0] for red color group channels (OUTR0 to OUTR15)
N/A (no default value) BC bits[6:0] for green color group channels (OUTG0 to OUTG15)
BC bits[6:0] for blue color group channels (OUTB0 to OUTB15)
8.3.2.7 Function Control (FC) Data Latch
The FC data latch is 5 bits long. This latch enables the auto display repeat and display timing reset functions,
and sets the DC data auto refresh, PWM control mode, and the LSD detection voltage. Each function is selected
by the data in the control data latch. When the device is powered on, the FC data are random. The FC data bit
assignment in the control data latch is shown in Table 5.
Table 5. Function Control Data Latch Bit Description
BIT
NUMBER
366
367
368
369
370
BIT
NAME
DEFAULT
VALUE
(Binary)
DESCRIPTION
DSPRPT
Auto display repeat mode enable bit
0 = Disabled, 1 = Enabled
When this bit is 0, the auto display repeat function is disabled. Each constant-current
output is turned on and off for one display period.
When this bit is 1, each output repeats the PWM control every 65,536 GSCLKs.
TMGRST
Display timing reset mode enable bit
0 = Disabled, 1 = Enabled
When this bit is 0, the GS counter is not reset and the outputs are not forced off even
when a LAT rising edge is input for a GS data write.
When this bit is 1, the GS counter is reset to 0 and all outputs are forced off at the
LAT rising edge for a GS data write. Afterwards, PWM control resumes from the next
GSCLK rising edge.
RFRESH
Auto data refresh mode enable bit
0 = Disabled, 1 = Enabled
When this bit is 0, the auto data refresh function is disabled. The data in the common
shift register are copied to the GS data latch at the next LAT rising edge for a GS
data write. DC data in the control data latch are copied to the DC data latch at the
same time.
When this bit is 1, the auto data refresh function is enabled. The data in the common
shift register are copied to the GS data latch at the 65,536th GSCLK after the LAT
rising edge for a GS data write. DC data in the control data latch are copied to the
DC data latch at the same time.
N/A
(no default
value)
ESPWM
ES-PWM mode enable bit
0 = Disabled, 1 = Enabled
When this bit is 0, the conventional PWM control mode is selected. If the TLC5955 is
used for multiplexing a drive, the conventional PWM mode should be selected to
prevent excess on or off switching.
When this bit is 1, ES-PWM control mode is selected.
LSDVLT
LSD detection voltage selection bit
LED short detection (LSD) detects a fault caused by a shorted LED by comparing the
OUTXn voltage to the LSD detection threshold voltage. The threshold voltage is
selected by this bit.
When this bit is 0, the LSD voltage is VCC × 70%. When this bit is 1, the LSD voltage
is VCC × 90%.
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8.3.3 Status Information Data (SID)
The status information data (SID) contains the status of the LED open detection (LOD) and LED short detection
(LSD). When the MSB of the common shift register is set to 0 and the RFRESH bit in the control data latch is 0,
the SID are loaded to the common shift register at the LAT falling edge after the data in the common shift
register are loaded to the grayscale data latch. If the common shift register MSB is 1, the SID are not loaded to
the common shift register.
When the MSB of the common shift register is set to 0 and the RFRESH bit in the control data latch is 1, the SID
are loaded to the common shift register at the GS counter 0000h just after LAT when the GS data are input. If
the common shift register MSB is 1, the SID are not loaded to the common shift register. When the RFRESH bit
is 1, the SCLK rising edge must be input with a low-level LAT signal after 65,538 GSCLKs (or more) are input
from the LAT rising signal input.
After being loaded into the common shift register, new SID data cannot be loaded until at least one new bit of
data is written into the common shift register. To recheck SID without changing the GS data, reprogram the
common shift register with the same data currently programmed into the GS latch. When LAT goes high, the GS
data do not change, but new SID data are loaded into the common shift register. LOD and LSD are shifted out of
SOUT with each SCLK rising edge. The SID load configuration is shown in Figure 24 and Table 6.
SID are loaded
to the common
shift register at
the LAT falling
edge when the
common shift
register MSB is 0.
SOUT
MSB
Latch
Select
bit
LOD
Data of
OUTB15
Common
Data Bit
767
LOD
Data of
OUTB0
LOD
Data of
OUTG0
LOD
Data of
OUTR0
LSD
Data of
OUTB15
Common Common Common Common
Data Bit Data Bit Data Bit Data Bit
722
721
720
719
LSD
Data of
OUTB0
LSD
Data of
OUTG0
LSD
Data of
OUTR0
LSB
Common Common Common Common
Data Bit Data Bit Data Bit Data Bit
672
671-0
674
673
SIN
SCLK
Common Shift Register (769 Bits)
Figure 24. SID Load Configuration
24
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Table 6. SID Load Description
COMMON SHIFT REGISTER BIT
NUMBER
671-0
LOADED SID
COMMON SHIFT REGISTER BIT
NUMBER
LOADED SID
No data loaded
720
OUTR0 LOD data
672
OUTR0 LSD data
(0 = No error, 1 = Error)
721
OUTG0 LOD data
673
OUTG0 LSD data
722
OUTB0 LOD data
674
OUTB0 LSD data
723
OUTR1 LOD data
675
OUTR1 LSD data
724
OUTG1 LOD data
676
OUTG1 LSD data
725
OUTB1 LOD data
677
OUTB1 LSD data
726
OUTR2 LOD data
678
OUTR2 LSD data
727
OUTG2 LOD data
679
OUTG2 LSD data
728
OUTB2 LOD data
680
OUTB2 LSD data
729
OUTR3 LOD data
681
OUTR3 LSD data
730
OUTG3 LOD data
682
OUTG3 LSD data
731
OUTB3 LOD data
683
OUTB3 LSD data
732
OUTR4 LOD data
684
OUTR4 LSD data
733
OUTG4 LOD data
685
OUTG4 LSD data
734
OUTB4 LOD data
686
OUTB4 LSD data
735
OUTR5 LOD data
687
OUTR5 LSD data
736
OUTG5 LOD data
688
OUTG5 LSD data
737
OUTB5 LOD data
689
OUTB5 LSD data
738
OUTR6 LOD data
690
OUTR6 LSD data
739
OUTG6 LOD data
691
OUTG6 LSD data
740
OUTB6 LOD data
692
OUTB6 LSD data
741
OUTR7 LOD data
693
OUTR7 LSD data
742
OUTG7 LOD data
694
OUTG7 LSD data
743
OUTB7 LOD data
695
OUTB7 LSD data
744
OUTR8 LOD data
696
OUTR8 LSD data
745
OUTG8 LOD data
697
OUTG8 LSD data
746
OUTB8 LOD data
698
OUTB8 LSD data
747
OUTR9 LOD data
699
OUTR9 LSD data
748
OUTG9 LOD data
700
OUTG9 LSD data
749
OUTB9 LOD data
701
OUTB9 LSD data
750
OUTR10 LOD data
702
OUTR10 LSD data
751
OUTG10 LOD data
703
OUTG10 LSD data
752
OUTB10 LOD data
704
OUTB10 LSD data
753
OUTR11 LOD data
705
OUTR11 LSD data
754
OUTG11 LOD data
706
OUTG11 LSD data
755
OUTB11 LOD data
707
OUTB11 LSD data
756
OUTR12 LOD data
708
OUTR12 LSD data
757
OUTG12 LOD data
709
OUTG12 LSD data
758
OUTB12 LOD data
710
OUTB12 LSD data
759
OUTR13 LOD data
711
OUTR13 LSD data
760
OUTG13 LOD data
712
OUTG13 LSD data
761
OUTB13 LOD data
713
OUTB13 LSD data
762
OUTR14 LOD data
714
OUTR14 LSD data
763
OUTG14 LOD data
715
OUTG14 LSD data
764
OUTB14 LOD data
716
OUTB14 LSD data
765
OUTR15 LOD data
717
OUTR15 LSD data
766
OUTG15 LOD data
718
OUTG15 LSD data
767
OUTB15 LOD data
719
OUTB15 LSD data
768
No data loaded
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8.3.4 LED Open Detection (LOD)
LOD detects a fault caused by an LED open circuit or a short from OUTXn to ground with low resistance by
comparing the OUTXn voltage to the LOD detection threshold voltage (0.3 V, typically). If the OUTXn voltage is
lower than the threshold voltage when OUTXn is on, that output LOD bit is set to 1 to indicate an open LED.
Otherwise, the LOD bit is set to 0. LOD data are only valid for outputs that are programmed to be on. LOD data
are latched into the LOD, LSD data latch at the 33rd GSCLK. LOD data for outputs programmed to be off at the
33rd GSCLK are always 0. The LED open detection circuit is shown in Figure 25 and Table 7 lists an LOD truth
table. Refer to Figure 26 for an LOD read timing diagram.
8.3.5 LED Short Detection (LSD)
LSD data detect a fault caused by a shorted LED between LED terminals by comparing the OUTXn voltage to
the LSD detection threshold voltage level set by LSDVLT in the control data latch. If the OUTXn voltage is higher
than the programmed voltage when OUTXn is on, the corresponding output LSD bit is set to 1 to indicate a
shorted LED. Otherwise, the LSD bit is set to 0. LSD data are only valid for outputs that are programmed to be
on. LSD data are latched into the LOD, LSD data latch at the 33rd GSCLK. LSD data for outputs programmed to
be off at the 33rd GSCLK are always 0. The LSD open detection circuit is shown in Figure 25 and Table 7 lists
an LSD truth table. Refer to Figure 26 for an LSD read timing diagram.
VLED
LED Lamp
LSD Data
OUTXn
1 = Error
VLSD
LOD Data
Constant current is set
by MC data.
PWM
Control
1 = Error
VLOD
GND
Figure 25. LOD and LSD Circuit
Table 7. LOD and LSD Truth Table
CONDITION
SID DATA
26
LOD
LSD
0
LED is not opened (VOUTXn > VLOD)
LED is not shorted (VOUTXn ≤ VLSD)
1
LED is open or shorted to GND (VOUTXn ≤ VLOD)
LED is shorted between anode and cathode, or shorted to
higher voltage side (VOUTXn > VLSD)
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1
2
3
4
5
31 32 33 34 35
65533 65535
65534 65536
1
2
3
4
5
GSCLK
Programmed output current
(ON)
OUTXn current
(When GSDATA=FFFFh)
0mA (OFF)
0mA (OFF)
Output current set by MC/DC/BC data
LOD data is always 0
when OUTXn is off.
48-bit LOD/LSD
Circuit Output Data
(Internal)
LOD/LSD data
aren’t stable just
after OUTXn on.
XXXXh
0000h
XXXXh
XXXXh
0000h
XXXXh
LOD/LSD data latch is updated at 33rd GSCLK of the display period.
96 Bit LOD/LSD
Data Latch
(Internal)
Old data
XXXXh
XXXXh
LAT signal for
grayscale data writing
LAT
When RFRESH bit is 1, SID is loaded
at 65536th GSCLK and SCLK must be
input after 1st GSCLK input.
769-bit common
Shift Register Data
(Internal)
Grayscale Data
XXXXh is loaded as SID.
Figure 26. LOD and LSD Read and Load Timing Diagram
8.3.6 Noise Reduction
Large surge currents may flow through the device and the board on which the device is mounted if all 48 outputs
turn on simultaneously at the start of each GS cycle. These large current surges can introduce detrimental noise
and electromagnetic interference (EMI) into other circuits. The TLC5955 independently turns the outputs on with
a series delay for each group to provide a soft-start feature. The output current sinks are grouped into eight
groups. The first output group that is turned on or off are OUTR4, OUTG4, OUTB4, OUTR11, OUTG11, and
OUTB11; the second output group is OUTX0 and OUTX15; the third output group is OUTX5 and OUTX10; the
fourth output group is OUTX1 and OUTX14; the fifth output group is OUTX2 and OUTX13; the sixth output group
is OUTX6 and OUTX9; the seventh output group is OUTX3 and OUTX12; and the eighth output group is OUTX7
and OUTX8. Each output group is turned on and off sequentially with a small delay between groups.
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8.4 Device Functional Modes
8.4.1 Maximum Current Control (MC) Function
The maximum output current per channel, IOLCMax, is programmed by the MC data and is set with the serial
interface. IOLCMax is the largest current for each output. Each OUTXn sinks the IOLCMax current when they turn on
and the dot correction and global brightness control data are set to the maximum value of 7Fh (127d).
When the device is powered on, the MC data are set to 0. MC data should be changed when all constant-current
outputs (OUTXn, where X = R, G, or B; n = 0 to 7) are off. MCX = 6 and MCX = 7 are used when VCC is greater
than 3.6 V. The same MC data must be written twice to change the maximum constant-current output. Table 8
shows the characteristics of the constant-current sink versus the maximum current (MC) control data.
Table 8. Maximum Constant-Current Output versus MC Data
MCX (1) DATA
DECIMAL
HEX
000 (default)
0 (default)
0 (default)
3.2
001
1
1
8.0
010
2
2
11.2
011
3
3
15.9
100
4
4
19.1
101
5
5
23.9
(3)
6
6
27.1
111 (3)
7
7
31.9
110
(1)
(2)
(3)
IOLCMax (mA), OUTXn (2)
BINARY
X = R, G, or B.
X = R, G, or B. n = 0 to 15.
MCX7 and MCX6 can be used when VCC is greater than 3.6 V.
8.4.2 Dot Correction (DC) Function
The TLC5955 can individually adjust the output current of each channel (OUTx0 to OUTx15, where x is R, G, or
B) by using DC. The DC function allows the brightness deviations of the LEDs connected to each output to be
individually adjusted. Each output DC is programmed with a 7-bit word, so the value is adjusted with 128 steps
within the range of 26.2% to 100% of IOLCMax. DC data are programmed into the TLC5955 with the serial
interface. When the device is powered on, the DC data in the control latch contains random data. Therefore, DC
data must be written to the DC data latch before turning the constant-current outputs on. Table 9 summarizes the
DC data value versus the set current value.
Table 9. DC Data versus Current Ratio and Set Current Value
DCXn
(1)
28
(1)
DATA
BINARY
DECIMAL
HEX
BC DATA (Hex)
RATIO OF
OUTPUT
CURRENT TO
IOLCMax (%)
000 0000
0
00
7F
26.2
8.36
0.84
000 0001
1
01
7F
26.7
8.54
0.86
000 0010
2
02
7F
27.3
8.73
0.88
—
—
—
—
—
—
—
111 1101
125
7D
7F
98.8
31.5
3.16
111 1110
126
7E
7F
99.4
31.7
3.18
111 1111
127
7F
7F
100.0
31.9
3.20
IOUT (mA)
(MC = 7, typical)
IOUT (mA)
(MC = 0, typical)
X = R, G, or B. n = 0 to 15.
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8.4.3 Global Brightness Control (BC) Function
The TLC5955 has the ability to adjust the output current of all constant-current outputs of each color group
(OUTR0 to OUTR15, OUTG0 to OUTG15, and OUTB0 to OUTB15) simultaneously to the same current ratio.
This function is called global brightness control (BC). The BC function allows the global brightness of LEDs
connected to the output to be adjusted. All outputs of each color group can be adjusted in 128 steps from 10% to
100% of the maximum output current, IOLCMax. BC data are programmed into the TLC5955 with the serial
interface. When the BC data change, the output current also changes immediately. When the device is powered
on, the BC data contain random data. Table 10 summarizes the BC data versus the set current value.
Table 10. BC Data versus Constant-Current Ratio and Set Current Value
BCX (1) DATA
(1)
(2)
BINARY
DECIMAL
HEX
DCXn (2) DATA
(Hex)
RATIO OF
OUTPUT
CURRENT TO
IOLCMax(%)
000 0000
0
00
7F
10.0
3.19
0.32
000 0001
1
01
7F
10.7
3.42
0.34
000 0010
2
02
7F
11.4
3.64
0.37
—
—
—
—
—
—
—
111 1101
125
7D
7F
98.6
31.5
3.15
111 1110
126
7E
7F
99.3
31.7
3.18
111 1111
127
7F
7F
100.0
31.9
3.20
IOUT (mA)
(MC = 7, typical)
IOUT (mA)
(MC = 0, typical)
X = R, G, or B.
X = R, G, or B. n = 0 to 15.
8.4.4 Grayscale (GS) Function (PWM Control)
The TLC5955 can adjust the brightness of each output channel using a pulse width modulation (PWM) control
scheme. The architecture of 16 bits per channel results in 65,536 brightness steps, from 0% up to 100%
brightness.
The PWM operation for OUTn is controlled by a 16-bit grayscale (GS) counter. The GS counter increments on
each GS reference clock (GSCLK) rising edge. The GS counter resets to 0000h when the LAT rising signal for a
GS data write is input with the display timing reset mode enabled.
The TLC5955 has two types of PWM control: conventional PWM control and enhanced spectrum (ES) PWM
control. The conventional PWM control can be selected when the ESPWM bit in the control data latch is 0. The
ES PWM control is selected when the ESPWM bit is 1. The conventional PWM control should be selected for
multiplexing a drive. The ES-PWM control should be selected for a static drive.
The on-time (tOUT_ON) of each output (OUTn) can be calculated by Equation 2.
tOUT_ON (ns) = tGSCLK (ns) × GSXn
where:
•
•
•
•
TGSCLK = one GS clock period,
GSXn = the programmed GS value for OUTXn (GSXn = 0d to 65535d),
X = R, G, or B for the red, green, or blue color group, and
n = 0 to 15.
(2)
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Table 11 summarizes the GS data values versus the output on-time duty cycle. When the device powers up, all
OUTXn are forced off, the GS counter initializes to 0000h, and the status remains the same until GS data are
written. After that, each OUTXn on and off status can be controlled by GS data and GSCLK.
Table 11. Output Duty Cycle and On-Time versus GS Data
GS DATA
30
GS DATA
DECIMAL
HEX
ON-TIME DUTY (%)
DECIMAL
HEX
ON-TIME DUTY (%)
0
1
0
0
32768
8000
50.000
1
0.002
32769
8001
2
50.002
2
0.003
32770
8002
50.003
50.005
3
3
0.005
32771
8003
—
—
—
—
—
—
8191
1FFF
12.498
40959
9FFF
62.498
8192
2000
12.500
40960
A000
62.500
8193
2001
12.502
40961
A001
62.502
—
—
—
—
—
—
16381
3FFD
24.996
49149
BFFD
74.995
16382
3FFE
24.997
49150
BFFE
74.997
16383
3FFF
24.998
49151
BFFF
74.998
16384
4000
25.000
49152
C000
75.000
16385
4001
25.002
49153
C001
75.002
16386
4002
25.003
49154
C002
75.003
16387
4003
25.005
49155
C003
75.005
—
—
—
—
—
—
24575
5FFF
37.498
57343
DFFF
87.498
24576
6000
37.500
57344
E000
87.500
24577
6001
37.502
57345
E001
87.502
—
—
—
—
—
—
32765
7FFD
49.995
65533
FFFD
99.995
32766
7FFE
49.997
65534
FFFE
99.997
32767
7FFF
49.998
65535
FFFF
99.998
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Conventional PWM Control
The first GS clock rising edge increments the GS counter by one and switches on all outputs with a non-zero GS
value programmed into the GS data latch. Each additional GS clock rising edge increases the corresponding GS
counter by one.
The GS counter keeps track of the number of clock pulses from the respective GS clock inputs. Each output
stays on while the counter is less than or equal to the programmed GS value. Each output turns off at the GS
counter value rising edge when the counter becomes greater than the output GS latch value. Figure 27 illustrates
the conventional PWM operation.
LAT
1
2
3
4
32768
32769
32770
---
65535
65536
1
2
3
4
---
GSCLK
OUTXn
(VOUTXnL)
(VOUTXnH)
OFF
No driver turns on when Grayscale data is zero.
ON
(GSDATA=000h)
T=GSCLK*1
(VOUTXnH)
OUTXn
OFF
ON
(GSDATA=001h)
(VOUTXnL)
T=GSCLK*2
(VOUTXnH)
OFF
OUTXn
(VOUTXnL)
ON
(GSDATA=002h)
T=GSCLK*3
(VOUTXnH)
OUTXn
OFF
(VOUTXnL)
ON
(GSDATA=003h)
T=GSCLK*32767
OUTXn
(VOUTXnH)
OFF
ON
(GSDATA=7FFFh)
OUTXn
(VOUTXnL)
T=GSCLK*32768
(VOUTXnH)
OFF
ON
(GSDATA=8000h)
(VOUTXnL)
T=GSCLK*32769
(VOUTXnH)
OFF
OUTXn
(VOUTXnL)
ON
(GSDATA=8001h)
T=GSCLK*65533
(VOUTXnH)
OUTXn
OFF
(VOUTXnL)
ON
(GSDATA=FFFDh)
T=GSCLK*65534
(VOUTXnH)
OFF
OUTXn
(VOUTXnL)
ON
(GSDATA=FFFEh)
T=GSCLK*65535
(VOUTXnH)
OFF
OUTXn
(VOUTXnL)
ON
(GSDATA=FFFFh)
OUTXn turn on at the first GSCLK rising edge except when GS data are 0 after the
LAT rising signal for GS data writes is input with the display timing reset mode enabled.
OUTXn do not turn on again except for when the LAT rising signal
for GS data writes is input with the display timing reset mode
enabled (TMGRST = 1), otherwise the auto repeat mode
(DSPRPT = 1) is enabled.
Figure 27. Conventional PWM Operation
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Enhanced Spectrum (ES) PWM Control
In this PWM control, the total display period is divided into 128 display segments. The total display period is the
time from the first GS clock (GSCLK) to the 65,536th GSCLK input. Each display segment has a maximum of
512 GSCLKs. The OUTXn on-time changes, depending on the 16-bit GS data. Refer to Table 12 for the
sequence of information and to Figure 28 for the timing information.
Table 12. ES PWM Drive Turn On-Time Length
GS DATA
32
DECIMAL
HEX
0
0000h
Does not turn on
OUTn DRIVER OPERATION
1
0001h
Turns on for one GSCLK period in the first display segment
2
0002h
Turns on for one GSCLK period in the first and 65th display segments
3
0003h
Turns on for one GSCLK period in the first, 65th, and 33rd display segments
4
0004h
Turns on for one GSCLK period in the first, 65th, 33rd, and 97th display segments
5
0005h
Turns on for one GSCLK period in the first, 65th, 33rd, 97th, and 17th display segments
6
0006h
Turns on for one GSCLK period in the first, 65th, 33rd, 97th, 17th, and 81st display segments
The number of display segments where OUTn is turned on for one GSCLK is incremented by increasing GS data
in the following order:
1 > 65 > 33 > 97 > 17 > 81 > 49 > 113 > 9 > 73 > 41 > 105 > 25 > 89 > 57 > 121 > 5 > 69 > 37 > 101 > 21 > 85 >
53 > 117 > 13 > 77 > 45 > 109 > 29 > 93 > 61 > 125 > 3 > 67 > 35 > 99 > 19 > 83 > 51 > 115 > 11 > 75 > 43 >
107 > 27 > 91 > 59 > 123 > 7 > 71 > 39 > 103 > 23 > 87 > 55 > 119 > 15 > 79 > 47 > 111 > 31 > 95 > 63 > 127 >
2 > 66 > 34 > 98 > 18 > 82 > 50 > 114 > 10 > 74 > 42 > 106 > 26 > 90 > 58 > 122 > 6 > 70 > 38 > 102 > 22 > 86
> 54 > 118 > 14 > 78 > 46 > 110 > 30 > 94 > 62 > 126 > 4 > 68 > 36 > 100 > 20 > 84 > 52 > 116 > 12 > 76 > 44
> 108 > 28 > 92 > 60 > 124 > 8 > 72 > 40 > 104 > 24 > 88 > 56 > 120 > 16 > 80 > 48 > 112 > 32 > 96 > 64 >
128.
—
—
127
007Fh
Turns on for one GSCLK period in the first to 127th display segments, but does not turn on in the 128th display
segment
128
0080h
Turns on for one GSCLK period in all display segments (first to 128th)
129
0081h
Turns on for two GSCLK periods in the first display period and for one GSCLK period in all other display periods
The number of display segments where OUTn is turned on for one GSCLK is incremented by increasing GS data
in the following order:
1 > 65 > 33 > 97 > 17 > 81 > 49 > 113 > 9 > 73 > 41 > 105 > 25 > 89 > 57 > 121 > 5 > 69 > 37 > 101 > 21 > 85 >
53 > 117 > 13 > 77 > 45 > 109 > 29 > 93 > 61 > 125 > 3 > 67 > 35 > 99 > 19 > 83 > 51 > 115 > 11 > 75 > 43 >
107 > 27 > 91 > 59 > 123 > 7 > 71 > 39 > 103 > 23 > 87 > 55 > 119 > 15 > 79 > 47 > 111 > 31 > 95 > 63 > 127 >
2 > 66 > 34 > 98 > 18 > 82 > 50 > 114 > 10 > 74 > 42 > 106 > 26 > 90 > 58 > 122 > 6 > 70 > 38 > 102 > 22 > 86
> 54 > 118 > 14 > 78 > 46 > 110 > 30 > 94 > 62 > 126 > 4 > 68 > 36 > 100 > 20 > 84 > 52 > 116 > 12 > 76 > 44
> 108 > 28 > 92 > 60 > 124 > 8 > 72 > 40 > 104 > 24 > 88 > 56 > 120 > 16 > 80 > 48 > 112 > 32 > 96 > 64 >
128.
—
—
255
00FFh
Turns on for two GSCLK periods in the first to 127th display segments and turns on one GSCLK period in the
128th display segment
256
0100h
Turns on for two GSCLK periods in all display segments (first to 128th)
257
0101h
Turns on for three GSCLK periods in the first display segments and for two GSCLK periods in all other display
segments
The number of display segments where OUTn is turned on for one GSCLK is incremented by increasing GS data
in the following order:
1 > 65 > 33 > 97 > 17 > 81 > 49 > 113 > 9 > 73 > 41 > 105 > 25 > 89 > 57 > 121 > 5 > 69 > 37 > 101 > 21 > 85 >
53 > 117 > 13 > 77 > 45 > 109 > 29 > 93 > 61 > 125 > 3 > 67 > 35 > 99 > 19 > 83 > 51 > 115 > 11 > 75 > 43 >
107 > 27 > 91 > 59 > 123 > 7 > 71 > 39 > 103 > 23 > 87 > 55 > 119 > 15 > 79 > 47 > 111 > 31 > 95 > 63 > 127 >
2 > 66 > 34 > 98 > 18 > 82 > 50 > 114 > 10 > 74 > 42 > 106 > 26 > 90 > 58 > 122 > 6 > 70 > 38 > 102 > 22 > 86
> 54 > 118 > 14 > 78 > 46 > 110 > 30 > 94 > 62 > 126 > 4 > 68 > 36 > 100 > 20 > 84 > 52 > 116 > 12 > 76 > 44
> 108 > 28 > 92 > 60 > 124 > 8 > 72 > 40 > 104 > 24 > 88 > 56 > 120 > 16 > 80 > 48 > 112 > 32 > 96 > 64 >
128.
—
—
65479
FEFFh
Turns on for 511 GSCLK periods in the first to 127th display segments, but only turns on for 510 GSCLK periods
in the 128th display segment
65480
FF00h
Turns on for 511 GSCLK periods in all display segments (first to 128th)
65481
FF01h
Turns on for 512 GSCLK periods in the first display period and for 511 GSCLK periods in the second to 128th
display segments
—
—
65534
FFFEh
Turns on for 512 GSCLK periods in the first to 63rd and 65th to 127th display segments; also turns on for 511
GSCLK periods in the 64th and 128th display segments
65535
FFFFh
Turns on for 512 GSCLK periods in the first to 127th display segments but only turns on for 511 GSCLK periods
in the 128th display segment
—
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LAT
1
2
3
511
513
512
514
16382 16385
32766
32769
49150
49153
16383
16386
32767
32770
49151
49154
16384
16387
32768
32771
49152
49155
65536
65023
65026
65534
65024
65535
65025
GSCLK
(Voltage Level = H)
OUTXn
ON
(GS Data = 0000h)
OUTXn
33rd
Period
64th
Period
65th
Period
96th
Period
97th
Period
127th
Period
128th
Period
1st
Period
(Voltage Level = L)
T = GSCLK x 1d
T = GSCLK x 1d
When Auto
Display Repeat
is On
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
OFF
ON
(GS Data = 0003h)
OUTXn
32nd
Period
OFF
ON
(GS Data = 0002h)
OUTXn
2nd
Period
OFF
ON
(GS Data = 0001h)
OUTXn
1st Period
OFF
T = GSCLK x 1d
OFF
ON
(GS Data = 0004h)
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 2d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 2d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 512d in 2nd to 63rd and 65rd to 127th Periods, T = GSCLK x 511d in 64th Period
T = GSCLK x 511d
T = GSCLK x 1d
OUTXn
OFF
ON
(GS Data = 0041h)
OUTXn
OFF
ON
(GS Data = 0080h)
OUTXn
OFF
ON
(GS Data = 0081h)
OUTXn
T = GSCLK x 511d
T = GSCLK x 511d
T = GSCLK x 511d in 2nd to 128th Periods
T = GSCLK x 512d
T = GSCLK x 511d in 2nd to 128th Periods
OFF
(GS Data = FF80h)
OUTXn
T = GSCLK x 2d
OFF
ON
(GS Data = 0082h)
OUTXn
T = GSCLK x 1d
OFF
ON
(GS Data = FF81h)
T = GSCLK x 512d
OUTXn
OFF
ON
(GS Data = FFFEh)
OUTXn
T = GSCLK x 512d
T = GSCLK x 512d in 2nd to 127th Periods
T = GSCLK x 511d
OFF
ON
(GS Data = FFFFh)
Figure 28. ES PWM Operation
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8.4.4.3 Auto Display Repeat Function
This function can repeat the total display period as long as GSCLK is present, as shown in Figure 29. This
function is switched on or off by the content of the DSPRPT bit in the control data latch.
When the DSPRPT bit is 1, auto display repeat is enabled and the entire display period repeats. When the
DSPRPT bit is 0, auto display repeat is disabled and the entire display period only executes one time after a LAT
signal rising edge is input for GS data writes when the display timing reset is enabled.
LAT
1
4
2
5
3
65534
1
65535
2
65533
65536
4
5
3
65534
1
65535
2
65533
65536
4
7
5
3
1
8
6
2
9
65534
1
65535
2
65536
GSCLK
1 (Auto Display
Repeat enabled)
DSPRPT= 0
(Auto Display
Repeat disabled)
TMGRST bit
in Control Data
Latch (Internal)
TMGRST bit=1
DSPRPT bit
in Control Data
Latch (Internal)
1st entire display period
2nd entire display period
Display period is repeated
by Auto DisplayRepeat
function.
OFF
OUTXn
3rd entire display period
1st entire
display period
OUTXn is forced off
when LAT rising edge is
input for GS data writing
with timing reset mode
enable (TMGRST=1).
ON
OUTXn is not turned on again
because Display Auto Repeat
is disable (DSPRPT=0).
(GSDATA=FFFFh)
Figure 29. Auto Display Repeat Function
34
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8.4.4.4 Display Timing Reset Function
The display timing reset function allows initializing the display timing with a LAT rising edge. This function can be
switched on or off with the TMGRST bit in the control data latch. When the TMGRST bit is 1, the GS counter is
reset to 0 and all outputs are forced off at the LAT rising edge for a GS data write. Furthermore, the 768-bit GS
data latch is updated with the data from the common shift register and the 336-bit DC data latch is updated with
the DC data in the 371-bit control data latch. When the TMGRST bit is 0, the GS counter is not reset and the
outputs are not forced off, even if a LAT rising edge is input. A timing diagram for this function is shown in
Figure 30.
Control Data Write (MSB of the Common Shift Register = 1)
SIN
764
DCR0
4A
DCR0
3A
DCR0
2A
DCR0
1A
765
766
767
768
DCR0
0A
Low
1
769
Grayscale Data Write (MSB of the Common Shift Register = 0)
Grayscale Data Write
GSB15 GSB15
14A
15A
Low
2
3
GSR0
3A
GSR0
2A
766
767
GSR0
1A
768
GSR0
0A
769
GSB15 GSB15 GSB15
15B
14B
13B
1
2
3
4
SCLK
LAT
GSCLK
DSPRPT Bit in Control Data
(Internal)
DSPRPT Bit = 1
TMGRST Bit in Control Data
(Internal)
TMGRST Bit = 1
RFRESH Bit in Control Data
(Internal)
RFRESH Bit = 0
Common Shift Register
(Internal)
SID are loaded at the LAT falling edge.
GS Counter Data
(Internal)
Internal LAT Enable
(Internal)
GS counter data are incremented
at each GSCLK rising edge.
0
GS counter data are incremented at each
GSCLK rising edge.
GS counter is reset to zero when LAT for
GS data writes is input with TMGRST = 1.
Always Enabled
Internal LAT Signal
(Internal)
GS Data Latch
(Internal)
Control Data Latch
(Internal)
Old Grayscale Data
New Control Data
Old Control Data
DC Data Latch
(Internal)
OUTXn
(1)
New Grayscale Data
New DC Data
Old DC Data
OUTXn are forced off when LAT for GS data
writes is input with the TMGRST bit = 1.
OFF
OUTXn are controlled by old GS, DC data.
ON
SOUT
High
DCR0
2A
DCR0
1A
DCR0
0A
OUTXn are controlled by new GS, DC data.
Low
LOD
B15A
LOD
G15A
LOD
R15A
LOD
B14A
Figure 30. Display Timing Reset Function (DSPRPT = 1, TMGRST = 1, and RFRESH = 0)
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8.4.4.5 Auto Data Refresh Function
This function delays updating the grayscale (GS) and dot correction (DC) data until the end of one entire display
period. If both DC data and GS data are written by the end of an entire display period, the input DC data are held
in the control data latch and the GS data are held in the common shift register. Both DC and GS data are copied
to the 336-bit DC data latch and 768-bit GS data latch at the end of an entire display period. The data latches
are used for the next display period. GS data are directly copied from the common shift register to the GS data
latch. Therefore, GS data must be written after the DC data are written. Furthermore, the GS data in the common
shift resistor must not be changed until all data are copied to the GS data latch. Figure 31 and Figure 32 show
timing diagrams for this function.
Control Data Write (MSB of the Common Shift Register = 1)
SIN
764
DCR0
4A
DCR0
3A
DCR0
2A
DCR0
1A
765
766
767
768
DCR0
0A
GSB15 GSB15
14A
15A
L
1
769
Grayscale Data Write
Grayscale Data Write (MSB of the Common Shift Register = 0)
2
3
GSR0
3A
GSR0
2A
766
767
GSR0
1A
768
L
GSR0
0A
GSB15
15B
1
769
2
SCLK
65535th GSCLK
65536th GSCLK
LAT
1
2
3
4
5
6
7
8
GSCLK
DSPRPT Bit
in Control Data
(Internal)
DSPRPT bit=1
TMGRST Bit
in Control Data
(Internal)
TMGRST bit=0
RFRESH Bit
in Control Data
(Internal)
RFRESH bit=1
CommonShift
Register
(Internal)
GS Counter
Data (Internal)
SID are loaded at 1st
GSCLK input.
GS counter data is incremented
at each GSCLK rising edge.
0
The internal LAT enable is set
to high level when LAT is input
for GS data writing.
Internal LAT
Enable
(Internal)
GS Data
Latch
(Internal)
The internal LAT enable
is set to low level when
1st GSCLK is input.
Old Grayscale Data
New Grayscale Data
Old DC Data
New DC Data
New Control Data
Old Control Data
DC Data
Latch
(Internal)
OUTn
at each GSCLK rising edge.
The internal LAT signal is generated
at 65536th GSCLK when Internal LAT
enable is high level only.
Internal
LAT Signal
(Internal)
Control Data
Latch
(Internal)
G S counter data is incremented
OFF
OUTn are controlled
by new GS/DC data.
OUTn are controlled by old GS/DC data.
ON
SOUT
H
DCR0
2A
DCR0
1A
DCR0
0A
L
LOD
B15A
LOD
G15A
Figure 31. Auto Data Refresh Function 1 (DSPRPT = 1, TMGRST = 0, and RFRESH = 1)
36
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Control Data Write (MSB of the Common Shi ft register = 1
SIN
764
DCR0
4A
DCR0
3A
DCR0
2A
DCR0
1A
765
766
767
768
Grayscale Data Write
Grayscale Data Write (MSB of the Common Shift Register = 0)
DCR0
0A
GSB15 GSB15
14A
15A
L
1
769
2
3
GSR0
3A
GSR0
2A
766
767
GSR0
1A
768
L
GSR0
0A
769
GSB15 GSB15 GSB15
15B
14B
13B
1
2
3
4
SCLK
LAT
GSCLK
DSPRPT bit
in Control Data
(Internal)
DSPRPT bit =1
TMGRST bit
in Control Data
(Internal)
TMGRST bit =0
RFRESH bit
in Control Data
(Internal)
RFRESH bit =0
CommonShift
Register
(Internal)
GS Counter
Data (Internal)
Internal LAT
Enable
(Internal)
SID are loaded at the LAT falling edge.
GS counter data is incremented
at each GSCLK rising edge.
Always enable
Internal
LAT Signal
(Internal)
GS Data
Latch
(Internal)
Control Data
Latch
(Internal)
New Grayscale Data
Old DC Data
New DC Data
New Control Data
Old Control Data
DC Data
Latch
(Internal)
OUTn
Old Grayscale Data
OFF
OUTn are controlled
by new GS/DC data.
OUTn are controlled
by old GS/DC data.
ON
SOUT
H
DCR0
2A
DCR0
1A
DCR0
0A
L
LOD
B15A
LOD
G15A
LOD
R15A
LOD
B14A
Figure 32. Auto Data Refresh Function 2 (DSPRPT = 1, TMGRST = 0, and RFRESH = 0)
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9 Applications and Implementation
9.1 Application Information
The device is a 48-channel, constant sink current, LED driver. This device is typically connected in series to drive
many LED lamps with only a few controller ports. Output current control data and PWM control data can be
written from the SIN input terminal. The PWM timing reference clock can be supplied from the GSCLK input
terminal. Also, the LED open and short error flag can be read out from the SOUT output terminal. Furthermore,
the device maximum GSCLK clock frequency is 33 MHz and can reduce flickering discernable by the human
eye.
9.2 Typical Application
9.2.1 Daisy-Chain Application
In this application, the device VCC and LED lamp anode voltages are supplied from different power supplies.
VLED
+
x48
x48
¼¼
¼
OUTR0
DATA
¼
SCLK
VCC
TLC5955
IC1
LAT
GSCLK
¼
OUTB15
SIN
SOUT
SCLK
LAT
OUTR0
OUTB15
SIN
¼
SOUT
VCC
SCLK
LAT
VCC
TLC5955
ICn
VCC
GSCLK
GSCLK
Controller
GND
GND
GND
GND
3
Error Read
Figure 33. Multiple Daisy-Chained TLC5955 Devices
9.2.1.1 Design Requirements
For this design example, use the following as the input parameters.
Table 13. Design Parameters
DESIGN PARAMETER
38
EXAMPLE VALUE
VCC input voltage range
3.0 V to 5.5 V
LED lamp (VLED) input voltage range
Maximum LED forward voltage (VF) + 0.3 V (knee voltage)
SIN, SCLK, LAT, and GSCLK voltage range
Low level = GND, High level = VCC
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9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Step-by-Step Design Procedure
To begin the design process, a few parameters must be decided upon. The designer needs to know the
following:
• Maximum output constant-current value for each color LED ramp.
• Maximum LED forward voltage (VF).
• Current ratio of red, green, and blue LED lamps for the best white balance.
• Are the auto display repeat function, display timing reset function, or auto data refresh function used?
• Which PWM control method is used: ES-PWM or conventional PWM?
• Is the LED short detect (LSD) function used? If so, which detection level (70% VCC or 90% VCC) is used?
9.2.1.2.2 Maximum Current (MC) Data
There are a total of nine bits of MC data for the red, green, and blue LED ramp. Select the MC data to be greater
than each LED ramp current and write the data with other control data.
9.2.1.2.3 Global Brightness Control (BC) Data
There are a total of three sets of 7-bit BC data for the red, green, and blue LED ramp. Select the BC data for the
best white balance of the red, green, and blue LED ramp and write the data with other control data.
9.2.1.2.4 Dot Correction (DC) Data
There are a total of 48 sets of 7-bit DC data for each current adjustment. Select the DC data for the best
uniformity of each color LED ramp and write the data with other control data.
9.2.1.2.5 Grayscale (GS) Data
There are a total of 48 sets of 16-bit GS data for the PWM control of each output. Select the GS data of the LED
ramp intensity and color control and write the data with other GS data.
9.2.1.2.6 Other Control Data
There are five bits control data to set the function mode for the auto display repeat, display timing reset, auto
data refresh, ES-PWM, and LSD functions explained in the Device Functional Modes section. Write the 5-bit
control data for the appropriate operation of the display system with MC, BC, and DC data as the control data.
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9.2.1.3 Application Curves
One LED connected to each output.
Ch1: VCC (2 V/div)
Ch1: VCC (2 V/div)
Ch2: VLED (2 V/div)
Ch2: VLED (2 V/div)
Ch3: VOUTB0 (1 V/div, Blue LED Connected)
Ch3: VOUTB0 (1 V/div, Blue LED Connected)
Ch4: LAT (5 V/div)
Ch4: LAT (5 V/div)
Time (400 s/div)
Time (40 ns/div)
MCX = 4
BCX = DCXn = 7Fh
VLED = 4.2 V
VCC = 3.3 V
TMGRST, RFRESH, ESPWM, LSDVLT = 0
GSCLK = 33 MHz
DSPRPT = 1
Figure 34. Output Waveform Immediately After First GS
Data Latch Input (GSXn = 0001h)
40
MCX = 4
BCX = DCXn = 7Fh
VLED = 4.2 V
VCC = 3.3 V
TMGRST, RFRESH, ESPWM, LSDVLT = 0
GSCLK = 33 MHz
DSPRPT = 1
Figure 35. Output Waveform Immediately After First GS
Data Latch Input (GSXn = 7FFFh)
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10 Power Supply Recommendations
The VCC power-supply voltage should be well regulated. An electrolytic capacitor must be used to reduce the
voltage ripple to less than 5% of the input voltage. Furthermore, the VLED voltage should be set to the voltage
calculated by Equation 3:
VLED ≥ LED VF × Number of LED Lamps Connected in Series + 0.3 V (20 mA for Constant-Current Example)
where:
•
VF = Forward voltage
(3)
Because the total current of the constant-current output is large, some electrolytic capacitors must be used to
prevent the OUTXn terminal voltage from dropping lower than the calculated voltage from Equation 3.
11 Layout
11.1 Layout Guidelines
1. Place the decoupling capacitor near the VCC and GND terminals.
2. Route the GND pattern as widely as possible for large GND currents. Maximum GND current is
approximately 1.53 A.
3. Routing between the LED cathode side and the device OUTXn should be as short and straight as possible to
reduce wire inductance.
4. The PowerPAD must be connected to the GND layer because the pad is not internally connected to GND
and should be connected to a heat sink layer to reduce device temperature.
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11.2 Layout Example
Via
Top-Side PCB Pattern
Bottom-Side PCB Pattern
VLED
LAT
SIN
SCLK
SIN
GND
SCLK
GSCLK
LAT
VCC
OUTB4
OUTB8
OUTR4
OUTR8
OUTG4
OUTG8
OUTB0
OUTB12
OUTR0
OUTR12
OUTG0
OUTG12
OUTB5
Power
OUTR9
OUTG5
OUTG9
Via to Heatsink Layer
OUTR13
OUTG1
OUTG13
OUTB2
OUTB14
OUTR2
OUTR14
OUTG2
OUTG14
OUTB2
OUTB10
OUTR6
OUTR10
OUTG6
OUTG10
OUTB6
OUTB15
OUTR3
OUTR15
OUTG3
OUTG15
OUTB7
OUTB11
OUTR7
OUTR11
OUTG7
OUTG11
SOUT
GND
To Next
SCLK
VLED
To Next
GSCLK
To Next
VLED
OUTB13
OUTR1
To Next To Next
LAT
SIN
GSCLK
OUTB9
OUTR5
OUTB1
To Next
VLED
GND
VCC
Figure 36. Layout Example
42
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
For the LED driver solution, go to www.ti.com/solution/lighting_signage.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• PowerPAD™ Thermally Enhanced Package Application Report, SLMA002
12.3 Trademarks
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLC5955DCA
ACTIVE
HTSSOP
DCA
56
35
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TLC5955
TLC5955DCAR
ACTIVE
HTSSOP
DCA
56
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TLC5955
TLC5955RTQR
ACTIVE
QFN
RTQ
56
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TLC5955
TLC5955RTQT
ACTIVE
QFN
RTQ
56
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TLC5955
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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