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TLC5958
SLVSCE7A – MAY 2014 – REVISED SEPTEMBER 2014
TLC5958 48-Channel, 16-Bit ES-PWM LED Driver with Pre-Charge FET, LED Open
Detection and Display Data Memory Support 32-Multiplexing
1 Features
2 Applications
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48 Channels Constant Current Sink Output
Sink Current Capability with Max BC/CC data:
– 25mA at 5VCC
– 20mA at 3.3VCC
Global Brightness Control (BC) : 3-Bit (8 Step)
Color Brightness Control (CC) for Each Color
Group:
9-Bit (512 Step), Three Groups
Grayscale(GS) Control with Multiplexed Enhanced
Spectrum(ES) PWM: 16bit
48K bit Grayscale Data Memory Support 32multiplexing
LED Power Supply Voltage Up To 10V
Vcc = 3.0V to 5.5V
Constant Current Accuracy
– Channel to Channel = ±1%(Typ), ±3%(Max)
– Device to Device = ±1%(Typ), ±2%(Max)
Data Transfer Rate: 25MHz
Gray Scale Clock: 33MHz
LED Open Detection (LOD)
Thermal Shut Down (TSD)
IREF Resistor Short Protection (ISP)
Power-Save Mode (PSM) with high speed
recovery
Delay Switching to Prevent Inrush Current
Pre-charge FET to Avoid Ghosting Phenomenon
Operating Temperature : –40°C to +85°C
LED Video Displays with Multiplexing System
LED Signboards with Multiplexing system
High Refresh Rate & High density LED Panel
3 Description
The TLC5958 is a 48 channels constant-current sink
driver for multiplexing system with 1 to 32 duty ratio.
Each channel has an individually-adjustable, 65536step, pulse width modulation (PWM) grayscale (GS).
48K bit display memory is implemented to increase
the visual refresh rate and to decrease the GS data
writing frequency.
The output channels are grouped into three groups,
each group has 16 channels. Each group has a 512step color brightness control (CC) function. The
maximum current value of all 48 channels can be set
by 8-step global brightness control (BC) function. CC
and BC can be used to adjust the brightness
deviation between LED drivers. GS, CC, and BC data
are accessible via a serial interface port.
Send request via email for Application Note: Build
High Density, High Refresh Rate, Multiplexing LED
Panel with TLC5958.
Device Information(1)
PART NUMBER
TLC5958
PACKAGE
VQFN (56)
BODY SIZE (NOM)
8.00 mm × 8.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Typical Application Circuit (Multiple Daisy-Chained TLC5958s)
VLED
SW
COM n
COM n
VLED
SW
COM 1
COM 1
VLED
SW
COM 0
COMSEL 0
COMSEL 1
COMSEL n
COM 0
DATA
SCLK
Controller
LAT
GCLK
FLAGS
READ
X 48
X 48
OUTR0
OUTB15
SIN
OUTR0
VCC
SCLK
IC1
LAT
OUTB15
SIN
SOUT
TLC5958
SOUT
TLC5958
SCLK
ICn
LAT
VCC
GCLK
VCC
VCC
GCLK
Thermal
Pad
IREF
Thermal
Pad
IREF
IREFGND
IREFGND
GND
GND
GND
GND
3
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLC5958
SLVSCE7A – MAY 2014 – REVISED SEPTEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Typical Application Circuit (Multiple DaisyChained TLC5958s)................................................
Revision History.....................................................
Description (Continued) ........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
2
3
3
5
8.1
8.2
8.3
8.4
8.5
8.6
5
5
5
6
7
9
Absolute Maximum Ratings ......................................
Handling Ratings ......................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
1
1
1
Parameter Measurement Information ................ 11
9.1 Pin Equivalent Input and Output Schematic
Diagrams.................................................................. 11
9.2 Timing Diagrams ..................................................... 13
10 Detailed Description ........................................... 14
10.1 Overview ............................................................... 14
10.2 Functional Block Diagram ..................................... 15
10.3 Device Functional Modes...................................... 16
11 Application and Implementation........................ 20
12 Power Supply Recommendations ..................... 20
13 Layout................................................................... 20
13.1 Layout Guidelines ................................................. 20
13.2 Layout Example .................................................... 20
14 Device and Documentation Support ................. 21
14.1 Trademarks ........................................................... 21
14.2 Electrostatic Discharge Caution ............................ 21
14.3 Glossary ................................................................ 21
15 Mechanical, Packaging, and Orderable
Information ........................................................... 21
5 Revision History
Changes from Original (May 2014) to Revision A
•
2
Page
Deleted Product Preview banner - set to Production Data; global change ........................................................................... 1
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TLC5958
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SLVSCE7A – MAY 2014 – REVISED SEPTEMBER 2014
6 Description (Continued)
The TLC5958 has one error flag: LED open detection (LOD), which can be read via a serial interface port. The
TLC5958 also has a power-save mode that sets the total current consumption to 0.8mA (typ) when all outputs
are off.
7 Pin Configuration and Functions
56 Pin
55 54 53 52 51 50 49
48 47
OUTR10
VCC
OUTB10
OUTG10
OUTG11
OUTR11
OUTR12
OUTB11
OUTB12
OUTG12
OUTG13
OUTR13
IREFGND
56
1
OUTB13
RTQ
(TOP VIEW)
46 45 44 43
42
SOUT
OUTR14
2
41
OUTB9
OUTG14
3
40
OUTG9
OUTB14
4
39
OUTR9
OUTR15
5
38
OUTB8
OUTG15
6
37
OUTG8
OUTB15
7
36
OUTR8
OUTR0
8
35
OUTB7
OUTG0
9
34
OUTG7
OUTB0
10
33
OUTR7
OUTR1
11
32
OUTB6
OUTG1
12
31
OUTG6
OUTB1
13
30
OUTR6
OUTR2
14
29
GCLK
LAT
27 28
SCLK
SIN
OUTB5
OUTR5
23 24 25 26
OUTG5
OUTB4
OUTG4
OUTR4
OUTB3
20 21 22
OUTG3
17 18 19
OUTB2
15 16
OUTR3
Thermal
PAD
(Solder side)
(GND terminal)
OUTG2
IREF
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
GCLK
29
I
Grayscale(GS) pulse width modulation (PWM) reference clock control for OUTXn.
Each GCLK rising edge increase the GS counter by1 for PWM control.
GND
ThermalPad
–
Power ground. The thermal pad must be soldered to GND on PCB.
IREF
1
–
Maximum constant-current value setting. The OUTR0 to OUTB15 maximum constant output
current are set to the desired values by connecting an external resistor between IREF and
IREFGND. See equation 1 for more detail. The external resistor should be placed close to
the device.
IREFGND
56
–
Analog ground. Dedicated ground pin for the external IREF resistor. This pin should be
connected to analog ground trace which is connected to power ground near the common
GND point of board.
LAT
27
I
The LAT falling edge latches the data from the common shift register into the GS data
memory or Function control(FC) register FC1 or FC2.
8, 11, 14, 17,
20, 23, 30,
33, 36, 39,
44, 47, 50,
53 ,2, 5
O
Constant current output for RED LED. Multiple outputs can be tied together to increase the
constant current capability. Different voltages can be applied to each output. These outputs
are turned on-off by GCLK signal and the data in GS data memory.
OUTR0-R15
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Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
OUTG0-G15
9, 12, 15, 18,
21, 24, 31,
34, 37, 40,
45, 48, 51,
54, 3, 6
O
Constant current output for GREEN LED. Multiple outputs can be tied together to increase
the constant current capability. Different voltages can be applied to each output. These
outputs are turned on-off by GCLK signal and the data in GS data memory.
OUTB0-B15
10, 13, 16,
19, 22, 25,
32, 35, 38,
41, 46, 49,
52, 55, 4, 7
O
Constant current output for BLUE LED. Multiple outputs can be tied together to increase the
constant current capability. Different voltages can be applied to each output. These outputs
are turned on-off by GCLK signal and the data in GS data memory.
28
I
Serial data shift clock. Data present on SIN are shifted to the 48-bit common shift register
LSB with the SCLK rising edge. Data in the shift register are shifted towards the MSB at
each SCLK rising edge. The common shift register MSB appears on SOUT.
SCLK
SIN
26
I
Serial data input of the 48-bit common shift register. When SIN is high level, the LSB is set
to '1' for only one SCLK input rising edge. If two SCLK rising edges are input while SIN is
high, then the 48-bit shift register LSB and LSB+1 are set to '1'. When SIN is low, the LSB is
set to '0' at the SCLK input rising edge.
SOUT
42
O
Serial data output of the 48-bit common shift register. SOUT is connected to the MSB of the
register.
VCC
43
–
Power-supply voltage.
4
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SLVSCE7A – MAY 2014 – REVISED SEPTEMBER 2014
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
PARAMETER
(2)
VCC
IOUT
VIN
(2)
VOUT
(2)
TJ(MAX)
(1)
(2)
MIN
MAX
UNIT
0.3
6.0
V
30
mA
SIN, SCLK, LAT, GCLK, IREF
–0.3
VCC+0.3
V
SOUT
–0.3
VCC+0.3
OUTx0 to OUTx15, x=R, G, B
–0.3
11
Supply voltage
VCC
Output current (dc)
OUTx0 to OUTx15, x=R, G, B
Input voltage
Output voltage
Operating junction temperature
V
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to device ground terminal.
8.2 Handling Ratings
Tstg
V(ESD)
(1)
(2)
(3)
MIN
MAX
UNIT
–55
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (2)
0
4000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (3)
0
1000
Storage temperature range
(1)
Electrostatic
discharge
V
Electrostatic discharge (ESD) measures device sensitivity and immunity to damage caused by assembly line electrostatic discharges
into the device.
Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows
safe manufacturing with a standard ESD control process.
Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
At TA = –40°C to +85°C, unless otherwise noted
MIN
NOM
MAX
UNIT
DC CHARACTERISTICS, VCC=3V to 5.5V
VCC
Supply voltage
VO
Voltage applied to output
OUTx0 to OUTx15, x=R, G, B
VIH
High level input voltage
SIN,SCLK,LAT,GCLK
VIL
Low level input voltage
SIN,SCLK,LAT,GCLK
IOH
High level output current
SOUT
-2
mA
IOL
Low level output current
SOUT
2
mA
IOLC
Constant output sink current
3
5.5
V
10
V
0.7×VCC
VCC
V
GND
0.3×VCC
OUTx0 to OUTx15, x=R, G, B,
3V ≤ VCC ≤ 3.6V
20
OUTx0 to OUTx15, x=R, G, B,
4V < VCC ≤ 5.5V
25
V
mA
TA
Operating free air temperature
–40
85
°C
TJ
Operation junction temperature
-40
125
°C
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Recommended Operating Conditions (continued)
At TA = –40°C to +85°C, unless otherwise noted
MIN
AC CHARACTERISTICS, VCC=3V to 5.5V
NOM
MAX
UNIT
(1)
FCLK(SCLK)
Data shift clock frequency
SCLK
25
MHz
FCLK(GCLK)
Grayscale control clock frequency
GCLK
33
MHz
tWH0
SCLK
10
tWL0
SCLK
10
GCLK
15
tWL1
GCLK
10
tSU0
SIN - SCLK↑
2
tSU1
LAT↑ - SCLK↑
3
LAT↓ - SCLK↑
5
Pulse duration
tWH1
tSU2
LAT↓ - SCLK↑, for READSID, READFC1,
and READFC2
Setup time
ns
ns
50
tSU3
LAT↓ (Vsync command) - GCLK↑
tSU4
The last LAT↓ for no all ‘0’ data latching to
resume normal mode – GCLK↑,
PSAVE_ENA bit = ‘1b’
50
µS
tSU5
The last GCLK↑ - the 1st GCLK↑ of next line
20
ns
tH0
SCLK↑ - SIN
tH1
Hold time
tH2
(1)
2500
2
SCLK↑ - LAT↑
2
SCLK↑ - LAT↓
13
ns
Specified by design
8.4 Thermal Information
TLC5958
THERMAL METRIC
(1)
RTQ
UNIT
56 PINS
RθJA
Junction-to-ambient thermal resistance
27.4
RθJC(top)
Junction-to-case (top) thermal resistance
13.6
RθJB
Junction-to-board thermal resistance
5.5
ψJT
Junction-to-top characterization parameter
0.2
ψJB
Junction-to-board characterization parameter
5.5
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.8
(1)
6
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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8.5 Electrical Characteristics
At VCC= 3.0V to 5.5V and TA= –40°C to 85°C, VLED=5.0V, Typical values are at VCC= 3.3V, TA= 25°C (unless otherwise
noted).
PARAMETER
VOH
Output voltage
VOL
TEST CONDITIONS
High
IOH = -2mA at SOUT
Low
IOL= 2 mA at SOUT
VLOD0
VLOD1
VLOD2
MIN
LODVTH = 00b
LED open detection threshold
VLOD3
TYP
VCC–0.4
MAX
UNIT
VCC
V
0.4
V
0.06
0.11
0.16
LODVTH = 01b
0.2
0.25
0.3
LODVTH = 10b
0.34
0.39
0.44
V
LODVTH = 11b
0.44
0.49
0.54
VIREF
Reference voltage output
RIREF = 6.2 kΩ (1mA target), BC=0h, CCR/G/B=81h
1.19
1.209
1.228
V
IIN
Input current (SIN, SCLK)
VIN = VCC or GND
1
µA
–1
ICC0
SIN/SCLK/LAT/GSCLK=GND, GSn=0000h, BC=0h,
CCR/G/B=81h, VOUTn = Vcc, RIREF=OPEN
5.5
7
ICC1
SIN/SCLK/LAT/GSCK=GND, GSn=0000h, BC=4h,
CCR/G/B=137h,VOUTn=Vcc, RIREF=7.5kΩ (Io=10mA target)
7
9
ICC2
SIN/SCLK/LAT=GND, GCLK=33MHz, TSU5 = 200nS,
8+8 mode, GSn=FFFFh, BC=4h, CCR/G/B=137h,
VOUTn=Vcc-1V when channel on, VOUTn=Vcc
when channel off. RIREF=7.5kΩ (Io=10mA target)
25
31
SIN/SCLK/LAT=GND, GCLK=33MHz, TSU5=200nS,
8+8 mode, GSn=FFFFh, BC=7h, CCR/G/B=1F5h,
VOUTn=Vcc-2.5V when channel on, VOUTn=Vcc
when channel off. RIREF=7.5kΩ (Io=25mA target)
28
ICC3
ICC4
In power save mode
0.9
1.5
Constant current error
(OUTx0-15, x=R/G/B)
Channel-tochannel (1)
±1%
±3%
ΔIOLC0
All OUTn=on, BC=0h, CCR/G/B=81h, VOUTn=VOUTfix=1V,
RIREF=6.2kΩ(1mA target), TA = +25°C, at same color
grouped output of OUTR0-15, OUTG0-15 and OUTB0-15
Constant current error
(OUTx0-15, x=R/G/B)
Device-todevice (2)
All OUTn=on, BC=0h, CCR/G/B=81h, VOUTn=VOUTfix=1V,
RIREF=6.2kΩ(1mA target), TA =+25°C, at same color
grouped output of OUTR0-15, OUTG0-15 and OUTB0-15
±1%
±2%
ΔIOLC1
ΔIOLC2
Line regulation (3)
VCC=3.0 to 5.5V, All OUTn=on, BC=0h, CCR/G/B=81h,
VOUTn=VOUTfix=1V, RIREF=6.2kΩ (1mA target)
±1
±1.5
%/V
ΔIOLC3
Load regulation (4)
All OUTn=on, BC=0h, CCR/G/B=81h, VOUTn=1 to 3V,
VOUTfix=1V, RIREF=6.2kΩ (1mA target)
±1
±1.5
%/V
(1)
Supply current (Vcc)
mA
33
The deviation of each outputs in same color group (OUTR0~15 or OUTG0~15 or OUTB0~15) from the average of same color group
constant current. The deviation is calculated by the formula. (X=R or G or B, n=0~15)
é
ù
ê
ú
IOUTXn
D (% ) = ê
- 1ú ´ 100
(IOUTX0
IOUTX1
IOUTX14
IOUTX15)
+
+
¼
+
+
ê
ú
16
ëê
ûú
spacer
The deviation of the average of constant-current in each color group from the ideal constant-current value. (X = R or G or B) :
é (IOUTX0 + IOUTX1 + ¼ + IOUTX15)
ù
- (Ideal Output Current) ú
ê
16
D (% ) = ê
ú ´ 100
Ideal Output Current
ê
ú
êë
úû
Ideal current is calculated by the following equation:
é VIREF ù
´
=
I deal Output (mA ) = Gain ´ ê
CCR
or
CCG,
CCB
/511d,
V
IREF
1.209V
(
)
(Typ ),
ú
êë RIREF (W) úû
Refer to Table 1 for the Gain at chosen BC.
spacer
(3) Line regulation is calculated by the following equation. (X=R or G or B, n=0~15):
é (IOUTXn at VCC = 5.5V) – (IOUTXn at VCC = 3.0V )ù
100
D (%V ) = ê
ú´
(IOUTXn at VCC = 3.0V )
êë
úû 5.5V – 3V
(2)
(4)
spacer
Load regulation is calculated by the following equation. (X=R or G or B, n=0~15):
é (IOUTXn at VOUTXn = 3V) – (IOUTXn at VOUTXn = 1V )ù
100
D (%V ) = ê
ú´
(IOUTXn at VOUTXn = 1V )
êë
úû 3V – 1V
spacer
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Electrical Characteristics (continued)
At VCC= 3.0V to 5.5V and TA= –40°C to 85°C, VLED=5.0V, Typical values are at VCC= 3.3V, TA= 25°C (unless otherwise
noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±1%
±3%
±1%
±2%
UNIT
ΔIOLC4
Constant current error
(OUTx0-15, x=R/G/B)
Channel-tochannel(1)
All OUTn=on, BC=7h, CCR/G/B=1F7h, VOUTn=VOUTfix=1V,
RIREF=7.5kΩ(25mA target), TA =+25°C, at same color
grouped output of OUTR0-15, OUTG0-15 & OUTB0-15
ΔIOLC5
Constant current error
(OUTx0-15, x=R/G/B)
Device-todevice(2)
All OUTn=on, BC=7h, CCR/G/B=1F7h, VOUTn=VOUTfix=1V,
RIREF=7.5kΩ(25mA target), TA = +25°C, at same color
grouped output of OUTR0-15, OUTG0-15 and OUTB0-15
ΔIOLC6
Line regulation (3)
VCC=3.0 to 5.5V, All OUTn=on, BC=7h, CCR/G/B=1F7h,
VOUTn=VOUTfix=1V, RIREF=7.5Kohm (25mA target)
±1
±1.5
%/V
ΔIOLC7
Load regulation(4)
All OUTn=on, BC=7h, CCR/G/B=1F7h, VOUTn=1 to 3V,
VOUTfix=1V, RIREF=7.5kΩ (25mA target)
±1
±1.5
%/V
170
180
°C
(5)
TTSD
Thermal shutdown threshold
THYS
Thermal shutdown hysterisis
VISP(in)
IREF resistor short protection threshold
VISP(out)
IREF resistor short-protection release
threshold
RPDWN
Pull-down resistor
LAT
RPUP
Pull-up resistor
GCLK
Knee voltage (OUTX 0~15), X=R/G/B
All OUTn=on, BC=4h, CCR/G/B=137h, Riref=7.5kΩ.
(Io=10mA target)
Vknee
(5)
8
(5)
160
0.135
10
°C
0.19
V
V
0.325
0.375
250
500
750
kΩ
250
500
750
kΩ
0.32
0.35
V
Specified by design.
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8.6 Typical Characteristics
VCC= 3.3V and TA= 25°C, unless otherwise noted.
35
10 mA
5 mA
20 mA
35
25 mA
1 mA
5 mA
10 mA
20 mA
30
Output Current (mA)
Output Current (mA)
30
1 mA
25
20
15
10
5
25
20
15
10
5
0
0
0.0
0.5
1.0
1.5
2.0
Output Voltage (V)
VCC = 5V
0.0
VCC = 3.3V
10
2
8
6
4
T
Ta
= ±40C
-40°C
A =
T
Ta
= 25C
25°C
A =
T
Ta
= 85C
85°C
A =
0.0
0.2
0.4
0.6
0.8
Temperature
Changing
±1
VCC=3.3
VCC = 3.3 V Min
VCC = 3.3 V Max
VCC=3.3
VCC = 5 V Min
VCC=5
VCC = 5 V Max
VCC=5
±2
0
CCR/G/B=1FFh,
BC=0
1
0
1 mA Min
1 mA Max
25 mA Min
25 mA Max
0
20
40
Ambient Temperature (C)
VCC = 5V
VOUTXn = 0.8V
60
25
30
C004
CCR/G/B=1FFh,
BC=0
5 mA
10 mA
20
20 mA
25 mA
15
10
5
0
80
0
CCR/G/B = 1FFh,
BC = 0
128
256
384
512
Color Control Data (Decimal)
C005
Figure 5. Constant-Current Error (CH-to-CH) vs Temperature
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20
1 mA
25
±20
15
Figure 4. Constant Current Error (CH-to-CH) vs Output
Current
2
±40
10
VOUTXn = 0.8V
30
±3
5
Output Current (mA)
Output Current (mA)
Constant-Current Error (%)
0
C003
3
±2
C002
CCR/G/B=1FFh,
BC=0
±3
Figure 3. Output Current vs Output Voltage
±1
2.0
1
1.0
Output Voltage (V)
VCC = 5V
1.5
Figure 2. Output Current vs Output Voltage
3
Constant-Current Error (%)
Output Current (mA)
Figure 1. Output Current vs Output Voltage
12
0
1.0
Output Voltage (V)
CCR/G/B=1FFh,
BC=0
2
0.5
C001
VCC = 5V
VOUTXn = 0.8V
C006
BC = 7
Figure 6. Color Control (CC) vs Output Current
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Typical Characteristics (continued)
VCC= 3.3V and TA= 25°C, unless otherwise noted.
30
30
5 mA
25
10 mA
20
Supply Current (mA)
Output Current (mA)
35
1 mA
20 mA
25 mA
15
10
5
25
20
15
10
5
0
1
2
3
4
5
6
7
8
Brightness Control Data (Decimal)
VCC = 5V
VOUTXn = 0.8V
0
CCR/G/B = 1FFh
VOUTXn = 0.8V
1.2
Supply Current (mA)
25
20
15
10
V
Vcc=3
CC = 3VV
V
Vcc=4
CC = 4VV
±40
±20
20
40
60
80
100
120
Ambient Temperature (C)
VOUTXn = 0.8V
CCR/G/B = 137h,
BC = 4, GCLK =
33MHz
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25
30
C008
GCLK = 33MHz,
GSXn = FFFFh
CCR/G/B=1FFh,
BC=0
1.0
0.8
0.6
0.4
VVcc=3V
CC = 3 V
VVcc=4V
CC = 4 V
VVcc=5.5V
CC = 5.5 V
0.0
±40
±20
0
20
40
60
80
Ambient Temperature (C)
C009
GSXn = FFFFh,
RIREF = 7.5kΩ
(10mA target)
Figure 9. Supply Current (Icc) vs Temperature
20
0.2
V
Vcc=5.5
CC = 5.5VV
0
15
Figure 8. Supply Current (Icc) vs Output Current
1.4
0
10
Output Current (mA)
30
5
5
C007
Figure 7. Brightness Control (BC) vs Output Current
Supply Current (mA)
V
Vcc=5
CC = 5VV
0
0
10
V
Vcc=3.3
CC = 3.3VV
VOUTXn = 0.8V
CCR/G/B = 137h,
BC=4
100
120
C010
GCLK=GND,
GSXn=0h
Figure 10. Supply Current in Power Save Mode (Icc)
vs Temperature
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9 Parameter Measurement Information
9.1 Pin Equivalent Input and Output Schematic Diagrams
VCC
VCC
INPUT
LAT
GND
GND
Figure 11. SIN, SCLK
Figure 12. LAT
VCC
VCC
GCLK
OUTPUT
GND
GND
Figure 13. GCLK
Figure 14. SOUT
(1) X=R or G or B, n=0~15
OUTXn(1)
GND
Figure 15. OUTR0/G0/B0 Through OUTR15/G15/B15
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Pin Equivalent Input and Output Schematic Diagrams (continued)
9.1.1 Test Circuits
(1) CL includes measurement probe and jig capacitance.
(2) X=R or G or B, n=0~15
(1) CL includes measurement probe and jig capacitance.
RL
VCC
VCC
VLED
VCC
OUTXn
VCC
(2)
SOUT
(1)
(1)
CL
CL
GND
GND
Figure 16. Rise Time and Fall Time Test Circuit for
OUTXn
Figure 17. Rise Time and Fall Time Test Circuit for
SOUT
(1) X=R or G or B, n=0~15
VCC
OUTR0
VCC
OUTXn
GND
(1)
VOUTXn
OUTB15
(1)
VOUTfix
Figure 18. Constant Current Test Circuit for OUTXn
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9.2 Timing Diagrams
tWH0,tWL0,tWH1,tWL1,tWH2
INPUT
50%
GND
tWH
tWL
tSU0,tSU1,tSU2,tSU3,tSU4,tH0,tH1,tH2
CLOCK
INPUT
(1)
50%
GND
tH
tSU
VCC
DATA/CONTROL
(1)
INPUT
50%
GND
tSU5
(2)
GCLK
1
2
3
255 256
257
1
2
255 256 257
TSU
(1) Input pulse rise and fall time is 1~3ns
(2) 8 + 8 mode (SEL_PWM=0)
Figure 19. Timing Diagrams
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10 Detailed Description
10.1 Overview
The TLC5958 is a 48 channels constant-current sink driver for multiplexing system with 1 to 32 duty ratio. Each
channel has an individually-adjustable, 65536-step, pulse width modulation (PWM) grayscale (GS).
48K bit display memory is implemented to increase the visual refresh rate and to decrease the GS data writing
frequency.
The TLC5958 support output current range from 1mA to 25mA, channel-to-channel accuracy is 3% max, deviceto-device accuracy is 2% max in all current range. Besides, it implement Low Gray Scale Enhancement
(LGSE™) technology to improve the display quality at low grayscale condition. These features make TLC5958
more suitable for high-density multiplexing application.
The output channels are grouped into three groups, each group has 16 channels. Each group has a 512-step
color brightness control (CC) function. The maximum current value of all 48 channels can be set by 8-step global
brightness control (BC) function. CC and BC can be used to adjust the brightness deviation between LED
drivers. GS, CC, and BC data are accessible via a serial interface port.
The TLC5958 has one error flag: LED open detection (LOD), which can be read via a serial interface port.
Besides, The TLC5958 also have Thermal shut down(TSD) and Iref resistor short protection(ISP), which make
sure a higher system reliability. The TLC5958 also has a power-save mode that sets the total current
consumption to 0.8mA (typ) when all outputs are off.
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10.2 Functional Block Diagram
OUTR0
OUTG0
OUTR1
OUTB0
OUTB15
OUTG15
VCC
VCC
LED Open Detection (LOD)
48
IREF
Reference
current
control
IREFGND
30
48CH Constant Current Sink
3bit BC and 27bit CC
Detection
Voltage
48
1
Programmable Group delay
2
48
Vsync
GS Counter
Line read counter and
Sub-period counter
ES-PWM Decoder and
timing control for 48CH
48
BANK_SEL
Line address
for read
Vsync
48kbit SRAM
BANK A
16bit x48CH
x 32Line
BANK B
16bit x48CH
x 32Line
Address
decoder and
writing control
WRTGS
48
Vsync
44bit FC1 register
LAT
WRTFC
17bit FC2 register
Command
Decoder
SCLK
43
LSB
MSB
READFC1/2
SOUT
48bit Common shift register
SIN
READSID
0
Thermal
Pad
Power
save
control
To all
analog
circuit
48
47
48bit LOD data
GND
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10.3 Device Functional Modes
After power on, all OUTXn of the TLC5958 are turned off. All the internal counters and function control registers
(FC1/FC2) are initialized. The following list is a brief summary of the sequence to operate the TLC5958, to give
users a general idea how the device works. After that, the function block related to each step is detailed in the
following sections.
1. According to required LED current, choose BC & CC code, select the current programming resistor RIREF.
2. Send WRTFC command to set FC1/2 register value if the default value need be changed.
3. Write GS data of all lines (max 32 lines) into one of the two memory BANKs.
4. Send Vsync command, the BANK with the GS data written just now will be displayed.
5. Input GCLK continuously, 257GCLK (or 513GCLK) as a segment. Between the interval of two segments,
supply voltage should be switched from one line to next line accordingly.
6. During the same period of step 5, GS data for next frame should be written into another BANK.
7. When the time of one frame ends, Vsync command should be input to swap the purpose of the two BANKs.
Repeat step 5 through 7.
10.3.1 Brightness Control (BC) Function
The TLC5958 is able to adjust the output current of all constant-current outputs simultaneously. This function is
called global brightness control (BC). The global BC for all outputs is programmed with a 3-bit word, thus all
output currents can be adjusted in 8 steps from 12.9% to 100% for a given current-programming resistor, RIREF
(See Table 2).
BC data can be set via the serial interface. When the BC data changes, the output current also changes
immediately. When the device is powered on, the BC data in the function control (FC) register FC1 is set to 4h
as the initial value.
10.3.2 Color Brightness Control (CC) Function
The TLC5958 is able to adjust the output current of each of the three color groups OUTR0-OUTR15, OUTG0OUTG15, and OUTB0-OUTB15 separately. This function is called color brightness control (CC). For each color,
it has 9-bit data latch CCR,CCG, or CCB in FC1 register . Thus, all color group output currents can be adjusted
in 512 steps from 0% to 100% of the maximum output current, IOLCMax. (See the next section for more detail
about IOLCMax). The CC data are entered via the serial interface. When the CC data change, the output current
also changes immediately.
When the IC is powered on, the CC data are set to ‘100h’. Equation 1 calculates the actual output current.
Iout(mA) = IOLCMax(mA) × ( CCR/511d or CCG/511d or CCB/511d)
(1)
Where:
IOLCMax = the maximum channel current for each channel, determined by BC data and RIREF (See Equation 2)
CCR/G/B = the color brightness control value for each color group in the FC1 register (000h to 1FFh)
Table 1 shows the CC data versus the constant-current against IOLCMax.
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Device Functional Modes (continued)
Table 1. CC Data vs Current Ratio and Set Current Value
RATIO OF OUTPUT
CURRENT
TO IolcMax(%, typical)
CC DATA (CCR or CCG or CCB)
OUTPUT CURRENT (mA, RIREF = 7.41 kΩ)
BC = 7h
(IolcMax =25mA)
BC = 0h
(IolcMax=3.2mA)
BINARY
DECIMAL
HEX
0 0000 0000
0
00
0
0
0
0 0000 0001
1
01
0.2
0.05
0.006
0 0000 0010
2
02
0.4
0.10
0.013
---
---
---
---
---
---
1 0000 0000
(Default)
256
(Default)
100
(Default)
50.1
12.52
1.621
---
---
---
---
---
---
1 1111 1101
509
1FD
99.6
24.90
3.222
1 1111 1110
510
1FE
99.8
24.95
3.229
1 1111 1111
511
1FF
100.0
25
3.235
10.3.3 Select RIREF For a Given BC
The maximum output current per channel, IOLCMax, is determined by resistor RIREF, placed between the IREF and
IREFGND pins, and the BC code in FC1 register. The voltage on IREF is typically 1.209V. RIREF can be
calculated by Equation 2.
Riref(kΩ) = Viref(V) / IOLCMax(mA) × Gain
(2)
Where:
VIREF = the internal reference voltage on IREF (1.209V, typical)
IOLCMax is the largest current for each output at CCR/G/B=1FFh.
Gain = the current gain at a selected BC code (See Table 2 )
Table 2. Current Gain Versus BC Code
BC DATA
GAIN
RATIO OF
GAIN / GAIN_MAX (AT MAX
BC)
BINARY
HEX
000 (recommend)
0 (recommend
20.4
12.9%
001
1
40.3
25.6%
010
2
59.7
52.4%
011
3
82.4
12.9%
100 (default)
4 (default)
101.8
64.7%
101
5
115.4
73.3%
110
6
144.3
91.7%
111
7
157.4
100%
NOTE: Recommend using a smaller BC code for better performance. For noise immunity purposes, suggest RIREF < 60 kΩ
10.3.4 Choosing BC/CC For a Different Application
BC is mainly used for global brightness adjustment between day and night. Suggested BC is 4h, which is in the
middle of the range, thus, one can change brightness up and down flexibly.
CC can be used to fine tune the brightness in 512 steps, this is suitable for white balance adjustment between
RGB color group. To get a pure white color, the general requirement for the luminous intensity ratio of R, G, B
LED is 3:6:1. Depending on the characteristics of the LED (Electro-Optical conversion efficiency), the current
ratio of R, G, B LED will be much different from this ratio. Usually, the Red LED needs the largest current. One
can choose 511d (the max value) CC code for the color group that needs the largest initial current, then choose
proper CC code for the other two color groups according to the current ratio requirement of the LED used.
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10.3.4.1 Example 1: Red LED Current is 20mA, Green LED Needs 12mA, Blue LED needs 8mA
1. Red LED needs the largest current, so choose 511d for CCR
2. 511 x 12mA / 20mA = 306.6, thus choose 307d for CCG. With same method, choose 204d for CCB.
3. According to the required red LED current, choose 7h for BC.
4. According to Equation 2, RIREF = 1.209V/20mA x 157.4 = 9.5 kΩ
In this example, we choose 7h for BC, instead of using the default 4h. This is because the Red LED current is
20mA, approaching the upper limit of current range. To prevent the constant output current from exceeding the
upper limit in case a larger BC code is input accidently, we choose the maximum BC code here.
10.3.4.2 Example 2: Red LED Current is 5mA, Green LED Needs 2mA, Blue LED Needs 1mA.
1. Red LED needs the largest current, so choose 511d for CCR.
2. 511 x 2mA / 5mA = 204.4, thus choose 204d for CCG. With same method, choose 102d for CCB.
3. According to the required blue LED current, choose 0h for BC.
4. According to Equation 2, RIREF = 1.209V / 5mA x 20.4 = 4.93 kΩ
In this example, we choose 0h for BC, instead of using the default 4h. This is because the Blue LED current is
1mA, is approaching the lower limit of current range. To prevent the constant output current from exceeding the
lower limit in case a lower BC code is input accidently, we choose the minimum BC code here. In general, if LED
current is in the middle of the range (i.e, 10mA), one can just use the default 4h as BC code.
10.3.5 LED Open Detection (LOD)
The LOD function detects faults caused by an open circuit in any LED string; or, a short from OUTXn to ground
with low impedance. It does this by comparing the OUTXn voltage to the LOD detection threshold voltage level
set by LODVLT in the FC1 register. If the OUTXn voltage is lower than the programmed voltage, the
corresponding output LOD bit will be set to '1' to indicate a open LED. Otherwise, the output of that LOD bit is '0'.
LOD data output by the detection circuit are valid only during the ‘on’ period of that OUTXn output channel. The
LOD data are always ‘0’ for outputs that are turned off.
10.3.6 Power Save Mode (PSM)
The power-save mode (PSM) is enabled by setting PSAVE_ENA (bit5 of FC2 register) to ‘1’. When power on,
this bit default is ‘0’.
When this function is enabled, if the GS data received for next frame is all ‘0’, IC will enter power save mode at
the moment Vsync command input.
When the IC is in power-save mode, it resumes normal mode when it detects non-zero GS data input. In powersave mode all analog circuits such as constant current output and the LOD circuit are not operational; the device
total current consumption, Icc, is below 1mA.
10.3.7 Internal Pre-Charge FET
The internal pre-charge FET can prevent ghosting of multiplexed LED modules. One cause of this phenomenon
is the charging current for parasitic capacitance of the OUTXn through the LED when the supply voltage switches
from one common line to the next common line.
To prevent this unwanted charging current, TLC5958 uses an internal FET to pull OUTXn up to VCC –1.4V
during the common line switching period. Thus, no charging current flows through LED and ghosting is
eliminated.
10.3.8 Thermal Shutdown (TSD)
The thermal shutdown (TSD) function turns off all IC constant-current outputs when the junction temperature (TJ)
exceeds 170°C (typ). It resumes normal operation when TJ falls below 160°C (typ).
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10.3.9 IREF Resistor Short Protection (ISP)
The Iref resistor short protection (ISP) function prevents unwanted large currents from flowing though the
constant-current output when the Iref resistor is shorted accidently. The TLC5958 turns off all output channels
when the Iref pin voltage is lower than 0.19V (typ). When the Iref pin voltage goes higher than 0.325V (typ), the
TLC5958 resumes normal operation.
10.3.10 Noise Reduction
Large surge currents may flow through the IC and the board on which the device is mounted if all 48 LED
channels turned on simultaneously at the 1st GCLK rising edge. This large surge current could induce
detrimental noise and electromagnetic interference (EMI) into other circuits.
The TLC5958 separates the LED channels into 12 groups. Each group turns on sequentially with some delay
between one group and the next group. By this operation, a soft-start feature provides for minimal inrush current.
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11 Application and Implementation
Send request via email for Application Note: Build High Density, High Refresh Rate, Multiplexing LED Panel with
TLC5958
12 Power Supply Recommendations
The VCC power supply voltage should be decoupled by placing a 0.1 µF ceramic capacitor close to VCC pin and
GND plane. Depending on panel size, several electrolytic capacitors must be placed on board equally distributed
to get a well regulated LED supply voltage (VLED). VLED voltage ripple should be less than 5% of its nominal
value. Furthermore, the VLED should be set to the voltage calculated by equation:
VLED > Vf + 0.4V (10mA constant current example)
(3)
Where: Vf = maximum forward voltage of LED
13 Layout
13.1 Layout Guidelines
1. Place the decoupling capacitor near the VCC pin and GND plane.
2. Place the current programming resistor Riref close to IREF pin and IREFGND pin.
3. Route the GND pattern as widely as possible for large GND currents. Maximum GND current is
approximately 1.2A
4. Routing between the LED cathode side and the device OUTXn pin should be as short and straight as
possible to reduce wire inductance.
5. The PowerPAD™ must be connected to GND plane because the pad is used as power ground pin internally,
there will be large current flow through this pad when all channels turn on. Furthermore, this pad should be
connected to a heat sink layer by thermal via to reduce device temperature. One suggested thermal via
pattern is shown as below. For more information about suggested thermal via pattern and via size, see "
PowerPAD Thermally Enhanced Package", SLMA002G.
13.2 Layout Example
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14 Device and Documentation Support
14.1 Trademarks
LGSE, PowerPAD are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
14.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
14.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
15 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLC5958RTQR
ACTIVE
QFN
RTQ
56
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TLC5958
TLC5958RTQT
ACTIVE
QFN
RTQ
56
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TLC5958
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of