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TLC6C598
SLIS177 – MAY 2016
TLC6C598 8-Bit Shift-Register LED Driver
1 Features
3 Description
•
•
•
The TLC6C598 device is a monolithic, mediumvoltage, low-current power 8-bit shift register
designed for use in systems that require relatively
moderate load power, such as LEDs.
1
•
•
•
•
•
•
Wide VCC From 3 V to 5.5 V
Output Maximum Rating of 40 V
Eight Power DMOS Transistor Outputs of 50-mA
Continuous Current With VCC = 5 V or 200-mA
PWM Current With Single-Pulse Duration Less
Than 1 ms and Average Current Less Than
50 mA
Thermal Shutdown Protection
Enhanced Cascading for Multiple Stages
All Registers Cleared With Single Input
Low Power Consumption
Slow Switching Time (tr and tf), Which Helps
Significantly With Reducing EMI
16-Pin TSSOP-PW Package
The TLC6C598 characterization is for operation over
the operating ambient temperature range of −40°C to
105°C.
2 Applications
•
•
•
•
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. Separate clocks are provided for both the
shift and storage register. Outputs are low-side, opendrain DMOS transistors with output ratings of 40 V
and 50 mA continuous sink-current OR 200-mA PWM
current with single-pulse duration less than 1 ms and
average current less than 50 mA capabilities when
VCC = 5 V. The device contains built-in thermal
shutdown protection and provides up to 2000 V of
ESD protection when tested using the human-body
model and the 200 V machine model.
Appliance Display Panel
Elevator Display Panel
PLC Function Indicator
Seven-Segment Display
Device Information(1)
PART NUMBER
TLC6C598
PACKAGE
BODY SIZE (NOM)
TSSOP (16)
5.00 mm x 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application Schematic
Power Supply
MCU Serial
Interface
4/3
8-Bit Shift Register
LED Driver
4/3
8-Bit Shift Register
LED Driver
Typical Cascade Topology
Power Supply
I/Os
MCU Serial
Interface
4/3
8-Bit ShiftRegister
LED Driver
3 ´ 8 LED Matrix
Typical Scan Topology
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLC6C598
SLIS177 – MAY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
4
5
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Timing Waveforms ....................................................
Typical Characteristics ..............................................
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
12
12
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application ................................................. 13
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 16
11.1 Layout Guidelines ................................................. 16
11.2 Layout Example .................................................... 16
12 Device and Documentation Support ................. 17
12.1
12.2
12.3
12.4
Parameter Measurement Information .................. 9
Detailed Description ............................................ 11
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
13 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
2
DATE
REVISION
NOTE
May 2016
*
Initial release
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5 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
V
1
16
GND
SER_IN
2
15
SRCK
DRAIN0
3
14
DRAIN7
DRAIN1
4
13
DRAIN6
DRAIN2
5
12
DRAIN5
DRAIN3
6
11
DRAIN4
CLR
7
10
RCK
G
8
9
CC
!
SER_OUT
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
CLR
7
I
Shift register clear, active-low. The storage register transfers data to the output buffer
when CLR is high. Driving CLR low clears all the registers in the device.
DRAIN0
3
O
Open-drain output, LED current-sink channel, connect to LED cathode
DRAIN1
4
O
Open-drain output, LED current-sink channel, connect to LED cathode
DRAIN2
5
O
Open-drain output, LED current-sink channel, connect to LED cathode
DRAIN3
6
O
Open-drain output, LED current-sink channel, connect to LED cathode
DRAIN4
11
O
Open-drain output, LED current-sink channel, connect to LED cathode
DRAIN5
12
O
Open-drain output, LED current-sink channel, connect to LED cathode
DRAIN6
13
O
Open-drain output, LED current-sink channel, connect to LED cathode
DRAIN7
14
O
Open-drain output, LED current-sink channel, connect to LED cathode
G
8
I
Output enable, active-low. LED-channel enable and disable input pin. Having G low
enables all drain channels according to the output-latch register content. When high, all
channels are off.
GND
16
—
RCK
10
I
Register clock. The data in each shift register stage transfers to the storage register at the
rising edge of RCK.
SER IN
2
I
Serial data input. Data on SER IN loads into the internal register on each rising edge of
SRCK.
SER OUT
9
O
Serial data output of the 8-bit serial shift register. The purpose of this pin is to cascade
several devices on the serial bus.
SRCK
15
I
Serial clock input. On each rising SRCK edge, data transfers from SER IN to the internal
serial shift registers.
VCC
1
I
Power supply pin for the device. TI recommends adding a 0.1-μF ceramic capacitor close
to the pin.
Power ground, the ground reference pin for the device. This pin must connect to the
ground plane on the PCB.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VCC
Logic supply voltage
–0.3
8
V
VI
Logic input-voltage range
–0.3
8
V
VDS
Power DMOS drain-to-source voltage
–0.3
42
V
Continuous total dissipation
See Thermal Information
TJ
Operating junction temperature range
–40
125
°C
Tstg
Storage temperature range
–55
165
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic discharge
Charged device model (CDM), per AEC
Q100-011
UNIT
±2000
All pins
±750
Corner pins (1, 8, 9, and
16)
±750
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN MAX
VCC
Supply voltage
3
VIH
High-level input voltage
VIL
Low-level input voltage
TA
Operating ambient temperature
5.5
2.4
–40
UNIT
V
V
0.7
V
105
°C
6.4 Thermal Information
TLC6C598
THERMAL METRIC (1)
PW (TSSOP)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
129.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
55.4
°C/W
RθJB
Junction-to-board thermal resistance
65.8
°C/W
ψJT
Junction-to-top characterization parameter
9.9
°C/W
ψJB
Junction-to-board characterization parameter
65.2
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
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6.5 Electrical Characteristics
VCC = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
DRAIN0 to DRAIN7. Drain-tosource voltage
High-level output voltage, SER
OUT
IOH = –20 μA
VOL
Low-level output voltage, SER
OUT
IOH = 20 μA
IIH
High-level input current
VCC = 5 V, VI = VCC
IIL
Low-level input current
VCC = 5 V, VI = 0
IOH = −4 mA
IOH = 4 mA
VCC = 5 V
0.001
0.01
0.25
0.4
V
V
μA
μA
0.1
1
All outputs on
88
160
200
Logic supply current at frequency
fSRCK = 5 MHz, CL = 30 pF
All outputs on
IDSx
Off-state drain current
VDS = 30 V
VCC = 5 V
VDS = 30 V, TC = 105°C
VCC = 5 V
Hysteresis
V
–0.2
ICC(FRQ)
Thermal shutdown trip point
V
4.69
All outputs off
VCC = 5 V, no clock signal
Thys
4.99
4.5
0.2
Logic supply current
TSHUTDOWN
V
4.9
VCC = 5 V
ICC
rDS(on)
UNIT
40
VOH
Static drain-source on-state
resistance
MAX
μA
μA
0.1
0.15
0.3
ID = 20 mA, VCC = 5 V, TA = 25°C,
Single channel ON
6
7.41
8.6
ID = 20 mA, VCC = 5 V, TA = 25°C,
All channels ON
6.7
8.3
9.6
ID = 20 mA, VCC = 3.3 V, TA = 25°C,
Single channel ON
7.9
9.34
11.2
ID = 20 mA, VCC = 3.3 V, TA = 25°C,
All channels ON
8.7
10.25
12.3
ID = 20 mA, VCC = 5 V, TA = 105°C,
Single channel ON
9.1
11.13
12.9
ID = 20 mA, VCC = 5 V, TA = 105°C,
All channels ON
10.3
12.28
14.5
ID = 20 mA, VCC = 3.3 V, TA = 105°C,
Single channel ON
11.6
13.69
16.4
ID = 20 mA, VCC = 3.3 V, TA = 105°C,
All channels ON
12.8
14.89
18.2
150
175
200
μA
Ω
ºC
15
ºC
6.6 Timing Requirements
MIN
NOM
MAX
UNIT
tsu
Setup time, SER IN high before SRCK↑
15
ns
th
Hold time, SER IN high after SRCK↑
15
ns
tw
SER IN pulse duration
40
ns
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6.7 Switching Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
Propagation delay time from G to output, low-to-high
level
tPHL
Propagation delay time from G to output, high-to-low
level
tr
tf
tpd
Propagation delay time, SRCK↓ to SER OUT
CL = 30 pF, ID = 48 mA
tor
SER OUT rise time (10% to 90%)
tof
SER OUT fall time (90% to 10%)
f(SRCK)
Serial clock frequency
CL = 30 pF, ID = 20 mA
tSRCK_WH
SRCK pulse duration, high
30
ns
tSRCK_WL
SRCK pulse duration, low
30
ns
6
220
ns
75
ns
Rise time, drain output
210
ns
Fall time, drain output
128
ns
49.4
ns
CL = 30 pF
20
ns
CL = 30 pF
20
CL = 30 pF, ID = 48 mA
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ns
10
MHz
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6.8 Timing Waveforms
Figure 1 shows the SER IN to SER OUT waveform. The output signal appears on the falling edge of the shift
register clock (SRCK) because there is a phase inverter at SER OUT (see Figure 13). As a result, it takes seven
and a half periods of SRCK for data to transfer from SER IN to SER OUT.
8
7
5
6
3
4
2
1
SRCK
SER IN
CLR
1
SER OUT
0
Figure 1. SER IN to SER OUT Waveform
Figure 2 shows the switching times and voltage waveforms. Tests for all these parameters took place using the
test circuit shown in Figure 11.
5V
G
50%
50%
0V
tPHL
tPLH
90%
Output
10 V
90%
10%
10%
0.5 V
tf
tr
5V
SRCK
50%
0V
tsu
th
5V
SER IN
50%
50%
0V
tw
Switching Times, Input Setup and Hold Waveforms
SRCK
50%
50%
tpd
tpd
50%
SER OUT
50%
SER OUT Propagation Delay Waveform
Figure 2. Switching Times and Voltage Waveforms
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6.9 Typical Characteristics
500
350
T A = –40°C
T A = 25°C
T A = 105°C
Supply Current (µA)
Supply Current (µA)
400
All Channels Off
All Channels On
300
300
200
250
200
150
100
100
50
0
0
0.1
1
10
3.0
100
Frequency (MHz)
3.5
Figure 3. Supply Current vs Frequency
Drain-Source On-State Resistance (W)
Drain-Source On-State Resistance (W)
8
6
4
TA = –40°C
TA = 25°C
TA = 105°C
10
14
12
10
8
6
4
TA = –40°C
TA = 25°C
2
TA = 105°C
0
20
Single channel on
30
40
50
0
60
10
20
30
40
50
60
Drain Current (mA)
VCC = 5 V
Single channel on
VCC = 3.3 V
Figure 5. Drain-to-Source On-State Resistance vs Drain
Current
Figure 6. Drain-to-Source On-State Resistance vs Drain
Current
14
18
Drain-Source On-State Resistance (W)
Drain-Source On-State Resistance (W)
6.0
16
Drain Current (mA)
12
10
8
6
4
TA = –40°C
2
TA = 25°C
TA = 105°C
0
0
10
16
14
12
10
8
6
4
TA = –40°C
2
TA = 25°C
TA = 105°C
0
20
30
40
50
60
0
10
All channels on
20
30
40
50
60
Drain Current (mA)
Drain Current (mA)
VCC = 5 V
All channels on
Figure 7. Drain-to-Source On-State Resistance vs Drain
Current
8
5.5
Figure 4. Supply Current vs Supply Voltage
10
0
5.0
V
12
0
4.5
Supply Voltage (V)
VCC = 5 V
2
4.0
C001
VCC = 3.3 V
Figure 8. Drain-to-Source On-State Resistance vs Drain
Current
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18
350
16
300
tplh
tPLH
tPHL
tphl
250
trtr
tftf
14
Switching Time (ns)
Drain-Source On-State Resistance (W)
Typical Characteristics (continued)
12
10
8
6
4
TA = –40°C
2
TA = 25°C
2.5
3.0
3.5
150
100
50
TA = 105°C
0
200
0
4.0
4.5
5.0
5.5
6.0
–40
6.5
0
–20
Supply Voltage (V)
All channels on
20
40
60
80
100
120
Ambient Temperature (°C)
IDS = 20 mA
V
Figure 9. Drain-to-Source On-State Resistance vs Supply
Voltage
Figure 10. Switching Time vs Ambient Temperature
7 Parameter Measurement Information
Figure 11 and Figure 12 show the resistive-load test circuit and voltage waveforms. One can see from Figure 12
that with G held low and CLR held high, the status of each drain changes on the rising edge of the register clock,
indicating the transfer of data to the output buffers at that time.
5V
10 V
VCC
CLR
ID
RL = 200 W
SRCK
Output
MCU
DRAIN
SER IN
CL = 30 pF
(see Note A)
RCK
G
GND
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A.
CL includes probe and jig capacitance.
Figure 11. Resistive-Load Test Circuit
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Parameter Measurement Information (continued)
8
7
6
5
4
3
2
1
SRCK
SER IN
G
RCK
0
CLR
1
DRAIN0
0
DRAIN1
0
DRAIN6
0
DRAIN7
0
Figure 12. Voltage Waveforms
10
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8 Detailed Description
8.1 Overview
The TLC6C598 device is a monolithic, medium-voltage, low-current 8-bit shift register designed to drive relatively
moderate load power such LEDs. The device contains an 8-bit serial-in, parallel-out shift register that feeds an 8bit D-type storage register. Thermal shutdown protection is also built-into the device.
8.2 Functional Block Diagram
G
RCK
DRAIN0
CLR
D
D
C1
SRCK
C1
CLR
CLR
D
D
DRAIN1
SER IN
C1
C1
CLR
CLR
D
D
C1
C1
CLR
CLR
D
D
C1
CLR
D
D
C1
DRAIN4
C1
CLR
CLR
D
D
C1
DRAIN5
C1
CLR
CLR
D
D
C1
DRAIN6
C1
CLR
CLR
D
D
CLR
DRAIN3
C1
CLR
C1
DRAIN2
DRAIN7
C1
CLR
GND
D
C1
SER OUT
CLR
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Figure 13. Logic Diagram (Positive) of TLC6C598
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8.3 Feature Description
8.3.1 Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 175°C
(typical). The thermal shutdown forces the device to have an open state when the junction temperature exceeds
the thermal trip threshold. Once the junction temperature decreases below 160°C (typical), the device begins to
operate again.
8.3.2 Serial-In Interface
The TLC6C598 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage
register. Data transfer through the shift and storage registers is on the rising edge of the shift register clock
(SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when
shift-register clear (CLR) is high.
8.3.3 Clear Registers
A logic low on the CLR pin clears all registers in the device. TI suggests clearing the device during power up or
initialization.
8.3.4 Output Channels
DRAIN0–DRAIN7. These pins can survive up to 40-V LED supply voltage.
8.3.5 Register Clock
RCK is the storage-register clock. Data in the storage register appears at the output whenever the output enable
(G) input signal is high.
8.3.6 Cascade Through SER OUT
By connecting the SER OUT pin to the SER IN input of the next device on the serial bus in cascade, the data
transfers to the next device on the falling edge of SRCK. This connection can improve the cascade application
reliability, as it can avoid the issue that the second device receives SRCK and data input on the same rising
edge of SRCK.
8.3.7
Output Control
Holding the output enable (pin G) high holds all data in the output buffers low, and all drain outputs are off.
Holding G low makes data from the storage register transparent to the output buffers. When data in the output
buffers is low, the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs are capable
of sinking current. This pin also can be used for global PWM dimming.
8.4 Device Functional Modes
8.4.1 Operation With VCC < 3 V
This device works normally within the range 3 V ≤ VCC ≤ 5.5 V. When the operating voltage is lower than 3 V,
correct behavior of the device, including communication interface and current capability, is not assured.
8.4.2 Operation With 5.5 V ≤ VCC ≤ 8 V
The device works normally in this voltage range, but reliability issues may occur if the device works for a long
time in this voltage range.
12
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TLC6C598 device is a serial-in, parallel-out, power and logic, 8-bit shift register with low-side open-drain
DMOS output ratings of 40-V and 50-mA continuous sink-current capabilities when VCC = 5 V. The device is
designed to drive resistive loads and is particularly well-suited as an interface between a microcontroller and
LEDs or lamps. The device also provides up to 2000 V of ESD protection when tested using the human body
model and 200 V when using the machine model.
9.2 Typical Application
Figure 14 shows a typical cascade application circuit with two TLC6C598 chips configured in cascade topology.
The MCU generates all the input signals.
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Typical Application (continued)
Battery 9 V–40 V
3 V–5.5 V
DRAIN0
DRAIN6
DRAIN1
DRAIN7
VCC
GND
SER IN
SRCK
MCU
G
SER OUT
CLR
RCK
DRAIN0
DRAIN1
DRAIN6
DRAIN7
VCC
SER IN
GND
SRCK
G
SER OUT
CLR
RCK
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Figure 14. Typical Application Circuit
9.2.1 Design Requirements
DESIGN PARAMETER
EXAMPLE VALUE
VBattery
9 V to 40 V
VCC_1
3.3 V
I(D0), I(D1), I(D2), I(D3) , I(D4), I(D5), I(D6), I(D7)
30 mA
VCC_2
5V
I(D8), I(D9), I(D10), I(D11) , I(D12), I(D13), I(D14), I(D15)
50 mA
14
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9.2.2 Detailed Design Procedure
To
•
•
•
begin the design process, the designer must decide on a few parameters, as follows:
Vsupply: LED supply voltage
VDx: LED forward voltage
I: LED current
With these parameters determined, the resistor in series with the LED can be calculated by using the following
equation:
R X = (VSupply - VDx ) / I
(1)
9.2.3 Application Curve
Figure 15. TLC6C598 Application Waveform
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10 Power Supply Recommendations
The TLC6C598 device is designed to operate with an input voltage supply range from 3 V to 5.5 V. This input
supply should be well regulated. TI recommends placing the ceramic bypass capacitors near the VCC pin.
11 Layout
11.1 Layout Guidelines
There are no special layout requirements for the digital signal pins. The only requirement is placing the ceramic
bypass capacitors near the corresponding pins.
Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heat-flow
path from the package to the ambient is through the copper on the PCB. Maximizing the copper coverage is
extremely important when the design does not include heat sinks attached to the PCB on the other side of the
package.
Add as many thermal vias as possible directly under the package ground pad to optimize the thermal conductivity
of the board.
All thermal vias should be either plated shut or plugged and capped on both sides of the board to prevent solder
voids. To ensure reliability and performance, the solder coverage should be at least 85%.
11.2 Layout Example
VCC
1
16
GND
SER IN
2
15
SRCK
DRAIN0
3
14
DRAIN7
DRAIN1
4
13
DRAIN6
DRAIN2
5
12
DRAIN5
DRAIN3
6
11
DRAIN4
CLR
7
10
RCK
G
8
9
SER OUT
Figure 16. TLC6C598 Example Layout
16
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Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TLC6C598
TLC6C598
www.ti.com
SLIS177 – MAY 2016
12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated device. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TLC6C598
17
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLC6C598PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
6C598I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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