TLC7524CPWRG4


 
 

   

  
 SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007 D Easily Interfaced to Microprocessors D On-Chip Data Latches D Monotonic Over the Entire A/D Conversion D D D OUT1 OUT2 GND DB7 DB6 DB5 DB4 DB3 Range Segmented High-Order Bits Ensure Low-Glitch Output Interchangeable With Analog Devices AD7524, PMI PM-7524, and Micro Power Systems MP7524 Fast Control Signaling for Digital Signal-Processor Applications Including Interface With TMS320 CMOS Technology 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 RFB REF VDD WR CS DB0 DB1 DB2 FN PACKAGE (TOP VIEW) KEY PERFORMANCE SPECIFICATIONS Resolution Linearity error Power dissipation at VDD = 5V Setting time Propagation delay time 1 OUT2 OUT1 NC RFB REF D D, N, OR PW PACKAGE (TOP VIEW) 8 Bits 1/2LSB Max 5mW Max 100ns Max 80ns Max GND DB7 NC DB6 DB5 description 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 VDD WR NC CS DB0 DB4 DB3 NC DB2 DB1 The TLC7524C, TLC7524E, and TLC7524I are CMOS, 8-bit, digital-to-analog converters (DACs) designed for easy interface to most popular microprocessors. 4 NC−No internal connection The devices are 8-bit, multiplying DACs with input latches and load cycles similar to the write cycles of a random access memory. Segmenting the high-order bits minimizes glitches during changes in the most significant bits, which produce the highest glitch impulse. The devices provide accuracy to 1/2LSB without the need for thin-film resistors or laser trimming, while dissipating less than 5mW typically. Featuring operation from a 5V to 15V single supply, these devices interface easily to most microprocessor buses or output ports. The 2- or 4-quadrant multiplying makes these devices an ideal choice for many microprocessor-controlled gain-setting and signal-control applications. The TLC7524C is characterized for operation from 0°C to 70°C. The TLC7524I is characterized for operation from −25°C to +85°C. The TLC7524E is characterized for operation from − 40°C to +85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright  1998−2007, Texas Instruments Incorporated 
 
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&-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0  !)) '!!&"&#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 

 
 

   

  
 SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007 functional block diagram REF R 15 2R R 2R R 2R 2R 2R 16 S-1 S-2 S-3 S-8 R 1 2 CS WR 12 3 Data Latches 13 4 DB7 (MSB) 5 DB6 6 DB5 RFB OUT1 OUT2 GND 11 DB0 (LSB) Data Inputs Terminal numbers shown are for the D or N package. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to 16.5V Digital input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to VDD + 0.3V Reference voltage, Vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25V Peak digital input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µA Operating free-air temperature range, TA: TLC7524C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C TLC7524I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25°C to +85°C TLC7524E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to +85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C Case temperature for 10 seconds, TC: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260°C Lead temperature 1,6mm (1/16 inch) from case for 10 seconds: D, N, or PW package . . . . . . . . . . . +260°C package/ordering information For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

 
 

   

  
 SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007 recommended operating conditions Supply voltage, VDD VDD = 5V MIN NOM MAX VDD = 15V MIN NOM MAX 4.75 14.5 5 5.25 ± 10 Reference voltage, Vref High-level input voltage, VIH 15 2.4 V 0.8 40 CS hold time, th(CS) V V 13.5 Low-level input voltage, VIL CS setup time, tsu(CS) 15.5 ± 10 UNIT 1.5 V 40 ns 0 0 ns Data bus input setup time, tsu(D) 25 25 ns Data bus input hold time, th(D) 10 10 ns Pulse duration, WR low, tw(WR) 40 40 TLC7524C Operating free-air temperature, TA ns 0 +70 0 +70 TLC7524I −25 +85 −25 +85 TLC7524E −40 +85 −40 +85 °C C electrical characteristics over recommended operating free-air temperature range, Vref = ±10V, OUT1 and OUT2 at GND (unless otherwise noted) PARAMETER IIH IIL IIkg TEST CONDITIONS High-level input current Low-level input current Output leakage current MIN VDD = 5V TYP MAX VI = VDD VI = 0 10 10 µA µA −10 −10 OUT1 WR, CS at 0V, ± 400 ± 200 OUT2 DB0−DB7 at VDD, Vref = ± 10V WR, CS at 0V, ± 400 ± 200 Quiescent DB0−DB7 at VIHmin or VILmax 1 2 mA Standby DB0−DB7 at 0V or VDD 500 500 µA 0.04 %FSR/% Supply current kSVS Supply voltage sensitivity, ∆gain/∆VDD ∆VDD = ± 10% Ci Input capacitance, DB0−DB7, WR, CS VI = 0 nA 0.01 OUT2 DB0−DB7 at 0V, WR, CS at 0V OUT1 OUT2 DB0−DB7 at VDD, 0.16 0.005 5 OUT1 Output capacitance UNIT DB0−DB7 at 0V, Vref = ± 10V IDD Co VDD = 15V TYP MAX MIN WR, CS at 0V Reference input impedance (REF to GND) 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 30 30 120 120 120 120 30 30 20 5 20 pF pF kΩ 3 

 
 

   

  
 SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007 operating characteristics over recommended operating free-air temperature range, Vref = ±10V, OUT1 and OUT2 at GND (unless otherwise noted) PARAMETER TEST CONDITIONS VDD = 5V MIN TYP MAX VDD = 15V TYP MIN MAX UNIT ± 0.5 ± 0.5 LSB Linearity error Gain error See Note 1 ± 2.5 ± 2.5 LSB Settling time (to 1/2 LSB) See Note 2 100 100 ns Propagation delay from digital input to 90% of final analog output current See Note 2 80 80 ns Feedthrough at OUT1 or OUT2 Vref = ±10V (100kHz sinewave) WR and CS at 0V, DB0−DB7 at 0V 0.5 0.5 %FSR Temperature coefficient of gain TA = +25°C to MAX ± 0.004 ± 0.001 NOTES: 1. Gain error is measured using the internal feedback resistor. Nominal full-scale range (FSR) = Vref − 1LSB. 2. OUT1 load = 100Ω, Cext = 13pF, WR at 0V, CS at 0V, DB0 − DB7 at 0V to VDD or VDD to 0V. operating sequence tsu(CS) th(CS) CS tw(WR) WR ÎÎÎ ÎÎÎ tsu(D) DB0−DB7 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 th(D) %FSR/°C 

 
 

   

  
 SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007 PRINCIPLES OF OPERATION voltage-mode operation It is possible to operate the current-multiplying DAC in these devices in a voltage mode. In the voltage mode, a fixed voltage is placed on the current output terminal. The analog output voltage is then available at the reference voltage terminal. Figure 1 is an example of a current-multiplying DAC, which is operated in voltage mode. R R R REF (Analog Output Voltage) 2R 2R 2R 0 2R 1 R OUT1 (Fixed Input Voltage) OUT2 Figure 1. Voltage Mode Operation The relationship between the fixed-input voltage and the analog-output voltage is given by the following equation: VO = VI (D/256) where VO = analog output voltage VI = fixed input voltage D = digital input code converted to decimal In voltage-mode operation, these devices meet the following specification: PARAMETER Linearity error at REF TEST CONDITIONS VDD = 5V, OUT1 = 2.5V, POST OFFICE BOX 655303 OUT2 at GND, • DALLAS, TEXAS 75265 MIN TA = +25°C MAX UNIT 1 LSB 5 

 
 

   

  
 SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007 PRINCIPLES OF OPERATION The TLC7524C, TLC7524E, and TLC7524I are 8-bit multiplying DACs consisting of an inverted R-2R ladder, analog switches, and data input latches. Binary-weighted currents are switched between the OUT1 and OUT2 bus lines, thus maintaining a constant current in each ladder leg independent of the switch state. The high-order bits are decoded. These decoded bits, through a modification in the R-2R ladder, control three equally-weighted current sources. Most applications only require the addition of an external operational amplifier and a voltage reference. The equivalent circuit for all digital inputs low is seen in Figure 2. With all digital inputs low, the entire reference current, Iref, is switched to OUT2. The current source I/256 represents the constant current flowing through the termination resistor of the R-2R ladder, while the current source IIkg represents leakage currents to the substrate. The capacitances appearing at OUT1 and OUT2 are dependent upon the digital input code. With all digital inputs high, the off-state switch capacitance (30pF maximum) appears at OUT2 and the on-state switch capacitance (120pF maximum) appears at OUT1. With all digital inputs low, the situation is reversed as shown in Figure 2. Analysis of the circuit for all digital inputs high is similar to Figure 2; however, in this case, Iref would be switched to OUT1. The DAC on these devices interfaces to a microprocessor through the data bus and the CS and WR control signals. When CS and WR are both low, analog output on these devices responds to the data activity on the DB0−DB7 data bus inputs. In this mode, the input latches are transparent and input data directly affects the analog output. When either the CS signal or WR signal goes high, the data on the DB0−DB7 inputs are latched until the CS and WR signals go low again. When CS is high, the data inputs are disabled regardless of the state of the WR signal. These devices are capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for 2-quadrant or 4-quadrant multiplication are shown in Figure 3 and Figure 4. Table 1 and Table 2 summarize input coding for unipolar and bipolar operation respectively. RFB R OUT1 30 pF IIkg Iref REF OUT2 I/256 120 pF IIkg Figure 2. TLC7524 Equivalent Circuit With All Digital Inputs Low 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

 
 

   

  
 SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007 PRINCIPLES OF OPERATION VDD Vref RA = 2 kΩ (see Note A) RB C (see Note B) RFB DB0−DB7 OUT1 − OUT2 + Output CS WR GND NOTES: A. RA and RB used only if gain adjustment is required. B. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent ringing or oscillation. Figure 3. Unipolar Operation (2-Quadrant Multiplication) Vref VDD 20 kΩ RA = 2 kΩ (see Note A) RB CS WR − C (see Note B) RFB DB0−DB7 20 kΩ Output OUT1 − OUT2 + + 10 kΩ 5 kΩ GND NOTES: A. RA and RB used only if gain adjustment is required. B. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent ringing or oscillation. Figure 4. Bipolar Operation (4-Quadrant Operation) Table 1. Unipolar Binary Code DIGITAL INPUT (see Note 3) MSB ANALOG OUTPUT LSB 11111111 10000001 10000000 01111111 00000001 00000000 Table 2. Bipolar (Offset Binary) Code DIGITAL INPUT (see Note 4) MSB ANALOG OUTPUT LSB −Vref (255/256) −Vref (129/256) 11111111 10000001 Vref (127/128) Vref (1/128) −Vref (128/256) = − Vref/2 −Vref (127/256) 10000000 0 01111111 −Vref (1/256) 0 00000001 −Vref (1/128) −Vref (127/128) 00000000 −Vref NOTE 3: LSB = 1/256 (Vref) NOTE 4: LSB = 1/128 (Vref) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 

 
 

   

  
 SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007 PRINCIPLES OF OPERATION microprocessor interfaces D0−D7 Data Bus Z−80A DB0−DB7 WR TLC7524 WR OUT1 OUT2 CS IORQ Decode Logic Address Bus A0−A15 Figure 5. TLC7524: Z-80A Interface Data Bus D0−D7 6800 DB0−DB7 φ2 WR TLC7524 OUT1 OUT2 CS VMA A0−A15 Decode Logic Address Bus Figure 6. TLC7524: 6800 Interface 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

 
 

   

  
 SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007 PRINCIPLES OF OPERATION microprocessor interfaces (continued) A8−A15 Address Bus 8051 Decode Logic 8-Bit Latch CS WR ALE TLC7524 DB0−DB7 OUT1 OUT2 WR AD0−AD7 Adress/Data Bus Figure 7. TLC7524: 8051 Interface POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 Revision History DATE REV 6/07 D PAGE SECTION DESCRIPTION Front Page — Deleted Available Options table. 2 — Inserted Package/Ordering information. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) (1) TLC7524CD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLC7524C Samples TLC7524CDG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLC7524C Samples TLC7524CDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLC7524C Samples TLC7524CFNR ACTIVE PLCC FN 20 1000 RoHS & Green SN Level-1-260C-UNLIM 0 to 70 TLC7524C Samples TLC7524CN ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TLC7524CN Samples TLC7524CNE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TLC7524CN Samples TLC7524CNS ACTIVE SO NS 16 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLC7524 Samples TLC7524CNSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLC7524 Samples TLC7524CPW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 P7524 Samples TLC7524CPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 P7524 Samples TLC7524ED ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TLC7524E Samples TLC7524EDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TLC7524E Samples TLC7524EN ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TLC7524EN Samples TLC7524ID ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -25 to 85 TLC7524I Samples TLC7524IDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -25 to 85 TLC7524I Samples TLC7524IFN ACTIVE PLCC FN 20 46 RoHS & Green SN Level-1-260C-UNLIM -25 to 85 TLC7524I Samples TLC7524IN ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -25 to 85 TLC7524IN Samples TLC7524IPW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -25 to 85 Y7524 Samples TLC7524IPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -25 to 85 Y7524 Samples The marketing status values are defined as follows: Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of