TLC876M, TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
features
applications
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
10-Bit Resolution 20 MSPS Sampling
Analog-to-Digital Converter (ADC)
Power Dissipation . . . 107 mW Typ
5-V Single Supply Operation
Differential Nonlinearity . . . ±0.5 LSB Typ
No Missing Codes
Power Down (Standby) Mode
Three State Outputs
Digital I/Os Compatible With 5-V or 3.3-V
Logic
Adjustable Reference Input
Small Outline Package (SOIC), Super Small
Outline Package (SSOP), or Thin Small
Outline Package (TSOP)
Pin Compatible With the Analog
Devices AD876
description
Communications
Multimedia
Digital Video Systems
High-Speed DSP Front-End . . . TMS320C6x
DB, DW, OR PW PACKAGE
(TOP VIEW)
AGND
DRVDD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DRGND
DGND
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
AVDD
AIN
CML
REFBS
REFBF
NC
REFTF
REFTS
DGND
AGND
DVDD
STBY
OE
CLK
The TLC876 is a CMOS, low-power, 10-bit, 20
13
16
MSPS analog-to-digital converter (ADC). The
14
15
speed, resolution, and single-supply operation
are suited for applications in video, multimedia,
NC – No internal connection
imaging, high-speed acquisition, and communications. The low-power and single-supply operation satisfy requirements for high-speed portable
applications. The speed and resolution ideally suit charge-coupled device (CCD) input systems such as color
scanners, digital copiers, electronic still cameras, and camcorders. A multistage pipelined architecture with
output error correction logic provides for no missing codes over the full operating temperature range. Force and
sense connections to the reference inputs provide a more accurate internal reference voltage to the reference
resistor string.
A standby mode of operation reduces the power to typically 15 mW. The digital I/O interfaces to either 5-V or
3.3-V logic and the digital output terminals can be placed in a high-impedance state. The format of the output
data is straight binary coding.
A pipelined multistaged architecture achieves a high sample rate with low power consumption. The TLC876
distributes the conversion over several smaller ADC sub-blocks, refining the conversion with progressively
higher accuracy as the device passes the results from stage to stage. This distributed conversion requires a
small fraction of the 1023 comparators used in a traditional flash ADC. A sample-and-hold amplifier (SHA) within
each of the stages permits the first stage to operate on a new input sample while the second through the fifth
stages operate on the four preceding samples.
The TLC876C is characterized for operation from 0°C to 70°C, the TLC876I is characterized for operation from
–40°C to 85°C, and the TLC876M is characterized for operation over the full military temperature range of –55°C
to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TLC876M, TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
AVAILABLE OPTIONS
PACKAGE
TA
SUPER SMALL
OUTLINE
(DB)
SMALL
OUTLINE
(DW)
TSSOP
(PW)
0°C to 70°C
TLC876CDB
TLC876CDW
TLC876CPW
–40°C to 85°C
TLC876IDB
TLC876IDW
TLC876IPW
–55°C to 125°C
—
TLC876MDW
—
functional block diagram
AIN
SHA†
27
SHA†
GAIN
SHA†
SHA†
GAIN
GAIN
SHA†
GAIN
ADC
ADC
DAC
2
ADC
ADC
DAC
2
ADC
DAC
2
DAC
2
2
Correction Logic
10
Output Buffers
12
10
† Sample and hold amplifier
2
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3
(MSB) D9
(LSB) D0
TLC876M, TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
equivalent input and output circuits
D0–D9 OUTPUT CIRCUIT
ALL DIGITAL INPUT CIRCUITS
AIN INPUT CIRCUIT
DVDD
DVDD
AVDD
DRVDD
DRVDD
30 Ω typ
AIN
0.5 pF typ
CLK
D0–D9
0.3 pF
DRGND
DGND
AGND
DRGND
DGND
REFERENCE INPUT CIRCUIT
AVDD
REFTF
30
AVSS
AVDD
REFTS
Internal Reference
Voltage
29
AGND
AVDD
REFBS
35
Internal Reference
Voltage
AVSS
AVDD
REFBF
34
AGND
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3
TLC876M, TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
Terminal Functions
TERMINAL
NAME
AGND
NO.
1, 19
AIN
27
AVDD
CLK
28
CML
I/O
DESCRIPTION
Analog ground
I
Analog input
5-V analog supply
15
I
Clock input
26
O
Bypass for an internal bias point. Typically a 0.1 µF capacitor minimum is connected from this terminal to ground.
DGND
14, 20
Digital ground
DVDD
18
5-V digital supply
DRVDD
DRGND
2
3.3-V/5-V digital supply. Supply for digital input and output buffers.
13
3.3-V/5-V digital ground. Ground for digital input and output buffers.
D0 –D9
3 – 12
O
Digital data out. D0:LSB, D9:MSB
OE
16
I
Output enable. When OE = low or NC, the device is in normal operating mode. When OE = high, D0–D9 are high
impedance.
REFBF
24
I
Reference bottom force
REFBS
25
I
Reference bottom sense
REFTF
22
I
Reference top force
REFTS
21
I
Reference top sense
STBY
17
I
Standby enable. When STBY = low or NC, the device is in normal operating mode. When STBY = high, the device
is in standby mode.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, AVDD to AGND, DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 V
Reference voltage input range to AGND, VI(REFTF), VI(REFBF), VI(REFBS),
VI(REFTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
Analog input voltage range to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V
Digital output voltage range applied from external source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to DVDD
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
Operating free-air temperature range, TA: TLC876C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
TLC876I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
TLC876M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DB
1353 mW
DW
1598 mW
DERATING FACTOR
ABOVE TA = 25°C ‡
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
10.82 mW/°C
866 mW
703 mW
—
12.78 mW/°C
1023 mW
831 mW
320 mW
PW
1207 mW
9.65 mW/°C
772 mW
627 mW
—
‡ This is the inverse of the traditional junction-to-ambient thermal resistance (RΘJA). Thermal resistance is not production tested,
and values given are for informational purposes only.
4
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TLC876M, TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
recommended operating conditions
analog and reference inputs
MIN
Reference input voltage (top), VI(REFT)
VI(REFB) + 1
0
Reference input voltage (bottom), VI(REFB)
Analog input voltage, VI(AIN)
1
NOM
MAX
UNIT
3.6
4.5
V
1.6
VI(REFT) – 1
V
2
Vpp
power supply
MIN
Supply voltage
AVDD †
DVDD†
NOM
MAX
4.5
5.25
4.5
5.25
DRVDD
3
† The voltage difference between AVDD and DVDD terminals cannot exceed 0.5 V to maintain performance specifications.
UNIT
V
5.25
digital inputs
MIN
High-level input voltage, VIH
Low-level input voltage, VIL
DRVDD = 3 V
DRVDD = 5 V
2.4
DRVDD = 5.25 V
DRVDD = 3 V
4.2
NOM
MAX
UNIT
V
4
0.6
DRVDD = 5 V
DRVDD = 5.25 V
1
V
1.05
Clock period, tc (see Figure 1)
50
ns
Pulse duration, clock high, tw(CLKH)
23
25
ns
Pulse duration, clock low, tw(CLKL)
23
25
ns
TLC876C
Operating free-air temperature, TA
0
70
TLC876I
–40
85
TLC876M
–55
125
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• DALLAS, TEXAS 75265
°C
5
TLC876M, TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
electrical characteristics at AVDD = DVDD = 5 V, DRVDD = 3.3 V, VI(REFT) = 3.6 V, VI(REFB) = 1.6 V,
fCLK = 20 MSPS (unless otherwise noted)
power supply
PARAMETER
IDD
Operating supply current
PD
TEST CONDITIONS
AVDD†
DVDD†
DRVDD
MIN
Power dissipation
PD(STBY)
Standby power
STBY = High
TYP
MAX
17
25
mA
2.7
5
mA
25
100
µA
mW
107
150
CLK running
45
85
CLK inhibited at VDD or 0 V
15
35
UNIT
mW
† The voltage difference between AVDD and DVDD terminals cannot exceed 0.5 V to maintain performance specifications.
digital logic inputs
PARAMETER
TEST CONDITIONS
MIN
IIH
IIH
High-level input current, STBY, OE
DVDD = 5 V
High-level input current, all other inputs
DVDD = 5 V
IIL
IIL(CLK)
Low-level input current
DVDD = 5V
–50
Low-level input current, CLK
DVDD = 5V
–10
Ci
Input capacitance
TYP
MAX
UNIT
1.9
mA
10
µA
50
µA
10
µA
5
pF
logic outputs
PARAMETER
VOH
High-level output voltage
TEST CONDITIONS
IOH = 50 µA
IOH = 0.5 mA
VOL
Low-level output voltage
IOL = 50 µA
IOL = 0.6 mA
Co
Output capacitance
IOZ
High-impedance-state output current
6
MIN
DRVDD = 3 V
DRVDD = 5 V
2.4
DRVDD = 5 V
DRVDD = 3.6 V
2.4
TYP
MAX
V
3.8
0.7
DRVDD = 5.25 V
DRVDD = 5.25 V
1.05
–10
• DALLAS, TEXAS 75265
V
0.4
5
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UNIT
pF
10
µA
TLC876M, TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
operating characteristics at AVDD = DVDD = 5 V, DRVDD = 3.3 V, VI(REFT) = 3.6 V, VI(REFB) = 1.6 V,
fCLK = 20 MSPS (unless otherwise noted)
dc accuracy
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Integral nonlinearity (INL)
± 1.5
Differential nonlinearity (DNL) (see Note 1)
± 0.5
Offset error
–0.4
%FSR
Gain error
0.2
%FSR
