TLIN1028-Q1
SLLSEX4A – AUGUST 2019 – REVISEDTLIN1028-Q1
OCTOBER 2020
SLLSEX4A – AUGUST 2019 – REVISED OCTOBER 2020
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TLIN1028-Q1 Automotive LIN 125-mA System Basis Chip (SBC)
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 (Grade 1): Qualified for automotive
applications
Local interconnect network (LIN) physical layer
specification ISO/DIS 17987–4 compliant and
conforms to SAE J2602 recommended practice for
LIN
Functional Safety-Capable
– Documentation available to aid functional safety
system design
Supports 12-V applications
Wide operating ranges
– ±58 V LIN bus fault protection
– LDO output supporting 3.3 V or 5 V
– Sleep mode: Ultra-low current
consumption allows wake-up event from:
• LIN bus or local wake through EN pin
– Power-up and down glitch-free operation
Protection features:
– ESD protection, VSUP under-voltage protection
– TXD dominant time out (DTO) protection,
Thermal shutdown
– Unpowered node or ground disconnection failsafe at system level
VCC sources up to 125 mA with DRB and DDA
package
Available in SOIC (8) and HSOIC (8) packages,
and leadless VSON (8) package with improved
automated optical inspection (AOI) capability
Body electronics and lighting
Hybrid, electric & powertrain systems
Automotive infotainment and cluster
Appliances
3 Description
The TLIN1028-Q1 is a local interconnect network
(LIN) physical layer transceiver, compliant to LIN 2.2A
ISO/DIS 17987–4 standards, with an integrated low
dropout (LDO) voltage regulator.
This LIN system basis chip (SBC) reduces system
complexity by providing a 3.3 V or 5 V rail with up to
70 mA (D) or 125 mA (DRB and DDA) of current to
power microprocessors, sensors or other devices.
The TLIN1028-Q1 has an optimized current-limited
wave-shaping driver which reduces electromagnetic
emissions (EME). The TLIN1028-Q1 converts the LIN
protocol data stream on the TXD input into a LIN bus
signal. The receiver converts the data stream to logiclevel signals that are sent to the microprocessor
through the open-drain RXD pin.
Device Information
PACKAGE(1)
PART NUMBER
BODY SIZE (NOM)
TLIN1028D-Q1
SOIC (8)
4.90 mm x 3.91 mm
TLIN1028DDA-Q1
HSOIC (8)
4.90 mm x 3.91 mm
TLIN1028DRB-Q1
VSON (8)
3.00 mm x 3.00 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
spacer
spacer
VBAT
VBAT
Leader Node
Follower Node
10 µF
10 µF
VSUP
Vcc
VDD
EN
2
Leader Node
Pull-up
MCU w/o
pullup
Low
Power
MCU
4
5
EN
LIN
LIN Bus
Low
Power
MCU
6
7
1
8
100 nF
VDD I/O
4
LIN Controller
Or
SCI/UART
5
nRST
LIN
LIN Bus
220 pF
RXD
TXD
GND
3,PAD
2
I/O
MCU w/o
pullup
220 pF
RXD
TXD
GND
VDD
1 kQ
VDD I/O
LIN Controller
Or
SCI/UART
VSUP
Vcc
100 nF
1
8
I/O
6
7
3,PAD
nRST
Simplified Schematics, Leader Node(1)
Simplified Schematics, Follower Node(2)
1. Leader represents industry norm ‘master’.
2. Follower represents industry norm ‘slave’.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
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Incorporated
intellectual
property
matters
and other important disclaimers. PRODUCTION DATA.
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SLLSEX4A – AUGUST 2019 – REVISED OCTOBER 2020
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings ....................................... 4
7.2 ESD Ratings .............................................................. 4
7.3 ESD Ratings, IEC Specification ................................. 4
7.4 Recommended Operating Conditions ........................5
7.5 Thermal Information ...................................................5
7.6 Power Supply Characteristics .................................... 6
7.7 Electrical Charateristics ............................................. 8
7.8 AC Switching Characteristics ................................... 11
7.9 Typical Characteristics.............................................. 12
8 Parameter Measurement Information.......................... 14
8.1 Test Circuit: Diagrams and Waveforms.....................14
9 Detailed Description......................................................23
9.1 Overview................................................................... 23
9.2 Functional Block Diagram......................................... 23
9.3 Feature Description...................................................23
9.4 Device Functional Modes..........................................27
10 Application and Implementation................................ 31
10.1 Application Information........................................... 31
10.2 Typical Application.................................................. 31
11 Power Supply Recommendations..............................36
12 Layout...........................................................................37
12.1 Layout Guidelines................................................... 37
12.2 Layout Example...................................................... 38
13 Device and Documentation Support..........................39
13.1 Documentation Support.......................................... 39
13.2 Related Links.......................................................... 39
13.3 Receiving Notification of Documentation Updates..39
13.4 Support Resources................................................. 39
13.5 Trademarks............................................................. 39
13.6 Electrostatic Discharge Caution..............................40
13.7 Glossary..................................................................40
14 Mechanical, Packaging, and Orderable
Information.................................................................... 40
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (August 2019) to Revision A (July 2020)
Page
• Changed the document status From: Advanced Information To: Production data ............................................ 1
• Added Feature: Functional Safety-Capable........................................................................................................1
2
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5 Description (continued)
Ultra-low current consumption is possible using the sleep mode which allows wake up via LIN bus or EN pin.
The LIN bus has two states: dominant state (voltage near ground) and recessive state (voltage near battery). In
the recessive state, the LIN bus is pulled high by the internal pull-up resistor (45 kΩ) and a series diode. No
external pull-up components are required for follower node applications. Leader node applications require an
external pull-up resistor (1 kΩ) plus a series diode per the LIN specification.
6 Pin Configuration and Functions
VSUP
1
8
VCC
EN
2
7
nRST
GND
3
6
TX D
LIN
4
5
RX D
VSUP
1
EN
2
GND
3
LIN
4
Th ermal
Pad
8
VCC
7
nRST
6
TX D
5
RX D
No t to scale
Figure 6-1. D Package, 8-Pin (SOIC), Top View
No t to scale
Figure 6-2. DRB Package, 8-Pin (VSON), Top View
VSUP
1
EN
2
8
VCC
7
nRST
6
TX D
5
RX D
Th ermal
GND
3
LIN
4
Pad
No t to scale
Figure 6-3. DDA Package, 8-Pin (HSOIC), Top View
Table 6-1. Pin Functions
PIN
NO.
(1)
(2)
(3)
NAME
TYPE(1)
DESCRIPTION
1
VSUP
2
EN
HV Supply In Device supply voltage (connected to battery in series with external reverse-blocking diode)
3
GND
4
LIN
HV I/O
5
RXD
DO
RXD output (open-drain) interface reporting state of LIN bus voltage
6
TXD
DI
TXD input interface to control state of LIN output
7
nRST
DO
Reset output (active low)
8
VCC
DI
Enable input
GND
Ground (2) (3)
Supply Out
LIN bus single-wire transmitter and receiver
Output voltage from integrated LDO
HV - High Voltage, DI - Digital Input, DO - Digital Output, HV I/O - High Voltage Input/Output
When the thermal pad is present, it must be soldered to ground plane.
If the DDA package is placed onto a D package footprint without the thermal pad soldered down, expect the performance to match the
D package and not the DDA package.
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7 Specifications
7.1 Absolute Maximum Ratings
(1)
MIN
MAX
UNIT
VSUP
Supply voltage range
–0.3
42
V
VLIN
LIN Bus input voltage
–58
58
V
VCC50
Regulated 5 V Output Supply
–0.3
6
V
VCC33
Regulated 3.3 V Output Supply
–0.3
4.5
V
VnRST
Reset output voltage
–0.3
VCC + 0.3
V
VLOGIC_INPUT
Logic input voltage
–0.3
6
V
VLOGIC_OUTPUT
Logic output voltage
–0.3
IVCC
VCC supply current(2)
6
V
300
mA
IO
Digital pin output current
–8
8
mA
IO(nRST_RXD)
Reset and RXD open-drain output current
–5
5
mA
TJ
Junction temperature
–40
165
°C
Tstg
Storage temperature range
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
Device will enter thermal shutdown prior to hitting this limit. If the limit is reached the device may sustain permanent damage.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM) classification level H2: VSUP, LIN, and
WAKE with respect to ground
±8000
Human body model (HBM) classification level 3A: all other pins, per
AEC Q100-002(1)
±4000
Charged device model (CDM)
classification level C5, per AEC Q100-011
±750
All pins
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 ESD Ratings, IEC Specification
V(ESD)
V(ESD)
Electrostatic discharge per IEC 62228-2
VSUP terminal to GND
(1),
LIN,
Powered electrostatic discharge per SAE
J2962-1(3)
VALUE
UNIT
Contact discharge
±15000
V
V
Indirect ESD discharge
±15000
Contact discharge
±8000
Air discharge
±25000
Pulse 1
4
-100
Transient
ISO 7637-2 and IEC 62215-3 transients per IEC
62228-1(2)
Pulse 2a
75
Pulse 3a
-150
Pulse 3b
100
Transient
ISO 7637 slow transients pulse
Per SAE J2962-1(4)
30
(1)
(2)
(3)
V
V
V
IEC 62228-2 ESD testing performed at third party. Different system-level configurations may lead to different results.
ISO 7637 is a system-level transient test. Different system-level configurations may lead to different results.
SAE J2962-1 Testing performed at third party US3 approved EMC test facility.
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(4)
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ISO 7637 is a system-level transient test. Results given here are specific to the SAE J2962-1 Test specification conditions. Different
system-level configurations may lead to different results.
7.4 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VSUP
Supply voltage
5.5
28
V
VLIN
LIN bus input voltage
0
28
V
VLOGIC5
Logic pin voltage
0
5.25
V
VLOGIC33
Logic pin voltage
0
3.465
V
IOH(DO)
Digital terminal HIGH level output current
IOL(DO)
Digital terminal LOW level output current
-2
mA
2
mA
C(VSUP)
VSUP supply capacitance
100
nF
C(VCC)
VCC supply capacitance; 20 µA to full load
1.5
µF
C(VCC)
VCC supply capacitance; no load to full load
ESRCO
Output ESR requirements
10
µF
0.001
2
Ω
7.5 Thermal Information
TLIN1028
THERMAL METRIC(1)
RθJA
D
DRB
DDA
UNIT
8 PINS
8 PINS
8 PINS
Junction-to-ambient thermal resistance
119.4
45.7
40.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
51.5
49.2
60.5
°C/W
RθJB
Junction-to-board thermal resistance
64.9
18.9
15.6
°C/W
ψJT
Junction-to-top characterization parameter
9.6
0.7
4.0
°C/W
ψJB
Junction-to-board characterization parameter
63.7
18.8
15.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
2.7
4.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.6 Power Supply Characteristics
parameters valid over –40℃ ≤ TJ ≤ 150 ℃ range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Device is operational beyond the LIN
defined nominal supply voltage range.
See Figure 8-1 and Figure 8-2
5.5
36
V
Normal and Standby Modes: Ramp
VSUP while LIN signal is a 10 kHz
square wave with 50 % duty cycle and
swing between 5.5 V ≤ VLIN ≤ 28 V.
See Figure 8-1 and Figure 8-2
5.5
28
V
Sleep Mode
5.5
28
V
3.5
4.2
V
2.1
2.7
V
SUPPLY VOLTAGE AND CURRENT
Operational supply voltage (ISO/DIS
17987 Param 10)(2)
VSUP
Nominal supply voltage (ISO/DIS
17987 Param 10)(2)
VSUP
UVSUPR
Under voltage VSUP threshold
Ramp Up
UVSUPF
Under voltage VSUP threshold
Ramp Down
UVHYS
Delta hysteresis voltage for VSUP
under voltage threshold
ISUP
Transceiver and LDO supply current
(D Package)
Transceiver normal mode dominant
plus LDO output
80
mA
ISUP
Transceiver and LDO supply current
(DRB and DDA Packages)
Transceiver normal mode dominant
plus LDO output
135
mA
ISUPTRXDOM
Supply current transceiver only
1.8
1.5
Normal Mode: EN = VCC, bus
dominant: total bus load where RLIN ≥
500 Ω and CLIN ≤ 10 nF
1.2
5
mA
Standby Mode: EN = 0 V, bus
dominant: total bus load where RLIN ≥
500 Ω and CLIN ≤ 10 nF
1
2.1
mA
450
775
µA
38
55
Normal Mode: EN = VCC,
Bus recessive: LIN = VSUP,
ISUPTRXREC
Supply current transceiver only(3)
Standby Mode: EN = 0 V, LIN =
recessive = VSUP, IOH from processor ≤
1 µA
µA
Added Standby Mode current through
the RXD pull-up resistor with a value
of 100 kΩ: EN = 0 V, LIN = recessive =
VSUP, RXD = GND(1)
ISUPTRXSLP
V
55
Sleep mode supply current transceiver 5.5 V < VSUP ≤ 28 V, LIN = VSUP, EN =
only
0 V, TXD and RXD floating
17
33
µA
REGULATED OUTPUT VCC
6
VCC
Regulated output (D package)
VSUP = 5.5 to 28 V, ICC = 1 to 70 mA
–2
2
%
VCC
Regulated output (DRB and DDA
package)
VSUP = 5.5 to 28 V, ICC = 1 to 125 mA
–2
2
%
∆VCC(∆VSUP)
Line regulation
VSUP = 5.5 to 28 V, ΔVCC, ICC = 10 mA
50
mV
∆VCC(∆VSUPL)
Load regulation (DRB and DDA
package)
ICC = 1 to 125 mA, VSUP = 14 V, ΔVCC
50
mV
∆VCC(∆VSUPL)
Load regulation (D package)
ICC = 1 to 70 mA, VSUP = 14 V, ΔVCC
50
mV
VDROP
Dropout voltage (5 V LDO) (DRB and
DDA package)
VSUP – VCC, ICC = 125 mA;
300
600
mV
VDROP
Dropout voltage (5 V LDO) (D
package)
VSUP – VCC, ICC = 70 mA;
300
600
mV
VDROP
Dropout voltage (3.3 V LDO) (DRB
and DDA package)
VSUP – VCC, ICC = 125 mA;
350
700
mV
VDROP
Dropout voltage (3.3 V LDO) (D
package)
VSUP – VCC, ICC = 70 mA;
350
700
mV
UVCC5R
Under voltage 5 V VCC threshold
Ramp Up
4.7
4.86
V
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7.6 Power Supply Characteristics (continued)
parameters valid over –40℃ ≤ TJ ≤ 150 ℃ range (unless otherwise noted)
PARAMETER
UVCC5F
TEST CONDITIONS
Under voltage 5 V VCC threshold
Ramp Down
(3)
UVCC33R
Under voltage 3.3 V VCC threshold
UVCC33F
Under voltage 3.3 V VCC threshold(3)
tDET(UVCC)
VCC undervoltage deglitch time. An
UVCC event will not be recognized
CnRST = 20pF
unless the duration is longer than this.
MIN
TYP
4.2
4.45
2.5
2.75
Ramp Up
Ramp Down
2.9
MAX
UNIT
V
3.1
V
V
1
15
µs
(3)
ICCOUT
Output current (D Package)
VCC in regulation with 12 V VSUP
0
70
mA
ICCOUT
Output current (DRB and DDA
package)
VCC in regulation with 12 V VSUP
0
125
mA
ICCOUTL
Output current limit
VCC short to ground
275
mA
PSRR
Power supply rejection ratio(3)
VRIP = 0.5 VPP, Load = 10 mA, ƒ = 100
Hz, CO = 10 μF
TSDR
Thermal shutdown temperature
Internal junction temperature - rising
TSDF
Thermal shutdown temperature
Internal junction temperature - falling
TSDHYS
Thermal shutdown hysteresis
(1)
(2)
(3)
60
dB
165
°C
150
10
°C
°C
RXD pin is an open-drain output. In standby mode RXD is pulled low which has the device pulling current through VSUP through the
pull-up resisitor to VCC. The value of the pull-up resistor impacts the standby mode current. A 10 kΩ resistor value can add as much
as 500 µA of current.
Operational supply voltage and nominal supply voltage are in relationship to the LIN transceiver. A VSUP above 28 V means the
device will function but may not meet the rest of the parametric data while the nominal range means the device will meet the
parametric data minus any differences provided in the test conditions.
Specified by design
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7.7 Electrical Charateristics
parameters valid over –40℃ ≤ TJ ≤ 150 ℃ range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.2
VCC
RXD OUTPUT TERMINAL (OPEN-DRAIN)
VOL
Based upon a 2 kΩ to 10 kΩ external
pull-up to VCC
Output low voltage
IOL
Low-level output current, open-drain
LIN = 0 V, RXD = 0.4 V
1.5
ILKG
Leakage current, high-level
LIN = VSUP, RXD = VCC
–5
mA
0
5
µA
0.8
V
TXD INPUT TERMINAL
VIL
Low-level input voltage
VIH
High-level input voltage
IIH
High-level input leakage current
RTXD
Internal pull-up resistor value
–0.3
2
TXD = high
5.5
V
–5
0
5
µA
125
350
800
kΩ
LIN TERMINAL (REFERENCED TO VSUP)
VOH
High-level output voltage(1)
LIN recessive, TXD = high, IO = 0 mA,
VSUP = 5.5 V to 36 V
VOL
Low-level output voltage(1)
LIN dominant, TXD = low, VSUP = 5.5
V to 36 V
VIH
High-level input voltage(1)
LIN recessive, TXD = high, IO = 0 mA,
VSUP = 5.5 V to 36 V
VIL
Low-level input voltage(1)
VSUP_NON_OP
VSUP where impact of recessive LIN bus <
5% (ISO/DIS 17987 Param 11)
0.85
VSUP
0.2
VSUP
0.47
0.6
VSUP
LIN dominant, TXD = low, VSUP = 5.5
V to 36 V
0.4
0.53
VSUP
TXD & RXD open, VLIN = 5.5 V to 42
V, Bus Load = 60 kΩ + diode and 1.1
kΩ + diode
–0.3
42
V
I BUS_LIM
TXD = 0 V, VLIN = 36 V, RMEAS = 440
Limiting current (ISO/DIS 17987 Param 12) Ω, VSUP = 36 V,
VBUSdom < 4.518 V; Figure 8-6
40
200
mA
I BUS_PAS_dom
Receiver leakage current, dominant
(ISO/DIS 17987 Param 13)
VLIN = 0 V, VSUP = 12 V Driver off/
recessive, RMEAS = 499 Ω; Figure 8-7
–1
I BUS_PAS_rec1
Receiver leakage current, recessive
(ISO/DIS 17987 Param 14)
VLIN ≥ VSUP, 5.5 V ≤ VSUP ≤ 36 V
Driver off, RMEAS = 1 kΩ; Figure 8-8
I BUS_PAS_rec2
Receiver leakage current, recessive
(ISO/DIS 17987 Param 14)
VLIN = VSUP, Driver off, RMEAS = 1 kΩ;
Figure 8-8
I BUS_NO_GND
Leakage current, loss of ground (ISO/DIS
17987 Param 15)
GND = VSUP, VSUP = 12 V, 0 V ≤ VLIN ≤
28 V, RMEAS = 1 kΩ; Figure 8-9
IBUS_NO_BAT
Leakage current, loss of supply (ISO/DIS
17987 Param 16)
0 V ≤ VLIN ≤ 28 V, VSUP = GND, RMEAS
= 10 kΩ; Figure 8-10
VBUSdom
Low-level input voltage (ISO/DIS 17987
Param 17)
LIN dominant (including LIN dominant
for wake up); Figure 8-3, Figure 8-4
VBUSrec
High-level input voltage (ISO/DIS 17987
Param 18)
LIN recessive; Figure 8-3, Figure 8-4
VBUS_CNT
Receiver center threshold (ISO/DIS 17987
Param 19)
VBUS_CNT = (VIL + VIH)/2; Figure
8-3, Figure 8-4
VHYS
Hysteresis voltage (ISO/DIS 17987 Param
20)(2)
VHYS = (VIL - VIH); Figure 8-3, Figure
8-4
VSERIAL_DIODE
Serial diode LIN term pull-up path (ISO/DIS
By design and characterization
17987 Param 21)
0.4
0.7
1.0
V
RPU
Internal Pull-up resistor to VSUP (ISO/DIS
17987 Param 26)
Normal and Standby modes
20
45
60
kΩ
IRSLEEP
Pull-up current source to VSUP
Sleep mode, VSUP = 12 V, LIN = GND
–2
µA
CLINPIN
Capacitance of the LIN pin (6)
25
pF
90
mA
20
µA
–8
8
µA
–1
1
mA
8
µA
0.4
0.6
0.475
VSUP
0.5
0.07
–20
VSUP
0.525
VSUP
0.175
VSUP
EN INPUT TERMINAL
8
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7.7 Electrical Charateristics (continued)
parameters valid over –40℃ ≤ TJ ≤ 150 ℃ range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIH
High-level input voltage
VIL
Low-level input voltage
VHYS
Hysteresis voltage
By design and characterization
IIL
Low-level input current
EN = Low
REN
Internal pull-down resistor
MIN
TYP
2
MAX
5.5
UNIT
V
–0.3
0.8
V
30
500
mV
–6
0
6
µA
125
350
800
kΩ
6
µA
0.2
VCC
nRST TERMINAL (OPEN DRAIN OUTPUT)
ILKG
Leakage current, high-level
LIN = VSUP, nRST = VCC
VOL
Low-level output voltage
Based upon external pull up to VCC
IOL
Low-level output current, open-drain
LIN = 0 V, nRST = 0.4 V
–6
1.5
mA
DUTY CYCLE CHARACTERISTICS
Duty Cycle 1 (ISO/DIS 17987 Param 27
and J2602 Normal battery)(3) (4)
THREC(MAX) = 0.744 x VSUP,
THDOM(MAX) = 0.581 x VSUP,
VSUP = 7 V to 18 V, tBIT = 50/52 µs,
D1 = tBUS_rec(min)/(2 x tBIT) (See Figure
8-11, Figure 8-12)
Duty Cycle 2 (ISO/DIS 17987 Param 28
and J2602 Normal battery)(3) (4)
THREC(MIN) = 0.422 x VSUP,
THDOM(MIN) = 0.284 x VSUP, VSUP = 7.6
V to 18 V,
tBIT = 50/52 µs (20 kbps), D2 = t
BUS_rec(MAX)/(2 x tBIT) (See Figure 8-11,
Figure 8-12)
Duty Cycle 3 (ISO/DIS 17987 Param 29
and J2602 Normal battery)(3) (4)
THREC(MAX) = 0.778 x VSUP, TH
DOM(MAX) = 0.616 x VSUP,
VSUP = 7 V to 18 V, tBIT = 96 µs (10.4
kbps),
D3 = tBUS_rec(min)/(2 x tBIT) (See Figure
8-11, Figure 8-12)
D4
Duty Cycle 4 (ISO/DIS 17987 Param 30
and J2602 Normal battery)(3) (4)
THREC(MIN) = 0.389 x VSUP,
THDOM(MIN) = 0.251 x VSUP,
VSUP = 7.6 V to 18 V, tBIT = 96 µs (10.4
kbps),
D4 = tBUS_rec(MAX)/(2 x tBIT) (See
Figure 8-11, Figure 8-12)
D1LB
Duty Cycle 1
J2602 Low battery (4) (5)
THREC(MAX) = 0.665 x VSUP, TH
DOM(MAX) = 0.499 x VSUP, VSUP = 5.5 V
to 7 V, tBIT = 50/52 µs, D1LB = t
BUS_rec(min)/(2 x tBIT) (See Figure 8-11,
Figure 8-12)
D2LB
Duty Cycle 2
J2602 Low battery (4) (5)
T THREC(MIN) = 0.496 x VSUP, TH
= 0.361 x VSUP, VSUP = 6.1 V
to 7.6 V, tBIT = 50/52 µs, D2LB = t
BUS_rec(MAX)/(2 x tBIT) (See Figure 8-11,
Figure 8-12)
Duty Cycle 3
J2602 Low battery (4) (5)
THREC(MAX) = 0.665 x VSUP, TH
DOM(MAX) = 0.499 x VSUP, VSUP = 5.5 V
to 7 V, tBIT = 96 µs, D3LB = t
BUS_rec(min)/(2 x tBIT) (See Figure 8-11,
Figure 8-12)
Duty Cycle 4
J2602 Low battery (4) (5)
T THREC(MIN) = 0.496 x VSUP, TH
= 0.361 x VSUP, VSUP = 6.1 V
to 7.6 V, tBIT = 96 µs, D4LB = t
BUS_rec(MAX)/(2 x tBIT) (See Figure 8-11,
Figure 8-12)
D1
D2
D3
D3LB
D4LB
(1)
(2)
0.396
0.581
0.417
0.59
0.396
DOM(MIN)
DOM(MIN)
0.581
0.417
0.59
SAE J2602 loads include: leader node: 5.5 nF; 4 kΩ and for a follower node: 5.5 nF; 875 Ω
VHYS is defined for both ISO 17987 and SAE J2602-1.
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(3)
(4)
(5)
(6)
10
ISO 17987 loads include 1 nF; 1 kΩ/ 6.8nF; 660 Ω/ 10 nF; 500 Ω; with tBIT values of 50 µs and 96 µs
SAE J2602 loads include: leader node: 5.5 nF; 4 kΩ/ 899 pF; 20 kΩ and for a follower node: 5.5 nF; 875 Ω/ 899 pF; 900 Ω; with tBIT
values of 52 µs and 96 µs
ISO 17987 does not have a low battery specification. Using the ISO 17987 loads these low battery duty cycle parameters are covered
for tBIT values of 50 µs and 96 µs
Specified by design
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7.8 AC Switching Characteristics
parameters valid over –40℃ ≤ TJ ≤ 150 ℃ range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DEVICE SWITCHING CHARACTERISTICS
trx_pdr
trx_pdf
Receiver rising/falling propagation delay
time (ISO/DIS 17987 Param 31)
RRXD = 2.4 kΩ, CRXD = 20 pF
(See Figure 8-13, Figure 8-14 and
Figure 8-18)
trs_sym
Symmetry of receiver propagation delay
time Receiver rising propagation delay
time (ISO/DIS 17987 Param 32)
Rising edge with respect to falling
edge, (trx_sym = trx_pdf – trx_pdr), RRXD
= 2.4 kΩ, CRXD = 20 pF (Figure 8-13,
Figure 8-14 and Figure 8-18)
tLINBUS
LIN wakeup time (minimum dominant time See Figure 8-17, Figure 9-3 and
on LIN bus for wakeup)
Figure 9-4
tCLEAR
Time to clear false wake-up prevention
logic if LIN bus had a bus stuck dominant
fault (recessive time on LIN bus to clear
bus stuck dominant fault)
tTXD_DTO
Dominant state time out
tEN
Enable pin deglitch time(1)
Time of enable pin state change
before initiating mode change or
sampling TXD pin: See Figure 8-15
–2
6
µs
2
µs
25
100
150
µs
8
17
50
µs
20
34
80
ms
12
µs
tMODE_CHANGE
Mode change delay time from normal
mode to sleep or standby modes
Time to change from normal mode to
sleep or standby after TXD pin
sampling after EN pin set low: See
Figure 8-15
20
µs
tMODE_CHANGE
Time to change from sleep mode to
Mode change delay time from sleep mode normal mode through EN pin and not
to normal mode
due to a wake event; RXD pulled up
to VCC: See Figure 8-15
400
µs
tNOMINT
Normal mode initialization time
Time for normal mode to initialize and
data on RXD pin to be valid after tEN:
See Figure 8-15
35
µs
tPWR
Power-up time
Upon power up, time it takes for
nRST to go high
2
ms
(1)
See Figure 9-4
3
Specified by design
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7.9 Typical Characteristics
80
130
75
125
70
120
65
115
110
LDO ICC (mA)
ICC (mA)
60
55
50
45
105
100
95
40
-40°C
25°C
85°C
105°C
115°C
125°C
35
30
25
90
-40°C
25°C
85°C
105°C
125°C
85
80
20
75
0
3
6
9
12
15
18
21
24
27
30
VSUP (V)
Package = D
5
VCC = 3.3 V
10
12.5
Package = DRB
Temp = Ambient
15
17.5
VSUP (V)
20
VCC = 3.3 V
22.5
25
27.5
30
Temp = Ambient
Figure 7-2. ICC vs VSUP vs Temperature
Figure 7-1. ICC vs VSUP vs Temperature
130
80
128
75
126
70
124
122
65
120
60
118
55
ICC (mA)
LDO ICC (mA)
7.5
D001
116
114
112
50
45
40
110
108
104
102
-40°C
25°C
85°C
105°C
115°C
125°C
35
-40°C
25°C
85°C
105°C
125°C
106
30
25
20
100
4
6
8
10
Package = DDA
12
14
16
18
VSUP (V)
20
VCC = 3.3 V
22
24
26
28
3
30
Temp = Ambient
6
9
12
Package = D
Figure 7-3. ICC vs VSUP vs Temperature
15
18
VSUP (V)
VCC = 5 V
21
24
27
30
33
D006
Temp = Ambient
Figure 7-4. ICC vs VSUP vs Temperature
130
130
120
120
110
110
100
100
LDO ICC (mA)
LDO ICC (mA)
90
90
80
70
80
70
60
60
50
-40°C
25°C
85°C
105°C
125°C
50
40
30
30
20
5
7.5
10
Package = DRB
12.5
15
17.5
VSUP (V)
VCC = 5 V
20
22.5
25
Temp = Ambient
Figure 7-5. ICC vs VSUP vs Temperature
12
-40°C
25°C
85°C
105°C
125°C
40
27.5
30
4
6
8
Package = DDA
10
12
14
VCC = 5 V
16
18
VSUP (V)
20
22
24
26
28
30
Temp = Ambient
Figure 7-6. ICC vs VSUP vs Temperature
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22
20
19
20
18
17
18
ISUP (PA)
ISUP (PA)
16
15
14
16
14
13
11
10
-40°C
25°C
85°C
105°C
115°C
125°C
12
-40°C
25°C
85°C
105°C
115°C
125°C
12
10
9
8
5
7.5
10
Package = D
12.5
15
17.5
VSUP (V)
20
22.5
25
27.5
30
5
7.5
10
12.5
15
D003
VCC = 3.3 V
Temp = Ambient
Package = DRB
17.5
VSUP (V)
20
22.5
25
27.5
30
D013
VCC = 3.3 V
Temp = Ambient
Figure 7-7. Sleep Mode Current Across VSUP and
Temperature
Figure 7-8. Sleep Mode Current Across VSUP and
Temperature
22
20
19
20
18
17
18
ISUP (PA)
ISUP (PA)
16
16
14
15
14
13
12
-40°C
25°C
85°C
105°C
115°C
125°C
12
10
10
9
8
8
5
7.5
10
Package = DDA
12.5
15
17.5
VSUP (V)
20
22.5
25
27.5
30
5
7.5
10
12.5
15
D023
VCC = 3.3 V
Temp = Ambient
Package = D
Figure 7-9. Sleep Mode Current Across VSUP and
Temperature
22
22
20
20
18
18
16
16
14
12
20
22.5
25
27.5
30
D008
VCC = 5 V
Temp = Ambient
14
-40°C
25°C
85°C
105°C
115°C
125°C
12
-40°C
25°C
85°C
105°C
115°C
125°C
10
17.5
VSUP (V)
Figure 7-10. Sleep Mode Current Across VSUP and
Temperature
ISUP (PA)
ISUP (PA)
-40°C
25°C
85°C
105°C
115°C
125°C
11
10
8
8
5
7.5
10
Package = DRB
12.5
15
17.5
VSUP (V)
20
VCC = 5 V
22.5
25
27.5
30
5
7.5
10
12.5
15
D018
Temp = Ambient
Figure 7-11. Sleep Mode Current Across VSUP and
Temperature
Package = DDA
VCC = 5 V
17.5
VSUP (V)
20
22.5
25
27.5
30
D028
Temp = Ambient
Figure 7-12. Sleep Mode Current Across VSUP and
Temperature
Note
For the LDO ICC vs VSUP vs Temperature typical curves the data was collected on a high-k EVM board
utilizing a forced air system. The curves show performance based upon thermal resistance RθJB.
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8 Parameter Measurement Information
8.1 Test Circuit: Diagrams and Waveforms
5
VCC
RXD
8
VCC
2
1
VSUP
EN
7
4
LIN
6
3
GND
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VPS
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 Hz
Jitter: < 25 ns
Measurement Tools
O-scope:
DMM
Figure 8-1. Test System: Operating Voltage Range with RX and TX Access
Trigger Point
Delta t = + 5 µs (tBIT
= 50 µs)
RX
2 * tBIT = 100 µs (20 kBaud)
Figure 8-2. RX Response: Operating Voltage Range
Period T = 1/f
LIN Bus Input
Amplitude
(signal range)
Frequency: f = 20 Hz
Symmetry: 50%
Figure 8-3. LIN Bus Input Signal
14
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5
VCC
RXD
8
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VCC
2
1
VPS
VSUP
EN
7
4
LIN
6
Pulse Generator
tR/tF: Square Wave: < 20 ns
:
tR/tF Triangle Wave: < 40ns
Frequency: 20 Hz
Jitter: < 25 ns
3
GND
Measurement Tools
O-scope:
DMM
Figure 8-4. LIN Receiver Test with RX access
5
VCC
8
VCC
Power Supply 1
Resolution: 10mV/ 1mA
Accuracy: 0.2%
1
2
EN
VSUP
VPS1
D
3
6
4
LIN
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
3
GND
RBUS
VPS2
Measurement Tools
O-scope:
DMM
Figure 8-5. VSUP_NON_OP Test Circuit
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5
VCC
1
VCC
2
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VPS
7
VSUP
EN
7
4
RMEAS =
440
LIN
Pulse Generator
tR/tF: Square Wave: < 20 ns
:
tR/tF Triangle Wave: < 40ns
Frequency: 20 Hz
T = 10 ms
Jitter: < 25 ns
6
3
TXD
GND
Measurement Tools
O-scope:
DMM
Figure 8-6. Test Circuit for IBUS_LIM at Dominant State (Driver on)
5
VCC
8
VCC
2
EN
7
6
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VPS
1
VSUP
4
RMEAS = 499 Ÿ
LIN
3
GND
Measurement Tools
O-scope:
DMM
Figure 8-7. Test Circuit for IBUS_PAS_dom; TXD = Recessive State VBUS = 0 V
16
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5
VCC
Power Supply 1
Resolution: 10mV/ 1mA
Accuracy: 0.2%
8
VCC
VPS1
2
1
EN
VSUP
4
7
LIN
6
GND
RMEAS
=1 kŸ
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VPS2
VPS2 2 V/s ramp
[8 V Æ 36 V]
3
V Drop across resistor
< 20 mV
Measurement Tools
O-scope:
DMM
Figure 8-8. Test Circuit for IBUS_PAS_rec
5
VCC
Power Supply 1
Resolution: 10mV/ 1mA
Accuracy: 0.2%
8
VCC
VPS1
2
EN
VSUP
1
4
7
LIN
6
GND
RMEAS
= 1 kŸ
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VPS2
3
VPS2 2 V/s ramp
[0 V Æ 36 V]
V Drop across resistor
< 1V
Measurement Tools
O-scope:
DMM
Figure 8-9. Test Circuit for IBUS_NO_GND Loss of GND
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5
VCC
8
VCC
2
1
VSUP
EN
7
LIN
6
GND
Power Supply 2
Resolution: 10mV/ 1mA
VPS Accuracy: 0.2%
RMEAS =
10 kŸ
4
VPS 2 V/s ramp
[0 V Æ 36 V]
3
V Drop across resistor
< 1V
Measurement Tools
O-scope:
DMM
Figure 8-10. Test Circuit for IBUS_NO_BAT Loss of Battery
5
VCC
8
VCC
2
EN
VSUP
VPS1
4
7
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 Hz
Jitter: < 25 ns
Power Supply 1
Resolution: 10mV/ 1mA
Accuracy: 0.2%
1
RMEAS
LIN
6
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
3
TXD
VPS2
GND
Measurement Tools
O-scope:
DMM
Figure 8-11. Test Circuit Slope Control and Duty Cycle
18
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tBIT
tBIT
RECESSIVE
TXD (Input)
DOMINANT
THREC(MAX)
Thresholds
RX Node 1
THDOM(MAX)
LIN Bus
Signal
VSUP
THREC(MIN)
Thresholds
RX Node 2
THDOM(MIN)
tBUS_REC(MIN)
tBUS_DOM(MAX)
RXD: Node 1
D1 (20 kbps)
D3 (10.4 kbps)
D = tBUS_REC(MIN)/(2 x tBIT)
tBUS_DOM(MIN)
tBUS_REC(MAX)
RXD: Node 2
D2 (20 kbps)
D4 (10.4 kbps)
D = tBUS_REC(MAX)/(2 x tBIT)
Figure 8-12. Definition of Bus Timing
VCC
2.4 kŸ
5
VCC
RXD
8
VCC
20 pF
2
1
VSUP
EN
VPS
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
4
7
LIN
3
6
GND
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 Hz
Jitter: < 25 ns
Measurement Tools
O-scope:
DMM
Figure 8-13. Propagation Delay Test Circuit
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THREC(MAX)
Thresholds
RX Node 1
THDOM(MAX)
LIN Bus
Signal
VSUP
THREC(MIN)
Thresholds
RX Node 2
THDOM(MIN)
RXD: Node 1
D1 (20 kbps)
D3 (10.4 kbps)
trx_pdr(1)
trx_pdf(1)
RXD: Node 2
D2 (20 kbps)
D4 (10.4 kbps)
trx_pdr(2)
trx_pdf(2)
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Figure 8-14. Propagation Delay
Wake Event
tMODE_CHANGE
tMODE_CHANGE
tNOMINT
tEN
EN
tEN
Can be high or low
TXD
MODE
RXD
Normal
Mirrors Bus
EN
Filter/TXD
Sampling
Window
Transition
Indeterminate Ignore
Sleep
¾
Standby
Enable
Filter
Wake Request
RXD = Low
Floating for sleep
Indeterminate Ignore
RXD
Normal
Mirrors
Bus
Can be high or low
TXD
MODE
Transition
Normal
Mirrors Bus
EN
Filter/TXD
Sampling
Window
Transition
Indeterminate Ignore
Enable
Filter
Standby
Wake Request
RXD = Low
Transition
Indeterminate Ignore
Normal
Mirrors
Bus
Figure 8-15. Mode Transitions
20
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EN
tEN
TXD
Weak Internal Pullup
Weak Internal Pullup
VSUP
LIN
RXD
Floating
MODE
Sleep
tMODE_CHANGE
+
tNOMINIT
Normal
Figure 8-16. Wakeup Through EN
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0.6 x VSUP
LIN
0.6 x VSUP
VSUP
0.4 x VSUP
0.4 x VSUP
t < tLINBUS
TXD
tLINBUS
Weak Internal Pullup
EN
RXD
MODE
Floating
Sleep
Standby
Normal
Figure 8-17. Wakeup through LIN
VSUP
100 nF
RLIN
VCC
10 µF
10 µF
EN
nRST
GND
TXD
RRXD
LIN
RXD
CLIN
CRXD
Figure 8-18. Test Circuit for AC Characteristics
22
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9 Detailed Description
9.1 Overview
The TLIN1028-Q1 LIN transceiver is a Local Interconnect Network (LIN) physical layer transceiver, compliant to
LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A and ISO/DIS 17987–4 with integrated wake-up and protection features. The
LIN bus is a single-wire, bidirectional bus that typically is used in low-speed in-vehicle networks with data rates
that range up to 20 kbps. The LIN receiver works up to 100 kbps supporting in-line programming. The device
converts the LIN protocol data stream on the TXD input into a LIN bus signal using a current-limited waveshaping driver which reduces electromagnetic emissions (EME). The receiver converts the data stream to logiclevel signals that are sent to the microprocessor through the open-drain RXD pin. The LIN bus has two states:
dominant state (voltage near ground) and recessive state (voltage near battery). In the recessive state, the LIN
bus is pulled high by the internal pull-up resistor (45 kΩ) and a series diode.
Ultra-low current consumption is possible using the sleep mode. The TLIN1028-Q1 provides two methods to
wake up from sleep mode: EN pin and LIN bus. The device integrates a low dropout voltage regulator with a
wide input from V SUP providing 5 V ±2% or 3.3 V ±2% with up to 125 mA of current depending upon system
implementation. nRST is asserted high when VCC increases above UVCC and stays high as long as VCC is above
this threshold.
9.2 Functional Block Diagram
VSUP
VCC
5.0-V or 3.3-V LDO
CNTL
POR
UV
DET
VSUP
RXD
VCC
VSUP/2
Comp
250 NŸ
Filter
nRST
45 k
Control
EN
Fault
Detection
& Protection
350 NŸ
VCC
GND
350 NŸ
TXD
LIN
Dominant
State
Timeout
DR/
Slope
CTL
Figure 9-1. Functional Block Diagram
9.3 Feature Description
9.3.1 LIN Pin
This high-voltage input or output pin is a single-wire LIN bus transmitter and receiver. The LIN pin can survive
transient voltages up to 58 V. Reverse currents from the LIN to supply (V SUP) are minimized with blocking
diodes, even in the event of a ground shift or loss of supply (VSUP).
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9.3.1.1 LIN Transmitter Characteristics
The transmitter meets thresholds and AC parameters according to the LIN specification. The transmitter is a lowside transistor with internal current limitation and thermal shutdown. During a thermal shutdown condition, the
transmitter is disabled to protect the device. There is an internal pull-up resistor with a serial diode structure to V
SUP, so no external pull-up components are required for the LIN follower node applications. An external pull-up
resistor and series diode to VSUP must be added when the device is used for a leader node application.
9.3.1.2 LIN Receiver Characteristics
The receiver characteristic thresholds are ratio-metric with the device supply pin according to the LIN
specification.
The receiver is capable of receiving higher data rates (> 100 kbps) than supported by LIN or SAEJ2602
specifications. This allows the TLIN1028-Q1 to be used for high-speed downloads at the end-of-line production
or other applications. The actual data rate achievable depends on system time constants (bus capacitance and
pull-up resistance) and driver characteristics used in the system.
9.3.1.2.1 Termination
There is an internal pull-up resistor with a serial diode structure to V SUP, so no external pull-up components are
required for the LIN follower node applications. An external pull-up resistor (1 kΩ) and a series diode to V SUP
must be added when the device is used for leader node applications as per the LIN specification.
Figure 9-2 shows a leader node configuration and how the voltage levels are defined
Simplified Transceiver
VLIN_Bus
VSUP
VSUP/2
RXD
Voltage drop across the
diodes in the pullup path
VBAT
VBattery
VSUP
Receiver
VLIN_Recessive
Filter
1k
45 kŸ
LIN
LIN Bus
VCC
350 k
TXD
GND
Transmitter
with slope control
VLIN_Dominant
t
Figure 9-2. Leader Node Configuration with Voltage Levels
9.3.2 TXD (Transmit Input)
TXD is the interface to the node processor’s LIN protocol controller that is used to control the state of the LIN
output. When TXD is low, the LIN output is dominant (near ground). When TXD is high, the LIN output is
recessive (near VSUP). See Figure 9-2. The TXD input structure is compatible with processors that use 3.3 V and
5 V VI and VO. TXD has an internal pull-up resistor. The LIN bus is protected from being stuck dominant through
a system failure driving TXD low through the dominant state time-out timer.
9.3.3 RXD (Receive Output)
RXD is the interface to the processor's LIN protocol controller, which reports the state of the LIN bus voltage. LIN
recessive (near VSUP) is represented by a high level on the RXD and LIN dominant (near ground) is represented
by a low level on the RXD pin. The RXD output structure is an open-drain output stage. This allows the device to
be used with 3.3 V and 5 V I/O processors. If the processor's RXD pin does not have an integrated pull-up, an
external pull-up resistor to the processors I and O supply voltage is required. In standby mode, the RXD pin is
driven low to indicate a wake-up request from the LIN bus from sleep mode. When going from normal mode to
24
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standby mode, the RXD pin is released and pulled-up to the voltage rail that the external pull-up resistor is
connected. A LIN bus wake event will cause the RXD pin to be pulled low indicating a wake request.
9.3.4 VSUP (Supply Voltage)
V SUP is the power supply pin. V SUP is connected to the battery through an external reverse-battery blocking
diode.
The VSUP pin is a high-voltage-tolerant pin. A decoupling capacitor with a value of 100 nF is recommended to be
connected close to this pin to improve the transient performance. If there is a loss of power at the ECU level, the
device has ultra low leakage from the LIN pin, which does not load the bus down. This is optimal for LIN systems
in which some of the nodes are unpowered (ignition supplied) while the rest of the network remains powered
(battery supplied). When VSUP drops low enough the regulated output drops out of regulation. The LIN bus works
with a V SUP as low as 5.5 V, but at a lower voltage, the performance is indeterminate and not ensured. If V SUP
voltage level drops enough, it triggers the UV SUP, and if it keeps dropping, at some point it passes the POR
threshold.
9.3.5 GND (Ground)
GND is the device ground connection. The device can operate with a ground shift as long as the ground shift
does not reduce the VSUP below the minimum operating voltage. If there is a loss of ground at the ECU level, the
device has ultra low leakage from the LIN pin, which does not load the bus down. This is optimal for LIN systems
in which some of the nodes are unpowered (ignition supplied) while the rest of the network remains powered
(battery supplied).
9.3.6 EN (Enable Input)
EN controls the operational modes of the device. When EN is high, the device is in normal operating mode
allowing a transmission path from TXD to LIN and from LIN to RXD. When EN is low, the device is put into sleep
or standby mode and there are no transmission paths available. EN has an internal pull-down resistor to ensure
the device remains in low power mode even if EN is left floating. EN should be held low until V SUP reaches the
expected system voltage level.
9.3.7 nRST (Reset Output)
The V CC pin is monitored for under voltage events. This pin is internally pulled up to V CC and when an
undervoltage event takes place, this pin is pulled low. The pin returns to V CC once the voltage on V CC exceeds
the under-voltage threshold. nRST is only dependent upon UVCC and not dependent upon the operational mode.
If UVCC takes place for longer than tDET(UVCC) nRST is pulled to ground. If a thermal shutdown event takes place,
this pin is pulled to ground.
9.3.8 VCC (Supply Output)
The V CC terminal can provide 5 V or 3.3 V with up to 125 mA to power up external devices when using high-k
boards and thermal management best practices in order to keep the virtual junction temperature below 165 °C
and avoid thermal shutdown.
9.3.9 Protection Features
The device has several protection features that are described as follows.
9.3.9.1 TXD Dominant Time Out (DTO)
During normal mode, if TXD is inadvertently driven permanently low by a hardware or software application
failure, the LIN bus is protected by the dominant state time-out timer. This timer is triggered by a falling edge on
the TXD pin. If the low signal remains on TXD for longer than tTXD_DTO , the transmitter is disabled, thus allowing
the LIN bus to return to recessive state and communication to resume on the bus. The protection is cleared and
the t TXD_DTO timer is reset by a rising edge on TXD. The TXD pin has an internal pull-up to ensure the device
fails to a known recessive state if TXD is disconnected. During this fault, the transceiver remains in normal mode
(assuming no change of state request on EN), the RXD pin reflects the LIN bus and the LIN bus pull-up
termination remains on.
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9.3.9.2 Bus Stuck Dominant System Fault: False Wake Up Lockout
The device contains logic to detect bus stuck dominant system faults and prevents the device from waking up
falsely during the system fault. Upon entering sleep mode, the device detects the state of the LIN bus. If the bus
is dominant, the wake-up logic is locked out until a valid recessive on the bus “clears” the bus stuck dominant,
preventing excessive current use. Figure 9-3 and Figure 9-4 show the behavior of this protection.
RXD
EN
LIN Bus
< tLINBUS
tLINBUS
< tLINBUS
Figure 9-3. No Bus Fault: Entering Sleep Mode with Bus Recessive Condition and Wakeup
RXD
EN
tLINBUS
tLINBUS
tLINBUS
LIN Bus
tCLEAR
< tCLEAR
Figure 9-4. Bus Fault: Entering Sleep Mode with Bus Stuck Dominant Fault, Clearing, and Wakeup
9.3.9.3 Thermal Shutdown
The LIN transmitter is protected by current-limiting circuit; however, if the junction temperature of the device
exceeds the thermal shutdown threshold, the device puts the LIN transmitter into the recessive state and turns
off the V CC regulator. The nRST pin is pulled to ground during a TSD event. Once the over-temperature fault
condition has been removed and the virtual junction temperature has cooled beyond the hysteresis temperature,
the transmitter is re-enabled. During this fault the device enters a TSD off mode. Once the junction temperature
cools, the device enters standby mode as per the state diagram.
9.3.9.4 Under Voltage on VSUP
The device contains a power-on reset circuit to avoid false bus messages during under voltage conditions when
VSUP is less than UVSUP.
9.3.9.5 Unpowered Device and LIN Bus
In automotive applications, some LIN nodes in a system can be unpowered (ignition supplied) while others in the
network remain powered by the battery. The device has extremely low unpowered leakage current from the bus,
so an unpowered node does not affect the network nor load it down.
26
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9.4 Device Functional Modes
The TLIN1028-Q1 has three functional modes of operation: normal, sleep, and standby. The next sections
describes these modes as well as how the device moves between the different modes. Figure 9-5 graphically
shows the relationship while Table 9-1 shows the state of pins.
Table 9-1. Operating Modes
Mode
EN
RXD
LIN BUS
Termination
Sleep
Low
Floating
Weak Current pull-up
Off
Ground
nRST is internally connected to the LDO output which
is pulled to ground in sleep mode.
Standby
Init
Low
Floating
45 kΩ (typical)
Off
Ramping
nRST is internally connected to the LDO output which
in standby init mode is pulled low until VCC raises
beyond UVCC threshold.
Standby
from
SLP
Low
Low
45 kΩ (typical)
Off
VCC
Wake-up event detected, waiting on processors to set
EN
nRST comes on to VCC once thresholds are met.
Standby
from
Norm
Low
High
45 kΩ (typical)
Off
VCC
LDO is on and RXD is high but if a LIN bus wake
event takes place RXD is pulled low.
Normal
High
LIN Bus
Data
45 kΩ (typical)
On
VCC
LIN transmission up to 20 kbps
TSD Off
NA
Floating
45 kΩ (typical)
Off
Ground
Transmitter
nRST
Comment
nRST is pulled low as the LDO is turned off which
means UVCC threshold has been met.
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Unpowered System
VSUP < UVSUP
VSUP < UVSUP
VSUP • 89SUP
Standby Init Mode
VCC > UVCC
EN = High
Transceiver: Off
WUP Receiver: Off
RXD: Floating
Termination: 45 NŸ
LDO: Ramping up
Any State
VCC > UVCC
EN = Low
Tj > TSD
TSD Off Mode
Standby Mode
EN = Low > tEN
AND TXD = High
AND nRST = High
Transceiver: Off
WUP Receiver: On
RXD: Signals wake event
Termination: 45 NŸ
LDO: On
nRST: High
Tj < TSD
Transceiver: Off
WUP Receiver: On
RXD: Floating
Termination: 45 NŸ
LDO: Off
nRST: Low (Fault Condition)
VSUP < UVSUP
LIN Bus Wake up
Unpowered State
EN = High > tEN
nRST = High
Normal Mode
Transceiver: On
WUP Receiver: Off
RXD: LIN Bus Data
Termination: 45 NŸ
LDO: On
nRST: High
VSUP < UVSUP
VSUP < UVSUP
EN = Low > tEN
AND TXD = Low
AND nRST = High
EN = High > tEN
Sleep Mode
Transceiver: Off
WUP Receiver: On
RXD: Floating
Termination: Weak pullup
LDO: Off
nRST: Float
Figure 9-5. Operating State Diagram
9.4.1 Normal Mode
If the EN pin is high after the device enters standby init mode, the device enters normal mode. If EN is low, it
enters standby mode. In normal operational mode, the receiver and transmitter are active and the LIN
transmission up to the LIN specified maximum of 20 kbps is supported. If TXD pin is dominant at the time of
entering normal mode the LIN transmitter is kept off until a recessive is applied to TXD. The receiver detects the
data stream on the LIN bus and outputs it on RXD for the LIN controller. A recessive signal on the LIN bus is a
digital high and a dominant signal on the LIN bus is a digital low. The driver transmits input data from TXD to the
LIN bus. Normal mode is entered as EN transitions high while the device is in sleep or standby mode for > t EN.
Once EN has been high for tEN the device enters normal mode after tMODE_CHANGE and tNOMINIT.
9.4.2 Sleep Mode
Sleep Mode is the power saving mode for the TLIN1028-Q1. Even with extremely low current consumption in
this mode, the device can still wake up from the LIN bus through a wake-up signal or if EN is set high for > t EN.
The wake-up events must be active for the respective time periods (tLINBUS).
While the device is in sleep mode, the following conditions exist:
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The LIN bus driver is disabled and the internal LIN bus termination is switched off (to minimize power loss if
LIN is short-circuited to ground). However, the weak current pull-up is active to prevent false wake-up events
in case an external connection to the LIN bus is lost.
The normal receiver is disabled.
EN input and LIN wake-up receiver are active.
9.4.3 Standby Mode
Standby mode is entered either by a wake-up event through LIN bus while the device is in sleep mode or by the
EN pin from normal or standby init modes. From normal mode EN must be low for > tEN and TXD and nRST are
high. RXD pin in standby mode is dependent upon how standby mode was entered. If entered from normal
mode or power up, RXD is high. If entered from sleep mode, RXD is pulled low to indicate a wake event. When
entering standby mode from normal or standby init modes, a wake event on the LIN bus causes the RXD pin to
be pulled low.
During power up, if EN is low the device goes into standby mode, and if EN is high, the device goes into normal
mode. EN has an internal pull-down resistor ensuring EN is pulled low if the pin is left floating in the system.
9.4.4 Wake-Up Events
There are two ways to wake-up from sleep mode:
•
•
Remote wake-up initiated by the falling edge of a recessive (high) to dominant (low) state transition on the
LIN bus where the dominant state is held for the tLINBUS filter time. After this tLINBUS filter time has been met
and a rising edge on the LIN bus going from dominant state to recessive state initiates a remote wake-up
event eliminating false wake ups from disturbances on the LIN bus or if the bus is shorted to ground.
Local wake-up through EN being set high for longer than tEN .
9.4.4.1 Wake-Up Request (RXD)
When the TLIN1028-Q1 encounters a wake-up event from the LIN bus, RXD goes low and the device transitions
to standby mode until EN is reasserted high and the device enters normal mode. Once the device enters normal
mode, the RXD pin releases the wake-up request signal and the RXD pin then reflects the receiver output from
the LIN bus.
9.4.5 Mode Transitions
When the device is transitioning between modes, the device needs the time t MODE_CHANGE and t NOMINT to allow
the change to fully propagate from the EN pin through the device into the new state.
9.4.6 Voltage Regulator
The device has an integrated high-voltage LDO that operates over a 5.5 V to 28 V input voltage range for both
3.3 V and 5 V V CC. The device has an output current capability of 70 mA and 125 mA depending upon package
and support fixed output voltages of 3.3 V (TLIN10283-Q1) or 5 V (TLIN10285-Q1). It features thermal shutdown
and short-circuit protection to prevent damage during over-temperature and over-current conditions
9.4.6.1 VCC
The VCC pin is the regulated output based on the required voltage. The regulated voltage accuracy is ± 2%. The
output is current limited. In the event that the regulator drops out of regulation, the output tracks the input minus
a drop based on the load current. When the input voltage drops below the UV SUP threshold, the regulator shuts
down until the input voltage returns above the UVSUPR level. The device monitors situations where VCC may drop
below the UVCC level thus causing the nRST pin to be pulled low.
9.4.6.2 Output Capacitance Selection
For stable operation over the full temperature range and with load currents up to 125 mA on V CC a certain
capacitance is expected and depends upon the minimum load current. To support no load to full load a value of
10 µF and ESR smaller than 2 Ω is needed. For 20 µA to full load an 1.5 µF capacitance can be used. The low
ESR recommendation is to improve the load transient performance.
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9.4.6.3 Low-Voltage Tracking
At low input voltages, the regulator drops out of regulation and the output voltage tracks input minus a voltage
based on the load current (IL) and power-switch resistor. This tracking allows for a smaller input capacitance and
can possibly eliminate the need for a boost converter during cold-crank conditions.
9.4.6.4 Power Supply Recommendation
The device is designed to operate from an input-voltage supply range between 5.5 V and 28 V. This input supply
must be well regulated. If the input supply is located more than a few inches from the device. The recommended
minimum capacitance at the pin is 100 nF . The max voltage range is for the LIN functionality. Exceeding 24V for
the LDO reduces the effective current sourcing capability due to thermal considerations.
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 Application Information
The TLIN1028-Q1 can be used as both a follower device and a leader device in a LIN network. The device
comes with the ability to support a remote wake-up requests. It can provide the power to the local processor.
10.2 Typical Application
The device comes with an integrated 45 kΩ pull-up resistor and series diode for follower node applications. For
leader node applications, an external 1 kΩ pull-up resistor with series blocking diode can be used. Figure 10-1
shows the device being used in both leader and follower node applications.
10 µF
Vcc VSUP
EN
8
2
100 nF(4)
1
Leader Node
Pull-up(3)
MCU w/o
pull-up(2)
VDD I/O
1 kQ
MCU
4
5
220 pF
RXD
TXD
GND
VBAT
LIN Controller
Or
SCI/UART(1)
LIN
6
7
GND
I/O
VDD
LIN Bus
Leader
Node
3
nRST
Follower
10 µF
Node
Vcc
I/O
VDD
EN
2
8
VSUP
100 nF(4)
1
MCU w/o
pull-up(2)
Follower Node(3)
VDD I/O
MCU
4
LIN Controller
Or
SCI/UART(1)
5
220 pF
RXD
TXD
GND
LIN
6
7
3
nRST
(1) If RXD on MCU or LIN follower node has internal pullup; no external pullup resistor is needed.
(2) If RXD on MCU or LIN follower node does not have an internal pullup requires external pullup resistor.
(3) Leader node applications require and external 1 lQ ‰µooµ‰ Œ •]•š}Œ v • Œ] o ]} .
(4) Decoupling capacitor values are system dependent but usually have 100 nF, 1 R& v H10 µF
Figure 10-1. Typical LIN Bus
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10.2.1 Design Requirements
10.2.1.1 Normal Mode Application Note
When using the TLIN1028-Q1 in systems which are monitoring the RXD pin for a wake-up request, special care
should be taken during the mode transitions. The output of the RXD pin is indeterminate for the transition period
between states as the receivers are switched. The application software should not look for an edge on the RXD
pin indicating a wake-up request until t MODE_CHANGE. This is shown in Figure 8-15 when transitioning to normal
mode there is an initialization period shown as tNOMINIT.
10.2.1.2 TXD Dominant State Timeout Application Note
The maximum dominant TXD time allowed by the TXD dominant state time out limits the minimum possible data
rate of the device. The LIN protocol has different constraints for leader and follower node applications; thus,
there are different maximum consecutive dominant bits for each application case and thus different minimum
data rates.
10.2.1.3 Brownout
Figure 10-17 and Figure 10-18 show the behavior of the LIN, nRST and V CC pins during a brownout condition.
For the TLIN10283-Q1, V SUP down to ~ 2.24 V has results as shown. For the TLIN10285-Q1, V SUP down to ~
2.63 V has results as shown. When VSUP drops below these levels the signals are indeterminate.
10.2.2 Detailed Design Procedures
For processors or LIN follower nodes with an internal pull-up on RXD, no external pull-up resistor is needed. For
processors or LIN follower nodes without internal pull-up on RXD, an external pull-up resistor is required. Leader
node applications require an external 1 kΩ pull-up resistor and serial diode.
32
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10.2.3 Application Curves
Characteristic curves below show the LDO performance ramping between 0 V and up to 7 V.
80
130
120
70
110
100
60
90
80
ISUP (mA)
ISUP (mA)
50
40
70
60
50
30
40
-40°C
25°C
85°C
105°C
115°C
125°C
20
10
-40°C
25°C
85°C
105°C
115°C
125°C
30
20
10
0
0
3
3.5
4
4.5
5
5.5
6
6.5
VSUP (V)
Package = D
0
7
VCC = 3.3 V
1.5
2
2.5
3
3.5
VSUP (V)
4
4.5
5
5.5
6
6.5
7
D012
VCC = 3.3 V
Temperature =
Ambient
ICC = 125 mA
Figure 10-3. ISUP vs VSUP vs Temperature
Figure 10-2. ISUP vs VSUP vs Temperature
130
75
120
70
65
110
60
100
55
90
50
80
45
ISUP (mA)
ISUP (mA)
1
Package = DRB
Temperature =
Ambient
ICC = 70 mA
70
60
50
40
35
30
25
40
20
-40°C
25°C
85°C
105°C
115°C
125°C
30
20
10
0
0.5
1
1.5
Package = DDA
2
2.5
3
3.5
VSUP (V)
4
4.5
5
5.5
6
6.5
-40°C
25°C
85°C
105°C
115°C
125°C
15
10
5
0
0
-5
7
0
0.5
1
1.5
2
2.5
3
D022
VCC = 3.3 V
Temperature =
Ambient
Package = D
ICC = 125 mA
3.5
VSUP (V)
4
4.5
5
5.5
6
6.5
7
D007
VCC = 5 V
Temperature =
Ambient
ICC = 70 mA
Figure 10-4. ISUP vs VSUP vs Temperature
Figure 10-5. ISUP vs VSUP vs Temperature
130
130
120
120
110
110
100
100
90
90
80
ISUP (mA)
80
ISUP (mA)
0.5
D002
70
60
50
70
60
50
40
40
30
-40°C
25°C
85°C
105°C
115°C
125°C
30
20
10
-40°C
25°C
85°C
105°C
115°C
125°C
20
10
0
0
-10
0
0.5
1
Package = DRB
1.5
2
2.5
3
3.5
VSUP (V)
4
VCC = 5 V
4.5
5
5.5
6
6.5
7
0
0.5
1
1.5
2
2.5
3
D017
Temperature =
Ambient
ICC = 125 mA
Package = DDA
VCC = 5 V
3.5
VSUP (V)
4
4.5
5
5.5
6
6.5
7
D027
Temperature =
Ambient
ICC = 125 mA
Figure 10-6. ISUP vs VSUP vs Temperature
Figure 10-7. ISUP vs VSUP vs Temperature
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16
18
14
16
14
12
12
ISUP (PA)
ISUP (PA)
10
8
10
8
6
6
-40°C
25°C
85°C
105°C
115°C
125°C
4
2
2
0
0
0
0.5
1
1.5
Package = D
2
2.5
3
3.5
VSUP (V)
4
4.5
5
5.5
6
6.5
0
0.5
1
1.5
2
2.5
3
D004
3.3 V VCC = Off
Temperature =
Ambient
Package = DRB
Mode = Sleep
3.5
VSUP (V)
4
4.5
5
5.5
6
6.5
D014
3.3 V VCC = Off
Temperature =
Ambient
Mode = Sleep
Figure 10-8. ISUP vs VSUP vs Temperature Rampdown
Figure 10-9. ISUP vs VSUP vs Temperature Rampdown
16
16
14
14
12
12
10
10
ISUP (PA)
ISUP (PA)
-40°C
25°C
85°C
105°C
115°C
125°C
4
8
6
8
6
-40°C
25°C
85°C
105°C
115°C
125°C
4
2
-40°C
25°C
85°C
105°C
115°C
125°C
4
2
0
0
0
0.5
1
1.5
Package = DDA
2
2.5
3
3.5
VSUP (V)
4
4.5
5
5.5
6
6.5
0
0.5
1
1.5
2
2.5
3
D024
3.3 V VCC = Off
Temperature =
Ambient
Package = D
Mode = Sleep
3.5
VSUP (V)
4
4.5
5
5.5
6
6.5
D009
5 V VCC = Off
Temperature =
Ambient
Mode = Sleep
Figure 10-10. ISUP vs VSUP vs Temperature Rampdown
Figure 10-11. ISUP vs VSUP vs Temperature Rampdown
18
16
16
14
14
12
12
ISUP (PA)
ISUP (PA)
10
10
8
8
6
6
-40°C
25°C
85°C
105°C
115°C
125°C
4
2
0
2
0
0
0.5
1
Package = DRB
1.5
2
2.5
3
3.5
VSUP (V)
5 V VCC = Off
4
4.5
5
5.5
6
6.5
0
0.5
1
D019
Temperature =
Ambient
Mode = Sleep
Package = DDA
1.5
2
2.5
3
3.5
VSUP (V)
5 V VCC = Off
4
4.5
5
5.5
6
6.5
D029
Temperature =
Ambient
Mode = Sleep
Figure 10-12. ISUP vs VSUP vs Temperature Rampdown
34
-40°C
25°C
85°C
105°C
115°C
125°C
4
Figure 10-13. ISUP vs VSUP vs Temperature Rampdown
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Figure 10-14. LIN Bus Performance
Figure 10-15. Dominant to Recessive Propagation
Delay
Figure 10-16. Recessive to Dominant Propagation
Delay
Figure 10-17. TLIN10283-Q1 Brownout
Figure 10-18. TLIN10285-Q1 Brownout
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11 Power Supply Recommendations
The TLIN1028-Q1 was designed to operate directly off a car battery, or any other DC supply ranging from 5.5 V
to 28 V . A 100 nF decoupling capacitor should be placed as close to the VSUP pin of the device as possible. For
applications where the device goes from no load to full load, a minimum decoupling capacitance to ground of 10
uF is recommended when the LDO turns on. If the device is going from 20 µA to full load then a minimum of 1.5
µF capacitance is recommended.
36
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12 Layout
PCB design should start with understanding that frequency bandwidth from approximately 3 MHz to 3 GHz is
needed thus high frequency layout techniques must be applied during PCB design. Placement at the connector
also prevents these noisy events from propagating further into the PCB and system.
12.1 Layout Guidelines
•
•
•
•
•
•
•
•
Pin 1 (VSUP): This is the supply pin for the device. A 100 nF decoupling capacitor should be placed as close
to the device as possible.
Pin 2 (EN): EN is an input pin that is used to place the device in a low power sleep mode. If this feature is not
used, the pin should be pulled high to the regulated voltage supply of the microprocessor through a series
resistor, values between 1 kΩ and 10 kΩ. Additionally, a series resistor may be placed on the pin to limit
current on the digital lines in the event of an over-voltage fault.
Pin 3 (GND): This is the ground connection for the device. This pin should be tied to the ground plane
through a short trace with the use of two vias to limit total return inductance.
Pin 4 (LIN): This pin connects to the LIN bus. For follower node applications, a 220 pF capacitor to ground is
implemented. For leader node applications, an additional series resistor and blocking diode should be placed
between the LIN pin and the VSUP pin. See Figure 10-1
Pin 5 (RXD): The pin is an open-drain output and requires and external pull-up resistor in the range of 1 kΩ
to 10 kΩ to function properly. If the microprocessor paired with the transceiver does not have an integrated
pull-up, an external pull-up resistor should be placed on RXD. If RXD is connected to the VCC pin a higher
pull-up resistor value can be used to reduce standby current.
Pin 6 (TXD): The TXD pin is the transmit input signal to the device from the processors. A series resistor can
be placed to limit the input current to the device in the event of an over voltage on this pin. A capacitor to
ground can be placed close to the input pin of the device to filter noise.
Pin 7 (nRST): This pin connects to the processors as a reset out.
Pin 8 (VCC): Output source, either 3.3 V or 5 V depending upon the version of the device.
Note
All ground and power connections should be made as short as possible and use at least two vias to
minimize the total loop inductance.
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12.2 Layout Example
VCC
VSUP
VSUP
1
U1
VCC
8
C4
C2
VCC
D2
Only needed for
the Leader node
GND
J1
R7
R3
GND
EN
R2
2
EN
nRST
7
TXD
6
C3
LIN
GND
GND
3
GND
R4
TXD
C1
GND
VCC
4
LIN
RXD
5
R1
GND
RXD
Figure 12-1. Layout Example
38
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
• LIN Standards:
– ISO/DIS 17987-1: Road vehicles -- Local Interconnect Network (LIN) -- Part 1: General information and
use case definition
– ISO/DIS 17987-4: Road vehicles -- Local Interconnect Network (LIN) -- Part 4: Electrical Physical Layer
(EPL) specification 12V/24V
– SAE J2602-1: LIN Network for Vehicle Applications
– LIN2.0, LIN2.1, LIN2.2 and LIN2.2A specification
• EMC requirements:
– SAE J2962-2: TBD
– HW Requirements for CAN, LIN, FR V1.3: German OEM requirements for LIN
– ISO 10605: Road vehicles - Test methods for electrical disturbances from electrostatic discharge
– ISO 11452-4:2011: Road vehicles - Component test methods for electrical disturbances from narrowband
radiated electromagnetic energy - Part 4: Harness excitation methods
– ISO 7637-1:2015: Road vehicles - Electrical disturbances from conduction and coupling - Part 1:
Definitions and general considerations
– ISO 7637-3: Road vehicles - Electrical disturbances from conduction and coupling - Part 3: Electrical
transient transmission by capacitive and inductive coupling via lines other than supply lines
– IEC 62132-4:2006: Integrated circuits - Measurement of electromagnetic immunity 150 kHz to 1 GHz Part 4: Direct RF power injection method
– IEC 61967-4
– CISPR25
• Conformance Test requirements:
– ISO/DIS 17987-7: Road vehicles -- Local Interconnect Network (LIN) -- Part 7: Electrical Physical Layer
(EPL) conformance test specification
– SAE J2602-2: LIN Network for Vehicle Applications Conformance Test
TLINx441 LDO Performance, SLLA427
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
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13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
40
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Mar-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLIN10283DDARQ1
ACTIVE SO PowerPAD
DDA
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
TLN83
TLIN10283DRBRQ1
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLN83
TLIN10283DRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLN83
TLIN10285DDARQ1
ACTIVE SO PowerPAD
DDA
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
TLN85
TLIN10285DRBRQ1
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLN85
TLIN10285DRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLN85
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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