TLK10002FPGAEVM

User's Guide SLLU148 – May 2011 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module This user’s guide describes the usage and construction of the TLK10002 evaluation module (EVM). This document provides guidance on proper use by showing some device configurations and test modes. In addition, design, layout, and schematic information is provided to the customer. Information in this guide can assist the customer in choosing the optimal design methods and materials in designing a complete system. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Contents Introduction .................................................................................................................. 4 EVM PCB and High-Speed Design Considerations .................................................................... 5 TLK10002EVM Kit Contents ............................................................................................... 6 Power ......................................................................................................................... 6 Control and Output Status Signals ....................................................................................... 7 MDIO ......................................................................................................................... 7 JTAG .......................................................................................................................... 8 Reset ......................................................................................................................... 8 Test and Setup Configurations ............................................................................................ 9 TLK10002EVM Motherboard Schematics .............................................................................. 17 TLK10002EVM Motherboard Bill of Materials ......................................................................... 37 TLK10002EVM Motherboard Layout .................................................................................... 42 TLK10002EVM FPGA Daughterboard Schematics ................................................................... 53 TLK10002EVM FPGA Daughterboard Bill of Materials .............................................................. 68 TLK10002EVM FPGA Daughterboard Layout ......................................................................... 73 TLK10002EVM SMA Breakout Board Schematics .................................................................... 83 TLK10002EVM SMA Breakout Board Layout ......................................................................... 88 List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 .................................................................................................... TLK10002EVM Motherboard............................................................................................. TLK10002EVM FPGA Daughterboard .................................................................................. TLK10002EVM SMA Breakout Board .................................................................................. TLK10002EVM Motherboard and FPGA Daughterboard ............................................................ CRPAT Test Setup With FPGA Generator and Verifier .............................................................. Optimizing the High-Speed Link of a System Board Through the GUI ............................................. TLK10002EVM Motherboard and SMA Breakout Board ............................................................. Cover Page and Index, Sheet 1 of 20 .................................................................................. USB Interface, Sheet 2 of 20 ............................................................................................ 1P0V, 1P5V, and 1P8V Regulators, Sheet 3 of 20 ................................................................... 2P5V and 3P3V Regulators, Sheet 4 of 20 ............................................................................ Power Distribution, Sheet 5 of 20 ....................................................................................... Device Power, Ground, and Local Decoupling, Sheet 6 of 20 ...................................................... Global Signals, Sheet 7 of 20 ............................................................................................ MDIO, JTAG, and I2C Interface, Sheet 8 of 20 ....................................................................... TLK10002EVM Boards SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 4 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 www.ti.com 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 2 .................................................................................................... Jitter Cleaner Control, Sheet 10 of 20 .................................................................................. Low-Speed Data Signals, Sheet 11 of 20 ............................................................................. High-Speed Data Signals, Sheet 12 of 20 ............................................................................. 1P0V, 2P5V, and 3P3V Regulator LEDs, Sheet 13 of 20 ........................................................... 1P5/8V Regulator LEDs, Sheet 14 of 20 .............................................................................. 5-V, 3P3V_PLL, and VDDO LEDs, Sheet 15 of 20 .................................................................. VDDA, VDDT, VDDD, and DVDD LEDs, Sheet 16 of 20 ............................................................ VDDRA LEDs, Sheet 17 of 20 ........................................................................................... VDDRB LEDs, Sheet 18 of 20 ........................................................................................... Jitter Cleaner Power LEDs, Sheet 19 of 20 ............................................................................ Board-To-Board Connector, Sheet 20 of 20 ........................................................................... Top Signal, Layer 1 ....................................................................................................... Internal Ground, Layer 2.................................................................................................. Internal Signal, Layer 3 ................................................................................................... Internal Ground, Layers 4, 6, 7, 9, 11, and 13......................................................................... Internal Power, Layer 5 ................................................................................................... Internal Power, Layer 8 ................................................................................................... Internal Power, Layer 10 ................................................................................................. Internal Signal, Layer 12.................................................................................................. Bottom Signal, Layer 14, Top View ..................................................................................... Bottom Signal, Layer 14, Flipped View ................................................................................. Cover Page and Index, Sheet 1 of 15 ................................................................................. USB Interface, Sheet 2 of 15 ............................................................................................ Regulators, Sheet 3 of 15 ............................................................................................... FPGA Power and Ground, Sheet 4 of 15 ............................................................................. FPGA Configuration, Sheet 5 of 15 ..................................................................................... FPGA Gigabit Transceivers, Sheet 6 of 15 ............................................................................ TI-Programmed Resources 1, Sheet 7 of 15 .......................................................................... TI-Programmed Resources 2, Sheet 8 of 15 .......................................................................... User Programmable Resources 1, Sheet 9 of 15 ..................................................................... User-Programmable Resources 2, Sheet 10 of 15 ................................................................... FPGA No Connects, Sheet 11 of 15 .................................................................................... Board-to-Board Connector, Sheet 12 of 15 ............................................................................ 1P2V LEDs, Sheet 13 of 15 .............................................................................................. 1P8V and 2P5V LEDs, Sheet 14 of 15 ................................................................................. 3P3V and 5-V LEDs, Sheet 15 of 15 ................................................................................... Top Signal, Layer 1 ....................................................................................................... Internal Ground, Layer 2.................................................................................................. Internal Signal, Layer 3 ................................................................................................... Internal Ground, Layers 4, 6, 7, 9, 11, and 13......................................................................... Internal Power, Layer 5 ................................................................................................... Internal Power, Layer 8 ................................................................................................... Internal Power, Layer 10 ................................................................................................. Internal Signal, Layer 12.................................................................................................. Bottom Signal, Layer 14, Top View ..................................................................................... Cover Page and Index, Sheet 1 of 4 .................................................................................... Channel-A Signals, Sheet 2 of 4 ........................................................................................ Channel-B Signals, Sheet 3 of 4 ........................................................................................ Clocks, Sheet 9 of 20 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 25 26 27 28 29 30 31 32 33 34 35 36 42 43 44 45 46 47 48 49 50 51 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 73 74 75 76 77 78 79 80 81 83 84 85 SLLU148 – May 2011 Submit Documentation Feedback www.ti.com 66 Common Signals, Sheet 4 of 4 .......................................................................................... 86 67 Top Signal, Layer 1 68 Internal Ground, Layer 2.................................................................................................. 89 69 Internal GND, Layers 3, 4, and 5 ........................................................................................ 90 70 Bottom Signal, Layer 6 ....................................................................................................... ................................................................................................... 88 91 List of Tables 1 2 3 4 5 6 ......................................................................... TLK10002EVM Motherboard Layer Construction ..................................................................... TLK10002EVM FPGA Daughterboard Bill of Materials .............................................................. TLK10002EVM FPGA Daughterboard Layer Construction .......................................................... TLK10002EVM SMA Breakout Board Bill of Materials ............................................................... TLK10002EVM SMA Breakout Board Layer Construction ........................................................... TLK10002EVM Motherboard Bill of Materials SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 37 52 68 82 87 92 3 Introduction Introduction J4 J10 INB2P J11 INB2N J8 OUTB1N J12 OUTB2N OUTB0P OUTB0N J2 J6 INB1P J7 INB1N J5 J3 INB0P INB0N J9 OUTB1P MDC_POST_LS GND REV NA 1 www.ti.com J13 OUTB2P MDIO_POST_LS JMP3 OUTB3N J16 OUTB3P J17 J15 INB3N JMP1 JMP5 VDDRA_LS J35 OUTA0N J32 INA0N J34 OUTA0P GND I2C_SDA I2C_SCL JMP5 6522850 GND JMP68 JMP67 GND J20 INA3N J21 INA3P J27 OUTA2N J31 OUTA1N J26 OUTA2P J30 OUTA1P J25 INA2P J29 INA1P J24 INA2N J28 INA1N C98 C87 C85 VDDT C93 C95 GND JMP1 GND VDDA C80 C121 GND C117 C111 REF CLK1n C110 REF CLK0p C109 J6 REFCLK0n C20 C18 1p0V ANALOG R52 JMP69 C107 J43 J33 INA0P P2 U8 EN DVDD C120 J44 HSTXBn HSTXBp C27 C25 R69 VDDD C119 J41 J42 C139 C140 C94 1p0V DIGITAL JMP3 C138 JMP41 BJ 5V TLK10002 EVM MOTHER BOARD REV NA JMP70 C91 C89 C90 C115 C114 C113 C130 JMP71 JMP74 U73 U10 EN GND J71 JMP55 J36 CHA_CLKOUTP + 5V PLUG JMP72 C84 C86 1p8V VDDRB_LS 1p5V VDDRB_HS U57 C268 C264 U70 C269 C123 C108 U76 C271 REF_SEL AUX_SEL MDE_SEL C285 PLL_LCK AUXn C245 P1 P14 C48 R120 C47 C293 C294 R495 PWR_DN GND VCCA R312 R315 VDDO C129 C125 JMP73 R494 J70 AUXp JMP58 SPI C124 JMP75 C99 JITTER CLEANER CLK U2 MOSI MISO C127 C270 C83 VCC_OUT C118 R537 R536 LE J37 CHA_CLKOUTN JMP35 VDDRA_HS C101 VCXO C97 C100 JMP63 JMP66 D41 VCC_IN C128 GND R86 JMP17 PLL_LOCK JMP64 GND R188 EN GND C82 C81 EN EN CHB_CLKOUTP J18 CHB_CLKOUTN J19 JMP2 C34 C33 C75 JMP9 C76 C79 LS_OK_IN_A LS_OK_OUT_A GND 1p5V U12 REG JITTER PLL U24 U79 3p3V REG GND LS_OK_IN_B LS_OK_OUT_B + 5V GND 1p8V U16 REG 6522852 J14 INB3P JMP4 TLK10002 EVM SMA BREAKOUT DAUGHTER BOARD GND MDC_PRE_LS MDIO_PRE_LS J22 OUTA3P REFCLK1p C243 J23 OUTA3N C22 9 C23 3 C24 1 5 7 C22 C23 1 C23 9 C247 C23 7 HSRXBp C23 TLK10002 TLK10002 J5 J72 U1 J7 D45 D44 1P2V_GTP D43 VCCINT_1P2V VCCMGT_1P2V U34 D50 D51 D42 1P2V D48 VCCCLK_3P3V U31 3P3V 2P5V VCCO_1P8V D49 VCCAUX_2P5V P1 P3 GND +5V +5V U33 U30 R55 U42 P2 U14 CHA_CLK_SEL GCLK14 TEST_PASS_B TST_PASS_B SW4 Q17 JMP3 19 18 16 17 15 14 13 GND RE-PROGRAM FPGA CLK1 JMP22 GCLK25 IO SIGNALS GCLK27 GCLK12 SW8 USB_ONLINE D16 MDIO Q31 3P3V Q32 JMP19 D15 USB_SUSP R352 R202 R201 R351 C4 2P5V JMP20 R197 MDIO C233 C236 C261 R199 MAIN RESET R10 R33 USB_/RST U6 LED9 RST R134 R5 R9 R6 R3 C1 R38 R39 MDIO_CON MDC SW3 R8 U5 D22 D23 U16 MDC_CON SW2 SW6 C5 C2 D13 R212 PB3 RESET R1 C9 R198 R206 R205 SW1 GND EN C55 Q19 GND EN 9 8 6 7 5 10 JMP8 LED10 D9 R226 LS_OK_IN_B D10 R224 RST JMP12 D39 D40 R289 R288 PB4 RESET 39 J2 R25 R34 C8 R131 LED2 SUSPENDED D11 R222 D54 R398 LED1 D27 R174 R287 JMP27 U27 C239 C238 C12 C11 C10 MDIO RESET D38 D41 U25 38 USB C234 U18 RST MDIO RST R189 LED12 D1 R242 RST PB4 LED11 RST D12 R220 R285 R292 LS_OK_OUT_A D2 R240 RST PB2 LED3 RST D25 R172 R273 C237 R188 JMP26 D35 D37 U23 PB2 RESET D32 R200 PB1 RESET R276 R278 R269 LED4 D3 R238 LS_OK_IN_A D4 R236 RST PB1 LED7 RST D24 R171 LED6 D5 R234 D52 D34 D36 U21 R272 5V R383 JMP25 R271 LED6 D7 R230 R69 DONE D6 R232 R68 JMP24 SW9 Q34 /BUSY D53 Q21 /INIT_B D19 D20 R191 D33 32 ON JMP21 JMP35 LOSA SW5 CHA_CLKn LOSB R175 LOSA 31 35 R26 CHA_CLKp TST_PASS_A R176 LOSB HSWAPEN 29 30 34 USB_RST 5 JMP15 D28 4 R377 R264 2 C 23 22 J8 28 36 37 R243 TLK CLK J3 26 27 33 J7 R2 C218 C211 C212 R265 D14 JMP21 SMA J9 24 25 R30 R40 R31 R32 JMP10 R177 D30 TEST_PASS_A D29 11 12 JMP6 1 23 J10 GCLK17 USB RESET 3 22 R214 R213 5 C R178 7 21 R132 21 19 C230 C228 C222 C224 C220 C215 C206 C205 23 25 VCCAUX_2P5V TMS TCK A J5 D31 G C JMP9 JTAG JMP29 L JMP23 20 J11 R266 J U44 GND GND R E C200 R267 N 2 4 6 9 L3 R78 TLK10002 EVM FPGA DAUGHTER BOARD REV NA 6522851 F H 1P2V GTP C57 C60 SW7 U13 R74 R80 R81 R75 R67 PROG_B_/RST C240 B D FG48 G C149 C157 C164 AE C173 C148 AC C156 AA C160 C154 W U I2C SDA JMP34 C227 C229 C223 C221 C216 C219 C204 C208 U1 R76 R79 U9 C29 PROG_B_RST D18 JMP18 E C203 C201 R86 R84 R83 5 XCF32P A C R88 R89 R87 R85 R82 C33 R49 R54 R52 R46 C30 JMP31 R70 D21 CHB_CLK_SEL C72 JMP36 1 C 23 L6 C69 SMA RST LS_OK_OUT_B PB3 D8 R228 RST LED8 R295 D26 R173 1 3 R77 R91 C256 C255 3 1 2 0 C246 R381 C247 C259 R385 R386 SCL GND U10 JMP11 TLK CLK PRTAD0 PRTAD1 PRTAD2 PRTAD3 PRTAD4 R11 R62 L4 IO_SIGNALS J6 U15 +5V BJ 3P3V REG C38 C23 C39 R66 R63 R58 R53 R51 R44 C24 C17 JMP30 GPIO_4 GPIO_3 GPIO_2 GPIO_5 L5 C251 R365 R362 R363 R366 R361 R364 C253 GND JMP15 7 JTAG C47 1P2V REG C61 C64 PLUG C56 GND EN JMP5 Q18 C46 Q16 2P5V REG JMP2 EN GND R56 GND R50 R42 JMP16 C18 CLK1 JMP13 GPIO_1 GND 3p3V REG C69 C68 EN GND JMP7 R65 R64 R60 C44 JMP32 JMP17 CHB_CLKP JMP14 C62 C61 U20 2p5V REG U60 U48 C260 C10 R41 R43 C12 R48 R40 C6 C65 J4 TDI SUSPEND CHB_CLKN C21 C213 C217 C235 ONLINE USB U11 R61 C67 LOOPBACK_B LOOPBACK_A LANE2_4_SELECT_B LANE2_4_SELECT_A TEST_EN_B TEST_EN_A PRBSEN PDTRXA_N TDO USB D4 D3 C13 C14 JMP33 1 C202 C207 MDIO U5R44 R36 C4 JMP50 MDC JMP47 R475 R474 R15 R14 SW2 R35 JMP13 EN U22 RESET RESET U7 R42 D42 RST RST C11 D1 D2 R2 TRST VDDRA_HS D36 D35 VDDRA_LS VDDRB_LS VDDRB_HS VDDO 1p8V D40 JC_VCC_IN D38 D26 D34 D39 1p5V D37 D33 D25 D46 VDDA D27 JC_VCCA JC_VCXO VDDD D19 JC_VCC_OUT DVDD D20 D47 D32 D44 VDDT D28 D31 1p0VA D30 D29 1p0VD D18 D17 D45 1p5V R1 RST RST R305 R18 C2 LOSA 2p5V 3p3V 3p3VP LOSB 5V PRBS PASS LS A OK LS B OK 1p8V USB RESET R306 R10 D22 R307 JMP62 SW1 D21 GND GND U8 C45 C51 6 3p3V JTAG_V SCANCFG1 JMP46 MAIN RST 2p5V MDIOV 3p3V R48 L1 C48 22 C U42 GND SCANCLK SCANCFG0 SCANOUT GND SW3 JMP52 SW4 U64 R28 R27 R5 R26 R3 R25C R8 I2C DISABLE STCI_VCC SCANIN JMP42 D43 JMP44 GND JMP48 LSOK OUTA JC RST JMP45 U41 D12 D13 GND JMP61 D14 D15 D16 LSOK OUTB U39 JMP43 RST RST BTN J65 GND 1P8V REG C31 Q15 U87 U67 C292 GND JMP57 JMP60 3p3V MAIN RESET D10 D11 C265 RESET C242 C241 C32 JMP1 EN GND U90 U63 C291 U51 U45 C267 C261 PDTRXB PDTRXA PRBS_EN CLKB_SEL CLKA_SEL TEST_EN LOSA GPIO GND PRBS PASS AMUXA AMUXB LOSB GND LS OKINB LS OKINA PRTAD4 PRTAD3 PRTAD2 JITTER CLEANER ON PRTAD1 SDA SCL JMP53 U7 R47 RATE_SEL_0 C245 XC6SLX75T C263 MOD DETECT RATE_SEL_1 C244 SPARTAN-6 C266 C243 XILINX RX_LOS C54 JMP76 TX_DISABLE J73 TX_FAULT PRTAD0 U39 U36 J8 STCI U43 JMP4 U40 1P8V U37 C24 0 TX DISABLE D50 C23 6 RX_LOS C22 8 TX_FAULT D49 C23 2 MOD DETECT TX DISABLE D52 4 8 D51 C23 0 J45 C23 J46 J47 C23 CLKOUTAp CLKOUTAn CLKOUTBp 6 C22 D48 J48 D46 CLKOUTBn C249 D47 HSRXBn JMP28 Figure 1. TLK10002EVM Boards WARNING This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at own expense will be required to take whatever measures may be required to correct this interference. The Texas Instruments (TI) TLK10002 SERDES evaluation module (EVM) boards are used to evaluate the functionality and the performance of the TLK10002 dual-channel, multi-rate transceiver device in a 144-ball PBGA package. The TLK10002 is a multigigabit transceiver intended for use in ultrahigh-speed, 4 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback EVM PCB and High-Speed Design Considerations www.ti.com bidirectional, point-to-point data transmission systems such as base station RRH (remote radio head) applications as well as any other high-speed application. All CPRI and OBSAI data rates from 1.2288 Gbps to 9.8304 Gbps and non-CPRI or OBSAI serial data rates between 1 Gbps and 10 Gbps are supported for the high-speed side. Each channel of the TLK10002 can be operated from a single, shared reference clock, or independently from separate reference clocks at different frequencies. The TLK10002 performs data serialization/de-serialization and clock extraction as a physical layer interface device. Flexible clocking schemes are provided to support various operations and include the support for clocking with an externally jitter-cleaned clock recovered from the high-speed side. Other features of the TLK10002 include an integrated latency measurement function, PRBS (27 - 1), (223 1), (231 - 1), and high, low, and mixed CRPAT long/short generation and verification for self-test, system-level support. Low-speed and high-speed side loopback modes are provided for self-test and system diagnostic purposes. The TLK10002 has an integrated loss-of-signal (LOS) detection function on both high-speed and low-speed sides. LOS is asserted in conditions where the input differential voltage swing is less than the LOS assert threshold. The input differential voltage swing must exceed the de-assert threshold for the LOS condition to be cleared. The low-speed side of the TLK10002 is ideal for interfacing with an FPGA or ASIC located on the same local physical system. The high-speed side is ideal for interfacing with remote systems through an optical fiber, an electrical cable, or a backplane interface. The TLK10002 supports operation with SFP and SFP+ optical modules. Both FPGA and optical interfaces are available in the evaluation kit for rapid prototyping and easy development. Configuration of the TLK10002 on a per-channel basis is available by way of accessing a register space of control bits available through a two-wire access port called the Management Data Input/Output (MDIO) interface as defined in Clause 22 of the IEEE 802.3 Ethernet Specification. (1) The TLK10002EVM GUI provides access to all the registers of every device used on any of the TLK10002 boards through a standard USB 1.1 interface. The boards can be configured if necessary to accept or provide MDIO signals from or to an external source by installing and uninstalling certain resistors. The TLK10002EVM board can be run from a single, 5-V power supply or 5-Vdc transformer. All voltages needed are regulated down through onboard LDO regulators which can be adjusted to the appropriate minimum, nominal, and maximum values through changing a single resistor value. Voltage monitor circuits with LEDs are included on all voltage rails for easy debugging and identification of valid power rails. All data I/O signals are broken out to connectors for easy and rapid prototyping; all control signals are easily controlled through the GUI or shunts on header blocks. 2 EVM PCB and High-Speed Design Considerations The board can be used to evaluate device parameters in addition to acting as a guide for high-speed board layout. As the frequency of operation increases, the board designer must take special care to ensure that the highest signal integrity is maintained. To achieve this, the board's impedance is controlled to 50-Ω single-ended or 100-Ω differential impedance for both the low- and high-speed differential serial and clock connections. Vias are minimized and, when necessary, are designed to minimize impedance discontinuities along the transmission line. Care was taken to control trace length mismatch (board skew) to less than ±0.5 mil. Overall, the board layout must be designed and optimized to support high-speed operation. Thus, understanding impedance control and transmission line effects are crucial when designing high-speed boards. Some of the advanced features offered by this board include: • The TLK10002 printed-circuit board (PCB) is designed for optimal high-speed signal integrity using Rogers Material for the outer signal layers and FR-4 for the inner layers. All gigabit and clock signals are routed over the Rogers Material for minimal signal loss. The optional FPGA and SMA Breakout Daughterboards use FR-4 for all layers. • SMA and header fixtures are easily connected to test equipment. • All input/output signals are accessible for rapid prototyping. (1) The MDIO register map is located within the TLK10002 Dual-Channel 10Gbps Multi-Rate Transceiver datasheet. SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 5 TLK10002EVM Kit Contents • • • • 3 www.ti.com The entire board can be powered from a single, 5-V power supply where the power planes can be supplied through onboard regulators or through separate headers for isolation. Onboard capacitors provide ac coupling of high-speed transmit and receive signals. Voltage monitoring LED circuits provide quick indication that the voltage is within specification. Provisions are included for use of an onboard CDCE72010 jitter cleaner to supply a reference clock signal. Note that by default the hardware is configured for external reference clocks only. TLK10002EVM Kit Contents The TLK10002EVM kit contains the following: • TLK10002EVM motherboard • TLK10002EVM User’s Guide (this document) • TLK10002 data sheet • CD-ROM containing user interface software and user guides The following two daughterboards may be ordered separately for evaluation of the TLK10002 low-speed side: • TLK10002EVM FPGA daughterboard • TLK10002EVM SMA breakout daughterboard 4 Power The TLK10002EVM can be operated off of a single, 5-V power supply with a 2.5-A or greater current rating, using the onboard, low-dropout (LDO) voltage regulators to generate the voltages required to correctly operate the TLK10002's 1-V and 1.5-V/1.8-V power rails. Additional 2.5-V and 3.3-V supplies have been added to support additional circuitry on the EVM board. Two-pin headers allow external laboratory power supplies to be used instead of the onboard LDO regulators if the ferrite beads at the source of the split planes are also removed. The LDO regulators used on the EVM are TI’s TPS74401 and are adjustable using a resistor divider between the output and a feedback pin. Each regulator has been set to provide the appropriate voltage with a slightly higher margin at the source to account for IR drop across the board. If more information on the use of these regulators is desired, consult the regulator data sheets found at www.ti.com. Several power supplies such as VDDRA_LS, VDDRB_LS, VDDRA_HS, VDDRB_HS, and VDDO can be operated off of either 1.5 V or 1.8 V depending on your specific setup. The EVM is designed to allow either of these voltages to be selected for use with the previously mentioned TLK10002 supply rails, but only allows either 1.5 V or 1.8 V to be selected at a time without some board modifications. Selection between 1.5 V and 1.8 V is performed by moving the jumper between the center pin and the respective 1p5V and 1p8V pins of JMP35. The 0-Ω resistors are located at the entrance point of each power plane and can be replaced with a ferrite bead of an appropriate value depending on the desired data rate if desired. See Figure 13 and Figure 14 of the TLK10002EVM Schematics for more specific information on how all the power planes are connected and sourced from either the regulators or external headers. 4.1 Power Monitoring LEDs Each plane of the TLK10002EVM has been equipped with a voltage monitoring circuit that monitors the voltage on the plane and lights the LEDs when the voltage is within the minimum/maximum data sheet limits for that power supply. A precision TI voltage reference chip is used along with 0.1% precision resistors to set minimum and maximum reference levels, providing a detection circuit that is accurate to approximately ±10 mV. The LEDs can be used as a basic indication of the status of power on the board being within the acceptable minimum/maximum limits given in the data sheet and not as a precise measurement tool, as some LED circuits may turn off at slightly different voltages when approaching the limits due to the manufacturing tolerances and available component values. If the LEDs fail to light, a problem exists with the voltage on the board that can result in damage to the board if the problem is not resolved. 6 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback Control and Output Status Signals www.ti.com 5 Control and Output Status Signals All of the external control and status pins on the TLK10002EVM have been consolidated to a single location on the board and broken out into several header blocks for easier reference. LEDs have been added to the LOSA, LOSB, PRBS_PASS, and PLL_LOCK of the CDCE72010 jitter cleaner lines in addition to the headers for scope probes to allow easy monitoring of the high/low value on the line. The LED is ON when the line is a logic high, and the LED is OFF when the line is a logic low. If the line is toggling, a dimming of the LED may be observed as the LED is pulsing on and off relative to the activity on the line. All status pins and external control pins of the TLK10002 and the CDCE72010 can also be monitored or set high/low through the GUI. The preferred method of setting these control pins is through the GUI via the TCA6424 I2C-to-GPIO IC located on the board. If shunts are placed on the header for a particular control pin, the signal is physically tied low and software control is not possible. Mixed use of the hardware and software setting of various control pins is discouraged. The I2C-based software control of the TLK10002 control pins can be disabled by placing a shunt on JMP44, which disables the level shifter attached to the signals by setting the enable pins low. This allows the onboard pullup resistors or shunts to ground on the header pins to set the high/low status of the control pins. If external control is desired, the Software Control radio button on the GUI front panel must be de-selected as well to disable the software portion of the interface. See the TLK10002 data sheet for a detailed description of the control signals. 6 MDIO The TLK10002 supports the Management Data Input/Output (MDIO) interface as defined in Clause 22 of the IEEE 802.3 Ethernet Specification. The MDIO allows register-based management and control of the serial links. Normal operation of the TLK10002 is possible without the use of this interface, although some additional features are accessible only through the MDIO interface. The MDIO management interface consists of a bidirectional data path (MDIO) and a clock reference (MDC). The port address is determined by control pins PRTAD[4:0] as described in Table 1 of the TLK10002 data sheet. In Clause 22, the top four control pins PRTAD[4:1] determine the device port address. In this mode, the two individual channels in TLK10002 are classified as two different ports. So, any PRTAD[4:1] value has two ports per TLK10002. The TLK10002 responds if the four MSBs of the PHY address field on MDIO protocol (PA[4:1]) matches PRTAD[4:1]. The LSB of PHY address field (PA[0]) will determine which channel/port within the TLK10002 to respond to. If PA[0] = 1’b0, TLK10002’s channel A responds. If PA[0] = 1’b1, TLK10002’s channel B responds. Write transactions that address an invalid register or read only registers are ignored. Read transactions of invalid registers return a 0. The TLK10002 requires either 1.5-V or 1.8-V I/O levels on the MDIO/MDC signals. Therefore, a bidirectional level shifter has been provided on board that level shift the 3.3-V MDIO and MDC signals to the appropriate 1.5-V/8-V levels. If a different MDIO controller is used that already has 1.5-V or 1.8-V signal levels, resistors R308, R309, R296, and R297 must be removed, thus disconnecting the level shifter. Resistors R293 and R295 can be installed which connect the TLK10002 MDIO and MDC signal pins directly to the pins of JMP50. A third option of using NFETs as level shifters has also been provided. Removing resistors R308, R309, R296, and R297, as well R293 and R295 if they were installed and installing an appropriate NFET such as Fairchild’s FDV301N allows for this third option of level shifting to be evaluated. The onboard TUSB3210 microcontroller is the preferred method of controlling the TLK10002 register stack and is the only way to interface the GUI with the board. SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 7 JTAG 7 www.ti.com JTAG The EVM also provides a separate connector to support the full five-pin JTAG interface of the TLK10002 with onboard level shifters to be compatible with most standard JTAG control interfaces to be used for manufacturing tests. The 3.3-V (header) side of the level shifter is connected to the header and the 1p5/8V side of the level shifter is connected to the TLK10002. If the level shifter is not needed, providing an external voltage of the appropriate signal level between pins 2 and 3 of JMP62 allows the signals to pass to the TLK10002 correctly. 8 Reset The TLK10002EVM comes configured for manual reset operations involving the pushbutton reset switch (SW3). When switch SW3 is pressed, the TLK10002 device RESET pin (RST_N) goes LOW, and the entire TLK10002 device is reinitialized. A TI TPS3125J18 ultralow-voltage processor supervisory circuit is used to control the reset line. During power-on, RESET pin of U37 is asserted when the supply voltage becomes higher than 0.75 V. Thereafter, the supply voltage supervisor monitors the voltage and keeps RESET output active as long as the voltage remains below the threshold voltage (VIT). An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time, td = 180 ms, starts after the voltage has risen above the threshold voltage (VIT). A manual reset input to the supervisory circuit, MR, accepts the input from the pushbutton switch SW3. A low level at MR causes RESET to become active, thus resetting the TLK10002 device whenever the pushbutton RESET is pressed. By placing a jumper on JMP43, the manual reset (/MR) is tied hard to ground causing the TLK10002 to be held in a constant state of reset without the need to continually hold the Reset Pushbutton SW3. The supervisory circuit releases the reset line to a HIGH 180 ms (td) from the time the MR line becomes greater than the threshold voltage (VIT). By removing the jumper from JMP42, the supervised reset circuit is disconnected from the RST_N line. Reset control from an external controller or piece of equipment can be connected directly to pin 2 (RST_N) of JMP42 and a ground pin GND has been added to the JMP42 header next to the RST_N pin to allow easy access for the return current on that cable. The CDCE72010 jitter cleaner RESET signal is also connected to the Main Reset pushbutton as well as individually controlled by pressing SW4. Note this RESET does not reset the CDCE72010 register stack settings and is only a PLL reset. NOTE: In order to keep the GUI settings and the device settings synchronized during the evaluation of the TLK10002, all RESET commands must be issued through the GUI via the TCA6424 I2C-to-GPIO device connected to the signals. When the software RESET buttons are pressed, the GUI adjusts its memory settings of the various registers in order to match the new values the devices will reflect after the hardware RESET is performed. If the buttons are pressed on the board, the GUI does not reflect the devices' true status and may result in erroneous results during testing because the device is not configured according to the GUI’s displayed results. 8 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback Test and Setup Configurations www.ti.com Depending on the power down and/or GUI termination sequence followed, the USB device may need to be RESET to allow re-enumeration to occur in future tests. When the board is powered on and the USB connection is enumerated, the USB online LED (D4) lights. If this LED fails to light, a PC-related issue may exist, and the PC must be restarted. The LED lights once the PC error is fixed. If the USB connection is improperly disconnected or terminated, the USB SUSPEND light D3 lights and is an indication that the USB connection is not properly established. 9 Test and Setup Configurations The TLK10002EVM has an SFP+ Optical Module Cage attached directly to channel A's high-speed signals through approximately 2 inches of trace over Rogers Low-Dielectric material. Channel B’s high-speed signals are attached to Edge Launch SMA connectors with 0.1-µF ac coupling capacitors on the RX lines, and 0-Ω resistors on the TX lines to facilitate an external loopback configuration with only a single set of capacitors in line. The capacitors or resistors must be carefully reworked as necessary to facilitate the test needs during evaluation. Placing two 0.1-µF ac coupling capacitors can result in lower performance and greater numbers of bit errors. All low-speed signals on both the RX and TX signals have 0.1-µF ac coupling capacitors and are routed to a Samtec SEAF board-to-board connector that mates with either the TLK10002EVM SMA breakout board for use in parametric and laboratory testing, or the TLK10002EVM FPGA breakout daughterboard for system-level evaluation. The MDIO bus that is connected to the TLK10002 is also routed to the SEAF board-to-board connector and can be used to interface with either the FPGA or an external system board via the post level shifter MDIO signal header on the SMA breakout board. SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 9 Test and Setup Configurations JITTER PLL C76 U12 1p5V REG U16 JMP9 C94 C87 C85 6522850 GND JMP68 C98 GND GND VDDT C93 C95 GND JMP1 1p0V ANALOG VDDA C80 C121 C120 C111 C110 REF CLK1n C23 REF CLK0p REFCLK0n C109 J6 C119 J43 HSTXBn HSTXBp C20 C18 EN DVDD C117 C23 7 GND J44 J42 U8 R52 JMP69 U79 U76 C271 R69 C107 JMP55 C27 C25 VDDD JMP3 J71 J41 TLK10002 EVM MOTHER BOARD REV NA JMP67 1p0V DIGITAL EN GND P2 PLUG JMP70 C91 C89 U73 C90 C115 JMP74 C114 U70 C269 U10 C139 C140 C86 C84 JMP72 C108 VDDRA_LS VDDRB_LS 1p8V C130 C129 C128 C270 PLL_LCK R495 AUX_SEL REF_SEL MDE_SEL PWR_DN AUXn C245 + 5V C138 JMP41 BJ 5V C293 C294 C285 R312 GND VCCA 1p5V VDDRB_HS AUXp R315 VDDO U57 C268 J70 C264 MISO JMP58 C127 JMP75 R494 C124 C125 C101 C123 C99 JITTER CLEANER CLK U2 MOSI VDDRA_HS JMP73 VCXO LE P1 P14 C48 R120 C47 JMP35 C118 R537 R536 VCC_IN C97 C100 C83 VCC_OUT JMP63 JMP66 D41 SPI JMP5 GND R86 JMP17 PLL_LOCK JMP64 GND R188 EN GND C82 C81 EN EN + 5V GND 1p8V REG C34 C33 C75 C79 C113 U24 JMP71 3p3V REG www.ti.com REFCLK1p C243 C2 29 C24 3 8 C23 C23 27 C2 31 C2 5 9 C247 C2 41 HSRXBp C23 TLK10002 TLK10002 J5 J72 U1 J7 HSRXBn D50 2 6 C23 TX DISABLE D49 C23 RX_LOS TX DISABLE D52 8 TX_FAULT C22 MOD DETECT D51 6 J45 4 J46 C23 CLKOUTAp CLKOUTAn J47 30 C2 CLKOUTBp C22 D48 J48 0 CLKOUTBn C249 J8 JMP76 U90 U63 C291 RX_LOS C266 C263 TX_FAULT U51 TX_DISABLE J73 U87 C292 U45 C261 RATE_SEL_1 C267 RATE_SEL_0 U67 MOD DETECT R18 C2 MDIO MDC JMP47 SW2 C4 USB D4 D3 ONLINE SUSPEND GND C69 C68 3p3V REG C13 C14 C62 C61 2p5V REG U60 U48 R41 R43 R35 U5R44 R36 R475 R474 R15 R14 JMP13 EN USB J65 C6 D2 R2 C10 U7 U20 RESET RESET D1 C12 R48 R40 R305 JMP50 D35 D39 D33 R1 RST RST R42 D42 RST JMP62 TRST VDDRA_HS D36 VDDRA_LS VDDRB_HS D40 D34 VDDO VDDRB_LS D38 D26 1p8V 1p5V D37 D25 JC_VCC_IN D46 JC_VCC_OUT D47 JC_VCXO JC_VCCA D44 D45 VDDD D19 D31 VDDA D27 DVDD D20 D32 D29 VDDT D28 D30 1p0VA 1p0VD D18 D17 1p5V D21 R306 SW1 1p8V R307 R10 D22 GND GND MDIOV 3p3V C11 LOSA SCANOUT JMP46 USB RESET JTAG_V SCANCFG1 STCI RST 2p5V 3p3V 2p5V 3p3V 3p3VP LOSB 5V PRBS PASS LS A OK LS B OK SCANCLK SCANCFG0 SCANIN MAIN RST SW3 JMP52 SW4 U64 U42 GND R28 R27 R5 R26 R3 R25 R8 I2C DISABLE STCI_VCC GND JMP42 D43 JMP44 JMP48 GND LSOK OUTA U41 D12 D13 GND JMP61 D14 D15 JMP60 3p3V D16 LSOK OUTB U39 JC RST JMP45 JMP43 RST RST BTN U22 GND JMP57 JMP53 MAIN RESET D10 D11 C265 RESET GND C260 PDTRXB PDTRXA PRBS_EN CLKB_SEL CLKA_SEL TEST_EN GPIO LOSA LOSB PRBS PASS AMUXA AMUXB GND GND LS OKINB LS OKINA PRTAD4 PRTAD3 PRTAD2 PRTAD0 JITTER CLEANER ON PRTAD1 SDA SCL EN GND JMP15 C7 R11 JTAG Figure 2. TLK10002EVM Motherboard 10 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback Test and Setup Configurations U39 D45 D44 VCCMGT_1P2V 1P2V_GTP U34 D42 1P2V U31 P1 +5V +5V U33 U30 U42 P3 GND R55 U36 D43 VCCINT_1P2V D51 D50 VCCCLK_3P3V 3P3V U43 D48 2P5V U40 JMP4 D49 VCCAUX_2P5V D47 VCCO_1P8V U37 1P8V D46 www.ti.com +5V Q17 Q19 GND EN GND EN JMP3 19 18 15 16 17 14 13 11 12 10 8 6 7 5 JMP22 GCLK25 IO SIGNALS GCLK27 GCLK12 38 39 USB R30 R40 R31 R32 J2 SW8 MDIO USB_ONLINE 3P3V 2P5V Q31 R199 R212 JMP20 R197 JMP19 MDIO C233 Q32 R200 R132 C236 C261 D15 USB_SUSP USB_RST C4 D16 R134 R5 R9 R6 R3 C1 R38 R39 R2 D13 D22 D23 MAIN RESET R10 R26 R33 USB_/RST U6 U5 MDIO_CON MDC SW4 R8 C5 C2 R352 R202 R201 R351 RST LED9 LED10 D9 R226 RST R1 C9 U16 C240 R289 PB3 RESET C8 R131 JMP12 SW6 R25 R34 LS_OK_IN_B D10 R224 LED1 D27 R174 JMP27 R287 R292 SW3 GND RE-PROGRAM FPGA CLK1 JMP8 R377 SW5 MDC_CON SW2 32 35 R198 R206 R205 SW1 31 34 C12 C11 C10 D39 D40 C239 R288 C238 R243 SW9 U27 PB4 RESET 29 30 36 37 MDIO RESET D38 D41 U25 28 C234 U18 RST MDIO RST R189 LED12 D1 R242 R188 RST PB4 LED11 RST D12 R220 R285 R276 LED2 SUSPENDED D11 R222 D54 R398 LED4 D3 R238 R273 C237 D32 JMP26 D35 D37 U23 PB2 RESET R191 D33 26 27 33 J7 Q34 PB1 RESET RST PB2 LED3 RST D25 R172 R271 R278 R269 JMP25 D34 D36 U21 R272 5V D52 R68 JMP24 R383 Q21 /INIT_B D19 D20 /BUSY D53 LS_OK_IN_A D4 R236 RST PB1 LED7 RST D24 R171 LED6 D7 R230 LED6 D5 R234 R69 DONE D6 R232 LOSA LS_OK_OUT_A D2 R240 D28 R265 24 25 ON JMP21 JMP35 LOSA J9 CHA_CLKn LOSB R175 23 J10 HSWAPEN JMP36 GCLK14 J8 JMP18 R264 J3 5 C 23 2 22 C R176 LOSB 22 TLK CLK TST_PASS_B CHA_CLKp PLUG BJ CHA_CLK_SEL C218 C211 C212 21 J11 GCLK17 USB RESET SMA JMP21 TDI TDO U14 TEST_PASS_B TST_PASS_A C55 C56 1 JMP15 R177 D30 TEST_PASS_A 4 JMP34 3 20 D14 5 JMP23 R214 R213 7 JMP10 J5 D29 TLK10002 EVM FPGA DAUGHTER BOARD REV NA 6522851 C227 C229 C223 C221 C216 C219 C204 C208 21 19 C230 C228 C222 C224 C220 C215 C206 C205 23 25 9 R67 PROG_B_/RST RST LS_OK_OUT_B PB3 D8 R228 RST LED8 R295 D26 R173 C246 C247 C235 VCCAUX_2P5V TMS TCK A JMP9 JTAG D31 G C GND R178 L U44 R78 R266 J E I2C GND R N 2 4 6 PRTAD0 PRTAD1 PRTAD2 PRTAD3 PRTAD4 GND C202 C207 C251 R365 R362 R363 R366 R361 R364 C253 F H FG48 G B D C200 R267 U R76 R79 XILINX E C203 C201 R86 R84 R83 5 XCF32P A C R87 R85 R82 XC6SLX75T R381 1 3 JMP29 D18 C149 C157 C164 AE C173 C148 AC C156 AA C160 C154 W SPARTAN-6 R385 R386 R88 R89 SW7 U13 R74 R80 R81 R75 D21 CHB_CLK_SEL C72 U1 L3 C57 C60 PROG_B_RST C69 TLK CLK C259 R77 R91 C256 C255 3 1 2 0 1 6 LOOPBACK_B LOOPBACK_A LANE2_4_SELECT_B LANE2_4_SELECT_A TEST_EN_B TEST_EN_A PRBSEN PDTRXA_N JMP31 R70 SMA U15 1P2V GTP JMP6 C38 C39 R66 R63 R58 L6 JMP11 C67 C21 C213 C217 L4 U9 C29 IO_SIGNALS J6 C 23 GPIO_5 GPIO_4 GPIO_3 GPIO_2 GPIO_1 J4 L5 C61 C64 9 Q18 C23 C24 JMP30 C17 C18 R53 R51 R44 R50 R42 CLK1 JMP14 JMP13 JMP32 C33 R49 R54 R52 R46 C30 1P2V REG JMP17 CHB_CLKP 22 C C65 1 SDA U10 C44 C48 CHB_CLKN R62 R65 R64 R60 C45 JMP33 SCL GND C47 3P3V REG U11 R61 C46 C32 L1 C51 JMP7 JMP5 U8 2P5V REG JMP2 R48 Q16 1P8V REG Q15 C31 R56 GND C242 C241 EN GND EN GND JMP1 U7 R47 JMP16 C245 GND EN C244 C243 C54 P2 JMP28 Figure 3. TLK10002EVM FPGA Daughterboard SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 11 Test and Setup Configurations www.ti.com J4 J5 J10 INB2P J7 INB1N J11 INB2N J8 OUTB1N J12 OUTB2N J9 OUTB1P J13 OUTB2P OUTB0P OUTB0N J3 INB0P INB0N GND MDC_POST_LS REV NA J2 J6 INB1P MDIO_POST_LS JMP3 OUTB3P J17 J15 INB3N JMP1 GND LS_OK_IN_B LS_OK_OUT_B GND LS_OK_IN_A LS_OK_OUT_A CHB_CLKOUTP J18 CHB_CLKOUTN J19 J37 CHA_CLKOUTN J36 CHA_CLKOUTP I2C_SDA J33 INA0P J35 OUTA0N J32 INA0N J34 OUTA0P J27 OUTA2N J31 OUTA1N J26 OUTA2P J30 OUTA1P J25 INA2P J29 INA1P J24 INA2N J28 INA1N JMP5 I2C_SCL JMP2 GND J20 INA3N J21 INA3P J22 OUTA3P 6522852 OUTB3N J16 J14 INB3P JMP4 TLK10002 EVM SMA BREAKOUT DAUGHTER BOARD GND MDC_PRE_LS MDIO_PRE_LS J23 OUTA3N Figure 4. TLK10002EVM SMA Breakout Board 12 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback Test and Setup Configurations JTAG D45 C54 +5V Q17 GND EN JMP3 18 19 GND RE-PROGRAM FPGA CLK1 JMP22 GCLK25 IO SIGNALS GCLK27 GCLK12 GCLK17 USB RESET USB R30 R40 R31 R32 J2 SW4 R26 R33 SW8 MDIO 3P3V 2P5V Q31 R199 Q32 R214 R213 JMP20 R197 JMP19 MDIO C233 R132 MAIN RESET C236 C261 D15 USB_SUSP D16 R134 C4 USB_ONLINE D14 USB_RST R2 USB_/RST U6 D13 R5 R9 R6 R3 C1 R38 R39 R352 R202 R201 R351 RST LED9 LED10 D9 R226 LS_OK_IN_B D10 R224 RST R131 R8 R10 SW6 C5 U5 D22 D23 C240 C239 R289 PB3 RESET R1 C9 U16 R11 SW3 16 17 15 14 13 11 12 JMP8 R377 RST LS_OK_OUT_B PB3 D8 R228 RST LED8 D26 R173 JMP12 D39 D40 C7 SW2 39 C2 R198 R206 R205 SW1 38 R25 R34 C8 R212 PB4 RESET R295 R287 LED1 D27 R174 LED12 D1 R242 R292 LED2 SUSPENDED D54 D11 R222 R398 PLUG BJ Q19 GND EN JMP6 9 8 10 4 6 7 5 3 JMP34 TLK10002 EVM FPGA DAUGHTER BOARD REV NA 6522851 GCLK14 C12 C11 C10 U27 U25 R288 R273 C237 PB2 RESET RST PB4 LED11 RST D12 R220 R285 RST PB2 LED3 RST D25 R172 R271 LED4 D3 R238 R276 R278 LS_OK_IN_A D4 R236 LED6 D7 R230 RST PB1 LED7 RST D24 R171 PB1 RESET JMP27 D38 D41 U23 SW5 SW9 MDIO RESET R188 JMP26 D35 D37 U21 R272 D52 Q21 /INIT_B R68 5V R383 /BUSY D53 R269 LED6 D5 R234 R69 DONE D6 R232 GND JMP15 JMP25 D34 D36 LS_OK_OUT_A D2 R240 JMP21 C62 C61 EN GND JMP24 32 C234 U18 RST MDIO RST R189 D32 29 30 31 35 R200 J65 USB D19 D20 C69 C68 3p3V REG EN R191 D33 28 36 37 R243 Q34 U48 JMP13 U22 R42 LOSA C238 U60 2p5V REG U20 C265 R41 C12 R48 R40 C6 D28 26 27 34 MDIO_CON MDC SUSPEND C13 C14 JMP35 LOSA R175 24 25 33 J7 CHA_CLKn LOSB LOSB J9 R265 MDC_CON ONLINE R28 R27 R5 R26 R3 R25 R8 C4 USB D4 D3 R35 U5R44 R36 R18 C2 R475 R474 R15 R14 SW2 R43 U7 CHA_CLKp TST_PASS_A R176 D29 C55 C56 3P3V REG J8 TST_PASS_B 23 J10 HSWAPEN JMP36 J3 JMP15 R177 D30 TEST_PASS_A 22 J11 TLK CLK JMP18 2 23 C U87 C292 U67 U45 RESET RESET D1 D2 R2 JMP47 MDC VDDRA_HS D36 D35 R1 RST RST R305 MDIO VDDRB_HS D40 D39 R306 JMP50 VDDRA_LS D33 R307 JMP62 TRST VDDRB_LS D38 D34 D37 VDDO D26 1p5V D25 JC_VCC_IN 1p8V JC_VCXO JC_VCC_OUT D47 D46 JC_VCCA D45 D44 VDDD D19 D31 GND GND MDIOV 3p3V C10 USB RESET C11 RST RST 2p5V 3p3V 2p5V PRBS PASS C260 U64 LOSA 3p3V 5V 3p3VP LOSB VDDT D28 VDDA D27 D32 1p0VA DVDD D20 D30 MAIN RST SW3 JMP52 SW4 JTAG_V D29 D17 1p5V D42 D43 JMP44 GND LSOK OUTA JMP48 D12 D13 D16 LSOK OUTB GND JMP61 D14 D15 LS A OK LS B OK 1p8V 1p0VD D18 D44 C218 C211 C212 JMP23 20 21 ON JMP42 GND SW1 D22 JMP43 R10 D21 C267 C261 PDTRXB PDTRXA PRBS_EN CLKB_SEL CLKA_SEL TEST_EN GPIO PRBS PASS LOSA LOSB AMUXA AMUXB GND GND LS OKINB LS OKINA PRTAD4 PRTAD3 PRTAD0 PRTAD2 MAIN RESET D10 D11 RST RST BTN ON PRTAD1 R178 GND JC RST JMP45 SCANCFG1 JMP46 STCI 1 2 CHA_CLK_SEL TEST_PASS_B RESET GND U42 SCANCLK SCANCFG0 J5 D31 STCI_VCC SCANIN JMP9 JTAG JITTER CLEANER JMP57 SCANOUT GND JMP29 SDA SCL I2C DISABLE C38 C39 R66 R63 R58 21 25 19 C230 C228 C222 C224 C220 C215 C206 C205 23 PRTAD0 PRTAD1 PRTAD2 PRTAD3 PRTAD4 TDI GND SDA 1 SMA 5 SCL GND 3 R264 I2C 5 U14 22 RATE_SEL_1 GND 1P2V_GTP JMP5 Q18 C46 1 23 E 7 C RATE_SEL_0 U41 G JMP10 TDO VCCAUX_2P5V TMS TCK U90 U63 C291 C266 C263 U51 TX_DISABLE RX_LOS U39 L J A 9 R78 R67 PROG_B_/RST R266 N C MOD DETECT JMP60 3p3V VCCMGT_1P2V GND EN B D F H C200 R267 R U44 TX_FAULT JMP53 U34 D42 D51 D43 VCCINT_1P2V 1P2V C23 0 C246 40 C2 32 36 C247 C235 C203 C201 E C149 C157 C164 AE C173 C148 AC C156 AA C160 C154 W 2 4 6 JMP76 D50 A C SW7 U13 R74 R80 R81 R75 D18 U R76 R79 5 L3 C57 C60 PROG_B_RST D21 CHB_CLK_SEL C72 U1 1P2V GTP JMP31 R70 C227 C229 C223 C221 C216 C219 C204 C208 C251 R365 R362 R363 R366 R361 R364 C253 GND C202 C207 C2 29 37 C2 33 41 C2 C2 C2 C2 D49 28 RX_LOS TX DISABLE D52 TX DISABLE TX_FAULT C2 MOD DETECT 34 D51 R86 R84 R83 FG48 38 30 D48 R87 R85 R82 G J8 J73 R88 R89 XCF32P C2 C2 J45 C2 J46 26 C2 CLKOUTAp CLKOUTAn L6 C69 SMA SPARTAN-6 27 31 35 R381 1 3 R77 R91 C256 C255 C64 JMP11 U15 L4 U9 C29 1P2V REG C61 C33 R49 R54 R52 R46 C30 IO_SIGNALS J6 C GPIO_4 GPIO_5 GPIO_3 GPIO_2 J4 L5 R62 U10 JMP17 CHB_CLKP XC6SLX75T C259 HSRXBn C47 TLK CLK U1 J47 2P5V REG R53 R51 R44 C24 C17 C18 GPIO_1 C98 C65 JMP7 R65 R64 R60 C44 JMP32 XILINX C2 C2 C2 39 TLK10002 TLK10002 LOOPBACK_B LOOPBACK_A LANE2_4_SELECT_B LANE2_4_SELECT_A TEST_EN_B TEST_EN_A PRBSEN PDTRXA_N R385 R386 CLKOUTBp U31 D50 3P3V JMP2 EN GND Q16 C32 1P8V REG R50 R42 JMP30 CHB_CLKN JMP14 CLK1 C51 C21 C213 C217 CLKOUTBn U11 R61 C67 J72 J7 U8 C45 REFCLK1p C2 C247 C242 C241 L1 JMP33 J5 HSRXBp J48 VCCCLK_3P3V U43 D48 2P5V D46 EN GND JMP1 Q15 C31 R56 GND JMP16 R48 C243 C249 +5V C48 JMP13 6522850 GND JMP68 GND C87 C94 C85 C121 VDDT C93 JMP67 C80 C95 GND JMP1 GND C117 C111 C110 C109 1 1p0V ANALOG VDDA C245 JMP21 REFCLK0n REF CLK1n EN C244 6 HSTXBp +5V U33 U30 U42 22 C J6 REF CLK0p C20 C18 R52 C120 C107 J43 C119 GND J44 J42 U8 DVDD JMP69 U79 U76 C271 C270 R69 JMP3 J71 J41 JMP55 C27 C25 U7 R47 TLK10002 EVM MOTHER BOARD REV NA VDDD HSTXBn P2 PLUG 1p0V DIGITAL EN GND C139 C140 JMP70 C91 C90 U73 C89 JMP74 C115 C114 C113 C130 C128 C129 U70 C269 U10 C243 C138 JMP41 BJ 5V C86 C84 JMP72 C108 VDDRA_LS VDDRB_LS 1p8V VDDO U57 C268 C264 R495 PLL_LCK REF_SEL AUX_SEL MDE_SEL PWR_DN AUXn C245 + 5V U39 U36 P1 P2 C293 C294 C285 R312 GND VCCA R315 1p5V VDDRB_HS J70 AUXp JMP58 C127 JMP75 C101 MISO C125 C124 R494 C100 JITTER CLEANER CLK U2 MOSI JMP4 P3 GND JMP35 C118 C99 LE P1 P14 C48 R120 C47 JMP9 R86 VDDRA_HS C123 VCXO C97 R537 R536 VCC_IN JMP73 C83 VCC_OUT JMP63 JMP66 D41 SPI JMP5 GND JMP17 PLL_LOCK JMP64 GND R188 EN GND C82 C81 EN EN C79 + 5V GND 1p8V REG C34 C33 U40 U16 1P8V 1p5V REG D47 VCCO_1P8V U12 C75 U37 C76 R55 JITTER PLL U24 JMP71 3p3V REG D49 VCCAUX_2P5V www.ti.com JMP28 Figure 5. TLK10002EVM Motherboard and FPGA Daughterboard A common method of evaluating the TLK10002 is to place the TLK10002 device in the transceiver mode with its high-speed signals externally looped back to itself. Using an external data source to generate and verify the data on the low-speed side of the device, data fully passes through the TLK10002 device exactly as it does in a system application. Figure 6 is a diagram of how to set up the TLK10002 motherboard and the FPGA daughterboard that uses the FPGA CRPAT generators and verifiers to evaluate the TLK10002. The same 122.88-MHz clock must be applied to both FPGA clock inputs as well as one of the TLK10002 reference clock inputs. Two 5-V power supplies are needed, and 5 V must be applied to both boards individually because no power is shared through the board-to-board connector. Channel B of the TLK10002 must have SMA cables connected as shown with TXBP/RXBP and TXBN/RXBN connected together. In order to evaluate Channel A, an SFP+ Optical Module and optical fiber are required. A single USB cable connected to the TLK10002 motherboard allows access to the registers of both boards. Note that the PRTAD device address pins of the TLK10002 boards must be different in order to prevent writing to the wrong device’s registers. The TLK10002 motherboard comes configured with PRTAD equal to address “0” and the FPGA daughterboard is configured with the address of “1.” In order communicate with the FPGA registers in the TLK10002EVM GUI, the PRTAD address of the FPGA daughterboard must first be entered into the Port Addr field on the Low Level Register Configuration tab and changed back to the TLK10002 address prior to re-accessing the TLK10002 registers. SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 13 Test and Setup Configurations www.ti.com SUSPEND D4 5 VC C M G T _1 P2V BJ Q 17 G ND EN JM P3 15 16 17 18 19 GND RE-PROGRAM FPGA CL K2 JMP22 GCLK2 5 IO SIGNALS GCLK27 30 31 32 GCLK12 39 USB R 30 R 40 R 31 R 32 J2 U18 D 16 D 22 D 23 C 236 U SB _ SU S P 3P 3V R 213 M DI O 2P 5V Q 31 R 19 9 Q 32 R 21 4 MAIN RESET U S B_ ON L I N E R2 C4 D 15 D1 4 U S B_ R ST R5 R9 R6 R3 C1 R 38 R 39 R 35 1 R 20 1 R 3 52 R 20 2 D 13 R 134 R 10 R 26 R 33 U6 U SB _ /R ST LS _ OK _I N _B RS T LS _ OK _O U T_ B D2 6 R 173 RS T R 1 31 R8 C5 U5 U 16 C 2 33 GND MAIN RST R1 C9 SW6 R34 C2 R 200 D 39 D40 U 27 PB4 RESET JMP 12 R 25 C8 R 1 32 R 171 R 172 D2 5 D2 4 R2 95 R 28 7 L S_ O K_ O U T_A D2 7 R 174 RS T PB 3 GND PB 4 RST R2 89 R 29 2 D41 RS T L S_ OK _ IN _ A R 242 R 240 L ED 2 D1 LE D 1 D2 LE D 3 R 238 R 236 R 28 5 D38 U25 PB3 RESET JMP 27 C 24 0 D5 4 MDIO RESET R189 D3 SU S PE N D ED 28 29 37 38 GCLK17 USB RESET C 12 C 11 C 10 JMP 20 R 197 SW1 SW2 SW3 XILINX JTAG PROGRAMMING INTERFACE SW4 SW8 JMP 19 POST _ LS MD I O R 205 MD I O MD C R 198 R 206 R11 JTAG 26 27 35 36 RST JMP 26 GND PB 3 RST 25 34 RST MDIO C 2 39 R2 73 U23 PB2 RESET 14 9 10 JM P8 GND JM P3 4 TLK10002 EVM FPGA DAUGHTER BOARD REV A 6522851 R37 7 GND MD I O R S T J M P 18 J M P 36 SW 5 GND C7 USB FOR TLK10002 GUI +5V Q 19 JM P6 8 6 7 4 5 3 1 2 R 26 4 GCL K14 HSWAPEN SW9 R 188 LE D 5 D4 R 232 R 234 D5 LE D 6 RS T PB 2 L ED 7 D6 RS T R2 76 D 35 D37 GND PB 2 RST C 2 37 R 27 1 R 27 8 JMP 25 C 23 8 R 226 R 230 R 238 D8 LE D 9 L ED 8 D7 R 224 L ED 11 D1 0 L ED 10 D9 RST PB 1 R 26 9 RS T R 222 R2 72 R 68 R 3 83 /B U SY D 53 R 243 24 33 J7 MD C J65 JMP 15 D34 D 36 U21 PB1 RESET J9 R 265 Q3 4 U 22 EN LE D 12 D 11 R 232 D ON E GND D12 R 69 GND PB 1 RST Q 21 / I NI T _B JMP 24 J10 C 234 R 191 D 33 D 32 L ED 4 JMP21 U 20 C68 C69 3p3V REG D 19 D 20 R 39 8 JMP 35 PB 4 RS T LOSB LOSA R175 LOSA USB GND GND EN C 38 C 39 0 CLK1 C 221 C 216 C 219 C 204 C 208 C 2 24 C2 20 C2 15 C 2 06 C2 05 J8 J3 21 22 23 J11 CHA_CLKp CHA_CLKn D 28 PLUG 3P3 VREG R 58 R 66 R 63 2 23 _SEL JMP 23 20 TLK CLK RS T C 61 C 62 2p 5VREG R 176 LOSB C 54 C 56 REG REG GND J MP 5 C 46 Q 18 C 23 C2 4 G PI O _5 G PI O _4 C 2 31 C 227 C 229 C 223 21 1 9 C 2 30 C2 28 C2 22 23 P R TA D 4 P R TA D 3 JM P21 C218 C211 C212 D 29 EN C55 D 52 5V JM P 4 GND EN 2P5 VREG R5 1 R4 4 R5 3 P R TA D 1 P R TA D 2 P R TA D 0 T DI T DO CHA _CLK TST _PASS _B TST _PASS _ A TEST _PASS _A 13 11 12 13 D4 3 D4 2 V C C I NT _1 P2V D5 1 D5 0 U3 4 1P2 V _G TP D4 4 1P 2V D4 9 D4 8 V C C CL K _3 P3V EN GND JM P 2 Q 16 C32 1P8V REG C 17 J M P3 0 25 1 SMA R2 88 U6 0 C2 65 U4 8 C 260 R4 1 C 13 C 14 R 42 R 40 C 12 R 48 C6 R 18 C2 R2 8 R2 7 R 5 R2 6 R 3 R2 5 R 8 ONLINE C 10 R 35 R 44 U5 R 36 C4 USBDD 43 R 43 U7 D2 M DC M DI O 3 U 14 C U8 7 U6 7 C 2 92 C 26 7 RESET RESET C11 D1 R2 R475 R474 R 15 R14 SW 2 JM P 50 D 35 D 39 D 33 D 37 U4 5 C 26 1 D 43 D 42 RST RST R 3 07 R 3 06 C 3 02 T RST V D DR A _H S D 36 V D DR A _L S V D DR B _L S V D DR B _H S D 40 D 34 D 38 V D DO JC _V C C _IN JC _V C X O JC _V C C _O U T D 26 D1 9 JC_ V C C A D2 0 1p 8V 1 p5V D 25 D 46 D 47 D 44 D 45 D2 7 VD D A VDDD JMP 47 R1 RST RST GND JMP 62 3p3V R 30 5 I2 C D IS A BL E JM P44 GN D GND L S O K O U TA JM P4 8 D1 2 D1 3 D 1 6 L S O K O U TB P RB S P AS S L OS A 2 p5V 3 p3V 3 p3V P LO SB 5 V D2 8 VD D T D V DD D 31 D 32 D 29 D 30 1p0V D 1p5 V 1p0 VA D 17 D 18 D 21 USB RESET GND R1 0 1p8 V 2p5V MDIOV SW 1 D 22 C 2 46 VCCAUX_2P5V T MS TCK U9 0 U6 3 C 29 1 C 266 U5 1 C 26 3 P D TR X B P D TR X A PR B S _EN C L KB _S E L C L K A_S E L TE ST _E N PA S S GP I O LO S A LO S B PR B S AM U X A GN D OK I N B LS OK I N A AM U X B LS PR T A D4 GND GND JM P 6 1 D1 4 D1 5 LS A O K 1 5 JMP15 R 177 JMP PROG _B _ /RST R 78 C 26 1 SCANCFG 7 JMP 10 D 30 C200 R 21 2 LS B O K JTAG_V SCANOUT C 24 7 C 203 C 201 R41 R 572 R41 0 468 5 R 570 R 416 TX D I S A BLE D5 0 R 418 TX D I S A BLE D4 9 R566 RX _L O S TX _F A ULT D5 2 D5 1 PR T A D2 PR T A D3 0 SCANIN GND MAIN RST SW 3 JMP 52 ON SCANCFG JMP 42 3p 3V 9 _B ON U 42 JMP 43 RST RST BTN SW 4 U 64 GND SCANCLK R178 MAIN RESET D 10 D 11 GND 57 G A 5 JMP L J TEST _PASS _B RESET JC RST N C J5 D 31 JITTER CLEANER GND PROG R 266 E GND GND SW7 _B _ RST R 67 R 267 R 6 JMP9 JTAG SDA JMP 29 SDA SCL JMP 46 F H 22 SCL GND C 149 C RATE _SEL _1 STCI _VCC FG4 8 71 5R 67 R5 569 R 65 5R RATE _SEL _0 U 41 D I2C MOD DETECT 3p 3V B _1 P2 V R 74 R 80 R 81 R 75 GND U44 J73 JMP 60 E 2 4 JMP 76 45 PROG C 157 C 164 AE C 173 C 148 AC C 156 C 160 AA C 154 W R 76 R 79 L3 IO_SIGNALS D 18 U 3 5 C VCCMGT U 13 U1 C 57 C 60 R 70 R86 R84 R 83 R 82 X C F32 P R412 R409 417 R J45 TX _ DISABLE JMP _1P 2V 1 P2V GTP JMP 31 GND D 21 C 72 R 88 R89 87 R 381 R R 85 A R91 C256 C255 CLKOUTAn CLKOUTAp RX _LOS U 39 U3 1 3P 3 V D4 6 V C C AU X _2 P5 V U 43 2P 5 V 1P 8V D4 7 V C CO _1 P 8V U 37 C 25 1 R 36 5 C 2 35 C 259 G TX_ FAULT JMP 53 L4 L6 C69 CHB _CLK _SEL _ B _ A 1 R413 MO D D E TE C T G PI O _3 G P I O _1 LANE 2_4 _SELECT LANE 2_4 _SELECT U9 C 29 1P2 V REG C 61 C64 JMP 11 C 21 C 213 C 217 R49 R46 C 30 VCCCLK _3 P 3V TEST _EN _B TEST _EN _A C 282 SFP+ MODULE WITH LOOPBACK J6 C 33 R54 R52 U10 VCCINT TLK CLK J8 D4 8 J4 L 5 C 65 R62 JMP 17 C67 R 36 2 R 36 3 R 36 6 R 36 1 R 36 4 C 25 3 _A CLKOUTBn PR T A D1 U4 0 D5 5 VI N T_ 1P 8V U4 8 GND Q 15 C3 1 R 56 V CC I N T _1P 8V JMP13 GND 6522850 JM P68 GND _B LOOPBACK C2 02 C2 07 5 3 5R74 R40 R 576 R40 5R78 R401 5R 80 R399 3 TL K 10 002 T LK10002 406 R R57 5 7 R404 R57 57 R 02 4R R400 3R79 J72 J 46 C47 R 65 R 64 R 60 JMP 32 CHB_ CLKPJMP 16 JMP 7 C 44 GND SPA RTAN -6 LOOPBACK PRBSEN PDTRXA _ N HSRXBn J47 U11 R 61 SMA R77 CLKOUTBp P2 U 15 U1 PR T A D 0 CHB_CLKN +5V +5V C 242 VCCO _1 P8 V GND JMP33 GND J7 C249 P1 C 45 R 385 U 47 R 386 STCI U8 R 48 REFCLK1p J5 J48 P3 U 33 C 241 L 1 VCCAUX _ 2P 5V C247 5V GND U 30 C 245 C 51 C243 HSRXBp GND C 48 C9 8 GND JM P67 C 94 C 86 C 87 C 95 GND GND C 11 9 C 11 0 C 11 1 C 10 9 1 C 93 C 244 26 REF CLK1n C 80 VDDT U42 2 C REF CLK0 p REFCLK0n 1p0 V ANALOG VDDA JM P70 C 117 J 6 HSTXBp R52 DVDD C 12 0 HSTXBn EN U7 GND C20 C18 J MP 1 R 69 J43 R 47 JMP 37 U8 VDDD JMP 3 GND J42 C 27 C 25 C 12 1 U 79 EN GND J44 P2 C140 C 85 C9 1 C9 0 C8 9 C 115 C 114 J M P 74 U 73 C 113 C 130 C 129 J M P 71 U 70 C 2 69 U 57 C 2 68 C 264 C 285 R49 5 AUXn J MP 1 5V 1p0V DIGITAL C 107 JMP 55 BJ PLUG TLK10002EVM MOTHER BOARD REV A U 39 C 243 JMP 41 JM P72 C 84 U 10 J71 J 41 C245 C 138 C 139 VDDRA_ LS VDDRB_ LS 1p8V VDDO C 108 C 27U17 6 A U X_ S EL C 128 J 70 C 293 C 294 P LL_ LC K M D E _S E L R E F_ S EL PWR _ D N GND VCCA R3 12 R 315 1p5V VDDRB_ HS R 494 C 1 25 C 124 AUXp JMP 58 SPI C 127 JM P 75 C 101 JITTER CLEANER CLK U 2 MOSI MISO C 12 3 C 118 C 99 R537 R536 VDDRA_HS C 97 JM P 73 VCC_OUT VCXO 63 JMP 66 U 36 XC6SLX75 T JM6 P4 LE C 100 C 83 JMP D 41 VCC_IN + 5V X ILINX GND PLL_LOCK R 120 P1 JMP 35 JMP 17 C 81 + 5V P 14 C 48 C 47 C 18 J MP 5 R 86 C 27 0 C 82 GND R 188 EN GND JM P 9 EN C 79 GND 1p8V REG EN JMP14 U 16 C 34 C 33 EN 1p5V REG R4 2 U 12 C 75 JM P69 C 76 R5 0 U24 122.88MHz CLK1 JITTER PLL 3p3V REG 5V G P I O _2 GND 122.88MHz GND PRE _LS GND JMP 28 122.88MHz Figure 6. CRPAT Test Setup With FPGA Generator and Verifier It is possible to use the Link Optimizer portion of the TLK10002 GUI to optimize the high-speed link on a third-party system board. Connect the TLK10002EVM SMA to the TLK10002EVM motherboard and connect the MDC_POST_LS and MDIO_POST_LS signals from the breakout board to the system board. Ensure that the system PRTAD[4:0] address is different than the motherboard’s PRTAD[4:0], and enter the system address in the Port Addr field on the Low Level Register Configuration tab of the TLK10002EVM GUI. 14 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback Test and Setup Configurations www.ti.com PRTAD 0 PRTAD 1 PRTAD 2 PRTAD 3 PRTAD 4 MDC M DIO TL 10 002 TLKK10002 SYSTEM BOARD THAT NEEDS TO BE OPTIMIZED GND JM P9 J11 INB2N J8 OUTB 1N J12 OUTB2N J9 OUTB 1P J13 OUTB 2P J M P 72 R 2 INB0N MDC_ POST_ LS GND 6522850 MDIO _POST_LS JMP3 MDC_PRE _LS GND GND JM P6 8 GND MDIO _PRE_LS J14 INB3P JMP4 OUTB3 N J16 C243 J15 INB3 N OUTB 3P J17 JMP1 GND LS_ OK_IN_B LS_OK_OUT_ B CHB _CLKOUTP J18 R X _L O S T X D I S AB L E T X D I S AB L E D5 2 D4 9 D5 0 CHB_ CLKOUTN J19 J36 CHA_ CLKOUTP JMP2 R572 T X _F AU L T 5468 M O D D E TE C T R571 7 R56 R569 65 D5 1 CLKOUTAp J45 R5 D4 8 CLKOUTAn J 46 J 47 R570 CLKOUTBp R566 J48 GND LS_ OK_IN_A LS_OK_OUT_A CLKOUTBn C249 5 3R 18 R HSRXBn J37 CHA _CLKOUTN R 36 J72 U1 J 7 R1 7 4 R57 6 R57 R 578 573 R 577 R 575 R C247 R580 HSRXBp R379 T LK 1 00 02 TLK10 002 J 5 J8 JMP J33 INA0P 76 TX _DISABLE U 90 U 63 3R 4 C 2 91 J35 OUTA0 N I2C_SDA U 87 C 29 2 RATE _ SEL _ 1 C 26 7 C 26 1 U4 5 RATE _ SEL _ 0 U6 7 MOD DETECT SDA I2C_SCL 3 R RX _ LOS C 26 6 C 2 63 TX _FAULT U 51 J73 J32 INA0N J34 OUTA0 P J27 OUTA2N OUTA1 N J26 OUTA2P J30 OUTA1 P D 37 ONLINE SUSPEND JM P5 C 62 C 61 U6 0 GND C 69 C 68 J23 OUTA3N U2 2 3p3 VREG J22 OUTA3P J25 INA2P USB EN R24 C 12 13 EN J6 5 R 43 R4 1 C 13 C 14 J31 GND J29 INA1P R 03 U 48 C 26 0 R 28 R 5 R 27 R 26 R 3 R8 R 25C C4 USB DD 43 C1 0 C6 R 44 U 5R 36 R1 8 C2 R 15 R 14 2p5V REG RESET RESET C1 1 MDIO 47 JM P5 0 JMP SW 2 R 35 R4 2 D4 2 D4 3 RST RST R 30 5 R 3 07 R 30 6 R475 R 474 TRST V D D R A_ H S D 36 D 35 V D D R B_ LS V D DR B _ H S D 40 V D D R A_ LS D 34 D 39 D 38 D 33 VDDO 1p8V J C_ VC C _ N I D 26 J C_V C C _ O U T D 46 1 p5V D 47 J C_V C X O D 44 JC _V C C A D 45 D2 0 D 27 D 19 V DD D D VD D V D D T D 28 D 30 V D DA 1 p0V A D 31 1p0 V D D 32 1p5 V D 29 1p8 V D 17 U7 D2 J21 INA3P 9 2 R D 18 D1 R2 R19 23 R D 21 R1 RST RST R 10 D 22 1 GND JMP 62 GND GND J20 INA3N JMP 52 SW 1 SCANCFG JMP 46 STCI D 25 PR B S PA S S L OS A JTAG_V SCANOUT SW 3 JMP 2p5 V 3p3 V 2p 5V 3p 3V 5V SCANIN 3p 3V P L O S B LS A O K 0 LS B O K SCANCFG MAIN RST MDIOV 3p3 V USB RESET C 30 2 U42 GND SW 4 U 64 GND SCANCLK JMP 43 JMP 42 MDC I 2C STCI _VCC DS I A B LE J M P 44 U 41 GND GND JM P 4 8 LS O K O U TA LS O K O U TB JC RST JMP 45 D1 2 D1 6 D1 4 D1 5 60 3 p3 V D1 3 U 39 JMP GND JM P 61 53 RST RST BTN U 20 GND 20 R JMP MAIN RESET D 10 D 11 C 265 RESET JMP 57 R4 8 R4 0 PD TR X A PD TR X B C LKB _ SE L C LK A_ S EL P RB S_ E N T E ST _E N G PI O LO SA LO SB PR B S PA SS A M UX A A M UX B G ND LS O KI NA GND LS O KI N B P R TAD 4 P R TAD 3 P RT AD 2 P RT AD 1 JITTER CLEANER GND ON P R TA D 0 SCL 6522852 16 R REFCLK1p TLK10002 EVM SMA BREAKOUT DAUGHTER BOARD R1 5 C 98 C 87 J M P6 7 C93 C 94 GND C 85 C 121 JM P7 0 C 80 VDDT R1 INB0P 1p0V ANALOG VDDA C 95 GND JM P 1 R 52 C 120 C 111 C 119 U 79 EN C 86 C9 1 C9 0 C8 9 C 11 5 C 11 3 C 11 4 J M P 74 C 13 0 C 12 9 U7 6 C 27 1 C 109 C 110 REF CLK1n J3 C 20 C 18 DVDD C117 J2 U8 VDDD J43 REF CLK0 p C 27 R69 EN GND J 44 J42 REFCLK0n J7 INB1 N P2 C 140 TLK10002 EVM MOTHER BOARD REV A C 25 JMP 3 J10 INB2P PLUG J 6 HSTXBp J6 INB1 P OUTB0P OUTB0 N 5V 1p0V DIGITAL C 107 JMP 55 JMP 41 BJ GND J41 C245 C 84 U 10 J71 HSTXBn J5 C 138 C 139 VDDRA_L S VDDRB_L S 1 p5V 1 p8V C 108 U7 0 C 26 9 J M P 71 C 12 8 U5 7 C 26 4 R495 AUXn C 27 0 A UX _ S EL R E F_ SE L M D E_ S E L P L L_ LC K P WR _ D N C293 C294 C 28 5 R 31 2 GND VCCA VDDO C 26 8 C 1 01 J70 AUXp R 315 C 127 JM P 75 C 1 25 C 124 R494 MISO JMP 58 SPI C 1 23 JITTER CLEANER U2 MOSI VDDRB_ HS VCC_ OUT C 118 C 99 CLK VDDRA_ HS C 97 JM P7 3 R537 R536 M J 6 P4 VCC _IN LE JMP 66 VCXO JMP 63 D 41 C 1 00 C 83 GND PLL_LOCK J4 + 5V JMP 35 JMP 17 C 81 P1 2 JM P5 R 86 R1 C 82 GND + 5V P 14 C 48 C 47 R 120 6 R R 18 8 C 79 EN GND GND 1p8V REG EN REV A U 16 C 34 C 33 EN R 11 1p5V REG U 12 C 75 J M P6 9 C 76 MDIO / MDC POST _LS SIGNALS CONNECTED TO SYSTEM BOARD 5V R 5 JITTER PLL U 24 U7 3 3p3V REG SET THE “PORT ADDR” FIELD OF THE GUI TO MATCH THE PRTAD [4:0] OF THE SYSTEM BOARD AND ENSURE IT IS DIFFERENT THAN THE PRTAD [4:0] OF THE EVM MOTHER BOARD J24 INA2N J28 INA1 N JMP 15 7 R 11 JTAG USB FOR TLK10002 GUI Figure 7. Optimizing the High-Speed Link of a System Board Through the GUI SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 15 Test and Setup Configurations JITTER PLL C76 U12 1p5V REG U16 C75 J11 INB2N J8 OUTB1N J12 OUTB2N J9 OUTB1P J13 OUTB2P MDIO_POST_LS GND MDC_PRE_LS MDIO_PRE_LS REFCLK1p OUTB3P J17 J15 INB3N C2 29 37 C2 33 C2 41 C2 27 31 35 JMP1 C2 C2 C2 39 J72 LS_OK_IN_B LS_OK_OUT_B U1 J7 HSRXBn CHB_CLKOUTP J18 J37 CHA_CLKOUTN CHB_CLKOUTN J19 J36 CHA_CLKOUTP JMP2 40 36 C2 C2 32 TX DISABLE D49 C2 RX_LOS TX DISABLE D52 D50 28 TX_FAULT C2 MOD DETECT 38 D51 C2 34 J45 30 J46 C2 CLKOUTAp CLKOUTAn J47 C2 CLKOUTBp 26 C2 D48 J48 GND LS_OK_IN_A LS_OK_OUT_A CLKOUTBn C249 GND C247 C2 TLK10002 TLK10002 J5 J8 JMP76 I2C_SDA U87 C292 U45 C261 RATE_SEL_1 C267 RATE_SEL_0 U67 MOD DETECT JMP47 SW2 ONLINE SUSPEND J35 OUTA0N J32 INA0N J34 OUTA0P J27 OUTA2N J31 OUTA1N J26 OUTA2P J30 OUTA1P J25 INA2P J29 INA1P J24 INA2N J28 INA1N C62 C61 U60 JMP5 J33 INA0P J21 INA3P U20 2p5V REG GND J20 INA3N U48 JMP13 C69 C68 GND EN J22 OUTA3P U22 3p3V REG C13 C14 R42 R41 R43 C12 R48 R40 C6 R35 U5R44 R36 C4 USB D4 D3 C10 U7 R18 C2 R475 R474 R15 R14 R28 R27 R5 R26 R3 R25 R8 VDDRA_HS D36 D1 D2 R2 MDC VDDRB_HS D40 D35 D39 R1 RST RST R305 MDIO VDDRA_LS JMP62 JMP50 VDDRB_LS D38 RESET RESET C11 RST USB RESET R306 TRST VDDO D26 D34 D33 D37 D25 JC_VCC_IN JC_VCXO JC_VCC_OUT 1p8V 1p5V D47 D46 D44 JC_VCCA D45 VDDD D19 DVDD D20 D32 D31 VDDA D27 1p0VA VDDT D28 D30 D29 D17 1p5V 1p8V 1p0VD D18 D22 R307 R10 D21 GND GND MDIOV 3p3V SW1 JMP46 STCI D42 D43 LOSA 3p3V SCANOUT SCANCFG1 MAIN RST SW3 JMP52 JTAG_V 2p5V 3p3V 5V PRBS PASS LS A OK LS B OK 3p3VP LOSB U42 GND SCANCLK SCANCFG0 GND 2p5V STCI_VCC SCANIN JMP42 SW4 U64 RST GND JMP48 JMP44 I2C DISABLE JMP43 RST RST BTN USB J65 GND JC RST JMP45 U41 D12 LSOK OUTA GND D14 D15 D13 U39 JMP60 3p3V D16 LSOK OUTB JMP61 JMP53 MAIN RESET D10 D11 C265 RESET JMP57 C260 PDTRXB PDTRXA PRBS_EN CLKB_SEL CLKA_SEL TEST_EN GPIO PRBS PASS LOSA LOSB AMUXA GND AMUXB GND LS OKINB LS OKINA PRTAD4 PRTAD3 PRTAD0 PRTAD2 JITTER CLEANER GND ON PRTAD1 SDA SCL I2C_SCL U90 U63 C291 RX_LOS C266 C263 TX_FAULT U51 TX_DISABLE J73 6522852 OUTB3N J16 J14 INB3P JMP4 C243 HSRXBp REV NA GND 6522850 GND JMP68 INB0N MDC_POST_LS JMP3 C98 GND C87 JMP67 C93 C94 C86 VDDT C95 GND JMP1 GND C80 C121 C120 GND C111 C110 C109 J6 C117 J3 INB0P 1p0V ANALOG VDDA C85 C91 C90 C107 J43 REF CLK1n EN DVDD C119 U76 C271 J44 REF CLK0p C20 C18 VDDD JMP3 J2 U8 R52 JMP69 J41 J42 REFCLK0n J7 INB1N OUTB0P OUTB0N P2 TLK10002 EVM MOTHER BOARD REV NA C27 C25 R69 EN GND C139 JMP70 U73 C89 JMP74 C115 C114 C113 C130 1p0V DIGITAL HSTXBn HSTXBp J10 INB2P C140 PLUG JMP72 C84 U10 J71 JMP55 J6 INB1P TLK10002 EVM SMA BREAKOUT DAUGHTER BOARD VDDRA_LS VDDRB_LS 1p8V C108 U70 C269 C129 C128 C270 R495 PLL_LCK REF_SEL AUX_SEL MDE_SEL PWR_DN AUXn C245 J5 C138 JMP41 BJ 5V C293 C294 C285 R312 GND VCCA 1p5V VDDRB_HS AUXp R315 VDDO U57 C268 J70 C264 MISO JMP58 C127 JMP75 R494 C124 C125 C101 C99 C123 VCXO JITTER CLEANER CLK U2 MOSI J4 + 5V JMP35 C118 R537 R536 LE P1 P14 C48 R120 C47 JMP9 R86 VDDRA_HS JMP73 VCC_OUT C83 VCC_IN C97 C100 JMP63 JMP66 D41 SPI JMP5 GND JMP17 PLL_LOCK JMP64 GND R188 EN GND C82 C81 EN EN C79 + 5V GND 1p8V REG C34 C33 U79 U24 JMP71 3p3V REG www.ti.com J23 OUTA3N EN GND JMP15 C7 R11 JTAG Figure 8. TLK10002EVM Motherboard and SMA Breakout Board 16 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM Motherboard Schematics www.ti.com 10 TLK10002EVM Motherboard Schematics 5 1 2 3 4 REVISIONS NOTES: ECR NUMBER DATE xx/xx/xx ------- ECR 1. PLACE NET NAMES ON ALL JUMPERS AND HEADERS. 2. PLACE ALL PARTS OTHER THAN SMP CONNECTORS ON A 0 OR 90 DEGREE ORIENTATION. 3. SERIAL DATA SHOULD BE ROUTED AS SINGLE-ENDED 50 OHM TRANSMISSION LINES ON OUTSIDE LAYERS. ROUTING DISTANCE SHOULD BE 3 INCHES OR LESS. 4. USE ROGERS MATERIAL FOR OUTSIDE LAYERS AND FR4-370 MATERIAL FOR INSIDE LAYERS. 5. SERIAL AND REFCLK NETS MUST MATCH WITHIN +/- 0.5 MILS D D 6. MATCH DIFFERENTIAL TRACE WIDTHS OF SERIAL AND REFCLK LINES WITH SMP/SMA PADS. 7. PLACE TI LOGO IN TOP SIDE METAL SCHEMATIC SHEET INDEX: SHEET 01: SHEET 02: SHEET 03: SHEET 04: SHEET 05: SHEET 06: SHEET 07: SHEET 08: SHEET 09: SHEET 10: SHEET 11: SHEET 12: SHEET 13: SHEET 14: SHEET 15: SHEET 16: SHEET 17: SHEET 18: SHEET 19: SHEET 20: C B TLK10002 CHAR COVER SHEET AND NOTES USB INTERFACE 1P0V, 1P5V, 1P8V REGULATORS 2P5V, 3P3V REGULATORS POWER DISTRIBUTION DEVICE POWER AND GROUND GLOBAL SIGNALS MDIO,JTAG, AND I2C INTERFACE CLOCKS JITTER CLEANER CONTROL LOW SPEED DATA SIGNALS HIGH SPEED DATA SIGNALS 1P0V, 2P0V, 3P3V REG LEDS 1P5V, 1P8V REG LEDS 5V, 3P3V PLL, AND VDDO LEDS VDDA, VDDT, VDDD, DVDD LEDS VDDRA LEDS VDDRB LEDS JITTER CLEANER POWER LEDS BOARD TO BOARD CONNECTOR C B TEXAS INSTRUMENTS A A SCHEMATIC TITLE TLK10002 EVM MOTHER BOARD ENGINEER J. NERGER DATE 11/18/10 PAGE TITLE LAYOUT G. ROTH TLK10002 DATA SHEET REVISION: 0.7 RELEASED DATA SHEET LAST UPDATED ON: 09/27/10 5 J. NERGER 4 2 3 DATE 11/18/10 DATE 11/18/10 COVER PAGE AND NOTES SIZE DOCUMENT NUMBER REV B 6522850 NA 1 SHEET of 20 1 Figure 9. Cover Page and Index, Sheet 1 of 20 SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 17 TLK10002EVM Motherboard Schematics www.ti.com 3P3V U7 D1 C1 USB_/RST_B 6 1 4 5 100K 100K R3 R5 2 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 38 8 9 4.99K R34 4.99K 4.99K R33 /VREN S2 S3 GND1 GND2 GND3 GND4 GND5 P3.0/S0/RXD P3.1/S1/TXD P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 WP EE_SCL EE_SCL_S EE_SDA SCL SDA 100 USB ONLINE LED B 3P3V SPI_MISO 10 SPI_MOSI SPI_ CLK SPI_SS1 10 10 10 S0 S1 3P3V A 14 15 20 1 4 2 3 6 7 63 64 12 11 58 57 56 55 54 53 52 51 R23 USB SPI BUS 22 23 25 26 27 28 29 30 R18 R19 TUSB3210 R45 R46 R47 EEPROM 24LC512-I/SM R32 DNI_4.99K 1.5K 1.5K 8 7 6 5 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 USB PROGRAMMING SWITCH 1 PIN DIP SMD SW1 1 2 R40 R41 R42 A0 VCC A1 WP A2 SCL VSS SDA 5 21 24 42 59 4.99K 0.1uF 0.1uF 0.1uF C14 C13 C12 1 2 3 4 R14 R15 R474 R475 X2 /VREN GREEN R25 R26 R27 R28 R24 2 DNI_4.99K DNI_4.99K DNI_4.99K R31 R30 R29 22pF C11 S3 U4 X1 X2 3P3V 31 32 33 34 35 36 40 41 USB_ONLINE_L DNI_4.99K 1M 1 6 61 60 12.00 MHZ 3P3V 2 DNI_4.99K TUSB3210 8,12,20 8,12,20 8 8 D4 1 USB_ONLINE X1 USB I2C BUS I2C_SDA I2C_SCL I2C_RESET I2C_INT R36 PUR DP DM 3P3V S2 DNI_4.99K DNI_4.99K DNI_4.99K 17 18 19 43 44 45 46 47 48 49 50 R35 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 4.99K 0.1uF C8 22pF R11 C 1p8VDD 4.99K 100K PUR DM C10 USB_SUSPENDED R44 33 33 16 3P3V R43 DP_CON 13 2K 2K R21 R22 DM_CON 3P3V R37 R38 R39 /RST 4.99K 4.99K 4.99K 4.99K 3 X1 A2 USB_SUSPENDED_B TEST0 TEST1 TEST2 RSV1 RSV2 NC1 NC2 NC3 NC4 NC5 NC6 S1 S2 2 PUR_R DP USB Type B Conn 4.99K 4.99K 4.99K VCC1 VCC2 VCC3 5 Q2 MMBT4401LT1 1.5K R20 B A1 D USB_RST_N 1 C9 1uF A0 USB SUSPEND LED 2K 2K 4.99K 4.99K 100K 0.1uF 0.1uF PUR_EN R17 15K C5 10uF R16 USB INTERFACE 100 1P8VDD 37 1 2 3 4 R4 MMBT4401LT1 SUSP R13 C7 0.1uF C6 C4 10 39 62 5V_USB 5V DM DP GND USB_SUSP_L 3P3V Light Touch Switch A 100K 2 U3 C J65 49.9 R10 USB RESET LED 100K USB_RST TPS3125J18 USB_/MR R8 100 3 4.99K USB_/RST R2 R7 4.99K 4 3 1 2 3 /RST GND RST /MR R450 SW2 1 2 5 VDD USB_RST_L Q1 1 U5 4 2 ORANGE 3P3V AND RESET MONITOR 5 USB /RESET LED D3 1 USB_SUSP_C VOLTAGE SUPERVISOR 0.1uF 100 RED E2 USB RESET PUSHBUTTON R1 D2 1 USB_RST_C ZXTD09N50DE6 C2 USB_/RST_L 2 3 B2 D 3P3V 2 GREEN C2 3P3V 1 USB_/RST_C B1 E1 USB_RST_B 1 2 3 4 5 TEXAS INSTRUMENTS R48 USB MDIO BUS USB_MDC USB_MDIO 8 8 PAGE TITLE USB INTERFACE SIZE B 5 3 4 2 DOCUMENT NUMBER REV NA 6522850 PAGE 2 of 20 1 Figure 10. USB Interface, Sheet 2 of 20 18 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM Motherboard Schematics www.ti.com 1 2 3 4 1.0V ANALOG REGULATOR 1.0V DIGITAL REGULATOR U8 DISABLE GND GND_PP 12 21 TPS74401RGW MUST USE TPS74401 3A LDO 1P0V_D_REG_EN NC1 NC2 NC3 DISABLE GND GND_PP 68uF 10uF 1uF C25 C27 1.13K 12 21 TPS74401RGW MUST USE TPS74401 3A LDO C28 0.001uF C24 16 FB 2 3 4 D R67 R66 1uF 4.99K 4.7uF 100uF C22 C23 1uF 10uF 68uF 1 2 1P0V_D 13 14 17 NC4 NC5 NC6 SS 1 18 19 20 9 PG EN 15 JMP3 OUT1 OUT2 OUT3 OUT4 BIAS 11 R69 R52 4.02K 4.02K C21 0.001uF IN1 IN2 IN3 IN4 10 16 FB NC1 NC2 NC3 C20 SS 1.13K 13 14 17 NC4 NC5 NC6 C18 EN 5V 1P0V_D_REG_SS 2 3 4 9 PG 5 6 7 8 1P0V_A C26 1P0V_A_REG_SS 1P0V_A_REG_EN BIAS U10 1 18 19 20 OUT1 OUT2 OUT3 OUT4 C17 15 C19 JMP1 1 2 11 IN1 IN2 IN3 IN4 R50 1uF 4.99K 10 R49 C16 C15 100uF D 4.7uF 5V 1P0V_A_REG_ADJ 5 6 7 8 1P0V_D_REG_ADJ 5 C C 1.8V REGULATOR 1.5V REGULATOR JMP9 1 2 DISABLE 1P8V_REG_EN FB NC1 NC2 NC3 GND GND_PP 16 12 21 10uF 1uF C47 C48 SS TPS74401RGW B MUST USE TPS74401 3A LDO C49 0.015uF R86 R120 4.30K MUST USE TPS74401 3A LDO C35 0.015uF 12 21 2 3 4 9 13 14 17 68uF NC4 NC5 NC6 3.57K PG EN 1P8V C46 15 BIAS 1 18 19 20 R118 1uF C45 4.99K R117 4.7uF C44 100uF C43 1uF 10uF 68uF 11 OUT1 OUT2 OUT3 OUT4 2.70K GND GND_PP TPS74401RGW DISABLE 10 IN1 IN2 IN3 IN4 16 FB NC1 NC2 NC3 5 6 7 8 5V C34 SS C33 13 14 17 NC4 NC5 NC6 4.12K 9 PG EN C32 BIAS 1P5V 1P8_VREG_SS 1P5V_REG_SS 1P5V_REG_EN 2 3 4 1 18 19 20 OUT1 OUT2 OUT3 OUT4 R84 1uF R83 11 15 JMP5 1 2 C31 4.99K 4.7uF C30 100uF C29 B 10 U16 IN1 IN2 IN3 IN4 1P5V_REG_EN_ADJ 5 6 7 8 5V 1P8V_REG_ADJ U12 A A TEXAS INSTRUMENTS PAGE TITLE 1P0V, 1P5V, 1P8V REGULATORS SIZE B 5 4 2 3 DOCUMENT NUMBER REV NA 6522850 PAGE 3 of 20 1 Figure 11. 1P0V, 1P5V, and 1P8V Regulators, Sheet 3 of 20 SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 19 TLK10002EVM Motherboard Schematics www.ti.com 2.5V REGULATOR 3.3V REGULATOR 12 21 GND GND_PP 1 2 3P3VREG_EN FB NC1 NC2 NC3 DISABLE GND GND_PP 16 12 21 TPS74401RGW C70 100pF 10uF 1uF C69 MUST USE TPS74401 3A LDO C R171 R154 C 9 13 14 17 68uF SS 2 3 4 D C68 NC4 NC5 NC6 3P3V 3.57K PG EN 1 18 19 20 C67 OUT1 OUT2 OUT3 OUT4 BIAS 15 1.54K MUST USE TPS74401 3A LDO IN1 IN2 IN3 IN4 R169 1uF C66 4.99K R168 4.7uF 100uF C65 C64 1uF 10uF C62 68uF C61 11 JMP15 TPS74401RGW C63 100pF 10 3P3VREG_SS NC1 NC2 NC3 3.57K 16 FB 5 6 7 8 5V 1.10K DISABLE 13 14 17 NC4 NC5 NC6 SS 2 3 4 2P5VREG_SS 2P5VREG_EN 9 PG EN 15 JMP13 1 2 BIAS 2P5V C60 11 1 18 19 20 OUT1 OUT2 OUT3 OUT4 R152 1uF R151 C59 4.99K 4.7uF 100uF C58 C57 10 U22 IN1 IN2 IN3 IN4 2P5VREG_ADJ 5 6 7 8 5V 3P3VREG_ADJ U20 D 1 2 3 4 5 3.3V PLL REGULATOR U24 5 6 7 8 5V IN1 IN2 IN3 IN4 OUT1 OUT2 OUT3 OUT4 1 18 19 20 3P3V_PLL B 1 2 3P3V_P_REG_EN DISABLE 3P3V_P_REG_SS 2 3 4 FB NC1 NC2 NC3 GND GND_PP 16 12 21 TPS74401RGW 1uF C76 R188 1.10K C77 MUST USE TPS74401 3A LDO 0.001uF 10uF 13 14 17 C75 SS 9 68uF NC4 NC5 NC6 3.57K PG EN C74 15 JMP17 BIAS R186 11 3P3V_P_REG_ADJ 1uF 10 C73 4.99K R185 C72 C71 4.7uF 100uF B A A TEXAS INSTRUMENTS PAGE TITLE 2P5V, 3P3V REGULATORS SIZE B 5 3 4 2 DOCUMENT NUMBER REV NA 6522850 PAGE 4 of 20 1 Figure 12. 2P5V and 3P3V Regulators, Sheet 4 of 20 20 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM Motherboard Schematics www.ti.com 1 2 3 4 5 NOTE: 1210 SIZED 0 OHM RESISTORS HAVE BEEN INSTALLED FOR THE FERRITE BEADS. PLANE FILTERING / BULK DECOUPLING 3P3V_PLL 1P5/8V 1P0V_A L2 L1 VDDRA_LS VDDA D D 1P5/8V 1P0V_A 0.01uF 1uF 0.1uF C86 C87 10uF C85 L3 VDDRA_HS 2 C80 0.01uF 1uF 0.1uF C90 Ferrite Bead_1210 L4 1 3P3V_PLL 2 C91 10uF Ferrite Bead_1210 1 C89 0.01uF C83 2 C84 1uF 0.1uF C82 10uF C79 C81 1 1 VDDT 2 0.1uF C95 0.01uF 1uF C94 C98 10uF C93 0.01uF 0.1uF C100 Ferrite Bead_1210 C101 1uF C132 10uF 2 C99 Ferrite Bead_1210 L10 1 BLM15HD102SN1D C97 JC_VCC_VCXO 10uF 1P5/8V 1P0V_D L6 3P3V_PLL L5 VDDRB_LS VDDD JC_VCCA 2 0.1uF C110 0.01uF 1uF C111 10uF C C109 Ferrite Bead_1210 C107 0.1uF C114 10uF 1uF C134 10uF Ferrite Bead_1210 BLM15HD102SN1D 0.01uF 1 2 C113 1 2 C115 1 L12 C108 C 3P3V_PLL JC_VCC_IN 1P5/8V 1P0V_D L8 L11 L7 VDDRB_HS DVDD 2 0.1uF C120 0.01uF 1uF C121 10uF 0.1uF C124 Ferrite Bead_1210 2 C119 1uF JC_VCC_OUT 10uF Ferrite Bead_1210 10uF 3P3V_PLL C123 C133 C117 1 0.01uF 2 C125 1 BLM15HD102SN1D C118 1 L13 2 BLM15HD102SN1D C135 1P5/8V L9 B 0.01uF 0.1uF C129 C130 1uF Ferrite Bead_1210 VDDO 2 10uF 1 C128 10uF B C127 1 P1 GND 5V_BJ 1 1 NOTE: PLACE GND BANANA JACKS 750 MIL P14 CENTER TO CENTER SPACING WITH A POWER BANANA JACK LOCATED BETWEEN TWO POWER JACKS AND OFFSET DIAGONALLY. L14 JMP41 2 D9 5V_SOURCE 1 1P8V 0.01uF 0.1uF A 2 1 3 Pin Berg TEXAS INSTRUMENTS C140 C139 C138 1 C137 SLEEVE C136 P26 3 1P5/8V JMP35 3 Ferrite Bead_1210 3 Pin Berg BAT60A 10V, 3A 5V_BARREL 1P5V 2 3 10uF 5V_DIODE 1uF 1 68uF 2 A 5V 1 5V_BJ PAGE TITLE TIP SHUNT 2 POWER DISTRIBUTION RAPC722 SILK = +5V 5 SIZE B 4 2 3 DOCUMENT NUMBER PAGE REV NA 6522850 5 of 20 1 Figure 13. Power Distribution, Sheet 5 of 20 SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 21 TLK10002EVM Motherboard Schematics www.ti.com 1 2 3 4 5 NOTES: TLK10002 DEVICE POWER / LOCAL DECOUPLING DECOUPLLING GENERAL GUIDELINES: VDDA 1. PLACE CAPACITORS SUCH THAT SMALLER VALUE CAPACITORS ARE NEARER THE DUT AND THEN SUCCESSIVELY PLACE LARGER VALUE CAPACITORS AS YOU MOVE AWAY FROM THE DUT. NOTE: PLACE CAPACITORS NEAR VDDO NOTE: PLACE CAPACITORS TLK10002 DEVICE VDDA VDDO NEAR TLK10002 DEVICE U1K 0.1uF 0.1uF 0.1uF TLK10002 JMP71 C149 0.1uF C146 K7 C7 0.1uF 0.1uF C145 1P5_8V_VDDO1 1P5_8V_VDDO0 C148 0.1uF C144 2 Pin Berg U1S 1 2 C147 0.1uF JMP67 C143 CDCE72010 DEVICE POWER / LOCAL DECOUPLING 0.1uF D D2 F2 G2 J2 F11 G10 C142 VDDO 1P0V_VDDA_LS_HS1 1P0V_VDDA_LS_HS2 1P0V_VDDA_LS_HS3 1P0V_VDDA_LS_HS4 1P0V_VDDA_LS_HS5 1P0V_VDDA_LS_HS6 C141 2. PLACE CAPACITORS NEAR VIAS AND CONNECTORS. THESE CAPACITORS SHOULD DECOUPLE THE DRIVER SUPPLY TO THE GROUND PLANE. IF A SIGNAL IS REFERENCED TO A POWER PLANE AND THIS POWER PLANE IS NOT ASSOCIATED WITH THE DRIVER SUPPLY, THEN THIS PLANE SHOULD ALSO BE DECOUPLED TO GROUND NEAR ALL ASSOCIATED VIAS AND CONNECTORS. VDDA 2 Pin Berg D 1 2 TLK10002 VDDT NOTE: PLACE CAPACITORS NEAR VDDT VDDRA_LS VDDRA_HS 0.1uF U1P C153 0.1uF 0.1uF C167 C168 2 Pin Berg 1 2 E11 C163 0.1uF TLK10002 JC_VCCA JMP69 1 2 CAPACITORS NEAR 1P5_8V_VDDRA_HS C166 2 Pin Berg VDDD 0.1uF 1 2 JMP73 NOTE: PLACE TLK10002 DEVICE E6 E8 F6 H6 H8 1P0V_VDDD1 1P0V_VDDD2 1P0V_VDDD3 1P0V_VDDD4 1P0V_VDDD5 JMP64 VDDRA_HS 0.1uF C161 CDCE72010 JC_VCCA 0.1uF 0.1uF 57 60 C164 CDCE72010 TLK10002 DEVICE VDDRB_LS VDDRB_LS VDDRB_LS DVDD JMP65 U1N 0.1uF 0.1uF 0.1uF JMP70 C172 C173 C174 0.1uF C169 TLK10002 0.1uF DVDD TLK10002 1 2 NOTE: PLACE CAPACITORS NEAR 2 Pin Berg 1 2 2 Pin Berg TLK10002 DEVICE VDDRB_HS VDDRB_HS VDDRB_HS 0.1uF E7 F7 G6 G8 H7 C170 CDCE72010 K3 TLK10002 DEVICE 1P0V_DVDD1 1P0V_DVDD2 1P0V_DVDD3 1P0V_DVDD4 1P0V_DVDD5 2 Pin Berg 1P5_8V_VDDRB_LS C171 C160 4 63 C159 C157 CDCE72010 U2B C158 1 2 DVDD NOTE: PLACE CAPACITORS NEAR JMP74 0.1uF U1Q 0.1uF 0.1uF 48 49 0.1uF 0.1uF U2F C 2 Pin Berg TLK10002 JC_VCCA VCC_PLL1 VCC_PLL2 2 Pin Berg 2 Pin Berg VDDD NOTE: PLACE CAPACITORS NEAR JC_VCC_IN U1M U2C VCC_IN1 VCC_IN2 VCCA1 VCCA2 1 2 TLK10002 DEVICE VDDRA_HS JC_VCC_IN C162 C155 VCC_CP GND_CP C C154 64 2 JMP72 NOTE: PLACE JC_VCC_IN VDDD U2G C152 2 Pin Berg 1 2 CDCE72010 C151 0.1uF 0.1uF C156 TLK10002 JMP63 TLK10002 C165 51 54 0.1uF VCC_VCXO1 VCC_VCXO2 C3 CAPACITORS NEAR 1 2 JC_VCC_VCXO U2D 1P5_8V_VDDRA_LS JMP68 C150 0.1uF 0.1uF JC_VCC_VCXO U1O 0.1uF JC_VCC_VCXO F4 G4 F9 0.1uF VDDT 1P0V_VDDT_LS_HS1 1P0V_VDDT_LS_HS2 1P0V_VDDT_LS_HS3 VDDRA_LS VDDRA_LS TLK10002 DEVICE U1L U1R 1P5_8V_VDDRB_HS J11 B JMP75 1 2 NOTE: PLACE CAPACITORS NEAR C188 DVDD TLK10002 TLK10002 DEVICE B 2 Pin Berg U1T 1P0V_VPP JC_VCC_OUT D7 JC_VCC_OUT U2A TLK10002 A 5 8 11 14 19 22 25 28 31 34 37 40 43 0.1uF 0.1uF 0.1uF JMP66 C187 C186 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C185 C184 C183 C182 C181 C180 C179 0.1uF C178 0.1uF C177 0.1uF C176 0.1uF JC_VCC_OUT C175 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 2 Pin Berg TLK10002 DEVICE GROUND U1U A2 A5 A11 B3 B4 B7 B11 C1 C6 C12 D3 D5 D10 D11 E2 E4 F1 F5 F8 F10 F12 1 2 CDCE72010 DEVICE GROUND CDCE72010 U2E GND1 GND_PAD 32 65 CDCE72010 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 G1 G3 G5 G7 G11 H2 H4 H11 J5 J12 K1 K6 K11 L3 L4 L7 L11 M2 M5 M12 A TEXAS INSTRUMENTS PAGE TITLE DEVICE POWER, GROUND, LOCAL DECOUPLING SIZE B TLK10002 5 3 4 2 DOCUMENT NUMBER PAGE REV NA 6522850 6 of 20 1 Figure 14. Device Power, Ground, and Local Decoupling, Sheet 6 of 20 22 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM Motherboard Schematics www.ti.com 5V I2C_REFCLKB_SEL_LS I2C_PRBSEN_LS I2C_LS_OK_IN_A_LS I2C_LS_OK_IN_B_LS 4.99K I2C_LOSA_LS I2C_LOSB_LS I2C_PRBS_PASS_LS I2C_LS_OK_OUT_A_LS I2C_LS_OK_OUT_B_LS I2C_REFCLKA_SEL I2C_REFCLKB_SEL I2C_PRBSEN I2C_LS_OK_IN_A I2C_LS_OK_IN_B P10 P11 P12 P13 P14 P15 P16 P17 130 6 MAIN_RST_B E1 C2 20K R259 4 MAIN_/RST_B 130 2 3 MAIN_/RST_C E2 5 ZXTD09N50DE6 C278 1uF 20 19 18 17 16 15 14 13 12 11 MAIN_RST_C B2 3P3V B1 VCCB B2 B3 B4 B5 B6 B7 B8 GND 1 B1 C I2C-TO-GPIO INPUT PINS A1 VCCA A2 A3 A4 A5 A6 A7 A8 OE R242 1 C1 20K R258 JMP61 U42A 1 2 3 4 5 6 7 8 I2C_LOSA I2C_LOSB I2C_PRBS_PASS I2C_LS_OK_OUT_A I2C_LS_OK_OUT_B VDDO P00 P01 P02 P03 P04 P05 P06 P07 1 3 5 7 LS_OK_IN_A LS_OK_IN_B 2 4 6 8 LS_OK_OUT_A LS_OK_OUT_B Header 4x2 5V 0 R256 R257 5V TCA6424 250 TXB0108PWR R282 R281 I2C_JC_PLL_LOCK R274 10 R254 R255 H5 A8 J4 M9 H10 B9 L10 J10 E9 K8 J9 C11 D4 I2C_PDTRXB_N U41 1 2 3 4 5 6 7 8 9 10 DNI_4.99K DNI_4.99K 49.9K 49.9K 49.9K 49.9K 49.9K 49.9K 49.9K REFCLKB_SEL PRBSEN D16 TESTEN GPIO 1 3 5 7 9 11 13 2 4 6 8 10 12 14 C276 1uF SCANCFG1_LS 1 1 1 D D13_1 D16_1 LOSB PRBS_PASS G S AMUXA AMUXB FDV301N FDV301N SCANIN_LS SCANCFG0_LS LOSA Q6 S S G PRBS_PASS_G Q4 D D12_1 LOSB_G D LOSA_G G 1 3 5 7 9 SCANCLK_LS 2 4 6 8 10 STCI_LS_EN 4 STCI_LS_VCCB_3V 1 2 3 FDV301N 1 D Q7 G S G D15_1 1 A1 VCCA A2 A3 A4 A5 A6 A7 A8 OE B1 VCCB B2 B3 B4 B5 B6 B7 B8 GND 20 19 18 17 16 15 14 13 12 11 FDV301N C277 1uF JMP46 SCANCFG1_CON SCANOUT_CON SCANIN_CON SCANCFG0_CON SCANCLK_CON 2 4 6 8 10 STCI INTERFACE A TEXAS INSTRUMENTS PAGE TITLE GLOBAL SIGNALS SIZE B 2 3 1 3 5 7 9 Header 5x2 BI-DIRECTIONAL LEVEL SHIFTER Header 5x2 5 1 2 3 4 5 6 7 8 9 10 TXB0108PWR FDV301N 0 3 Pin Berg U39 SCANOUT_LS JMP48 R261 STCI_LS_VCCB REFCLKA_SEL DNI_0 4.99K PDTRXB_N R267 PDTRXA_N R271 R266 R534 R265 R264 R262 R263 JMP45 Q5 JMP60 R260 Header 7x2 Q3 VDDO S DNI_0 DNI_0 DNI_0 DNI_0 DNI_0 3P3V VDDO D14_1 LS_OK_IN_A_CONNECTOR LS_OK_OUT_A_CONNECTOR D DNI_4.99K DNI_4.99K 20 LS_OK_IN_B_CONNECTOR LS_OK_OUT_B_CONNECTOR LS_OK_OUT_B_G 20 20 R284 250 0 GREEN 2D16_2 R280 2D13_2 RED D13 A SCANIN 5V 250 0 R279 R278 D12 RED 2D12_2 R273 250 0 TLK10002 5V LS_OK_OUT_A_G 20 8 5V B GREEN 2 D14 TLK10002 D15 GREEN 2 D14_2 B10 L8 D9 H9 LS_OK_IN_A LS_OK_IN_B LS_OK_OUT_A LS_OK_OUT_B D15_2 U1E R275 B RESET_N PDTRXA_N PDTRXB_N REFCLKA_SEL REFCLKB_SEL PRBSEN TESTEN GPI0 LOSA LOSB PRBS_PASS AMUXA AMUXB PUSHBUTTON Light Touch Switch U38 9 10 11 12 13 14 15 16 D 2 Pin Berg MAIN RESET U42B I2C_PDTRXA_N BI-DIRECTIONAL LEVEL SHIFTER R247 R248 R249 R250 R251 R252 R253 U1F 20 19 18 17 16 15 14 13 12 11 TXB0108PWR R272 0 0 0 0 0 R276 R283 R285 R286 R287 B1 VCCB B2 B3 B4 B5 B6 B7 B8 GND TCA6424 VDDO 1 2 VDDO A1 VCCA A2 A3 A4 A5 A6 A7 A8 OE 1 2 4.99K 4.99K JMP44 VDDO 1 2 5 1 I2C_REFCLKA_SEL_LS C279 1uF 4 3 GREEN 2 4.99K I2C_PDTRXB_N_LS I2C_LS2_EN C JMP43 MAIN_RST_SIGNAL SW3 I2C-TO-GPIO OUTPUT PINS C275 1uF U64 1 2 3 4 5 6 7 8 9 10 I2C_PDTRXA_N_LS 2 Pin Berg I2C CONTROL ENABLE 4 BI-DIRECTIONAL LEVEL SHIFTER R464 0 0 0 0 0 0 0 /MR 0 R466 I2C_MAIN_RESET R459 R460 R461 R462 R463 R532 R533 VDD TPS3125J18 3 Pin Berg C274 1uF /RST GND RST R246 100K R244 5V MAIN_/RST_L 3P3V C190 1uF D11 VDDO C189 0.1uF 2 MAIN_RST R245 4.99K D 5 RED 1 2 3 MAIN_/RST MAIN_RST_L AND RESET MONITOR U37 49.9 R243 MAIN_RESET_HS D10 0 MAIN_RST_DIR SN74AVCH1T45DBV 3 VOLTAGE SUPERVISOR 250 RESET_N_LS 2 6 5 4 VCCB DIR B R241 4.99K R240 DNI_4.99K R277 1 RESET_N VCCA GND A 3P3V 0 U36 1 2 3 JMP42 C283 1uF R486 R239 4.99K 3P3V MAIN_RESET 10 C282 1uF 1 VDDO 10K 3P3V R465 VDDO 2 3 4 5 DOCUMENT NUMBER PAGE REV NA 6522850 7 of 20 1 Figure 15. Global Signals, Sheet 7 of 20 SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 23 TLK10002EVM Motherboard Schematics www.ti.com 1 2 3 4 5 PLACE R293 AND R295 BETWEEN THE S AND D PINS OF Q8 AND Q9 SO THAT ONLY ONE CAN BE INSTALLED AT A TIME 2P5V D VDDO D VDDO S MDC_OUT_POST_LS MDIO R289 DNI_0 DNI_0 R288 R292 R294 MDIO_OUT_POST_LS R293 MDIO INTERFACE D DNI_FDV301N DNI_0 JMP50 4 2 MDIO_CON R295 MDC DNI_0 3P3V 0 0 DNI_2K D DNI_FDV301N DNI_2K S G G Q9 R291 20 20 MDC_POST_LS_CONNECTOR MDIO_POST_LS_CONNECTOR 2K 2K Q8 R290 VDDO MDC_CON 3 1 Header 2x2 2P5V VDDO PRTAD1 PRTAD0 MDIO_POST_LS Header 5x2 8 7 6 5 MDIO_LS_EN DNI_0 DNI_0 R298 R299 C MDIO_PRE_LS PRTAD ADDRESS HEADER 0 0 R308 R309 MDC_PRE_LS PCA9306DCT TLK10002 DNI_2K EN VREF2 SCL2 SDA2 DNI_2K GND VREF1 SCL1 SDA1 R307 1 2 3 4 MDC_POST_LS R306 PRTAD2 U43 DNI_0 PRTAD3 2 4 6 8 10 R311 PRTAD4 PRTAD3 PRTAD2 PRTAD1 PRTAD0 Header T 4pin C286 1uF JMP53 1 3 5 7 9 4.99K MDC_DUT C R305 PRTAD4 1 MDIO_LS_VCCB M8 J6 L9 G9 E10 4 VDDO DNI_0 MDIO_DUT R310 J7 J8 R300 R301 R302 R303 R304 MDIO MDC R296 R297 U1I 4.99K 4.99K 4.99K 4.99K 4.99K R451 R491 0 0 JMP52 USB_MDC USB_MDIO 2 2 DO NOT OVERLAP RESISTOR PADS BI-DIRECTIONAL LEVEL SHIFTER 7 SCANIN MDC_PRE_LS_CONNECTOR MDIO_PRE_LS_CONNECTOR 20 20 3P3V B B 3P3V JMP62 R268 DNI_0 R269 0 JTAG_LS_VCCB_3V 1 2 3 3P3V DNI_2K DNI_2K DNI_4.99K DNI_4.99K VDDO 3P3V VDDO TRST_N TDO TDI TMS TCK A E5 D6 C8 B8 D8 TRST_N TDO TDI TMS TCK TLK10002 JTAG_LS_EN A1 VCCA A2 A3 A4 A5 A6 A7 A8 OE B1 VCCB B2 B3 B4 B5 B6 B7 B8 GND TDO_LS TDI_LS TMS_LS TCK_LS 2 4 6 8 10 Header 5x2 I2C_GPIO_ADDR_22 26 VCCI SCL SDA ADDR RESET 25 33 GND PP INT 31 2,12,20 2,12,20 R476 R477 R472 R473 VCCP JMP47 1 3 5 7 9 TRST_N_LS C281 1uF U42D 27 JTAG INTERFACE 4.99K U1J 20 19 18 17 16 15 14 13 12 11 C280 1uF R467 R270 U40 1 2 3 4 5 6 7 8 9 10 JTAG_LS_VCCB 4.99K 3 Pin Berg I2C_SCL_CONNECTOR I2C_SDA_CONNECTOR 29 30 I2C_GPIO_22_SCL R508 R509 0 0 I2C_SCL_SOURCE I2C_GPIO_22_SDA 28 I2C_GPIO_22_RESET R510 0 I2C_RESET_SOURCE 32 I2C_GPIO_22)INT R511 0 I2C_INT_SOURCE I2C_SDA_SOURCE I2C_SCL I2C_SDA 2,12,20 2,12,20 I2C_RESET 2 I2C_INT 2 TCA6424 A I2C-TO-GPIO CONTROL PINS TXB0108PWR I2C DEVICE ADDRESS 22 (HEX) BI-DIRECTIONAL LEVEL SHIFTER TEXAS INSTRUMENTS PAGE TITLE MDIO, JTAG, AND I2C INTERFACE SIZE B 5 3 4 2 DOCUMENT NUMBER PAGE REV NA 6522850 8 of 20 1 Figure 16. MDIO, JTAG, and I2C Interface, Sheet 8 of 20 24 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM Motherboard Schematics www.ti.com 1 2 3 4 5 NOTE: 1. MATCH REFCLK0/1_P/N AND CLKOUT0/1_P/N TRACE LENGTHS TO EACHOTHER J41 REFCLK0P REFCLK0P_SMP J45 SMA SURFACE CLKOUTAP CLKOUTAP_SMP 0.1uF C191 OVERLAP CAPACITOR PADS U2N C193 DNI_0.1uF CLKOUTAP CLKOUTAP_PRI_REF_P C194 DNI_0.1uF REFCLK0N_U0N C195 DNI_0.1uF CLKOUTAN CLKOUTAN_PRI_REF_N C196 DNI_0.1uF DNI_150 DNI_150 CDCE72010 R499 R498 0.1uF C198 0.1uF C197 OVERLAP CAPACITOR PADS M10 M11 REFCLK0P J43 K9 K10 REFCLK1P REFCLK1P_SMP REFCLK1N REFCLK0P REFCLK0N REFCLK1P REFCLK1N TLK10002 J46 CLKOUTAN A9 A10 CLKOUTBP CLKOUTBN TLK10002 J47 SMA SURFACE OVERLAP CAPACITOR PADS CLKOUTBP C202 DNI_0.1uF CLKOUTBN CLKOUTBN_PRI_REF_N C204 DNI_0.1uF 0.1uF C205 OVERLAP CAPACITOR PADS CLKOUTBP CLKOUTBP_SMP 0.1uF C200 C203 DNI_0.1uF REFCLK1N_U1N CDCE72010 DNI_150 C9 C10 CLKOUTAP CLKOUTAN C201 DNI_0.1uF REFCLK1P_U1P 10 9 DNI_150 OVERLAP CAPACITOR PADS U1G 0.1uF C199 OVERLAP CAPACITOR PADS 0.1uF C206 CDCE72010 CLKOUTBP_PRI_REF_P 61 62 C SEC_REF_N SEC_REF_P U2M OVERLAP CAPACITOR PADS J44 J48 CLKOUTBN CLKOUTBN_SMP REFCLK1N R497 D SMA SURFACE U1H SMA SURFACE SMA SURFACE R496 PRI_REF_N PRI_REF_P U2L CLKOUTAN_SMP REFCLK1P U1P U1N 58 59 REFCLK0N_SMP REFCLK0N C CDCE72010 J42 REFCLK0N U2O SMA SURFACE OVERLAP CAPACITOR PADS REFCLK0P_U0P 7 6 U0P U0N D 0.1uF C192 REFCLK1N_SMP SMA SURFACE SMA SURFACE JC_VCC_VCXO U2P U2P U2N DNI_83 DNI_83 U2P C287 0.1uF CHB_CLKOUTN_CONNECTOR 20 U2R 13 12 U4P U4N CDCE72010 U2N C288 0.1uF 24 23 CDCE72010 CHB_CLKOUTP_CONNECTOR 20 DNI_150 R536 R537 DNI_150 U2S B U5P U5N 27 26 B CDCE72010 AUX_IN_P_SMP SMA SURFACE C293 0.1uF AUX_IN_P U2W R535 100 J71 DNI_150 DNI_150 C294 0.1uF 42 41 U2T U9P_AUXIN_P U9N_AUXIN_N U6P U6N CDCE72010 AUX_IN_N U3P U2Q DNI_130 AUX_IN_N_SMP SMA SURFACE DNI_130 AUX_IN_N R500 AUX_IN_P R501 J70 U3P U3N C289 0.1uF CHA_CLKOUTP_CONNECTOR 21 20 U7P U7N CDCE72010 U3N C290 0.1uF 30 29 CDCE72010 U2U 20 36 35 CDCE72010 CHA_CLKOUTN_CONNECTOR 20 DNI_150 DNI_150 R493 R492 R495 R494 U2V U8P U8N 39 38 R502 R503 CDCE72010 A A TEXAS INSTRUMENTS PAGE TITLE CLOCKS SIZE B 5 4 2 3 DOCUMENT NUMBER PAGE REV NA 6522850 9 of 20 1 Figure 17. Clocks, Sheet 9 of 20 SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 25 TLK10002EVM Motherboard Schematics www.ti.com 1 2 3 4 5 U2J JC_VCC_VCXO PLL_LOCK TESTOUTA CP_OUT D 56 JC_VBB 55 JC_STATUS JC_VCC_VCXO C272 0.1uF 50 1 JC_TESTOUTA 3 JC_CP_OUT R312 DNI_4.99K JITTER CLEANER LOOP FILTER VCXO_EN_NC 5V 1K 12K CDCE72010 C207 0.01uF R313 5K R314 7.15K C208 0.022uF R315 DNI_4.99K D VCXO_IN_P VCXO_IN_N U2K JMP58 1 3 5 7 EXT_JC_SPI_MISO JC_RC D41_2 GREEN 7 I2C_JC_PLL_LOCK SPI INTERFACE I2C-TO-GPIO OUTPUT PINS 1 U42C I2C_JC_AUX_SEL JC_VCC_OUT D41_1 I2C_JC_REF_SEL I2C_JC_MODE_SEL 0 0 0 0 0 S G 49.9K 49.9K 49.9K 49.9K D JC_PLL_LOCK_G 2 4 6 8 Header 4x2 DNI_0 DNI_0 DNI_0 DNI_0 2 JITTER CLEANER PLL LOCK LED C209 22uF X5R D41 17 18 19 20 21 22 23 24 P20 P21 P22 P23 P24 P25 P26 P27 U2H SPI_LE SPI_CLK SPI_MOSI SPI_MISO 45 46 44 15 0 0 0 0 R504 R505 R506 R507 JC_SPI_LE JC_SPI_CLK JC_SPI_MOSI JC_SPI_MISO 0 0 0 0 R487 R488 R489 R490 JC_SPI_LE_SOURCE JC_SPI_CLK_SOURCE JC_SPI_MOSI_SOURCE JC_SPI_MISO_SOURCE SPI_SS1 SPI_ CLK SPI_MOSI 2 2 2 SPI_MISO 2 C CDCE72010 DO NOT OVERLAP RESISTOR PADS R444 R443 R442 R441 R440 R434 R435 R436 R437 TCA6424 JMP55 1 3 5 7 9 JC_PLL_LOCK 18 47 16 17 33 VCXO_OUTP 122.8 MHZ VCXO FDV301N AUX_SEL REF_SEL MODE_SEL POWER_DOWN RESET CDCE72010 53 52 VCXO_OUTN EXT_JC_SPI_LE I2C_JC_POWER_DOWN U2I VCC OUTn OUTp EXT_JC_SPI_CLK Q10 0 VC OE_NC GND 6 5 4 EXT_JC_SPI_MOSI R432 R433 250 R438 VCXO TCO-2111T R439 C C285 0.1uF Y1 1 2 3 VCXO_VC R468 R469 R470 R471 VBB STATUS JC_AUX_SEL JC_REF_SEL JC_MODE_SEL JC_POWER_DOWN 2 4 6 8 10 JC_RESET Header 5x2 CDCE72010 3P3V 3P3V 100 R447 4.99K I2C_JC_RESET 100 0 R445 R446 3P3V JMP57 1 2 B B A VCC B GND Y 5 C284 1uF 4 MAIN_JC_RESET_AND R457 0 JC_RESET_SIGNAL SN74LVC1G08-Q1DBV 4 VDD /MR /RST GND RST JC_/RST_B 6 E1 JC_/RST R456 JC_RST C2 100K JC_RST_B 4 1 JC_RST_L 2 JITTER CLEANER RESET LED 1 JC_/RST_C B1 100K R455 TPS3125J18 AND GATE USED TO CONNECT C1 100K 49.9 R453 VOLTAGE SUPERVISOR A U82 R454 1 2 3 RED R449 U84 5 1 JC_RESET_SWITCH C273 0.1uF U6 1 2 3 MAIN_RESET 3P3V 3P3V AND 7 4.99K DNI_0 R452 D43 3P3V Light Touch Switch GREEN 2 JITTER CLEANER RESET PUSHBUTTON JITTER CLEANER /RESET LED 2 Pin Berg D42 R448 1 2 5 JC_/RST_L SW4 4 3 2 3 JC_RST_C A B2 AND RESET MONITOR AND ISOLATE MAIN RESET WITH E2 5 JITTER CLEANER RESET TEXAS INSTRUMENTS ZXTD09N50DE6 PAGE TITLE JITTER CLEANER CONTROL SIZE B 5 3 4 2 DOCUMENT NUMBER PAGE REV NA 6522850 10 of 20 1 Figure 18. Jitter Cleaner Control, Sheet 10 of 20 26 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM Motherboard Schematics www.ti.com 1 2 3 4 5 NOTE: 1. MATCH LOW SPEED INPUT AND OUTPUT TRACE LENGTHS TO EACHOTHER 2. MATCH HIGH SPEED TRANSMIT AND RECEIVE TRACE LENGTHS TO EACHOTHER INA3P INB3P INA3P_CONNECTOR INSTALL 0-OHM RESISTOR C210 20 20 INB3P_CONNECTOR 0.1uF 0.1uF INA3N INSTALL 0-OHM RESISTOR INSTALL 0-OHM RESISTOR C211 INB3N C212 INA3N_CONNECTOR 20 20 INB3N_CONNECTOR INA2P_CONNECTOR 20 20 INB2P_CONNECTOR 0.1uF 0.1uF INSTALL 0-OHM RESISTOR C213 D D INA2P INSTALL 0-OHM RESISTOR INB2P C214 0.1uF C216 0.1uF 0.1uF C215 0.1uF C217 INA2N INB2N INA2N_CONNECTOR INSTALL 0-OHM RESISTOR 20 20 INB2N_CONNECTOR INA1P INSTALL 0-OHM RESISTOR INSTALL 0-OHM RESISTOR INSTALL 0-OHM RESISTOR INB1P C218 INA1P_CONNECTOR 20 20 INB1P_CONNECTOR INA1N_CONNECTOR 20 20 INB1N_CONNECTOR 0.1uF 0.1uF INSTALL 0-OHM RESISTOR C219 U1C U1D INA3P INA3N INA2P INA2N INA1P INA1N C INA0P INA0N OUTA3P OUTA3N OUTA2P OUTA2N OUTA1P OUTA1N OUTA0P OUTA0N D1 E1 INA1N INSTALL 0-OHM RESISTOR B2 C2 C220 0.1uF 0.1uF C222 20 20 0.1uF K2 L2 INSTALL 0-OHM RESISTOR C223 INB1P INB1N INB0N INA0N_CONNECTOR INSTALL 0-OHM RESISTOR INB2P INB2N INB0P_CONNECTOR 0.1uF INA0N A4 A3 L1 M1 INB0P INA0P_CONNECTOR INSTALL 0-OHM RESISTOR INB3P INB3N INSTALL 0-OHM RESISTOR C221 INA0P A1 B1 M3 M4 INB1N C224 20 20 INB0N_CONNECTOR 0.1uF 0.1uF H1 J1 INSTALL 0-OHM RESISTOR C225 INB0P INB0N M7 M6 F3 E3 OUTA3P C226 B5 B6 20 20 OUTB3P_CONNECTOR 0.1uF 0.1uF L6 L5 C227 OUTA3N C228 20 20 OUTB3N_CONNECTOR 0.1uF 0.1uF J3 H3 OUTB2P OUTA2P_CONNECTOR 20 20 OUTB1P OUTB1N C229 OUTA2P C230 OUTB2P OUTB2N K5 K4 OUTB3N OUTA3N_CONNECTOR A6 A7 OUTB3P OUTB3N OUTB3P OUTA3P_CONNECTOR C4 C5 OUTB0P OUTB0N OUTB2P_CONNECTOR 0.1uF 0.1uF C C231 TLK10002 TLK10002 OUTA2N OUTB2N OUTA2N_CONNECTOR C232 0.1uF C234 0.1uF C236 0.1uF C238 0.1uF C240 0.1uF 20 20 OUTB2N_CONNECTOR 0.1uF C233 0.1uF C235 0.1uF C237 0.1uF C239 0.1uF C241 OUTA1P B OUTB1P OUTA1P_CONNECTOR 20 20 B OUTB1P_CONNECTOR OUTA1N OUTB1N OUTA1N_CONNECTOR 20 20 OUTB1N_CONNECTOR OUTA0P OUTB0P OUTA0P_CONNECTOR 20 20 OUTB0P_CONNECTOR OUTA0N OUTB0N OUTA0N_CONNECTOR 20 20 OUTB0N_CONNECTOR A A TEXAS INSTRUMENTS PAGE TITLE LOW SPEED DATA SIGNALS SIZE B 5 4 2 3 DOCUMENT NUMBER PAGE REV NA 6522850 11 of 20 1 Figure 19. Low-Speed Data Signals, Sheet 11 of 20 SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 27 TLK10002EVM Motherboard Schematics www.ti.com 1 2 3 4 5 3P3V J73B 1 U93 C1 100K 6 TX_DISABLE_/RST_B E1 THE MODULE. R548 C2 100K 4 TX_DISABLE_RST_B 7 9 RATE_SEL_0 RATE_SEL_1 10 11 14 VEER1 VEER2 VEER3 4 RX_LOS_B 100 RX_LOS_L 2 2 3 RX_LOS_C B2 E2 R551 1 17 20 C2 44.2K C 3P3V 100 E1 R553 VEET1 VEET2 VEET3 R540 B1 3P3V 3P3V_TX MOD-DEF2_SDA MOD-DEF1_SCL MOD-DEF0_ABS 6 TX_FAULT_B TX_FAULT_C 5 ZXTD09N50DE6 TX_FAULT SFP_PLUS_CONN_WITH_CAGE RX_LOS RATE_SEL_0 B RATE_SEL_1 MOD_DEF2_SDA 2 4 6 8 10 12 14 16 3P3V B 1 MOD_DEF1_SCL JMP76 1 3 5 7 9 11 13 15 2 6 3P3V_RX 1 MODULE_DETECT_L 3 8 C1 44.2K ORANGE R554 R555 OVERLAP RESISTOR PADS DNI_0 DNI_0 I2C_SDA I2C_SCL 2,8,20 2,8,20 4 5 0 0 RED R549 RX_LOS R550 R552 U94 2 TX_DISABLE TLK10002 1 TX_FAULT YELLOW HSRXAN 5 ZXTD09N50DE6 1 13 12 HSRXAP TX_DISABLE_RST_C D48 B12 A12 3 D52 RDP RDN 15 VCCR HSRXAP HSRXAN E2 16 3P3V D51 VCCT 2 4.99K TDP TDN DISABLE_SFP+_TX HSTXAN 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 18 19 HSTXAP R556 R557 R558 R559 R560 R561 R562 R563 D12 E12 TX_DISABLE C 3P3V_RX J73A HSTXAP HSTXAN TX_DISABLE_/RST_C B2 3P3V_TX U1A 1 B1 MODULE CAGE NEAR THE MIDDLE OF 100 R546 3P3V R547 /MR TPS3125J18 D 2 0.1uF 49.9 4 RED ONE ON EACH SIDE OF OPTICAL C301 C299 COMMON PATH TO GROUND. PLACE 22uF RESISTORS ARE USED TO PROVIDE C300 0.1uF R543 VDD R545 1 /RST GND RST 2TX_FAULT_L TX_DISABLE_RST TX_DISABLE_RST_L 4.7uH 1 L16 2 D50 0 0 5 GREEN 1 2 3 TX_DISABLE_/RST 3P3V_RX R542 R544 C298 0.1uF U92 100K D49 R541 SFP_PLUS_CONN_WITH_CAGE 100 3P3V 2TX_DISABLE_/RST_L R538 0.1uF 3P3V 3P3V R539 4.99K C297 C296 3P3V 100 4.7uH 22uF L15 2 0.1uF 40 39 38 37 36 35 34 33 32 31 3P3V_TX 1 D 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 33 32 31 C295 21 22 23 24 25 26 27 28 29 30 MODULE_DETECT_D R564 Q12 MODULE_DETECT_G G S G D D Q11 S Header 8x2 MOD_DEF0_MODULE_DETECT FDV301N FDV301N J5 HSTXBP HSTXBP_SMA EDGE LAUNCH U1B C243 HSTXBP HSTXBN A K12 L12 HSTXBP H12 G12 HSRXBP HSTXBN J6 HSTXBN HSTXBN_SMA A EDGE LAUNCH C245 HSRXBP HSRXBN 0 OHM RES 0 OHM RES HSRXBP_SMA J7 HSRXBP HSRXBN_SMA J8 HSRXBN TEXAS INSTRUMENTS EDGE LAUNCH HSRXBN C247 0.1uF TLK10002 PAGE TITLE HIGH SPEED DATA SIGNALS EDGE LAUNCH C249 0.1uF SIZE B 5 3 4 2 DOCUMENT NUMBER PAGE REV NA 6522850 12 of 20 1 Figure 20. High-Speed Data Signals, Sheet 12 of 20 28 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM Motherboard Schematics www.ti.com 1 2 3 4 5 NOTE: VOLTAGE WINDOW DETECTOR CIRCUITS MONITOR THE VOLTAGE ON THE PLANE AND LIGHTS THE APPROPRIATE LED IF IT IS WITHIN THE ALLOWABLE DATASHEET RANGE. D D 4P096V_REF1 5V 5V 4P096V_REF2 5V 5V U44 3 U48A LM339A VCC GND R319 5V C260 0.47uF REF2940 12 + - 3 OUT 14 R329 3 IN_N 105K 3 IN_P R332 3.48K 9.76K 1P0V_D_0P85V_VREF 10 4 IN_P 4 IN_N + - 4 OUT 4P096V_REF2 R330 9 8 3P3V 3 IN_N + - 3 OUT 14 R333 2K 13 11 10K 3P3V_3P0V_VREF 1 3P3V_C D20 BLUE 2 1 B1 E2 3 IN_P 3 B2 1.65K 3P3V_3P6V_VREF R335 6 5V LM339A U48D ZXTD09N50DE6 1 D19 105K U49 C1 5 ZXTD09N50DE6 10 4 IN_P 4 IN_N B LM339A U48E 11 2 E1 5 BLUE 2 2 OUT 1 B1 2 2 R323 + - 2 LM339A U45E 2 IN_N 4 E2 1P0V_D_B 8 2 IN_P C2 33.2K 9 4 2P5V_2P3V_VREF B2 C1 LM339A 5 10K 3 C LM339A U48C R327 C2 6 5V 1P0V_D 1 2P5V_C U46 E1 4P096V_REF1 1P0V_D_1P15V_VREF 1 1 2 4 U45D 1 OUT 2P5V_B 2 OUT 1 IN_N + - 3P3V_B + - 1 IN_P 105K 2 IN_N 6 2P5V 1P0V_D_C 2 IN_P 7 2P5V_2P7V_VREF R331 4 BLUE 2 9.76K 6.04K R325 1.8K 1P0V_A_B 5 5V LM339A U48B R322 LM339A U45C 1P0V_A_0P85V_VREF BLUE 1 D18 1 OUT R321 1 IN_N + - D17 6 1 IN_P 105K 7 1P0V_A R334 49.9 49.9 1 4P096V_REF2 33.2K R324 3.48K B 49.9 VIN LM339A U45B R328 5V GND 5V 1P0V_A_1P15V_VREF R326 3 12 3P3V_L GND R318 LM339A VCC 1P0V_A_L U45A 2 2P5V_L 3 R317 5V C261 0.47uF 4P096V_REF1 C VOUT 1P0V_D_L REF2940 R316 1 VIN R320 U47 5V GND 1P0V_A_C 3 49.9 2 VOUT + - 4 OUT 13 A A TEXAS INSTRUMENTS PAGE TITLE 1P0V, 2P5V, 3P3V, 5V REGULATOR LEDS SIZE B 5 4 2 3 DOCUMENT NUMBER PAGE REV NA 6522850 13 of 20 1 Figure 21. 1P0V, 2P5V, and 3P3V Regulator LEDs, Sheet 13 of 20 SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 29 TLK10002EVM Motherboard Schematics www.ti.com 3 4 5 1 2 NOTE: VOLTAGE WINDOW DETECTOR CIRCUITS MONITOR THE VOLTAGE ON THE PLANE AND LIGHTS THE APPROPRIATE LED IF IT IS WITHIN THE ALLOWABLE DATASHEET RANGE. D D 4P096V_REF3 5V 5V 49.9 2 VOUT 49.9 U50 REF2940 5V 3 U51A LM339A VCC GND 12 1P5V_L C263 0.47uF 4P096V_REF3 5V 1P5V_1P35V_VREF 4 2 IN_N 2 OUT 2 U52 C2 C1 4P096V_REF3 105K 3 OUT 14 R349 1P8V 3 IN_N + - R352 2K 5 ZXTD09N50DE6 B LM339A U51E 11 R354 2 1 B1 E2 3 IN_P 1P8V_B 8 B 6 5V LM339A U51D 12.4K 9 3 B2 E1 1P8V_1P625V_VREF 1 + - 4 R348 1P8V_C 2 IN_P BLUE 2 10K 1P5V_B R346 C LM339A U51C 5 BLUE 1 R344 2K D22 1 OUT R341 1 IN_N + - D21 6 1P5V C 1 IN_P 1 7 1P5V_C 1P5V_1P625V_VREF 105K 18K 2 LM339A U51B R340 1P8V_L 1 VIN R337 5V GND R336 3 10K 1P8V_1P35V_VREF 10 4 IN_P 4 IN_N + - 4 OUT 13 A A TEXAS INSTRUMENTS PAGE TITLE 1P5V AND 1P8V REGULATOR LEDS SIZE B 5 3 4 2 DOCUMENT NUMBER PAGE REV NA 6522850 14 of 20 1 Figure 22. 1P5/8V Regulator LEDs, Sheet 14 of 20 30 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM Motherboard Schematics www.ti.com 1 2 3 4 5 NOTE: VOLTAGE WINDOW DETECTOR CIRCUITS MONITOR THE VOLTAGE ON THE PLANE AND LIGHTS THE APPROPRIATE LED IF IT IS WITHIN THE ALLOWABLE DATASHEET RANGE. D D 4P096V_REF5 5V 5V 5V 4P096V_REF6 U56 2 IN_N + - 2 OUT U58 C2 LM339A + - 3 OUT 14 R368 3 IN_N 105K 3 IN_P R369 2K B VDDO_1P8V_B 8 49.9 R358 1 OUT 3P3V_PLL_L 2 BLUE LM339A U60C 5 R366 3 10K 3P3V_PLL_3P0V_VREF 4 2 IN_P 2 IN_N + - 2 OUT 2 U61 C2 2 E1 6 E2 5 LM339A U60D 9 ZXTD09N50DE6 8 3 IN_N + - 3 OUT 2 1 B1 E2 3 IN_P 3 B2 1 B1 C 5 14 ZXTD09N50DE6 B LM339A U57E LM339A U60E 11 R370 1 D27 1 IN_N 1 49.9 2 LM339A + - C1 12.4K 9 6 3P3V_PLL 1 IN_P 4 C1 VDDO 7 B2 E1 6 5V VDDO_2P0V_VREF 5V 1 1 2 4P096V_REF5 U57D 12 R364 2K 4 R367 GND 3P3V_PLL_C 2 IN_P LM339A VCC 3P3V_PLL_B 4 U60A 1.65K 3P3V_PLL_3P6V_VREF VDDO_1P8V_C VDDO_1P35V_VREF BLUE 2 10K 3 U60B R361 LM339A VDDO_1P5V_B 5 R365 BLUE 1 R363 2K U57C 5V C265 0.47uF 4P096V_REF6 105K 1 OUT R360 1 IN_N + - D25 6 VDDO 1 IN_P 1 REF2940 LM339A U57B 18K 7 5V GND VIN 5V VDDO_1P625V_VREF 3 12 105K GND 2 R362 LM339A VCC VDDO_1P8V_L U57A VDDO_1P5V_L 3 R357 5V C264 0.47uF 4P096V_REF5 C VOUT D26 REF2940 R356 1 VIN R359 U59 5V GND VDDO_1P5V_C 3 49.9 2 VOUT 10K 10 4 IN_N + - 4 OUT 13 11 10 5V 4 IN_P 4 IN_N + - 4 OUT 13 BLUE 2 5V_L R371 49.9 VDDO_1P675V_VREF 4 IN_P A 1 D28 A TEXAS INSTRUMENTS PAGE TITLE 5V, 3P3V PLL, AND VDDO LEDS SIZE B 5 4 2 3 DOCUMENT NUMBER PAGE REV NA 6522850 15 of 20 1 Figure 23. 5-V, 3P3V_PLL, and VDDO LEDs, Sheet 15 of 20 SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 31 TLK10002EVM Motherboard Schematics www.ti.com 1 2 3 4 5 NOTE: VOLTAGE WINDOW DETECTOR CIRCUITS MONITOR THE VOLTAGE ON THE PLANE AND LIGHTS THE APPROPRIATE LED IF IT IS WITHIN THE ALLOWABLE DATASHEET RANGE. D D 4P096V_REF7 5V 5V 4P096V_REF8 5V 5V U62 3 VDDT_L U67A LM339A VCC GND 14 VDDT_B 3 OUT 105K + - R388 3.48K 9.76K VDDT_0P85V_VREF 10 4 IN_P 4 IN_N + - 4 OUT R386 C2 DVDD_1P15V_VREF 9 8 DVDD 3 IN_N + - 3 OUT 14 R389 3.48K 13 11 R391 9.76K DVDD_0P85V_VREF 49.9 R375 2 1 B1 E2 3 IN_P 3 B2 33.2K ZXTD09N50DE6 D32 BLUE D31 105K U68 6 5V LM339A U67D 5 ZXTD09N50DE6 10 4 IN_P 4 IN_N B LM339A U67E 11 2 4P096V_REF8 5 BLUE 2 2 OUT E1 B1 2 2 R379 + - 1 LM339A U63E 2 IN_N 2 R385 3 IN_N 2 IN_P 4 E2 3 IN_P 4 C1 33.2K 8 VDDD_0P85V_VREF B2 C1 LM339A 5 9.76K 3 C LM339A U67C R383 C2 E1 9 1 1 U85 6 5V VDDT 1 1 2 4P096V_REF7 U63D 1 OUT VDDD_B 2 OUT 1 IN_N + - DVDD_B + - 4 VDDT_1P15V_VREF 6 1 IN_P 105K 2 IN_N 7 VDDD VDDT_C 2 IN_P VDDD_1P15V_VREF R387 4 VDDA_C 9.76K 33.2K R381 3.48K VDDA_B 5 5V LM339A U67B R378 LM339A U63C VDDA_0P85V_VREF BLUE 1 D30 1 OUT R377 1 IN_N + - D29 6 VDDA 1 IN_P 105K 7 BLUE 2 4P096V_REF8 33.2K R380 3.48K R390 12 DVDD_L 49.9 49.9 5V C267 0.47uF REF2940 LM339A U63B B 1 5V VDDA_1P15V_VREF R384 5V GND VIN 4P096V_REF7 R382 3 12 DVDD_C GND R374 LM339A VCC VDDA_L U63A VDDD_L 3 1 5V C266 0.47uF 2 VDDD_C REF2940 C VOUT R373 1 VIN R376 U65 5V GND R372 3 49.9 2 VOUT + - 4 OUT 13 A A TEXAS INSTRUMENTS PAGE TITLE VDDA, VDDT, VDDD, DVDD LEDS SIZE B 5 3 4 2 DOCUMENT NUMBER PAGE REV NA 6522850 16 of 20 1 Figure 24. VDDA, VDDT, VDDD, and DVDD LEDs, Sheet 16 of 20 32 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM Motherboard Schematics www.ti.com 1 2 3 4 5 NOTE: VOLTAGE WINDOW DETECTOR CIRCUITS MONITOR THE VOLTAGE ON THE PLANE AND LIGHTS THE APPROPRIATE LED IF IT IS WITHIN THE ALLOWABLE DATASHEET RANGE. D D 4P096V_REF9 5V 5V 4P096V_REF10 5V 5V U69 2 IN_N + - 2 OUT 2 U71 C2 4 C1 LM339A 3 IN_P + - 3 OUT 14 R405 3 IN_N R408 2K VDDRA_LS_1P8V_B 8 105K 9 VDDRA_LS 3 LM339A 5 10K VDDRA_HS_1P35V_VREF 4 2 IN_P 2 IN_N + - 2 OUT R410 10K VDDRA_LS_1P675V_VREF 10 4 IN_P 4 IN_N + - 4 OUT 2 U74 C2 4 2 E1 LM339A U73D R406 12.4K VDDRA_HS_2P0V_VREF ZXTD09N50DE6 9 8 VDDRA_HS 3 IN_P 3 IN_N + - 3 OUT 14 R409 2K 13 11 R411 6 5V 5 10K VDDRA_HS_1P675V_VREF 10 4 IN_P 4 IN_N 3 R395 2 BLUE D36 C B2 1 2 1 B1 E2 5 ZXTD09N50DE6 B LM339A U73E 11 1 4P096V_REF10 E2 VDDRA_HS_1P8V_L R394 1 OUT R399 1 1 IN_N + - U73C B1 49.9 49.9 6 VDDRA_HS 1 IN_P R401 2K R403 VDDRA_HS_1P5V_L 2 7 BLUE VDDRA_HS_1P625V_VREF 105K BLUE 18K D35 49.9 R393 2 5V LM339A U73B R398 LM339A U70E 12 C1 12.4K VDDRA_LS_2P0V_VREF B 6 5V U70D GND B2 E1 4P096V_REF9 R404 LM339A VCC 1 2 IN_P U73A VDDRA_HS_1P8V_C 4 3 VDDRA_HS_1P5V_B VDDRA_LS_1P35V_VREF 5V C269 0.47uF REF2940 VDDRA_HS_1P8V_B 10K 1 LM339A VDDRA_LS_1P5V_B 5 R402 BLUE 1 R400 2K U70C 1 4P096V_REF10 2 1 OUT R397 1 IN_N + - D33 6 VDDRA_LS 1 IN_P 105K 7 VIN LM339A U70B 18K VDDRA_LS_1P625V_VREF 5V GND 1 5V 3 VDDRA_HS_1P5V_C 12 105K GND 2 R407 LM339A VCC VDDRA_LS_1P8V_L U70A VDDRA_LS_1P8V_C 3 VDDRA_LS_1P5V_L 5V C268 0.47uF 4P096V_REF9 C VOUT D34 REF2940 R392 1 VIN R396 U72 5V GND VDDRA_LS_1P5V_C 3 49.9 2 VOUT + - 4 OUT 13 A A TEXAS INSTRUMENTS PAGE TITLE VDDRA_LS AND VDDRA_HS LEDS SIZE B 5 4 2 3 DOCUMENT NUMBER PAGE REV NA 6522850 17 of 20 1 Figure 25. VDDRA LEDs, Sheet 17 of 20 SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 33 TLK10002EVM Motherboard Schematics www.ti.com 1 2 3 4 5 NOTE: VOLTAGE WINDOW DETECTOR CIRCUITS MONITOR THE VOLTAGE ON THE PLANE AND LIGHTS THE APPROPRIATE LED IF IT IS WITHIN THE ALLOWABLE DATASHEET RANGE. D D 4P096V_REF11 5V 5V 4P096V_REF12 5V 5V U75 2 IN_N + - 2 OUT 2 U77 C2 4 C1 LM339A 3 IN_P + - 3 OUT 14 R425 3 IN_N R428 2K VDDRB_LS_1P8V_B 8 105K 9 VDDRB_LS 3 LM339A 5 10K VDDRB_HS_1P35V_VREF 4 2 IN_P 2 IN_N + - 2 OUT R430 10K VDDRB_LS_1P675V_VREF 10 4 IN_P 4 IN_N + - 4 OUT 2 U80 C2 4 2 E1 LM339A U79D R426 12.4K VDDRB_HS_2P0V_VREF ZXTD09N50DE6 9 8 VDDRB_HS 3 IN_P 3 IN_N + - 3 OUT 14 R429 2K 13 11 R431 6 5V 5 10K VDDRB_HS_1P675V_VREF 10 4 IN_P 4 IN_N 3 R415 2 BLUE D40 C B2 1 2 1 B1 E2 5 ZXTD09N50DE6 B LM339A U79E 11 1 4P096V_REF12 E2 VDDRB_HS_1P8V_L R414 1 OUT R419 1 1 IN_N + - U79C B1 49.9 49.9 6 VDDRB_HS 1 IN_P R421 2K R423 VDDRB_HS_1P5V_L 2 7 BLUE VDDRB_HS_1P625V_VREF 105K BLUE 18K D39 49.9 R413 2 5V LM339A U79B R418 LM339A U76E 12 C1 12.4K VDDRB_LS_2P0V_VREF B 6 5V U76D GND B2 E1 4P096V_REF11 R424 LM339A VCC 1 2 IN_P U79A VDDRB_HS_1P8V_C 4 3 VDDRB_HS_1P5V_B VDDRB_LS_1P35V_VREF 5V C271 0.47uF REF2940 VDDRB_HS_1P8V_B 10K 1 LM339A VDDRB_LS_1P5V_B 5 R422 BLUE 1 R420 2K U76C 1 4P096V_REF12 2 1 OUT R417 1 IN_N + - D37 6 VDDRB_LS 1 IN_P 105K 7 VIN LM339A U76B 18K VDDRB_LS_1P625V_VREF 5V GND 1 5V 3 VDDRB_HS_1P5V_C 12 105K GND 2 R427 LM339A VCC VDDRB_LS_1P8V_L U76A VDDRB_LS_1P8V_C 3 VDDRB_LS_1P5V_L 5V C270 0.47uF 4P096V_REF11 C VOUT D38 REF2940 R412 1 VIN R416 U78 5V GND VDDRB_LS_1P5V_C 3 49.9 2 VOUT + - 4 OUT 13 A A TEXAS INSTRUMENTS PAGE TITLE VDDRB_LS AND VDDRB_HS LEDS SIZE B 5 3 4 2 DOCUMENT NUMBER PAGE REV NA 6522850 18 of 20 1 Figure 26. VDDRB LEDs, Sheet 18 of 20 34 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM Motherboard Schematics www.ti.com 1 2 3 4 5 NOTE: VOLTAGE WINDOW DETECTOR CIRCUITS MONITOR THE VOLTAGE ON THE PLANE AND LIGHTS THE APPROPRIATE LED IF IT IS WITHIN THE ALLOWABLE DATASHEET RANGE. D D 4P096V_REF13 5V 5V 4P096V_REF14 5V 5V U81 U91 C2 LM339A 3 OUT 14 JC_VCCA_B + - R527 3 IN_N 105K 3 IN_P 3 JC_VCC_IN_3P0V_VREF 4 2 IN_N + - 2 OUT R522 10K JC_VCCA_3P0V_VREF 10 4 IN_P 4 IN_N + - C2 4P096V_REF14 LM339A U87D 1.65K JC_VCC_OUT_3P6V_VREF ZXTD09N50DE6 9 8 JC_VCC_OUT 13 11 R512 6 5V 5 3 IN_P 3 IN_N + - 3 OUT 14 10K JC_VCC_OUT_3P0V_VREF 10 4 IN_P 4 IN_N JC_VCC_OUT_L 2 BLUE C D47 BLUE U88 3 B2 E1 R513 2K 4 OUT 105K 2 1 R515 R521 R514 2 IN_P 2 B1 49.9 49.9 10K 2 1 B1 E2 5 ZXTD09N50DE6 B LM339A U87E 11 JC_VCC_IN_L 2 5 R520 D46 49.9 2 R516 LM339A U87C LM339A U90E 1 C1 E2 R525 2K B 6 1.65K 8 1 OUT 4 C1 9 1 IN_N B2 E1 JC_VCCA 1 1 2 5V U90D LM339A + - 1 2 OUT 4P096V_REF13 JC_VCCA_3P6V_VREF 6 JC_VCC_IN 1 IN_P R519 2K 4 R524 5V 7 JC_VCC_OUT_C + - 12 1 2 IN_N GND JC_VCC_IN_B 2 IN_P LM339A VCC JC_VCC_OUT_B 4 U87A 1.65K JC_VCC_IN_3P6V_VREF JC_VCCA_C JC_VCC_VCXO_3P0V_VREF BLUE 2 10K 3 U87B R517 LM339A JC_VCC_VCXO_B 5 R530 BLUE 105K 1 R529 2K U90C 5V C292 0.47uF 4P096V_REF14 1 OUT R526 1 IN_N + - D44 6 JC_VCC_VCXO 1 IN_P 1 REF2940 LM339A U90B 1.65K 7 5V GND JC_VCC_IN_C 5V JC_VCC_VCXO_3P6V_VREF 3 VIN 12 105K GND 2 R518 LM339A VCC JC_VCCA_L U90A JC_VCC_VCXO_L 3 R531 5V C291 0.47uF 4P096V_REF13 C VOUT D45 REF2940 R523 1 VIN R528 U83 5V GND JC_VCC_VCXO_C 3 49.9 2 VOUT + - 4 OUT 13 A A TEXAS INSTRUMENTS PAGE TITLE JITTER CLEANER POWER LEDS SIZE B 5 4 2 3 DOCUMENT NUMBER PAGE REV NA 6522850 19 of 20 1 Figure 27. Jitter Cleaner Power LEDs, Sheet 19 of 20 SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 35 TLK10002EVM Motherboard Schematics www.ti.com J72A 11 11 11 11 11 11 11 11 OUTB2N_CONNECTOR OUTB2P_CONNECTOR 9 9 INB2P_CONNECTOR INB2N_CONNECTOR OUTB3N_CONNECTOR OUTB3P_CONNECTOR 11 11 C INB1P_CONNECTOR INB1N_CONNECTOR OUTB1N_CONNECTOR OUTB1P_CONNECTOR 11 11 11 11 INB0P_CONNECTOR INB0N_CONNECTOR OUTB0N_CONNECTOR OUTB0P_CONNECTOR 11 11 D A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 INB3P_CONNECTOR INB3N_CONNECTOR CHB_CLKOUTP_CONNECTOR CHB_CLKOUTN_CONNECTOR 7 LS_OK_IN_B_CONNECTOR 7 LS_OK_OUT_B_CONNECTOR A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 SEAF_ASP-134486-01 J72B B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 11 11 B OUTA3P_CONNECTOR OUTA3N_CONNECTOR 11 11 INA2N_CONNECTOR INA2P_CONNECTOR 11 11 OUTA2P_CONNECTOR OUTA2N_CONNECTOR 11 11 OUTA1P_CONNECTOR OUTA1N_CONNECTOR 11 11 11 11 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K40 INA3N_CONNECTOR INA3P_CONNECTOR INA1N_CONNECTOR INA1P_CONNECTOR OUTA0P_CONNECTOR OUTA0N_CONNECTOR 11 11 INA0N_CONNECTOR INA0P_CONNECTOR A 9 9 CHA_CLKOUTP_CONNECTOR CHA_CLKOUTN_CONNECTOR 7 LS_OK_IN_A_CONNECTOR 7 LS_OK_OUT_A_CONNECTOR K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K40 SEAF_ASP-134486-01 5 8 MDIO_PRE_LS_CONNECTOR 8 MDC_PRE_LS_CONNECTOR C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 SEAF_ASP-134486-01 J72K 11 11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 SEAF_ASP-134486-01 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J33 J34 J35 J36 J37 J38 J39 J40 8 MDIO_POST_LS_CONNECTOR 8 MDC_POST_LS_CONNECTOR SEAF_ASP-134486-01 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 E36 E37 E38 E39 E40 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 I2C_SCL_CONNECTOR 2,8,12 I2C_SDA_CONNECTOR G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 J72H H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 SEAF_ASP-134486-01 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40 D C SEAF_ASP-134486-01 J72F F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 E36 E37 E38 E39 E40 SEAF_ASP-134486-01 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 B J72I MOUNT1 MOUNT2 MOUNT3 MOUNT4 1 2 3 4 SEAF_ASP-134486-01 A TEXAS INSTRUMENTS PAGE TITLE SAMTEC SEAF BOARD TO BOARD CONNECTOR SEAF_ASP-134486-01 3 4 J72G 2,8,12 SEAF_ASP-134486-01 J72E J72J J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J33 J34 J35 J36 J37 J38 J39 J40 J72D J72C B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 1 2 3 4 5 2 SIZE DOCUMENT NUMBER REV B 6522850 NA PAGE 20 of 20 1 Figure 28. Board-To-Board Connector, Sheet 20 of 20 36 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM Motherboard Bill of Materials www.ti.com 11 TLK10002EVM Motherboard Bill of Materials Table 1. TLK10002EVM Motherboard Bill of Materials Item Qty Reference Part Part Number Manufacturer 1 58 C191, C199, C210, C218, C226, C234, C243, C293, C198, 0.1μF C206, C217, C225, C233, C241, C290, 0201 CAP C0201X5R6R3-104KNE Venkel 2 64 C2, C4, C6, C7, C8, C12, C13, C14, C141, C142, 0.1μF C143, C144, C145, C146, C147, C148, C149, C150, C151, C152, C153, C154, C155, C156, C157, C158, C159, C160, C161, C162, C163, C164, C165, C166, C167, C168, C169, C170, C171, C172, C173, C174, C175, C176, C177, C178, C179, C180, C181, C182, C183, C184, C185, C186, C187, C188, C189, C272, C285, C295, C297, C298, C299, C301 0402 CAP C0402X7R160-104KNE Venkel 3 13 C260, C261, C263, C264, C265, C266, C267, C268, 0.47μF C269, C270, C271, C291, C292 0402 CAP C0402X5R6R3-474KNE Venkel 4 14 C9, C190, C274, C275, C276, C277, C278, C279, C280, C281, C282, C283, C284, C286 1.0μF 0402 CAP C0402X5R6R3-105KNE Venkel 5 2 C10, C11 22pF 0402 CAP C0402COG500-220JNE Venkel 6 1 C208 0.022μF 0603 CAP GRM188R72A223KAC4D Murata Electronics North America 7 1 C273 0.1μF 0603 CAP C0603X7R500-104KNE Venkel 8 7 C19, C26, C31, C45, C59, C66, C73 1.0μF 0603 CAP C1608X7R1C105K TDK Corporation 9 1 C207 10000pF 0603 CAP C1608X7R1H103K TDK Corporation 10 7 C21, C28, C35, C49, C63, C70, C77 1000pF 0603 CAP C0603X7R101-102KNE Venkel 11 1 C5 10μF 0603 CAP ECJ-1VB0J106M Panasonic 12 7 C16, C23, C30, C44, C58, C65, C72 4.7μF 0603 CAP C0603C475K8PACTU Kemet 13 11 C83, C87, C91, C98, C101, C111, C115, C121, C125, C130, C140 0.01μF 0805 CAP GRM21BR72A103KA01L Murata Electronics North America 14 15 C79, C80, C84, C93, C97, C107, C108, C117, C118, C127, C132, C133, C134, C135, C137 10μF 0805 CAP EMK212BJ106KG-T Taiyo Yuden 15 2 C296, C300 22μF 0805 CAP C0805C226M9PACTU Kemet 16 11 C82, C86, C90, C95, C100, C110, C114, C120, C124, C129, C139 0.1μF 1206 CAP C1206C104J5RACTU Kemet 17 18 C20, C27, C34, C48, C62, C69, C76, C81, C85, C89, C94, C99, C109, C113, C119, C123, C128, C138 1.0μF 1206 CAP C1206X7R250-105KNE Venkel 18 7 C18, C25, C33, C47, C61, C68, C75 10μF 1206 CAP C1206X7R160-106KNE Venkel 19 1 C209 22μF 1206 CAP GCM31CR70J226KE23L Murata Electronics North America 20 8 C17, C24, C32, C46, C60, C67, C74, C136 68μF 1210 CAP C3225X5R0J686M TDK Corporation 21 7 C15, C22, C29, C43, C57, C64, C71 100μF 1812 CAP GRM43SR60J107ME20L Murata Electronics North America C192, C200, C211, C219, C227, C235, C245, C294 Value C193, C201, C212, C220, C228, C236, C247, SLLU148 – May 2011 Submit Documentation Feedback C194, C202, C213, C221, C229, C237, C249, C195, C203, C214, C222, C230, C238, C287, C196, C204, C215, C223, C231, C239, C288, C197, C205, C216, C224, C232, C240, C289, TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 37 TLK10002EVM Motherboard Bill of Materials www.ti.com Table 1. TLK10002EVM Motherboard Bill of Materials (continued) 38 Item Qty Reference Value Part Part Number Manufacturer 22 6 R296, R297, R308, R309, R451, R491 0.0 (Zero Ohm) 0201 RES CR0201-20W-000T Venkel 23 1 R535 100 0201 RES ERJ-1GEF1000C Panasonic - ECG 24 41 R273, R286, R445, R486, R507, R552 0402 RES ERJ-2GE0R00X Panasonic - ECG 25 1 R433 1.00K 0402 RES RG1005P-102-B-T5 Susumu Co Ltd 26 1 R24 1.00M 0402 RES CR0402-16W-1004FT Venkel 27 3 R20, R41, R42 1.50K 0402 RES RG1005P-152-B-T5 Susumu 28 6 R330, R361, R515, R517, R524, R528 1.65K 0402 RES ERJ-2RKF1651X Panasonic - ECG 29 1 R325 1.80K 0402 RES RG1005P-182-B-T5 Susumu Co Ltd 30 19 R327, R335, R346, R354, R365, R366, R370, R402, 10.0K R403, R410, R411, R422, R423, R430, R431, R512, R520, R522, R530 0402 RES RG1005P-103-B-T5 Susumu Co Ltd 31 5 R1, R2, R4, R23, R551 100 0402 RES RG1005P-101-B-T5 Susumu Co Ltd 32 10 R3, R5, R10, R11, R13, R17, R454, R456, R546, R548 100K 0402 RES RG1005P-104-B-T5 Susumu 33 25 R321, R323, R329, R331, R341, R349, R360, R362, 105K R368, R377, R379, R385, R387, R397, R399, R405, R407, R417, R419, R425, R427, R516, R518, R526, R527 0402 RES ERJ-2RKF1053X Panasonic - ECG 34 1 R432 12.0K 0402 RES RG1005P-123-B-T5 Susumu 35 6 R348, R367, R404, R406, R424, R426 12.4K 0402 RES RG1005P-1242-B-T5 Susumu Co Ltd 36 1 R16 15.0K 0402 RES RG1005P-153-B-T5 Susumu 37 6 R340, R359, R396, R398, R416, R418 18.0K 0402 RES RG1005P-183-B-T5 Susumu Co Ltd 38 22 R14, R15, R18, R19, R333, R344, R352, R363, 2.00K R364, R369, R400, R401, R408, R409, R420, R421, R428, R429, R513, R519, R525, R529 0402 RES RG1005P-202-B-T5 Susumu 39 2 R258, R259 20.0K 0402 RES RG1005P-203-B-T5 Susumu 40 6 R278, R280, R281, R282, R284, R439 249 0402 RES RR0510P-2490-D Susumu Co Ltd 41 6 R324, R332, R380, R381, R388, R389 3.48K 0402 RES ERJ-2RKF3481X Panasonic - ECG 42 2 R21, R22 33 0402 RES RR0510R-330-D Susumu Co Ltd 43 6 R320, R328, R376, R378, R384, R386 33.2K 0402 RES RR0510P-3322-D Panasonic - ECG 44 46 R7, R25, R26, R27, R28, R32, R33, R34, R43, R44, 4.99K R45, R46, R47, R48, R245, R247, R248, R249, R250, R251, R252, R253, R254, R255, R270, R300, R301, R302, R303, R304, R434, R435, R436, R437, R450, R474, R475, R556, R557, R558, R559, R560, R561, R562, R563, R564 0402 RES RG1005P-4991-B-T5 Susumu Co Ltd 45 2 R549, R553 44.2K 0402 RES TNPW040244K2BEED Vishay/Dale 46 1 R8 49.9 0402 RES RG1005P-49R9-B-T5 Susumu Co Ltd R274, R287, R457, R487, R508, R275, R438, R459, R488, R509, R276, R440, R460, R489, R510, R277, R441, R461, R490, R511, R279, R442, R462, R504, R532, R283, R443, R463, R505, R533, R285, 0.0 (Zero Ohm) R444, R466, R506, R550, TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM Motherboard Bill of Materials www.ti.com Table 1. TLK10002EVM Motherboard Bill of Materials (continued) Item Qty Reference Value Part Part Number Manufacturer 47 1 R322 6.04K 0402 RES RG1005P-6041-B-T5 Susumu Co Ltd 48 6 R326, R334, R382, R383, R390, R391 9.76K 0402 RES RG1005P-9761-B-T5 Susumu Co Ltd 49 2 R261, R269 0.0 (Zero Ohm) 0603 RES ERJ-3GEY0R00V Panasonic - ECG 50 2 R171, R188 1.10K 0603 RES RG1608P-112-B-T5 Susumu Co Ltd 51 2 R50, R67 1.13K 0603 RES RR0816P-1131-D-06H Susumu Co Ltd 52 1 R154 1.54K 0603 RES RR0816P-1541-D-19H Susumu Co Ltd 53 1 R465 10.0K 0603 RES ERA-3AEB103V Panasonic - ECG 54 6 R446, R447, R538, R540, R545, R547 100 0603 RES RG1608P-101-B-T5 Susumu Co Ltd 55 3 R244, R455, R541 100K 0603 RES TNPW06031003BT9 Vishay/Dale 56 2 R242, R246 130 0603 RES RG1608P-131-B-T5 Susumu Co Ltd 57 2 R288, R289 2.00K 0603 RES RN731JTTD2001B25 KOA Speer 58 1 R120 2.67K 0603 RES RG1608P-2671-B-T5 Susumu Co Ltd 59 4 R118, R152, R169, R186 3.57K 0603 RES RG1608P-3571-B-T5 Susumu Co Ltd 60 2 R52, R69 4.02K 0603 RES RG1608P-4021-B-T5 Susumu Co Ltd 61 1 R84 4.12K 0603 RES RG1608P-4121-B-T5 Susumu Co Ltd 62 1 R86 4.30K 0603 RES RG1608P-432-B-T5 Susumu Co Ltd 63 17 R49, R66, R83, R117, R151, R168, R185, R239, 4.99K R241, R267, R272, R305, R448, R449, R464, R467, R539 0603 RES RG1608P-4991-B-T5 Susumu Co Ltd 64 1 R313 0603 RES RG1608P-4991-B-T5 Susumu Co Ltd 65 29 R243, R357, R393, R514, 0603 RES RG1608P-49R9-B-T1 Susumu Co Ltd 66 1 R314 7.15K 0603 RES RG1608P-7151-B-T5 Susumu Co Ltd 67 2 R542, R544 0.0 (Zero Ohm) 0805 RES RC0805JR-070RL Yageo America 68 10 L1, L2, L3, L4, L5, L6, L7, L8, L9, L14 0.0 (Zero Ohm) 1210 RES RK73Z2ETTE KOA Speer 69 4 L10, L11, L12, L13 1000uH 0603 600mA IND BLM18HE102SN1D Murata Electronics North 70 2 L15, L16 4.7μH 1210 220mA IND NLV32T-4R7J-PF TDK Corporation 71 26 D17, D18, D19, D20, D21, D22, D25, D26, D27, D28, D29, D30, D31, D32, D33, D34, D35, D36, D37, D38, D39, D40, D44, D45, D46, D47 LED - Blue C170 HSMR-C170 Avago Technologies US Inc. 72 9 D1, D4, D11, D14, D15, D16, D41, D42, D49 LED - Green C170 HSMG-C170 Avago Technologies US Inc. 73 2 D3, D48 LED - Orange C170 HSMD-C170 Avago Technologies US Inc. 74 7 D2, D10, D12, D13, D43, D50, D51 LED - Red C170 SML-LXT0805IW-TR Lumex Opto/Components 75 1 D52 LED - Yellow C170 SML-LXT0805YW-TR Lumex Opto/Components 76 1 D9 Zener Diode 3A, 10V SOD-323 BAT 60A E6327 Infineon Technologies 77 8 Q3, Q4, Q5, Q6, Q7, Q10, Q11, Q12 NFET SOT-23 FDV301N Fairchild Semiconductor 78 2 Q1, Q2 NPN SOT-23-3 MMBT4401 Fairchild Semiconductor 4.99K R316, R358, R394, R521, R317, R371, R395, R523, SLLU148 – May 2011 Submit Documentation Feedback R318, R372, R412, R531, R319, R336, R337, R356, 49.9 R373, R374, R375, R392, R413, R414, R415, R453, R543 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 39 TLK10002EVM Motherboard Bill of Materials www.ti.com Table 1. TLK10002EVM Motherboard Bill of Materials (continued) 40 Item Qty Reference Value Part Part Number Manufacturer 79 18 U7, U38, U46, U49, U52, U58, U61, U68, U71, U74, U77, U80, U82, U85, U88, U91, U93, U94 Dual NPN SOT-23-6 ZXTD09N50DE6TA Zetex Inc 80 13 U45, U48, U51, U57, U60, U63, U67, U70, U73, U76, U79, U87, U90 Differential Comparator 14-TSSOP LM339APWR Texas Instruments 81 1 U1 10Gbps SerDes 144-BGA TLK10002 Texas Instruments 82 4 U39, U40, U41, U64 Bi-Directional Level Shifter 20-TSSOP TXB0108PWR Texas Instruments 83 7 U8, U10, U12, U16, U20, U22, U24 Adjustable LDO 20-VQFN TPS74401RGWT Texas Instruments 84 1 U42 I2C to GPIO Expander 32-QFN TCA6424RGJR Texas Instruments 85 1 U3 USB Microcontroller 64-LQFP TUSB3210PM Texas Instruments 86 1 U2 Jitter Cleaner 64-QFN CDCE72010RGCT Texas Instruments 87 1 U4 512Kb EEPROM 8-SOIC 24LC512-I/SM Microchip Technology 88 1 U43 Bi-Directional Level Shifter 8-SSOP PCA9306DCTR Texas Instruments 89 13 U44, U47, U50, U56, U59, U62, U65, U69, U72, U75, U78, U81, U83 Precision Voltage Reference SOT-23-3 REF2940AIDBZT Texas Instruments 90 1 U6 2-Input AND Gate SOT-23-5 SN74LVC1G08DBVR Texas Instruments 91 4 U5, U37, U84, U92 Voltage Supervisor with Manual Reset SOT-23-5 TPS3125J18DBVR Texas Instruments 92 1 U36 Bi-Directional Level Shifter SOT-23-6 SN74AVCH1T45DCKR Texas Instruments 93 1 Y1 122.88 MHz VCXO 13.9mmX8.75mm TCO-2111T 122.8800MHZ Toyocom 94 1 X1 12.000MHz Crystal SMD ECS-120-32-5PVX ECS Inc 95 3 SW2, SW3, SW4 Momentary Push Button Switch 6.00mm x 6.00mm EVQ-PBE05R Panasonic - ECG 96 1 SW1 1-Position Dip Switch SMT SDA01H0SB ITT Cannon - CK 97 1 J73 SFP+ Connector SMT 1888247-1 Amp/Tyco 98 1 J72 Board-to-Board Connector SMT ASP-134486-01 Samtec 99 23 JMP1, JMP3, JMP5, JMP9, JMP13, JMP15, JMP17, JMP43, JMP44, JMP57, JMP63, JMP64, JMP65, JMP66, JMP67, JMP68, JMP69, JMP70, JMP71, JMP72, JMP73, JMP74, JMP75 1X2 0.1" HTSW-150-08-G-S Samtec 100 5 JMP35, JMP41, JMP42, JMP60, JMP62 1X3 0.1" HTSW-150-08-G-S Samtec 101 1 JMP52 1X4T 0.1" HTSW-150-08-G-S Samtec 102 1 JMP45 2X7 0.1x0.1" HTSW-150-08-G-D Samtec 103 5 JMP46, JMP47, JMP48, JMP53, JMP55 2X5 0.1x0.1" HTSW-150-08-G-D Samtec 104 1 JMP50 2X2 0.1x0.1" HTSW-150-08-G-D Samtec 105 2 JMP58, JMP61 2X4 0.1x0.1" HTSW-150-08-G-D Samtec 106 1 JMP76 2X8 0.1x0.1" HTSW-150-08-G-D Samtec 107 1 P26 Power Jack 2.1mm PJ-002AH CUI Inc 108 2 P1, P14 Banana Plug - Metal 4mm 108-0740 -001 Emerson Network Pwr Co 109 1 J65 USB - B Type B Type 897-43-004-90-000000 Mill-Max Manufacturing Co 110 4 J5, J6, J7, J8 Edge Launch SMA RF Screw Type 32K243-40ML5 Rosenberger 111 10 J41, J42, J43, J44, J45, J46, J47, J48, J70, J71 Surface Mount SMA T/H_SMT SMA 32K141-40ML5 Rosenberger TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM Motherboard Bill of Materials www.ti.com Table 1. TLK10002EVM Motherboard Bill of Materials (continued) Item Qty Reference Value Part Part Number Manufacturer 112 4 Standoff 10mm 10,15) .400 SO-1015-03-01-02 Samtec 113 4 Screws 4-40/0.25"- Screws 4-40/0.25"- Screws PMSSS 440 0025 PH Building Fasteners 114 4 Standoff 0.5" 0.5" 2027 Keystone Electronics 115 18 Shunt 0.1" SP 0.1" SP 151-8000-E Kobiconn 116 60 R298, R299, R536, R537, R492, R493, R494, R495, DNI R496, R497, R498, R499, R500, R501, R502, R503, R264, R265, R266, R271, R452, R468, R469, R470, R471, R534, R554, R555, R476, R477, R29, R30, R31, R35, R36, R37, R38, R39, R40, R240, R256, R257, R262, R263, R472, R473, R260, R268, R292, R293, R294, R295, R310, R311, R290, R291, R306, R307, R312, R315 117 2 Q8, Q9 SLLU148 – May 2011 Submit Documentation Feedback DNI TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 41 TLK10002EVM Motherboard Layout 12 www.ti.com TLK10002EVM Motherboard Layout 6522850 TLK10002 EVM MOTHER BOARD REV NA JN Figure 29. Top Signal, Layer 1 42 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM Motherboard Layout www.ti.com Figure 30. Internal Ground, Layer 2 SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 43 TLK10002EVM Motherboard Layout www.ti.com Figure 31. Internal Signal, Layer 3 44 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM Motherboard Layout www.ti.com Figure 32. Internal Ground, Layers 4, 6, 7, 9, 11, and 13 SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 45 TLK10002EVM Motherboard Layout www.ti.com VDDD VDDRB_HS VDDA VDDRB_LS VDDRA_HS 3P3V MDIO_LS_VCCB Figure 33. Internal Power, Layer 5 46 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM Motherboard Layout www.ti.com JC_VCC_IN JC_VCCA VDDA 5V VDDT 3P3V_TX 3P3V_RX Figure 34. Internal Power, Layer 8 SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 47 TLK10002EVM Motherboard Layout www.ti.com 3P3V_PLL JC_VCC_OUT JC_VCC_VCXO VDDO DVDD VDDRA_LS 2P5V Figure 35. Internal Power, Layer 10 48 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM Motherboard Layout www.ti.com Figure 36. Internal Signal, Layer 12 SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 49 TLK10002EVM Motherboard Layout www.ti.com Figure 37. Bottom Signal, Layer 14, Top View 50 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM Motherboard Layout www.ti.com Figure 38. Bottom Signal, Layer 14, Flipped View SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 51 TLK10002EVM Motherboard Layout www.ti.com Table 2. TLK10002EVM Motherboard Layer Construction SUBCLASS NAME TOP L2_GND L3_SIG2 L4_GND L5_PWR L6_GND L7_GND L8_PWR L9_GND L10_PWR L11_GND L12_SIG3 L13_GND BOTTOM (1) 52 TYPE MATERIAL THICKNESS (MIL) DIELECTRIC CONSTANT LOSS TANGENT 1 WIDTH (MIL) SURFACE AIR CONDUCTOR COPPER DIELECTRIC Rogers PLANE COPPER DIELECTRIC FR-4 CONDUCTOR COPPER 1.2 1 0 DIELECTRIC FR-4 10 4.1 0.035 PLANE COPPER 1.2 1 0 DIELECTRIC FR-4 5 4.1 0.035 CONDUCTOR COPPER DIELECTRIC FR-4 PLANE COPPER DIELECTRIC FR-4 PLANE COPPER 1.2 1 0 DIELECTRIC FR-4 10 4.1 0.035 PLANE COPPER 1.2 1 0 DIELECTRIC FR-4 5 4.1 0.035 PLANE COPPER DIELECTRIC FR-4 PLANE COPPER DIELECTRIC FR-4 PLANE COPPER 1.2 1 0 DIELECTRIC FR-4 10 4.1 0.035 CONDUCTOR COPPER 1.2 1 0 DIELECTRIC FR-4 5 4.1 0.035 PLANE COPPER DIELECTRIC Rogers CONDUCTOR COPPER SURFACE AIR COUPLING TYPE/SPACING (MIL) IMPEDANCE (Ω) (1) 0 1.9 2.8 0 5 3.6 0.035 1.2 1 0 5 4.1 0.035 1.2 1 0 5 4.1 0.035 1.2 1 0 5 4.1 0.035 1.2 1 0 5 4.1 0.035 1.2 1 0 5 4.1 0.035 1.2 1 0 5 4.1 0.035 1.9 1 0 4.50 Edge/3.00 98.821 6.00 NONE/NONE 48.85 6.0 NONE/NONE 48.588 10 NONE/NONE 49.737 The Impedance is set to be slightly less than 50 Ω or 100 Ω on the traces in order to compensate for slight over-etching during the manufacturing process. The end impedance after etching should result in a 50 or 100-Ω Impedance. Always consult with your board manufacturer for their process/design requirements to ensure the desired impedance is achieved. TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM FPGA Daughterboard Schematics www.ti.com 13 TLK10002EVM FPGA Daughterboard Schematics 5 1 2 3 4 REVISIONS NOTES: ECR NUMBER ECR DATE xx/xx/xx ------- 1. PLACE NET NAMES ON ALL JUMPERS AND HEADERS. 2. PLACE ALL PARTS OTHER THAN SMA CONNECTORS ON A 0 OR 90 DEGREE ORIENTATION. 3. SERIAL DATA SHOULD BE ROUTED AS 100 OHM DIFFERENTIALLY COUPLED OR SINGLE-ENDED 50 OHM TRANSMISSION LINES ON OUTSIDE LAYERS. ROUTING DISTANCE SHOULD BE 5 INCHES OR LESS. ALL OTHER DATA LINES SHOULD BE 50 OHM IMPEDIANCE ON INTERNAL OR EXTERNAL LAYERS. ROUTED POWER SHOULD BE A MINIMUM OF 40 MILS WIDE. D 4. USE ROGERS MATERIAL FOR OUTSIDE LAYERS AND FR4-370 MATERIAL FOR INSIDE LAYERS. D 5. SERIAL AND REFCLK NETS MUST MATCH WITHIN +/- 0.5 MILS 6. MATCH DIFFERENTIAL TRACE WIDTHS OF SERIAL AND REFCLK LINES WITH SMP/SMA PADS. 7. PLACE TI LOGO, BOARD NAME, JN COMBO LOGO, AND THE BOARD NUMBER IN TOP SIDE METAL. SCHEMATIC SHEET INDEX: SHEET 01: SHEET 02: SHEET 03: SHEET 04: SHEET 05: C SPARTAN-6 BOARD COVER SHEET AND NOTES USB INTERFACE C REGULATORS FPGA POWER AND GROUND FPGA CONFIGURATION SHEET 06: FPGA MULTI-GIGABIT TRANSCEIVERS SHEET 07: TI PROGRAMMED RESOURCES 1 SHEET 08: TI PROGRAMMED RESOURCES 2 SHEET 09: FPGA USER PROGRAMMABLE RESOURCES 1 SHEET 10: FPGA USER PROGRAMMABLE RESOURCES 2 SHEET 11: FPGA NO CONNECTS SHEET 12: BOARD TO BOARD CONNECTOR SHEET 13: 1P2V SUPPLY LEDS SHEET 14: 1P8V AND 2P5V SUPPLY LEDS SHEET 15: 3P3V AND 5V SUPPLY LEDS B B TEXAS INSTRUMENTS A A SCHEMATIC TITLE ENGINEER J. NERGER DATE TLK10002 EVM SPARTAN-6 FPGA DAUGHTER BOARD 11/15/10 PAGE TITLE LAYOUT J. NERGER DATE 11/15/10 COVER SHEET AND NOTES TLK10002 DATA SHEET REVISION: 0.7 RELEASED J. NERGER DATA SHEET LAST UPDATED ON: 09/27/10 5 4 2 3 DATE 11/15/10 SIZE DOCUMENT NUMBER REV B 6522851 NA 1 SHEET of 15 1 Figure 39. Cover Page and Index, Sheet 1 of 15 SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 53 TLK10002EVM FPGA Daughterboard Schematics www.ti.com 3P3V U6 D13 C1 USB_/RST_B 6 1 C2 4 D15 R3 R5 2 USB_/RST USB_RST TPS3125J18 100K 0.1uF 0.1uF USB_RST_N VCC1 VCC2 VCC3 /RST 3 100K 0.1uF C6 PUR DM 22pF C8 1M 1 6 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 3P3V P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 R18 R17 100 USB ONLINE LED P3.0/S0/RXD P3.1/S1/TXD P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 EE_SCL_S EE_SDA 12 11 SCL SDA DNI_4.99K DNI_4.99K S0 S1 TEST0 TEST1 TEST2 RSV1 RSV2 NC1 NC2 NC3 NC4 NC5 NC6 EE_SCL 58 57 56 55 54 53 52 51 R26 GND1 GND2 GND3 GND4 GND5 R25 4.99K 5 21 24 42 59 /VREN S2 S3 3P3V 22 23 25 26 27 28 29 30 4.99K 38 8 9 /VREN P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 3P3V A R38 R39 TUSB3210 TEXAS INSTRUMENTS USB MDIO BUS R40 5 USB_ONLINE_L B R24 4.99K R23 4.99K WP 1 USB_ONLINE R35 R36 R37 EEPROM 24LC512-I/SM R22 DNI_4.99K 1.5K 1.5K 8 7 6 5 31 32 33 34 35 36 40 41 14 15 20 1 4 2 3 6 7 63 64 A0 VCC A1 WP A2 SCL VSS SDA X1 X2 USB PROGRAMMING SWITCH 1 PIN DIP SMD SW6 1 2 R30 R31 R32 1 2 3 4 GREEN 2 D16 TUSB3210 X2 4.99K 0.1uF 0.1uF 0.1uF C12 C11 C10 DNI_4.99K DNI_4.99K DNI_4.99K PUR DP DM 43 44 45 46 47 48 49 50 2 DNI_4.99K DNI_4.99K DNI_4.99K R21 R20 R19 22pF C9 S3 A2 17 18 19 61 60 S2 A1 USB_SUSPENDED C X1 12.00 MHZ U4 16 4.99K 33 33 13 1p8VDD 3P3V 3P3V A0 USB_SUSPENDED_B R34 DP_CON USB Type B Conn R27 R28 R29 100K 1 R13 10uF C3 S1 S2 2 PUR_R DP R15 R16 DM_CON B 4.99K 4.99K 4.99K 49.9 R9 5 Q14 MMBT4401LT1 X1 A R8 D 1P8VDD 37 PUR_EN 1.5K USB SUSPEND LED MMBT4401LT1 SUSP 5V_USB R14 100 R10 10 39 62 R11 C2 0.1uF C5 C4 C C7 1uF R4 ORANGE 2 USB_SUSP_L 3P3V 15K USB RESET LED U3 Light Touch Switch R12 100 R33 USB_/MR R2 3 4.99K 1 2 3 /RST GND RST /MR USB_RST_L 100K R7 4 3 VDD USB /RESET LED 2K 2K 4 100 R6 4.99K 5 0.1uF R1 Q13 1 U5 SW5 1 2 3 4 1 3P3V AND RESET MONITOR C1 USB RESET PUSHBUTTON 5V DM DP GND USB_SUSP_C USB_/RST_L RED 2 5 VOLTAGE SUPERVISOR 3P3V USB INTERFACE 1 D14 3 100K 100K E2 J2 USB_RST_C GREEN 2 2 ZXTD09N50DE6 1 2 5 1 B2 D 3P3V USB_/RST_C B1 E1 USB_RST_B 1 2 3 4 5 USB_MDC USB_MDIO 3 4 2 8 8 PAGE TITLE USB INTERFACE SIZE DOCUMENT NUMBER REV B 6522851 NA PAGE 2 of 15 1 Figure 40. USB Interface, Sheet 2 of 15 54 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM FPGA Daughterboard Schematics www.ti.com TPS74401RGW JMP3 1 2 1P2VG_REG_EN C33 0.001uF DISABLE FB NC1 NC2 NC3 GND GND_PP Q17 12 21 TPS74401RGW 10uF 1uF 4.75K G S FDV301N R54 FDV301N 20 C 107 27 R55 4.99K R56 FDV301N C30 R52 R53 C D 16 GRD_1P2V_G 1.65K 68uF 13 14 17 C29 SS 9 2.49K NC4 NC5 NC6 C28 PG EN 1P2V_GTP R46 BIAS 1 18 19 20 R49 R51 G 2 3 4 OUT1 OUT2 OUT3 OUT4 1P2VG_REG_ADJ 1uF C27 4.7uF 4.99K R45 100uF C26 C25 10uF 68uF 3.57K 1uF C24 15 16 12 21 GRD_2P5V 1P8V_REG_TRIM Q16 11 IN1 IN2 IN3 IN4 1P2VG_REG_TRIM C32 0.001uF DISABLE 10 1P2VG_REG_SS GND GND_PP 5 6 7 8 5V 0 FB NC1 NC2 NC3 C23 SS 9 13 14 17 C22 NC4 NC5 NC6 R44 1uF 2 3 4 PG EN R48 R47 GRD_1P8V S C21 2P5V_REG_EN BIAS 2P5V D 1 2 2P5V_REG_SS 4.7uF 4.99K R43 100uF C20 C19 10uF 1uF C18 3.57K 68uF JMP2 2.80K G 15 16 12 21 R50 D Q15 5V 11 1 18 19 20 2P5V_REG_TRIM C31 0.001uF DISABLE TPS74401RGW 10 OUT1 OUT2 OUT3 OUT4 0 GND GND_PP 13 14 17 U9 IN1 IN2 IN3 IN4 D FB NC1 NC2 NC3 9 C17 SS 0 1P8V_REG_EN NC4 NC5 NC6 5 6 7 8 5V S 1 2 2 3 4 1P8V_REG_SS JMP1 PG EN 1P8V C16 R41 15 BIAS 1 18 19 20 R42 11 OUT1 OUT2 OUT3 OUT4 1P8V_REG_ADJ 1uF 4.99K 10 C15 100uF 4.7uF C14 C13 D U8 IN1 IN2 IN3 IN4 2P5V_REG_ADJ U7 5 6 7 8 1.2V GTP REGULATOR 2.5V REGULATOR 1.8V REGULATOR 5V 1 2 3 4 5 JMP4 1 SILKSCREEN "ENABLED" 2 GLOBAL_REGULATOR_DISABLE 1.2V REGULATOR 3.3V REGULATOR GND GND_PP DISABLE C46 0.001uF TPS74401RGW 16 12 21 JMP6 1 2 DISABLE C47 0.001uF FB NC1 NC2 NC3 GND GND_PP Q19 1uF B 16 12 21 TPS74401RGW R64 4.75K G S S G C45 13 14 17 10uF SS 9 C44 NC4 NC5 NC6 2.49K PG EN 1P2V GRD_1P2V 3P3V_REG_TRIM GRD_3P3V 2.80K D Q18 BIAS 1 18 19 20 R62 R63 R61 1P2V_REG_EN 2 3 4 OUT1 OUT2 OUT3 OUT4 68uF 15 IN1 IN2 IN3 IN4 C43 1uF C42 4.99K 11 R59 4.7uF 100uF C41 C40 1uF C39 10uF 68uF 3.57K 10 1P2V_REG_SS FB NC1 NC2 NC3 C38 SS 9 13 14 17 C37 NC4 NC5 NC6 5 6 7 8 5V 0 3P3V_REG_EN PG EN 0 1 2 2 3 4 BIAS 3P3V D JMP5 OUT1 OUT2 OUT3 OUT4 R58 15 U10 IN1 IN2 IN3 IN4 3P3V_REG_ADJ 1uF C34 4.99K 11 3P3V_REG_SS B 10 R57 C36 C35 4.7uF 100uF 5V 1 18 19 20 R60 U11 5 6 7 8 1P2V_REG_ADJ SILKSCREEN "DISABLED" 3 Pin Berg 1P2V_REG_TRIM 3 R65 FDV301N FDV301N 107 R66 27 A A TEXAS INSTRUMENTS PAGE TITLE REGULATORS 5 4 2 3 SIZE DOCUMENT NUMBER REV B 6522851 NA PAGE 3 of 15 1 Figure 41. Regulators, Sheet 3 of 15 SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 55 TLK10002EVM FPGA Daughterboard Schematics www.ti.com 2 Pin Berg 2 L4 VCCINT_1P2V 2 MGTAVTTTX_267 MGTAVTTRX_267 MGTAVCC_267 MGTAVCCPLL0_267 MGTAVCCPLL1_267 1 2 L5 VCCO_4_0 VCCO_4_1 VCCO_4_2 VCCO_4_3 VCCO_4_4 VCCO_4_5 VCCO_4_6 VCCAUX_2P5V D25 G22 H25 J21 K23 M20 M25 VCCO_5_0 VCCO_5_1 VCCO_5_2 VCCO_5_3 VCCO_5_4 VCCO_5_5 VCCO_5_6 1 A1 A11 A15 A17 A21 A26 A9 AB16 AB2 AB20 AB25 AC11 AC13 AC15 AC17 AD19 AD21 AD7 AD9 AE10 AE18 AE20 AE22 AE6 AE8 AF1 AF10 AF12 AF16 AF18 AF26 B17 B19 B7 B9 C18 C20 C6 C8 D10 D12 D14 D16 D4 0.1uF 0.1uF C83 C84 C85 C86 C87 C88 C89 C90 C91 C92 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C105 C106 C107 C108 C109 C110 C111 C112 C113 C114 C115 C116 C117 C118 C119 C120 C121 C122 C123 C124 C125 C126 C127 C128 C129 C130 C131 C132 C133 C134 C135 C136 C137 C138 C139 C140 C141 C142 0.1uF C82 0.1uF C104 0.1uF C81 0.1uF C103 0.1uF C80 0.1uF C102 0.1uF C79 0.1uF C101 0.1uF C78 0.1uF C100 0.1uF C77 0.1uF 0.1uF C76 0.1uF C99 0.1uF C75 0.1uF C98 0.1uF C74 0.1uF C97 NOTE: 1210 SIZED 0-OHM RESISTORS HAVE 0.1uF C73 0.1uF C96 6SLX75TFGG676 0.1uF 2 C72 VCCMGT_1P2V C95 C71 L18 L22 L5 M17 N10 R22 U12 U14 U18 U6 V17 V9 W13 0.1uF C70 VCCAUX_13 VCCAUX_14 VCCAUX_15 VCCAUX_16 VCCAUX_17 VCCAUX_18 VCCAUX_19 VCCAUX_20 VCCAUX_21 VCCAUX_22 VCCAUX_23 VCCAUX_24 VCCAUX_25 C94 B BEEN INSTALLED IN PLACE OF FERRITE BEADS. 1uF 0.1uF 0.01uF C56 2 U1R C93 C69 2 Pin Berg VCCAUX_0 VCCAUX_1 VCCAUX_2 VCCAUX_3 VCCAUX_4 VCCAUX_5 VCCAUX_6 VCCAUX_7 VCCAUX_8 VCCAUX_9 VCCAUX_10 VCCAUX_11 VCCAUX_12 0.1uF JMP34 P12 P14 P15 R11 R12 R13 R14 R15 R16 R17 T11 T13 T15 T17 U10 U16 0.1uF 1 0.01uF 0.1uF 1uF 10uF Ferrite Bead_1210 VCCINT_16 VCCINT_17 VCCINT_18 VCCINT_19 VCCINT_20 VCCINT_21 VCCINT_22 VCCINT_23 VCCINT_24 VCCINT_25 VCCINT_26 VCCINT_27 VCCINT_28 VCCINT_29 VCCINT_30 VCCINT_31 0.1uF VCCCLK_3P3V 2 VCCINT_0 VCCINT_1 VCCINT_2 VCCINT_3 VCCINT_4 VCCINT_5 VCCINT_6 VCCINT_7 VCCINT_8 VCCINT_9 VCCINT_10 VCCINT_11 VCCINT_12 VCCINT_13 VCCINT_14 VCCINT_15 0.1uF L6 VCCINT_1P2V U1P 2 C67 C68 C66 C65 VCCINT_1P2V 1 SHUNT VCCAUX_2P5V 0.1uF 0.01uF 0.1uF 1uF 10uF JMP33 K11 K17 L12 L14 L16 M11 M12 M13 M14 M15 M16 N12 N13 N15 N16 P11 D RAPC722 SILK = +5V U1O AA5 AB18 AB8 AC21 AC7 D20 D6 E17 G5 J10 J18 K13 K15 6SLX75TFGG676 2 Pin Berg 3P3V TIP 1 6SLX75TFGG676 2 Ferrite Bead_1210 3 Pin Berg AF20 AC19 AD17 AD15 AE16 VCCAUX_2P5V 1 SLEEVE AF8 AC9 AD11 AE12 AD13 0.1uF 2P5V D2 F4 H2 J6 K4 M2 M7 2 Pin Berg 2 P2 3 VCCO_1P8V JMP32 C64 C63 0.01uF 0.1uF 1uF 10uF C62 C61 C VCCMGT_1P2V MGTAVTTTX_245 MGTAVTTRX_245 MGTAVCC_245 MGTAVCCPLL0_245 MGTAVCCPLL1_245 5V 1 5V_SOURCE VCCMGT_1P2V VCCO_1P8V Ferrite Bead_1210 3 Ferrite Bead_1210 0.1uF 1 AD2 P4 P9 T2 T7 W4 W6 Y2 VCCO_3_0 VCCO_3_1 VCCO_3_2 VCCO_3_3 VCCO_3_4 VCCO_3_5 VCCO_3_6 VCCO_3_7 1 BAT60A 10V, 3A 0.1uF 1P2V VCCO_2_0 VCCO_2_1 VCCO_2_2 VCCO_2_3 VCCO_2_4 VCCO_2_5 VCCO_2_6 VCCO_2_7 VCCO_2_8 VCCO_2_9 1 2 2 10uF MGTAVTTTX_123 MGTAVTTRX_123 MGTAVCC_123 MGTAVCCPLL0_123 MGTAVCCPLL1_123 A19 D18 C16 C14 B15 C55 1 JMP31 C60 C59 0.01uF 0.1uF 1uF C58 C57 10uF Ferrite Bead_1210 L2 JMP7 5V_BJ 5V_DIODE D17 VCCO_1P8V AA14 AA20 AB6 AE14 AE23 AE4 W11 W15 Y18 Y8 BANANA JACK. C54 2 5V_BJ VCCMGT_1P2V VCCO_1P8V 1 5V_BJ 68uF VCCMGT_1P2V MGTAVTTTX_101 MGTAVTTRX_101 MGTAVCC_101 MGTAVCCPLL0_101 MGTAVCCPLL1_101 P1 C53 L3 1P2V_GTP VCCO_1_0 VCCO_1_1 VCCO_1_2 VCCO_1_3 VCCO_1_4 VCCO_1_5 VCCO_1_6 VCCO_1_7 CENTER TO CENTER SPACING WITH A POWER P3 C52 2 C51 2 Pin Berg VCCO_0_0 VCCO_0_1 VCCO_0_2 VCCO_0_3 VCCO_0_4 VCCO_0_5 VCCO_0_6 VCCO_0_7 VCCO_0_8 VCCO_0_9 A7 D8 C10 B11 C12 1 JMP30 NOTE: PLACE GND BANANA JACKS 750 MIL VCCMGT_1P2V U1N AB23 AD25 P18 P23 T25 W21 W23 Y25 5V_BARREL 0.01uF 0.1uF C49 C48 10uF 1uF 1 2 C50 1 Ferrite Bead_1210 D VCCO_1P8V U1Q B13 C22 C4 E21 F13 F8 G18 H11 H16 J14 1 VCCO_1P8V VCCO_1P8V 1 2 3 4 5 L1 1P8V 6SLX75TFGG676 VCCO_1P8V VCCINT_1P2V GND_0 GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24 GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67 GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82 GND_83 GND_84 GND_85 GND_86 GND_87 GND_88 E15 E19 E22 E7 F2 F25 G14 H23 H4 J19 J8 K16 K2 K25 L11 L13 L15 L17 M22 M5 N11 N14 P13 P16 P2 P20 P25 P7 T10 T12 T14 T16 T18 T21 T5 U11 U17 V2 V25 V8 Y10 Y14 Y23 Y4 Y7 C B 6SLX75TFGG676 VCCAUX_2P5V A 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C143 C144 C145 C146 C147 C148 C149 C150 C151 C152 C153 C154 C155 C156 C157 C158 C159 C160 C161 C162 C163 C164 C165 C166 C167 C168 C169 C170 C171 C172 C173 C174 C175 C176 C177 C178 C179 C180 C181 C182 C183 C184 C185 C186 C187 C188 C189 C190 C191 C192 C193 C194 C195 C196 C197 C198 C199 A TEXAS INSTRUMENTS 5 3 4 2 PAGE TITLE FPGA POWER AND GROUND SIZE DOCUMENT NUMBER REV B 6522851 NA PAGE 4 of 15 1 Figure 42. FPGA Power and Ground, Sheet 4 of 15 56 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM FPGA Daughterboard Schematics www.ti.com 5V IO_L2N_CMPMOSI_2 PROGRAMMING V19 RFUSE 0 CMPCS_B_2 IO_L74N_DOUT_BUSY_1 IO_L31N_GCLK30_D15_2 IO_L31P_GCLK31_D14_2 IO_L30P_GCLK1_D13_2 IO_L14N_D12_2 IO_L14P_D11_2 IO_L13N_D10_2 IO_L64N_D9_2 IO_L64P_D8_2 IO_L48P_D7_2 IO_L62N_D6_2 IO_L62P_D5_2 IO_L49N_D4_2 IO_L49P_D3_2 IO_L12N_D2_MISO3_2 IO_L12P_D1_MISO2_2 IO_L3P_D0_DIN_MISO_MISO1_2 R380 C200 IO_L48N_RDWR_B_VREF_2 AF23 CSI_B IO_L3N_MOSI_CSI_B_MISO0_2 SW7 AD22 M0 AF24 IO_L13P_M1_2 IO_L1N_M0_CMPMISO_2 R373 R374 R375 R376 DONE_2 IO_L1P_CCLK_2 DNI_4.99K DNI_4.99K DNI_4.99K DNI_4.99K R387 R367 R368 R369 R_SEL1_P1 D 100 R_SEL0_P1 /INIT_B_D 4.99K R77 D1 D0 D7_P0 D6_P0 D5_P0 D4_P0 D3_P0 D2_P0 D1_P0 D0_P0 A6 A5 B5 C5 D5 E5 H5 H6 AF25 DONE_/CE_P0 B4 AE24 CCLK B3 CCLK STUB MUST BE LESS VCCO(1) VCCO(2) VCCO(3) VCCO(4) BUSY CEO REV_SEL1 REV_SEL0 EN_EXT_SEL CF DNC(1) DNC(2) DNC(3) DNC(4) DNC(5) DNC(6) DNC(7) DNC(8) DNC(9) DNC(10) DNC(11) D7 D6 D5 D4 D3 D2 D1 D0 B2 C6 D6 G5 B3 R91 C /CEO_P0_/CE_P1 VCCAUX_2P5V A3 VCCJ E6 TDOP1_TDIP0 A1 A2 B6 F1 F5 F6 H1 D1 A4 C3 C4 D3 D4 E3 E4 F2 F3 F4 G2 TCK TDI E2 H3 G1 B VCCAUX_2P5V 1 3 5 7 9 11 13 C2 2 4 6 8 10 12 14 TMS TCK TDO TDI E6 Header 7x2 KEYED OE/RESET A1 A2 B6 F1 F5 F6 H1 A24 G21 VCCO_1P8V LOCAL DECOUPLING FOR PROM0/1 0.1uF 0.1uF 250 0.1uF R398 0.1uF 2SUSPENDED_L 0.1uF RED D 1 0.1uF D54 SUSPENDED_D C256 C255 C254 LED INDICATES FPGA IS IN SUSPENDED STATE C253 S G TDO GND(1) GND(2) GND(3) GND(4) GND(5) GND(6) GND(7) TMS TCK TDI H3 G1 A TEXAS INSTRUMENTS FPGA CONFIGURATION PROGRAM_B 2 3 E2 PAGE TITLE XCF32P-TFBGA FDV301N 4 VCCINT_1P2V VCCAUX_2P5V LOCAL DECOUPLING FOR PROM_0/1 F21 5V Q35 H2 0.1uF TDO_P0_TDI_FPGA 0.1uF C23 C260 A3 C259 INIT_B_OE/RESET 0.1uF AE3 6SLX75TFGG676 SUSPENDED_G TMS XCF32P-TFBGA AF3 2 Pin Berg 0 GND(1) GND(2) GND(3) GND(4) GND(5) GND(6) GND(7) JMP9 CLKOUT H2 TDO 0.1uF TDO VCCO_1P8V R379 OE/RESET D2 CE CLK C2 CLKOUT 0.1uF TCK SUSPEND PLACE JUMPER FOR NORMAL OPERATION. CLK C250 TMS IO_L74P_AWAKE_1 Y22 SUSPEND CE C249 VBATT AC23 R393 D0_P1 100 D2 C252 4.99K R397 R396 R394 R395 0 0 TDI V22 VBATT R392 R71 S D3 0 0 0 0 0 0 0 0 VCCINT(1) VCCINT(2) VCCINT(3) VCCJ VFS JMP35 4.99K D1_P1 D7 D6 D5 D4 D3 D2 D1 D0 VCCAUX_2P5V IO_L65P_INIT_B_2 R90 D S S D4 VCCO_1P8V PROGRAM_B_2 W22 VFS 5 R388 DNI_4.99K 4.99K R370 4.99K R372 4.99K R371 /BUSY_D 4.99K R382 D S D5 C251 DNI_4.99K DNI_4.99K DNI_4.99K AF2 REMOVE JUMPER TO SUSPEND FPGA. D2_P1 THAN 8MM IN LENGTH IO_L65N_CSO_B_2 1 2 /EN_EXT_SEL_P1 250 R69 2DONE_L D19 1 DONE_D R384 D S R82 R83 R84 R85 R86 R87 R88 R89 D6 VCCAUX_2P5V A D3_P1 A4 C3 C4 D3 D4 E3 E4 F2 F3 F4 G2 0.1uF 3P3V D4_P1 D1 CF DNC(1) DNC(2) DNC(3) DNC(4) DNC(5) DNC(6) DNC(7) DNC(8) DNC(9) DNC(10) DNC(11) C248 PUSHBUTTON D5_P1 REV_SEL1 REV_SEL0 EN_EXT_SEL D 0.1uF Light Touch Switch VCCAUX_2P5V M1 D6_P1 D2 CEO C247 4 3 A6 A5 B5 C5 D5 E5 H5 H6 D7_P1 BUSY 0.1uF 1 2 5 RE-PROGRAM FPGA D7 G4 G3 H4 B2 C6 D6 G5 VCCO(1) VCCO(2) VCCO(3) VCCO(4) C246 PROG_B_RST_SIGNAL VCCO_1P8V VCCINT(1) VCCINT(2) VCCINT(3) C235 1 2 AF13 AE13 AB14 W18 W17 AF22 AA6 AA7 AA10 W7 W8 AF6 AD6 W19 V18 AD23 BUSY_P0 C1 0 R381 BUSY 0.1uF R78 PROG_B_RST R81 AB11 RDWR_B JMP8 AC24 PROM 0 C258 4 10K /MR 0.1uF VDD 5 4.99K 4.99K 4.99K 4.99K 49.9 /RST GND RST 2 Pin Berg B R80 Y19 TPS3125J18 100K PROG_B_/RST 1 2 3 RFUSE VCCO_1P8V U13 G4 G3 H4 0 0 0 0 0 0 0 0 R353 R354 R355 R356 R357 R358 R359 R360 C1 B4 R_SEL1_P0 IO_L2P_CMPCLK_2 AA22 BUSY_P1 VCCO_1P8V U2 R_SEL0_P0 PULLUPS DURING 0 R389 VCCO_1P8V B1 E1 G6 VCCO_1P8V U44 B1 E1 G6 VCCO_1P8V VCCINT_1P2V PROM 1 VCCINT_1P2V PROGRAMMING G G /EN_EXT_SEL_P0 AND RESET MONITOR IO_L39N_M1ODT_1 G DNI_4.99K DNI_4.99K DNI_4.99K DNI_4.99K TO ENABLE Y21 ZXTD09N50DE6 ERROR DURING FDV301N R385 R361 R362 R363 VOLTAGE SUPERVISOR IO_L39P_M1A3_1 LED INDICATES CRC FDV301N DNI_4.99K 4.99K 4.99K 4.99K 2 Pin Berg PLACE JUMPER T23 250 0 R73 R386 R364 R365 R366 T22 INIT_B_G 0.1uF 1 2 5 FDV301N C257 E2 Q22 DNI_4.99K JMP36 G Q21 /INIT_B_G 2/INIT_B_L R68 FDV301N 330 B2 Q20 PROGRAMMING FDV301N R391 PROG_B_RST_C Q33 RED D20 1 WHEN BUSY R390 4.99K D21 1 2 3 IS COMPLETE 5V LED INDICATES G DNI_4.99K VCCO_1P8V H20 G20 L23 L24 N19 N20 N21 N22 P17 P19 N23 N24 R18 R19 P21 P22 R20 R21 P24 P26 R23 R24 T24 T26 V24 V26 Q34 R76 PROG_B_RST_B 20K R75 PROG_B_/RST_B 20K R74 C IO_L1P_A25_5 IO_L1N_A24_VREF_5 IO_L29P_A23_M1A13_1 IO_L29N_A22_M1A14_1 IO_L30P_A21_M1RESET_1 IO_L30N_A20_M1A11_1 IO_L31P_A19_M1CKE_1 IO_L31N_A18_M1A12_1 IO_L32P_A17_M1A8_1 IO_L32N_A16_M1A9_1 IO_L33P_A15_M1A10_1 IO_L33N_A14_M1A4_1 IO_L34P_A13_M1WE_1 IO_L34N_A12_M1BA2_1 IO_L35P_A11_M1A7_1 IO_L35N_A10_M1A2_1 IO_L36P_A9_M1BA0_1 IO_L36N_A8_M1BA1_1 IO_L37P_A7_M1A0_1 IO_L37N_A6_M1A1_1 IO_L38P_A5_M1CLK_1 IO_L38N_A4_M1CLKN_1 IO_L44P_A3_M1DQ6_1 IO_L44N_A2_M1DQ7_1 IO_L45P_A1_M1LDQS_1 IO_L45N_A0_M1LDQSN_1 R377 C2 LED INDICATES 250 R383 5V /BUSY_G PROGRAMMING B1 E1 4 1PROG_B_/RST_C RED C1 AA26 DONE_G U12 IO_L47N_LDC_M1DQ1_1 2 1 D18 SUCESSFULLY PRESSED. IO_L63P_SCP7_0 IO_L63N_SCP6_0 IO_L64P_SCP5_0 IO_L64N_SCP4_0 IO_L65P_SCP3_0 IO_L65N_SCP2_0 IO_L66P_SCP1_0 IO_L66N_SCP0_0 AA25 AD24 2/BUSY_L 0 PUSHBUTTON WAS IO_L48P_HDC_M1DQ8_1 4.99K PROVIDE FEEDBACK THE PROG_B_RST_L GREEN 2 PROGRAM_B NET AND 130 PROG_B_/RST_L STATUS OF THE IO_L47P_FWE_B_M1DQ0_1 B22 A22 G19 F19 B23 A23 D21 D22 R70 LEDS INDICATE THE 6 5V W25 W26 R79 R67 IO_L46N_FOE_B_M1DQ3_1 GREEN IO_L46P_FCS_B_M1DQ2_1 0 BUSY_G IO_L1P_HSWAPEN_0 each. VCCO_1P8V RED D53 1 R72 H7 HSWAPEN 130 Guide) Page 20. Available from Digikey in two packages for 26.25 D 5V 5V U1A D 5V 1 2 3 4 5 XILINX Platform FLASH PROM XCF32P compatable with Spartan-6 FPGA Devices as found in table 1-2 of UG161 (Platform Flash PROM User SIZE DOCUMENT NUMBER REV B 6522851 NA PAGE 5 of 15 1 Figure 43. FPGA Configuration, Sheet 5 of 15 SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 57 TLK10002EVM FPGA Daughterboard Schematics www.ti.com 1 2 3 4 5 U1E U1B 12 12 LS_A3_RX_P_CONNECTOR LS_A3_RX_N_CONNECTOR B10 A10 LS_A3_CLK_P C206 LS_A3_CLK_N 12 CHA_CLKN_CONNECTOR CHA_CLKP_CONNECTOR C201 0.1uF C203 0.1uF MGTRXP0_245 MGTRXN0_245 MGTREFCLK0P_245 MGTREFCLK0N_245 0.1uF C205 0.1uF VCCCLK_3P3V AC8 AD8 AE11 AF11 LS_B3_CLK_P C208 LS_B3_CLK_N 0.1uF VCCCLK_3P3V LS_B3_CLKOUT_P LS_B3_CLKOUT_N 9 10 12 12 C OUTP0 OUTN0 3 Pin Berg VCCCLK_3P3V 83 83 LS_A2_RX_P_CONNECTOR LS_A2_RX_N_CONNECTOR MGTREFCLK1P_245 MGTREFCLK1N_245 AC12 AD12 LS_B2_CLK_P C219 LS_B2_CLK_N 4.99K 0.1uF C216 0.1uF MGTRXP1_245 MGTRXN1_245 AE9 AF9 AC10 AD10 5 R93 1 9 10 2 2 CHB_CLK_SEL 3 OUTP0 OUTN0 3 Pin Berg VCCCLK_3P3V 12 12 LS_B1_RX_P_CONNECTOR LS_B1_RX_N_CONNECTOR C 6SLX75TFGG676 C222 C224 0.1uF OUTP3 OUTN3 GND 130 130 3 4 AC18 AD18 12 12 LS_B2_TX_P_CONNECTOR LS_B2_TX_N_CONNECTOR 12 12 LS_B2_RX_P_CONNECTOR LS_B2_RX_N_CONNECTOR 15 16 LS_B3_CLKOUT_P MGTREFCLK0P_267 MGTREFCLK0N_267 AC16 AD16 LS_B1_CLK_P LS_B1_CLK_N C221 C223 0.1uF 0.1uF LS_B3_CLKOUT_N LS_B1_CLKOUT_P THERMAL PAD OUTP3 OUTN3 GND R123 R124 AE19 AF19 R100 R104 R105 130 130 R116 R117 R110 R111 INP1 INN1 150 150 17 1 OUTP2 OUTN2 R121 R122 MGTRXP0_267 MGTRXN0_267 VCCCLK_3P3V 83 83 150 150 6 7 R112 R113 R101 R102 130 130 R108 R109 130 130 150 150 15 16 0.1uF INP0 INN0 17 B CHB_CLK1_N LS_A1_CLK_N U1D MGTTXP0_267 MGTTXN0_267 THERMAL PAD OUTP1 OUTN1 1 150 150 LS_A1_CLK_P LS_B2_CLKOUT_N CHA_CLK1_P D15 C15 12 12 13 14 LS_B2_CLKOUT_P CHA_CLK1_N LS_A1_RX_P_CONNECTOR LS_A1_RX_N_CONNECTOR 3 4 R119 R120 D17 C17 12 12 VCCCLK_3P3V R114 R115 R106 R107 MGTREFCLK0P_123 MGTREFCLK0N_123 LS_A1_TX_P_CONNECTOR LS_A1_TX_N_CONNECTOR INP1 INN1 R125 R118 MGTRXP0_123 MGTRXN0_123 B18 A18 OUTP2 OUTN2 LS_B1_CLKOUT_N 150 150 MGTTXP0_123 MGTTXN0_123 LS_A1_CLKOUT_N U1C B LS_A1_CLKOUT_P 13 14 11 12 LS_B1_CLKOUT_P 83 83 INP0 INN0 6 7 150 150 OUTP1 OUTN1 R103 6SLX75TFGG676 11 12 CHB_CLK_SEL1 1uF 0.1uF C214 VCC JMP11 LS_B0_CLKOUT_N 12 12 LS_B1_TX_P_CONNECTOR LS_B1_TX_N_CONNECTOR VAC_REF IN_SEL LS_B0_CLKOUT_P MGTTXP1_245 MGTTXN1_245 8 CHB_CLK0_N 3 150 150 D9 C9 12 12 2 CHA_CLK_SEL R98 R96 LS_A2_TX_P_CONNECTOR LS_A2_TX_N_CONNECTOR LS_A2_CLKOUT_P B8 A8 2 U15 VAC_REFB CHB_CLK1_P 1 IN_SEL LS_B2_CLKOUT_N MGTRREF_245 CHB_CLK_SEL0 0.1uF CHA_CLK0_P C215 0.1uF CHA_CLK_SEL0 C220 LS_A2_CLK_N 4.99K LS_A2_CLK_P C209 0.1uF 0.1uF 5 AB10 D 4.99K VCC LS_B2_CLKOUT_P R99 R97 VAC_REF MGTAVTTRCAL_245 R95 49.9 MGTRREF_245 CHA_CLK0_N 8 C218 D11 C11 LS_A2_CLKOUT_N MGTRXP1_101 MGTRXN1_101 0.1uF C202 C213 4.99K VAC_REFA AB12 R92 C212 U14 MGTAVTTRCAL_245 CHA_CLK_SEL1 1uF 0.1uF C211 MGTRREF_101 LS_A3_CLKOUT_P LS_A3_CLKOUT_N E9 C210 0.1uF JMP10 MGTTXP1_101 MGTTXN1_101 CHB_CLKN_CONNECTOR CHB_CLKP_CONNECTOR VCCMGT_1P2V MGTAVTTRCAL_101 0.1uF E11 R94 49.9 MGTREFCLK1P_101 MGTREFCLK1N_101 0.1uF C204 0.1uF 12 12 CHB_CLK0_P VCCCLK_3P3V VCCMGT_1P2V MGTRREF_101 12 12 LS_B0_RX_P_CONNECTOR LS_B0_RX_N_CONNECTOR C207 VCCCLK_3P3V D MGTAVTTRCAL_101 12 12 LS_B0_TX_P_CONNECTOR LS_B0_TX_N_CONNECTOR 83 83 MGTREFCLK0P_101 MGTREFCLK0N_101 12 AE7 AF7 C217 MGTRXP0_101 MGTRXN0_101 12 12 LS_A3_TX_P_CONNECTOR LS_A3_TX_N_CONNECTOR D7 C7 MGTTXP0_245 MGTTXN0_245 150 150 MGTTXP0_101 MGTTXN0_101 B6 A6 CDCLVP1204 LS_B1_CLKOUT_N R128 R129 R126 R127 LS_A0_CLKOUT_N LS_A0_CLKOUT_P CDCLVP1204 J4 J3 CHA_CLKN CHB_CLKN CHA_CLK1_N_SMA C225 0.1uF CHB_CLK1_N_SMA C226 0.1uF CHB_CLK1_P_SMA C231 0.1uF SMA SURFACE SMA SURFACE MGTREFCLK1P_123 MGTREFCLK1N_123 B16 A16 LS_A0_CLK_P LS_A0_CLK_N C230 C228 0.1uF MGTREFCLK1P_267 MGTREFCLK1N_267 0.1uF J5 CHA_CLKP A CHA_CLK1_P_SMA C232 MGTTXP1_123 MGTTXN1_123 MGTRXP1_123 MGTRXN1_123 LS_A0_TX_P_CONNECTOR LS_A0_TX_N_CONNECTOR D19 C19 LS_A0_RX_P_CONNECTOR LS_A0_RX_N_CONNECTOR LS_B0_CLK_P LS_B0_CLK_N C229 C227 0.1uF 0.1uF LS_B0_CLKOUT_P J6 LS_B0_CLKOUT_N CHB_CLKP 0.1uF SMA SURFACE SMA SURFACE B20 A20 AE17 AF17 MGTTXP1_267 MGTTXN1_267 12 12 MGTRXP1_267 MGTRXN1_267 12 12 AE21 AF21 AC20 AD20 A 12 12 LS_B3_TX_P_CONNECTOR LS_B3_TX_N_CONNECTOR 12 12 LS_B3_RX_P_CONNECTOR LS_B3_RX_N_CONNECTOR TEXAS INSTRUMENTS PAGE TITLE FPGA GIGABIT TRANSCEIVERS 6SLX75TFGG676 6SLX75TFGG676 5 3 4 2 SIZE DOCUMENT NUMBER REV B 6522851 NA PAGE 6 of 15 1 Figure 44. FPGA Gigabit Transceivers, Sheet 6 of 15 58 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM FPGA Daughterboard Schematics www.ti.com 1 2 3 4 5 5V VCCO_1P8V VOLTAGE SUPERVISOR /MR 4 R131 130 VDD JMP12 1 2 MAIN_RST_SIGNAL SW8 TPS3125J18 4 3 1 2 5 VCCO_1P8V 2 Pin Berg MAIN RESET D22 PUSHBUTTON 1 U17 R149 JMP13 1 3 5 7 9 11 13 15 PRBSEN TEST_EN_A TEST_EN_B LANE2_4_SELECT_A LANE2_4_SELECT_B LOOPBACK_A LOOPBACK_B C1 20K MAIN_RST_B 2 4 6 8 10 12 14 16 6 E1 R150 C2 20K MAIN_/RST_B 4 1 MAIN_RST_C B1 2 1 PDTRXA_N 4.99K 4.99K 4.99K 4.99K 4.99K F7 B4 U15 V16 AA15 AB15 AA21 AB21 R144 R145 R146 R147 R148 RESET_N_(IO_L2P_0) D23 IO_L3P_0 IO_L22P_0 IO_L17P_2 IO_L17N_2 IO_L28P_2 IO_L28N_2 IO_L15P_2 IO_L15N_2 H8 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K IO_L2P_0 R136 R137 R138 R139 R140 R141 R142 R143 Light Touch Switch U1G D R134 /RST GND RST GREEN 2 VCCO_1P8V 100K MAIN_RST_L R135 5V 2 MAIN_RST D 5 RED 1 2 3 MAIN_/RST C233 0.1uF 10K AND RESET MONITOR U16 49.9 R132 R133 MAIN_/RST_L R130 4.99K 130 VCCO_1P8V 3 MAIN_/RST_C B2 E2 5 Header 8x2 C IO_L5P_2 IO_L5N_2 IO_L33P_2 IO_L33N_2 IO_L34N_2 AB22 AC22 Y12 AA12 Y13 1 3 5 7 9 GPIO_1_(IO_L5P_2) GPIO_2_(IO_L5N_2) GPIO_3_(IO_L33P_2) GPIO_4_(IO_L33N_2) GPIO_5_(IO_L34N_2) C ZXTD09N50DE6 JMP14 2 4 6 8 10 VCCO_1P8V 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K Header 5x2 JMP15 H9 A3 U19 U20 1 3 5 7 LOSA_(IO_L13P_0) LOSB_(IO_L14P_0) TEST_PASS_A_(IO_L68P_1) TEST_PASS_B_(IO_L68N_1) 2 4 6 8 R151 R152 R153 R154 R155 R156 R157 R158 R159 R160 R161 R162 R163 R164 R165 R166 R167 R168 R169 R170 IO_L13P_0 IO_L14P_0 IO_L68P_1 IO_L68N_1 JMP16 1 U1L IO_L32N_GCLK28_2 Header 4x2 AF14 IO_SIGNALS_CLK1 V11 Y11 V10 AB9 AA9 Y6 Y5 AC5 AF4 AD4 AC3 AB4 AA4 AA3 V7 V6 U9 U8 R9 P10 IO_SIGNALS_0 2 Pin Berg 2 JMP17 B IO_L58P_0 IO_L59P_0 IO_L67P_1 IO_L66P_1 H17 C21 AA23 T19 5V 5V 5V 5V 5V 5V 5V LS_OK_IN_A_CONNECTOR 12 LS_OK_OUT_A_CONNECTOR LS_OK_IN_B_CONNECTOR 12 12 LS_OK_OUT_B_CONNECTOR 12 5V FDV301N 5 FDV301N FDV301N FDV301N FDV301N FDV301N 250 GREEN 2TEST_PASS_B_L 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 IO_SIGNALS_1 IO_SIGNALS_2 IO_SIGNALS_3 IO_SIGNALS_4 IO_SIGNALS_5 IO_SIGNALS_6 IO_SIGNALS_7 IO_SIGNALS_8 IO_SIGNALS_9 IO_SIGNALS_10 IO_SIGNALS_11 IO_SIGNALS_12 IO_SIGNALS_13 IO_SIGNALS_14 IO_SIGNALS_15 IO_SIGNALS_16 IO_SIGNALS_17 IO_SIGNALS_18 IO_SIGNALS_19 6SLX75TFGG676 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 B Header 2x20 1 D31 R186 1 TEST_PASS_B_D A TEXAS INSTRUMENTS D Q30 PAGE TITLE G FPGA TI PROGRAMMED RESOURCES S S G TEST_PASS_B_G TEST_PASS_A_D D LOSB_D D Q29 S G TEST_PASS_A_G 1 D30 GREEN 2TEST_PASS_A_L LOSB_L 0 FDV301N 4 R185 2 RED D29 Q28 S S G LOSB_G 1 D LOSA_D LOSA_G Q27 G R178 250 R177 250 R176 0 250 R175 LOSA_L R184 2 R183 RED D28 ORANGE 2LS_OK_OUT_B_L D27 R182 1 LS_OK_OUT_B_D Q26 S G D LS_OK_IN_B_D D Q25 LS_OK_OUT_B_G 1 D26 YELLOW 2LS_OK_IN_B_L 0 0 250 R174 250 R173 0 250 R172 0 R181 ORANGE 2LS_OK_OUT_A_L 1 G LS_OK_IN_B_G LS_OK_OUT_A_D D Q24 S G S Q23 D LS_OK_IN_A_D LS_OK_IN_A_G A LS_OK_OUT_A_G 1 D25 R180 R179 D24 YELLOW 2LS_OK_IN_A_L 0 0 R171 250 6SLX75TFGG676 IO_L46P_2 IO_L41P_2 IO_L46N_2 IO_L47N_2 IO_L47P_2 IO_L7P_3 IO_L7N_3 IO_L61P_2 IO_L63N_2 IO_L63P_2 IO_L8N_3 IO_L8P_3 IO_L2P_3 IO_L2N_3 IO_L9P_3 IO_L9N_3 IO_L18P_3 IO_L18N_3 IO_L53P_M3CKE_3 IO_L55P_M3A13_3 FDV301N 2 3 SIZE DOCUMENT NUMBER REV B 6522851 NA PAGE 7 of 15 1 Figure 45. TI-Programmed Resources 1, Sheet 7 of 15 SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 59 TLK10002EVM FPGA Daughterboard Schematics www.ti.com 1 2 3 4 5 5V VCCO_1P8V 130 VCCO_1P8V VOLTAGE SUPERVISOR 4 /MR 130 R188 JMP18 MDIO_RST_SIGNAL 1 2 SW9 4 3 1 2 5 2 Pin Berg MDIO RESET D32 PUSHBUTTON C1 20K C2 20K MDIO_/RST_B 4 JMP29 B1 12 12 2 1 3 I2C_SDA_CONNECTOR I2C_SCL_CONNECTOR 3 2 4 Header 2x2 1 E1 R194 MDIO_RST_C D33 6 1 GREEN 2 U19 MDIO_RST_B I2C INTERFACE 1 Light Touch Switch R193 D R191 VDD MDIO_RST_L /RST GND RST TPS3125J18 2 MDIO_RST 100K R192 5V RED D 5 R189 1 2 3 MDIO_/RST C234 0.1uF 10K AND RESET MONITOR U18 49.9 R190 MDIO_/RST_L R187 4.99K MDIO_/RST_C B2 E2 C 5 C ZXTD09N50DE6 2P5V VCCO_1P8V VCCO_1P8V Q31 Q32 2P5V 1 3 0 0 PRTAD1 PRTAD0 MDC_POST_LS MDIO_POST_LS Header 5x2 C261 1uF U45 GND VREF1 SCL1 SDA1 EN VREF2 SCL2 SDA2 8 7 6 5 MDIO_LS_EN MDIO_LS_VCCB MDC_PRE_LS MDIO_PRE_LS PCA9306DCT 6SLX75TFGG676 DNI_2K 1 2 3 4 R214 2 4 6 8 10 4.99K C236 1uF JMP21 1 3 5 7 9 PRTAD3 PRTAD2 R212 MDC_(IO_L34P_GCLK19_0) DNI_2K 2 R203 R204 PRTAD4 R201 R202 H12 J15 J16 G16 F20 4.99K 4.99K 4.99K 4.99K 4.99K MDIO_(IO_L33N_0) R213 IO_L33P_0 IO_L43P_0 IO_L48P_0 IO_L56P_0 IO_L57P_0 G13 E13 JMP20 3 Pin Berg VCCO_1P8V 2 4 Header 2x2 VCCO_1P8V MDIO_RESET DNI_2K MDC_CON DNI_0 0 0 3P3V R207 R208 R209 R210 R211 IO_L33N_0 IO_L34P_GCLK19_0 G11 JMP19 1 3 MDIO_CON DNI_0 R200 U1F IO_L32N_0 DNI_2K DNI_0 MDC DNI_0 R199 PRE-LEVEL SHIFTED MDIO D R206 MDIO R196 R195 1 3 Header 2x2 R351 R352 B S DNI_FDV301N R205 DNI_0 DNI_0 2 4 D DNI_FDV301N JMP28 R198 S POST-LEVEL SHIFTED MDIO R197 G INSTALLED AT A TIME 2K 2K Q32 SO THAT ONLY ONE CAN BE G THE S AND D PINS OF Q31 AND 12 12 MDIO_POST_LS_CONNECTOR MDC_POST_LS_CONNECTOR VCCO_1P8V PLACE R199 AND R200 BETWEEN B MDIO INTERFACE R215 R216 0 0 R217 R218 DNI_0 DNI_0 12 12 MDC_PRE_LS_CONNECTOR MDIO_PRE_LS_CONNECTOR USB_MDC USB_MDIO 2 2 DO NOT OVERLAP RESISTOR PADS PRTAD ADDRESS HEADER BI-DIRECTIONAL LEVEL SHIFTER A A TEXAS INSTRUMENTS PAGE TITLE TI PROGRAMMED RESOURCES 1 5 3 4 2 SIZE DOCUMENT NUMBER REV B 6522851 NA PAGE 8 of 15 1 Figure 46. TI-Programmed Resources 2, Sheet 8 of 15 60 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM FPGA Daughterboard Schematics www.ti.com 1 2 3 4 5 U1H LED1 LED2 LED3 LED4 LED5 LED6 LED7 D LED8 LED9 LED10 LED11 LED12 R242 250 0 1 1 D1 YELLOW 2LED1_L 250 R240 R241 0 5V D2 1 D3 ORANGE 2LED2_L 250 R238 5V R239 0 R237 GREEN 2LED3_L 0 250 R236 2LED4_L D4 1 1 1 5V RED 250 R234 R235 0 5V D5 YELLOW 2LED5_L 250 R232 R233 0 5V D6 1 1 D7 ORANGE 2LED6_L 250 R230 5V R231 0 GREEN 2LED7_L 250 R229 2LED8_L RED D8 1 LED1_D LED2_D FDV301N D Q1 S G S G FDV301N LED1_G D LED3_D LED2_G Q2 S G S FDV301N D Q3 G S G FDV301N LED3_G Q4 D LED4_D LED5_D LED4_G LED6_D FDV301N D Q5 S S G FDV301N LED5_G Q6 D LED7_D LED6_G LED8_D G S S FDV301N FDV301N D Q7 G S G LED7_G Q8 D LED9_D LED8_G D LED9_G D R228 0 R227 R226 250 0 R225 D9 1 LED10_D 5V C Q9 G FDV301N 5V YELLOW 2LED9_L 0 250 ORANGE 2LED10_L R224 250 LED11_D 1 Q10 S G FDV301N 5V D10 R223 0 Q11 S G FDV301N 5V D11 GREEN 2LED11_L R222 250 2LED12_L R220 LED12_D Q12 D LED12_G C LED11_G 1 D12 RED R219 5V R221 0 5V 6SLX75TFGG676 LED10_G D B5 J11 F22 J20 AB24 AC25 W20 Y17 AD3 AC2 L9 L4 D IO_L24P_0 IO_L32P_0 IO_L6P_M5A10_5 IO_L7P_M5WE_5 IO_L49P_M1DQ10_1 IO_L50P_M1UDQS_1 IO_L4P_2 IO_L16P_2 IO_L33P_M3DQ12_3 IO_L34P_M3UDQS_3 IO_L70P_M4RASN_4 IO_L71P_M4A5_4 FDV301N VCCO_1P8V J7 0 R243 GCLK17 GCLK17_SMA R244 R245 R246 R247 R248 R249 R250 R251 R252 R253 R254 R255 R256 R257 R258 R259 R260 R261 R262 R263 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K SMA SURFACE U1I B IO_L43N_GCLK22_IRDY2_M3CASN_3 R6 J8 JMP23 1 IO_SIGNALS_CLK2 2 Pin Berg 2 A U3 U4 R4 R3 N2 N1 M3 M1 P8 N7 N5 N4 M4 N8 N9 M10 L2 L1 K3 K1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 IO_SIGNALS_20 IO_SIGNALS_21 IO_SIGNALS_22 IO_SIGNALS_23 IO_SIGNALS_24 IO_SIGNALS_25 IO_SIGNALS_26 IO_SIGNALS_27 IO_SIGNALS_28 IO_SIGNALS_29 IO_SIGNALS_30 IO_SIGNALS_31 IO_SIGNALS_32 IO_SIGNALS_33 IO_SIGNALS_34 IO_SIGNALS_35 IO_SIGNALS_36 IO_SIGNALS_37 IO_SIGNALS_38 IO_SIGNALS_39 GCLK14 GCLK14_SMA SMA SURFACE B U1J JMP22 IO_L10N_3 IO_L10P_3 IO_L52P_M3A8_3 IO_L52N_M3A9_3 IO_L59P_M4DQ14_4 IO_L59N_M4DQ15_4 IO_L60P_M4DQ12_4 IO_L60N_M4DQ13_4 IO_L53N_M3A12_3 IO_L51N_M3A4_3 IO_L54P_M3RESET_3 IO_L54N_M3A11_3 IO_L58P_4 IO_L51P_M3A10_3 IO_L55N_M3A14_3 IO_L57P_3 IO_L61P_M4UDQS_4 IO_L61N_M4UDQSN_4 IO_L62P_M4DQ10_4 IO_L62N_M4DQ11_4 0 R264 IO_L35P_GCLK17_0 IO_L36N_GCLK14_0 IO_L37N_GCLK12_0 IO_L41P_GCLK27_M3DQ4_3 IO_L42P_GCLK25_TRDY2_M3UDM_3 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 C13 A12 A14 T3 V4 GCLK17 J9 GCLK14 GCLK12 0 R265 GCLK12 GCLK12_SMA GCLK27 SMA SURFACE GCLK25 J10 6SLX75TFGG676 0 R266 GCLK27 GCLK27_SMA SMA SURFACE J11 0 R267 GCLK25 GCLK25_SMA SMA SURFACE A Header 2x20 6SLX75TFGG676 TEXAS INSTRUMENTS PAGE TITLE FPGA USER PROGRAMMABLE RESOURCES 5 4 2 3 SIZE DOCUMENT NUMBER REV B 6522851 NA PAGE 9 of 15 1 Figure 47. User Programmable Resources 1, Sheet 9 of 15 SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 61 TLK10002EVM FPGA Daughterboard Schematics www.ti.com 1 2 3 5V C2 20K 4 PB1_/RST_B 1 D34 PB1_RST_C R281 6 PB2_RST_B 1 C2 4 PB2_/RST_B 1 130 PB2_RST_C B1 20K LEDS INDICATE THE 2 3 PB2_/RST_C LEDS INDICATE THE B2 STATUS OF THE E2 5 STATUS OF THE PUSHBUTTON1 NET AND E2 5 PUSHBUTTON2 NET AND PROVIDE FEEDBACK THE C PROVIDE FEEDBACK THE PUSHBUTTON WAS ZXTD09N50DE6 R276 PB2_RST_L 2 MAIN RESET E1 R283 D 2 Pin Berg C1 20K PB1_/RST_C B2 1 2 PUSHBUTTON D36 2 3 R271 1 2 5 U24 B1 E1 R282 4 3 Light Touch Switch GREEN 2 C1 20K JMP25 PB2_RST_SIGNAL SW2 1 U22 6 4 1 MAIN RESET PUSHBUTTON PB1_RST_B /MR TPS3125J18 2 Pin Berg Light Touch Switch R280 VDD GREEN 2 1 2 5 /RST GND RST D37 4 3 100K 5V RED TPS3125J18 PB2_RST R279 5 D35 1 2 C238 0.1uF 10K R269 JMP24 PB1_RST_SIGNAL SW1 1 2 3 1 4 /MR 130 VDD AND RESET MONITOR U23 49.9 PB2_/RST R278 /RST GND RST PB1_RST_L 100K R275 2 R277 VOLTAGE SUPERVISOR 5V RED PB1_RST D 5 R272 1 2 3 PB1_/RST C237 0.1uF 10K AND RESET MONITOR U21 49.9 R270 4.99K R273 VOLTAGE SUPERVISOR VCCO_1P8V 130 VCCO_1P8V PB1_/RST_L R268 4.99K R274 5V VCCO_1P8V 130 VCCO_1P8V PB2_/RST_L 4 5 PUSHBUTTON WAS ZXTD09N50DE6 SUCESSFULLY PRESSED. C SUCESSFULLY PRESSED. U1M PUSHBUTTON1 PUSHBUTTON2 PUSHBUTTON3 PUSHBUTTON4 5V C2 20K PB4_/RST_B 4 C1 20K 6 E1 PB4_/RST_C R299 C2 20K PB3_/RST_B 4 1 130 PB3_RST_C B1 2 1 PB3_RST_B 3 PB3_/RST_C LEDS INDICATE THE B2 STATUS OF THE E2 5 STATUS OF THE PUSHBUTTON4 NET AND E2 5 PUSHBUTTON3 NET AND PROVIDE FEEDBACK THE ZXTD09N50DE6 B RED U28 R297 R295 PB3_RST_L 2 2 Pin Berg Light Touch Switch LEDS INDICATE THE B2 1 2 MAIN RESET 1 3 1 2 5 PB3_/RST_L D38 2 R287 10K 4 3 PUSHBUTTON B1 E1 R298 PB4_RST_C JMP27 PB3_RST_SIGNAL SW4 D41 6 1 5V D40 C1 PB4_RST_B 4 1 U26 C240 0.1uF D39 130 MAIN RESET Light Touch Switch 20K /MR 5 TPS3125J18 2 Pin Berg PUSHBUTTON R296 100K VDD 1 B 1 2 5 R294 /RST GND RST PB4_/RST_L 4 3 PB3_RST R292 1 2 1 2 3 PB3_/RST R289 R285 JMP26 PB4_RST_SIGNAL SW3 TPS3125J18 AND RESET MONITOR U27 49.9 GREEN 2 4 /MR PB4_RST_L 100K 5 VDD R293 2 PB4_RST R291 /RST GND RST VOLTAGE SUPERVISOR 5V RED 1 2 3 PB4_/RST C239 0.1uF 10K AND RESET MONITOR U25 49.9 VCCO_1P8V R286 4.99K 130 VCCO_1P8V VOLTAGE SUPERVISOR R290 5V VCCO_1P8V 130 VCCO_1P8V R284 4.99K R288 6SLX75TFGG676 GREEN 2 IO_L11P_M5CLK_5 IO_L13P_M5CLK_5 IO_L74P_M4A0_4 IO_L76P_M4A7_4 B25 M18 L7 L10 PROVIDE FEEDBACK THE PUSHBUTTON WAS PUSHBUTTON WAS ZXTD09N50DE6 SUCESSFULLY PRESSED. SUCESSFULLY PRESSED. A A TEXAS INSTRUMENTS PAGE TITLE FPGA USER PROGRAMMABLE RESOURCES 2 5 3 4 2 SIZE DOCUMENT NUMBER REV B 6522851 NA PAGE 10 of 15 1 Figure 48. User-Programmable Resources 2, Sheet 10 of 15 62 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback G7 G8 F6 C3 B3 G6 F5 G9 A2 E6 E5 A4 A5 D13 A13 B12 B14 K12 J12 H15 J17 F17 E20 G17 B21 H18 H19 B24 A25 K18 K19 D23 C24 H21 H22 G23 J22 E23 E24 L19 K20 C25 C26 B26 K21 K22 M19 F23 G24 J23 J24 E25 E26 D24 D26 F24 F26 H24 H26 G25 G26 K24 K26 J25 J26 M24 M26 L25 L26 N25 N26 M21 M23 L20 L21 N17 N18 U23 U24 R25 R26 V23 W24 U25 U26 AD26 AB26 AC26 Y24 Y26 AE25 AE26 U21 C IO_L1N_VREF_0 IO_L2N_0 IO_L3N_0 IO_L4P_0 IO_L4N_0 IO_L5P_0 IO_L5N_0 IO_L13N_0 IO_L14N_0 IO_L8P_0 IO_L8N_VREF_0 IO_L22N_0 IO_L24N_0 IO_L34N_GCLK18_0 IO_L35N_GCLK16_0 IO_L36P_GCLK15_0 IO_L37P_GCLK13_0 IO_L38P_0 IO_L38N_VREF_0 IO_L43N_0 IO_L48N_0 IO_L56N_0 IO_L57N_0 IO_L58N_0 IO_L59N_0 IO_L62P_0 IO_L62N_VREF_0 IO_L2P_M5A13_5 IO_L2N_M5A14_5 IO_L3P_M5RESET_5 IO_L3N_M5A11_5 IO_L4P_M5CKE_5 IO_L4N_M5A12_5 IO_L5P_M5A8_5 IO_L5N_M5A9_5 IO_L6N_M5A4_5 IO_L7N_M5BA2_5 IO_L8P_M5A7_5 IO_L8N_M5A2_5 IO_L9P_M5BA0_5 IO_L9N_M5BA1_5 IO_L10P_M5A0_5 IO_L10N_M5A1_5 IO_L11N_M5CLKN_5 IO_L12P_M5A3_5 IO_L12N_M5ODT_5 IO_L13N_M5A6_5 IO_L14P_M5RASN_5 IO_L14N_M5CASN_5 IO_L15P_M5UDM_5 IO_L15N_M5LDM_5 IO_L16P_M5DQ4_5 IO_L16N_M5DQ5_5 IO_L17P_M5DQ6_5 IO_L17N_M5DQ7_5 IO_L18P_M5LDQS_5 IO_L18N_M5LDQSN_5 IO_L19P_M5DQ2_5 IO_L19N_M5DQ3_5 IO_L20P_M5DQ0_5 IO_L20N_M5DQ1_5 IO_L21P_M5DQ8_5 IO_L21N_M5DQ9_5 IO_L22P_M5DQ10_5 IO_L22N_M5DQ11_5 IO_L23P_M5UDQS_5 IO_L23N_M5UDQSN_5 IO_L24P_M5DQ12_5 IO_L24N_M5DQ13_5 IO_L25P_M5DQ14_5 IO_L25N_M5DQ15_5 IO_L26P_5 IO_L26N_VREF_5 IO_L27P_5 IO_L27N_5 IO_L28P_1 IO_L28N_VREF_1 IO_L40P_GCLK11_M1A5_1 IO_L40N_GCLK10_M1A6_1 IO_L41P_GCLK9_IRDY1_M1RASN_1 IO_L41N_GCLK8_M1CASN_1 IO_L42P_GCLK7_M1UDM_1 IO_L42N_GCLK6_TRDY1_M1LDM_1 IO_L43P_GCLK5_M1DQ4_1 IO_L43N_GCLK4_M1DQ5_1 IO_L48N_M1DQ9_1 IO_L49N_M1DQ11_1 IO_L50N_M1UDQSN_1 IO_L51P_M1DQ12_1 IO_L51N_M1DQ13_1 IO_L52P_M1DQ14_1 IO_L52N_M1DQ15_1 IO_L53P_1 D IO_L53N_VREF_1 IO_L66N_1 IO_L67N_1 IO_L69P_1 IO_L69N_VREF_1 IO_L4N_VREF_2 IO_L16N_VREF_2 IO_L29P_GCLK3_2 IO_L29N_GCLK2_2 IO_L30N_GCLK0_USERCCLK_2 IO_L32P_GCLK29_2 IO_L34P_2 IO_L41N_VREF_2 IO_L61N_VREF_2 IO_L1P_3 IO_L1N_VREF_3 IO_L17P_3 IO_L17N_VREF_3 IO_L31P_3 IO_L31N_VREF_3 IO_L32P_M3DQ14_3 IO_L32N_M3DQ15_3 IO_L33N_M3DQ13_3 IO_L34N_M3UDQSN_3 IO_L35P_M3DQ10_3 IO_L35N_M3DQ11_3 IO_L36P_M3DQ8_3 IO_L36N_M3DQ9_3 IO_L37P_M3DQ0_3 IO_L37N_M3DQ1_3 IO_L38P_M3DQ2_3 IO_L38N_M3DQ3_3 IO_L39P_M3LDQS_3 IO_L39N_M3LDQSN_3 IO_L40P_M3DQ6_3 IO_L40N_M3DQ7_3 IO_L41N_GCLK26_M3DQ5_3 IO_L42N_GCLK24_M3LDM_3 IO_L43P_GCLK23_M3RASN_3 IO_L44P_GCLK21_M3A5_3 IO_L44N_GCLK20_M3A6_3 IO_L45P_M3A3_3 IO_L45N_M3ODT_3 IO_L46P_M3CLK_3 IO_L46N_M3CLKN_3 IO_L47P_M3A0_3 IO_L47N_M3A1_3 IO_L48P_M3BA0_3 IO_L48N_M3BA1_3 IO_L49P_M3A7_3 IO_L49N_M3A2_3 IO_L50P_M3WE_3 IO_L50N_M3BA2_3 IO_L57N_VREF_3 IO_L58N_VREF_4 IO_L63P_M4DQ8_4 IO_L63N_M4DQ9_4 IO_L64P_M4DQ0_4 IO_L64N_M4DQ1_4 IO_L65P_M4DQ2_4 IO_L65N_M4DQ3_4 IO_L66P_M4LDQS_4 IO_L66N_M4LDQSN_4 IO_L67P_M4DQ6_4 IO_L67N_M4DQ7_4 IO_L68P_M4DQ4_4 IO_L68N_M4DQ5_4 IO_L69P_M4UDM_4 IO_L69N_M4LDM_4 IO_L70N_M4CASN_4 IO_L71N_M4A6_4 IO_L72P_M4A3_4 IO_L72N_M4ODT_4 IO_L73P_M4CLK_4 IO_L73N_M4CLKN_4 IO_L74N_M4A1_4 IO_L75P_M4BA0_4 IO_L75N_M4BA1_4 IO_L76N_M4A2_4 IO_L77P_M4WE_4 IO_L77N_M4BA2_4 IO_L78P_M4A10_4 IO_L78N_M4A4_4 IO_L79P_M4A8_4 IO_L79N_M4A9_4 IO_L80P_M4CKE_4 IO_L80N_M4A12_4 IO_L81P_M4RESET_4 IO_L81N_M4A11_4 IO_L82P_M4A13_4 IO_L82N_M4A14_4 IO_L83P_4 IO_L83N_VREF_4 U22 T20 AA24 V20 V21 Y20 AA17 AE15 AF15 AC14 AD14 W14 AA11 AD5 AB5 AC4 V5 W5 U7 T6 AB3 AB1 AD1 AC1 AE2 AE1 AA2 AA1 Y3 Y1 W2 W1 V3 V1 U2 U1 T1 W3 R7 R2 R1 R8 T8 U5 T4 R10 T9 P3 P1 N6 P6 P5 R5 M9 N3 J2 J1 H3 H1 G2 G1 F3 F1 E2 E1 D3 D1 J4 J3 L8 L3 M8 M6 K5 J5 L6 B2 B1 K10 G4 G3 J9 J7 C2 C1 K9 K8 E4 E3 K7 K6 H6 H5 www.ti.com TLK10002EVM FPGA Daughterboard Schematics 5 5 SLLU148 – May 2011 Submit Documentation Feedback 4 B 4 3 F9 E8 D5 C5 H10 G10 F10 E10 G12 F11 F12 E12 V12 W12 AB13 AA13 W10 W9 AE5 AF5 Y9 AA8 AB7 AC6 IO_L15P_0_NC IO_L15N_0_NC IO_L16P_0_NC IO_L16N_0_NC IO_L21P_0_NC IO_L21N_0_NC IO_L23P_0_NC IO_L23N_0_NC IO_L30P_0_NC IO_L30N_0_NC IO_L31P_0_NC IO_L31N_0_NC IO_L35P_2_NC IO_L35N_2_NC IO_L36P_2_NC IO_L36N_2_NC IO_L50P_2_NC IO_L50N_2_NC IO_L51P_2_NC IO_L51N_2_NC IO_L52P_2_NC IO_L52N_2_NC IO_L53P_2_NC IO_L53N_2_NC IO_L39P_0_NC IO_L39N_0_NC IO_L40P_0_NC IO_L40N_0_NC IO_L41P_0_NC IO_L41N_0_NC IO_L49P_0_NC IO_L49N_0_NC IO_L50P_0_NC IO_L50N_0_NC IO_L51P_0_NC IO_L51N_0_NC IO_L18P_2_NC IO_L18N_2_NC IO_L19P_2_NC IO_L19N_2_NC IO_L20P_2_NC IO_L20N_2_NC IO_L24P_2_NC IO_L24N_VREF_2_NC IO_L26P_2_NC IO_L26N_2_NC IO_L27P_2_NC IO_L27N_2_NC 2 3 2 Copyright © 2011, Texas Instruments Incorporated 1 U1K 6SLX75TFGG676 D C U1S J13 H13 F14 E14 K14 H14 F16 E16 G15 F15 F18 E18 AA19 AB19 W16 Y16 AA18 AB17 Y15 AA16 V14 V15 U13 V13 B 6SLX75TFGG676 A A FPGA NO CONNECTS PAGE TITLE TEXAS INSTRUMENTS SIZE DOCUMENT NUMBER REV B 6522851 1 NA 11 of PAGE 15 Figure 49. FPGA No Connects, Sheet 11 of 15 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module 63 TLK10002EVM FPGA Daughterboard Schematics C A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 LS_B0_TX_P_CONNECTOR LS_B0_TX_N_CONNECTOR 6 6 LS_B0_RX_N_CONNECTOR LS_B0_RX_P_CONNECTOR 6 6 LS_B1_TX_P_CONNECTOR LS_B1_TX_N_CONNECTOR 6 6 LS_B1_RX_N_CONNECTOR LS_B1_RX_P_CONNECTOR 6 6 LS_B2_RX_N_CONNECTOR LS_B2_RX_P_CONNECTOR 6 6 LS_B2_TX_P_CONNECTOR LS_B2_TX_N_CONNECTOR 6 6 LS_B3_RX_N_CONNECTOR LS_B3_RX_P_CONNECTOR 6 6 LS_B3_TX_P_CONNECTOR LS_B3_TX_N_CONNECTOR 6 6 CHB_CLKP_CONNECTOR CHB_CLKN_CONNECTOR B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 6 6 7 LS_OK_OUT_B_CONNECTOR 7 LS_OK_IN_B_CONNECTOR SEAM_ASP-134488-01 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 MDIO_PRE_LS_CONNECTOR MDC_PRE_LS_CONNECTOR SEAM_ASP-134488-01 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 8 8 B A J1J K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K40 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K40 6 6 LS_A3_TX_N_CONNECTOR LS_A3_TX_P_CONNECTOR LS_A3_RX_P_CONNECTOR LS_A3_RX_N_CONNECTOR 6 6 LS_A2_TX_N_CONNECTOR LS_A2_TX_P_CONNECTOR 6 6 LS_A2_RX_P_CONNECTOR LS_A2_RX_N_CONNECTOR 6 6 LS_A1_RX_P_CONNECTOR LS_A1_RX_N_CONNECTOR 6 6 LS_A1_TX_N_CONNECTOR LS_A1_TX_P_CONNECTOR 6 6 LS_A0_RX_P_CONNECTOR LS_A0_RX_N_CONNECTOR 6 6 LS_A0_TX_N_CONNECTOR LS_A0_TX_P_CONNECTOR 6 6 CHA_CLKP_CONNECTOR CHA_CLKN_CONNECTOR 6 6 7 LS_OK_OUT_A_CONNECTOR LS_OK_IN_A_CONNECTOR 7 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J33 J34 J35 J36 J37 J38 J39 J40 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 E36 E37 E38 E39 E40 MDIO_POST_LS_CONNECTOR MDC_POST_LS_CONNECTOR I2C_SCL_CONNECTOR 8 I2C_SDA_CONNECTOR 8 SEAM_ASP-134488-01 8 8 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40 D C SEAM_ASP-134488-01 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 B J1I MOUNT1 MOUNT2 MOUNT3 MOUNT4 I1 I2 I3 I4 SEAM_ASP-134488-01 A TEXAS INSTRUMENTS PAGE TITLE SEAM_ASP-134488-01 SEAM_ASP-134488-01 5 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 SAMTEC SEAM BOARD TO BOARD CONNECTOR SEAM_ASP-134488-01 SEAM_ASP-134488-01 J1H G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 J1F E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 E36 E37 E38 E39 E40 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J33 J34 J35 J36 J37 J38 J39 J40 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 SEAM_ASP-134488-01 J1E J1K J1G J1D C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 SEAM_ASP-134488-01 1 2 J1C J1B A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 3 4 5 J1A D www.ti.com 3 4 2 SIZE DOCUMENT NUMBER REV B 6522851 NA PAGE 12 of 15 1 Figure 50. Board-to-Board Connector, Sheet 12 of 15 64 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM FPGA Daughterboard Schematics www.ti.com 1 2 3 4 5 NOTE: VOLTAGE WINDOW DETECTOR CIRCUITS MONITOR THE VOLTAGE ON THE PLANE AND LIGHTS THE APPROPRIATE LED IF IT IS WITHIN THE ALLOWABLE DATASHEET RANGE. D D 4P096V_REF1 5V 5V 4P096V_REF2 5V 5V U29 2 OUT 2 U31 C2 4 LM339A U30D 9 8 3 IN_P 3 IN_N + - 3 OUT 14 R313 VCCINT_1P2V R316 2.8K B 2 IN_N + - 2 OUT R318 10K VCCINT_1P2V_1P05V_VREF 10 4 IN_P 4 IN_N + - 4 OUT 4P096V_REF2 C2 LM339A U33D R314 9 VCCMGT_1P2V_1P34V_VREF 8 VCCMGT_1P2V 3 IN_N + - 3 OUT 14 R317 2.8K 13 11 10K VCCMGT_1P2V_1P05V_VREF 10 4 IN_P 4 IN_N R303 VCCMGT_1P2V_L 2 1 B1 E2 3 IN_P 3 B2 26.1K ZXTD09N50DE6 R319 6 5V 5 D45 BLUE U34 E1 5 ZXTD09N50DE6 B LM339A U33E 11 2 1 LM339A U30E 2 IN_P 2 B1 E2 VCCINT_1P2V_B VCCINT_1P2V_1P34V_VREF 4 1P2V_GTP_1P05V_VREF C1 26.1K 105K R312 10K 4 C1 6 5V 5 R311 B2 E1 4P096V_REF1 3 VCCMGT_1P2V_C + - 1P2V_GTP_B 2 IN_N VCCMGT_1P2V_B 2 IN_P C LM339A R315 4 VCCINT_1P2V_C 1P2V_1P05V_VREF 1P2V_C 10K 1P2V_B R310 1 1 1 OUT BLUE 2 1 IN_N R309 2.8K 2 LM339A + - D44 6 1P2V_GTP 1 IN_P 105K 7 U33C 5 12 26.1K 1P2V_GTP_1P34V_VREF LM339A 49.9 49.9 R302 GND 1P2V_GTP_L LM339A VCC 5V 2 2 BLUE BLUE 1 R308 2.8K U30C U33A U33B R306 D43 105K 1 R305 1 IN_N 1 OUT D42 6 1P2V + - 3 4P096V_REF2 26.1K 1 IN_P 5V C242 0.47uF REF2940 LM339A U30B 1 1 49.9 5V 7 5V GND VIN 4P096V_REF1 1P2V_1P34V_VREF 3 12 R307 GND 105K LM339A VCC 1P2V_L U30A VCCINT_1P2V_L 3 1P2V_GTP_C 5V C241 0.47uF 2 1 REF2940 C VOUT R301 1 VIN R304 U32 5V GND R300 3 49.9 2 VOUT + - 4 OUT 13 A A TEXAS INSTRUMENTS PAGE TITLE 1P2V SUPPLY LEDS 5 4 2 3 SIZE DOCUMENT NUMBER REV B 6522851 NA PAGE 13 of 15 1 Figure 51. 1P2V LEDs, Sheet 13 of 15 SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 65 TLK10002EVM FPGA Daughterboard Schematics www.ti.com 1 2 3 4 5 NOTE: VOLTAGE WINDOW DETECTOR CIRCUITS MONITOR THE VOLTAGE ON THE PLANE AND LIGHTS THE APPROPRIATE LED IF IT IS WITHIN THE ALLOWABLE DATASHEET RANGE. D D 4P096V_REF3 5V 5V 4P096V_REF4 5V 5V U35 2 OUT 2 U37 C2 4 LM339A U36D 9 8 3 IN_P 3 IN_N + - 3 OUT 14 R333 VCCO_1P8V R336 2K B VCCO_1P8V_B VCCO_1P8V_2P0V_VREF 2P5V_2P3V_VREF 2 IN_P 2 IN_N + - 2 OUT R338 10K VCCO_1P8V_1P675V_VREF 10 4 IN_P 4 IN_N + - 4 OUT E1 4P096V_REF4 E2 LM339A U39D R334 VCCAUX_2P5V_2P7V_VREF 9 8 VCCAUX_2P5V E2 3 IN_P 3 IN_N + - 3 OUT 14 R337 1.8K 13 11 10K VCCAUX_2P5V_2P3V_VREF 10 4 IN_P 4 IN_N R323 VCCAUX_2P5V_L BLUE 2 1 B1 6.04K ZXTD09N50DE6 R339 6 5V 5 3 B2 1 B1 D49 BLUE U40 C2 5 ZXTD09N50DE6 B LM339A U39E 11 2 2 LM339A U36E 4 C1 12.4K 105K R332 10K 4 C1 6 5V 5 R331 B2 E1 4P096V_REF3 3 2P5V_C + - 2P5V_B 2 IN_N VCCAUX_2P5V_B 2 IN_P C LM339A R335 4 VCCO_1P8V_C 1P8V_1P675V_VREF 1P8V_C 10K 1P8V_B R330 1 1 1 OUT R329 1.8K VCCAUX_2P5V_C 1 IN_N + - 2 LM339A 2 6 2P5V 1 IN_P 105K 7 U39C 5 12 6.04K 2P5V_2P7V_VREF LM339A 49.9 49.9 R322 GND 2P5V_L LM339A VCC 5V 2 2 BLUE BLUE 1 R328 2K U36C U39A U39B R326 D47 105K 1 R325 1 IN_N 1 OUT D46 6 1P8V + - 3 4P096V_REF4 12.4K 1 IN_P 5V C244 0.47uF REF2940 LM339A U36B 1 D48 49.9 5V 7 5V GND VIN 4P096V_REF3 1P8V_2P0V_VREF 3 12 R327 GND 105K LM339A VCC 1P8V_L U36A VCCO_1P8V_L 3 1 5V C243 0.47uF 2 1 REF2940 C VOUT R321 1 VIN R324 U38 5V GND R320 3 49.9 2 VOUT + - 4 OUT 13 A A TEXAS INSTRUMENTS PAGE TITLE 1P8V AND 2P5V SUPPLY LEDS 5 3 4 2 SIZE DOCUMENT NUMBER REV B 6522851 NA PAGE 14 of 15 1 Figure 52. 1P8V and 2P5V LEDs, Sheet 14 of 15 66 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM FPGA Daughterboard Schematics www.ti.com 1 2 3 4 5 NOTE: VOLTAGE WINDOW DETECTOR CIRCUITS MONITOR THE VOLTAGE ON THE PLANE AND LIGHTS THE APPROPRIATE LED IF IT IS WITHIN THE ALLOWABLE DATASHEET RANGE. D D 4P096V_REF5 5V 5V 49.9 5V LM339A VCC GND 5V 12 4P096V_REF5 5V 5V_L 2 2 BLUE 1 BLUE 1 R345 2K D51 1 OUT R344 1 IN_N + - D50 6 3P3V 1 IN_P 105K 7 R342 LM339A U42B 1.65K 3P3V_3P6V_VREF 49.9 U42A VCCCLK_3P3V_L 3 C245 0.47uF 3P3V_L REF2940 C 1 1 VIN C 49.9 5V GND R343 R341 2 VOUT R340 U41 3 LM339A 4 2 IN_N + - 2 OUT 2 U43 B2 E1 C1 4P096V_REF5 8 3 IN_N + - 3 OUT 14 R348 VCCCLK_3P3V 3 IN_P R349 2K 2 1 B1 E2 5 ZXTD09N50DE6 B LM339A U42E 11 R350 VCCCLK_3P3V_B 9 105K 1.65K VCCCLK_3P3V_3P6V_VREF B 6 5V LM339A U42D R347 3 1 C2 4 BLUE 2 IN_P D52 3P3V_3P0V_VREF VCCCLK_3P3V_C 10K 3P3V_C R346 3P3V_B 2 U42C 5 10K VCCCLK_3P3V_3P0V_VREF 10 4 IN_P 4 IN_N + - 4 OUT 13 A A TEXAS INSTRUMENTS PAGE TITLE 3P3V AND 5V SUPPLY LEDS 5 4 2 3 SIZE DOCUMENT NUMBER REV B 6522851 NA PAGE 15 of 15 1 Figure 53. 3P3V and 5-V LEDs, Sheet 15 of 15 SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 67 TLK10002EVM FPGA Daughterboard Bill of Materials 14 www.ti.com TLK10002EVM FPGA Daughterboard Bill of Materials Table 3. TLK10002EVM FPGA Daughterboard Bill of Materials 68 Item Qty Reference Value Part Part Number Manufacturer 1 24 C201, C202, C203, C204, C205, C206, C207, C208, C215, C216, C219, C220, C221, C222, C223, C224, C225, C226, C227, C228, C229, C230, C231, C232 0.1μF 0201 CAP C0201X5R6R3-104KNE Venkel 2 164 C1, C2, C4, C5, C6, C10, C11, C12, 0.1μF C73, C74, C75, C76, C77, C78, C79, C80, C81, C82, C83, C84, C85, C86, C87, C88, C89, C90, C91, C92, C93, C94, C95, C96, C97, C98, C99, C100, C101, C102, C103, C104, C105, C106, C107, C108, C109, C110, C111, C112, C113, C114, C115, C116, C117, C118, C119, C120, C121, C122, C123, C124, C125, C126, C127, C128, C129, C130, C131, C132, C133, C134, C135, C136, C137, C138, C139, C140, C141, C142, C143, C144, C145, C146, C147, C148, C149, C150, C151, C152, C153, C154, C155, C156, C157, C158, C159, C160, C161, C162, C163, C164, C165, C166, C167, C168, C169, C170, C171, C172, C173, C174, C175, C176, C177, C178, C179, C180, C181, C182, C183, C184, C185, C186, C187, C188, C189, C190, C191, C192, C193, C194, C195, C196, C197, C198, C199, C200, C209, C210, C212, C214, C217, C218, C233, C234, C235, C237, C238, C239, C240, C246, C247, C248, C249, C250, C251, C252, C253, C254, C255, C256, C257, C258, C259, C260 0402 CAP C0402X7R160-104KNE Venkel 3 5 C241, C242, C243, C244, C245 0.47μF 0402 CAP C0402X5R6R3-474KNE Venkel 4 5 C7, C211, C213, C236, C261 1.0μF 0402 CAP C0402X5R6R3-105KNE Venkel 5 2 C8, C9 22pF 0402 CAP C0402COG500-220JNE Venkel 6 5 C15, C21, C27, C34, C42 1.0μF 0603 CAP C1608X7R1C105K TDK Corporation 7 5 C31, C32, C33, C46, C47 1000pF 0603 CAP C0603X7R101-102KNE Venkel 8 1 C3 10μF 0603 CAP ECJ-1VB0J106M Panasonic 9 5 C14, C20, C26, C36, C41 4.7μF 0603 CAP C0603C475K8PACTU Kemet TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM FPGA Daughterboard Bill of Materials www.ti.com Table 3. TLK10002EVM FPGA Daughterboard Bill of Materials (continued) Item Qty Reference Value Part Part Number Manufacturer 10 6 C51, C56, C60, C64, C67, C72 0.01μF 0805 CAP GRM21BR72A103KA01L Murata Electronics North America 11 6 C49, C55, C59, C63, C68, C71 0.1μF 1206 CAP C1206C104J5RACTU Kemet 12 11 C18, C24, C30, C39, C45, C50, C54, C58, C62, C66, C70 1.0μF 1206 CAP C1206X7R250-105KNE Venkel 13 11 C17, C23, C29, C38, C44, C48, C53, C57, C61, C65, C69 10μF 1206 CAP C1206X7R160-106KNE Venkel 14 6 C16, C22, C28, C37, C43, C52 68μF 1210 CAP C3225X5R0J686M TDK Corporation 15 5 C13, C19, C25, C35, C40 100μF 1812 CAP GRM43SR60J107ME20L Murata Electronics North America 16 18 R82, R83, R84, R85, R86, R87, R88, R89, R353, R354, R355, R356, R357, R358, R359, R360, R381, R389 0.0 (Zero Ohm) 0201 RES CR0201-20W-000T Venkel 17 8 R108, R109, R112, R113, R119, R120, R123, R124 130 0201 RES RR0306P-131-D Susumu Co Ltd 18 16 R96, R97, R98, R99, R106, R107, R110, R111, R118, R121, R122, R125, R126, R127, R128, R129 150 0201 RES ERJ-1GEF1500C Panasonic - ECG 19 8 R101, R102, R104, R105, R114, R115, R116, R117 82.5 0201 RES ERJ-1GEF82R5C Panasonic - ECG 20 38 R72, R73, R179, R180, R181, R182, R183, R184, R185, R186, R201, R202, R203, R204, R215, R216, R219, R221, R223, R225, R227, R229, R231, R233, R235, R237, R239, R241, R243, R264, R265, R266, R267, R379, R380, R384, R392, R393 0.0 (Zero Ohm) 0402 RES ERJ-2GE0R00X Panasonic - ECG 21 1 R18 1.00M 0402 RES CR0402-16W-1004FT Venkel 22 3 R14, R31, R32 1.50K 0402 RES RG1005P-152-B-T5 Susumu 23 2 R343, R347 1.65K 0402 RES ERJ-2RKF1651X Panasonic - ECG 24 2 R329, R337 1.80K 0402 RES RG1005P-182-B-T5 Susumu Co Ltd 25 17 R78, R132, R189, R272, R273, R288, 10.0K R289, R310, R311, R318, R319, R330, R331, R338, R339, R346, R350 0402 RES RG1005P-103-B-T5 Susumu Co Ltd 26 6 R1, R2, R4, R17, R77, R91 0402 RES RG1005P-101-B-T5 Susumu Co Ltd 27 13 R3, R5, R9, R10, R11, R13, R81, 100K R135, R192, R277, R279, R291, R294 0402 RES RG1005P-104-B-T5 Susumu 28 10 R305, R307, R313, R315, R325, R327, R333, R335, R344, R348 0402 RES ERJ-2RKF1053X Panasonic - ECG SLLU148 – May 2011 Submit Documentation Feedback 100 105K TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 69 TLK10002EVM FPGA Daughterboard Bill of Materials www.ti.com Table 3. TLK10002EVM FPGA Daughterboard Bill of Materials (continued) 70 Item Qty Reference Value Part Part Number Manufacturer 29 2 R324, R332 12.4K 0402 RES RG1005P-1242-B-T5 Susumu Co Ltd 30 14 R67, R70, R131, R134, R188, R191, R269, R271, R276, R278, R285, R287, R292, R295 130 0402 RES RG1005P-131-B-T5 Susumu Co Ltd 31 1 R12 15.0K 0402 RES RG1005P-153-B-T5 Susumu 32 8 R38, R39, R195, R196, R328, R336, R345, R349 2.00K 0402 RES RG1005P-202-B-T5 Susumu 33 4 R308, R309, R316, R317 2.80K 0402 RES RG1005P-2801-B-T5 Susumu Co Ltd 34 14 R74, R75, R149, R150, R193, R194, R280, R281, R282, R283, R296, R297, R298, R299 20.0K 0402 RES RG1005P-203-B-T5 Susumu 35 24 R68, R69, R171, R172, R173, R174, R175, R176, R177, R178, R220, R222, R224, R226, R228, R230, R232, R234, R236, R238, R240, R242, R383, R398 249 0402 RES RR0510P-2490-D Susumu Co Ltd 36 4 R304, R306, R312, R314 26.1K 0402 RES RG1005P-2612-B-T5 Susumu Co Ltd 37 2 R15, R16 33 0402 RES RR0510R-330-D Susumu Co Ltd 38 1 R76 330 0402 RES RG1005P-331-B-T5 Susumu Co Ltd 39 95 R6, R7, R22, R23, R24, R33, R34, R35, R36, R37, R40, R71, R79, R90, R92, R93, R100, R103, R130, R136, R137, R138, R139, R140, R141, R142, R143, R144, R145, R146, R147, R148, R151, R152, R153, R154, R155, R156, R157, R158, R159, R160, R161, R162, R163, R164, R165, R166, R167, R168, R169, R170, R187, R207, R208, R209, R210, R211, R244, R245, R246, R247, R248, R249, R250, R251, R252, R253, R254, R255, R256, R257, R258, R259, R260, R261, R262, R263, R268, R270, R284, R286, R364, R365, R366, R370, R371, R372, R373, R374, R375, R376, R377, R382, R397 4.99K 0402 RES RG1005P-4991-B-T5 Susumu Co Ltd 40 21 R8, R80, R94, R95, R133, R190, R274, R275, R290, R293, R300, R301, R302, R303, R320, R321, R322, R323, R340, R341, R342 49.9 0402 RES RG1005P-49R9-B-T5 Susumu Co Ltd 41 2 R326, R334 6.04K 0402 RES RG1005P-6041-B-T5 Susumu Co Ltd 42 5 R47, R48, R49, R61, R62 0.0 (Zero Ohm) 0603 RES ERJ-3GEY0R00V Panasonic - ECG TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM FPGA Daughterboard Bill of Materials www.ti.com Table 3. TLK10002EVM FPGA Daughterboard Bill of Materials (continued) Item Qty Reference Value Part Part Number Manufacturer 43 1 R51 1.65K 0603 RES RG1608P-1651-B-T5 Susumu Co Ltd 44 2 R54, R65 107 0603 RES RR0816P-1070-B-T5-04A Susumu Co Ltd 45 2 R46, R60 2.49K 0603 RES RG1608P-2491-B-T5 Susumu Co Ltd 46 1 R50 2.80K 0603 RES RR0816P-2801-D-44H Susumu Co Ltd 47 1 R63 1.10K 0603 RES RG1608P-112-B-T5 Susumu Co Ltd 48 1 R53 20 0603 RES RR0816Q-200-D Susumu Co Ltd 49 2 R56, R66 27 0603 RES CR0603-16W-27R0FT Venkel 50 3 R42, R44, R58 3.57K 0603 RES RG1608P-3571-B-T5 Susumu Co Ltd 51 2 R52, R64 4.75K 0603 RES RG1608P-4751-B-T5 Susumu Co Ltd 52 7 R41, R43, R45, R55, R57, R59, R212 4.99K 0603 RES RG1608P-4991-B-T5 Susumu Co Ltd 53 6 L1, L2, L3, L4, L5, L6 0.0 (Zero Ohm) 1210 RES RK73Z2ETTE KOA Speer 54 11 D42, D43, D44, D45, D46, D47, D48, D49, D50, D51, D52 LED - Blue Diffused C170 HSMR-C170 Avago Technologies US 55 15 D3, D7, D11, D13, D16, D18, D19, D23, D30, D31, D33, D36, D37, D40, D41 LED - Green Diffused C170 HSMG-C170 Avago Technologies US 56 6 D2, D6, D10, D15, D25, D27 LED - Orange Diffused C170 HSMD-C170 Avago Technologies US 57 16 D4, D8, D12, D14, D20, D21, D22, D28, D29, D32, D34, D35, D38, D39, D53, D54 LED - Red Diffused C170 SML-LXT0805IW-TR Lumex Opto/Components 58 5 D1, D5, D9, D24, D26 LED - Yellow C170 SML-LXT0805YW-TR Lumex Opto/Components 59 1 D17 Zener Diode SOD-323 BAT 60A E6327 Infineon Technologies 60 31 Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q33, Q34, Q35 NFET SOT-23 FDV301N Fairchild Semiconductor 61 2 Q13, Q14 NPN SOT-23-3 MMBT4401 Fairchild Semiconductor 62 13 U6, U12, U17, U19, U22, U24, U26, U28, U31, U34, U37, U40, U43 Dual NPN SOT-23-6 ZXTD09N50DE6TA Zetex Inc 63 5 U30, U33, U36, U39, U42 Differential Comparator 14-TSSOP LM339APWR Texas Instruments 64 2 U14, U15 Clock Buffer 16-HQFN CDCLVP1204 Texas Instruments 65 5 U7, U8, U9, U10, U11 Adjustable LDO 20-VQFN TPS74401RGWT Texas Instruments 66 2 U2, U44 32MB EEPROM 48-CSBGA XCF32PFSG48C Xilinx Inc 67 1 U3 USB Microcontroller 64-LQFP TUSB3210PM Texas Instruments 68 1 U1 Spartan-6 FPGA 676-BGA 6SLX75TFGG676 Xilinx Inc 69 1 U4 512KB EEPROM 8-SOIC 24LC512-I/SM Microchip Technology SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 71 TLK10002EVM FPGA Daughterboard Bill of Materials www.ti.com Table 3. TLK10002EVM FPGA Daughterboard Bill of Materials (continued) 72 Item Qty Reference Value Part Part Number Manufacturer 70 1 U45 Bi-Directional Level Shifter 8-SSOP PCA9306DCTR Texas Instruments 71 5 U29, U32, U35, U38, U41 Precision Voltage Reference SOT-23-3 REF2940AIDBZT Texas Instruments 72 8 U5, U13, U16, U18, U21, U23, U25, U27 Voltage Supervisor with manual Reset SOT-23-5 TPS3125J18DBVR Texas Instruments 73 1 X1 12.000MHz Crystal SMD ECS-120-32-5PVX ECS Inc 74 8 SW1, SW2, SW3, SW4, SW5, SW7, SW8, SW9 Momentary Push Button 6.00mm x 6.00mm EVQ-PBE05R Panasonic - ECG 75 1 SW6 1-Pos Dip Switch SMT SDA01H0SB ITT Cannon - C&K 76 1 J1 Board to Board Connector SMT ASP-134488-01 Samtec 77 21 JMP1, JMP2, JMP3, JMP5, JMP6, JMP8, JMP12, JMP16, JMP18, JMP23, JMP24, JMP25, JMP26, JMP27, JMP30, JMP31, JMP32, JMP33, JMP34, JMP35, JMP36 1X2 0.1" HTSW-150-08-G-S Samtec 78 5 JMP4, JMP7, JMP10, JMP11, JMP20 1X3 0.1" HTSW-150-08-G-S Samtec 79 1 JMP9 14 Pin - Shrouded 0.1" SP N2514-6002RB 3M 80 3 JMP19, JMP28, JMP29 2X2 0.1x0.1" HTSW-150-08-G-D Samtec 81 1 JMP15 2X4 0.1x0.1" HTSW-150-08-G-D Samtec 82 2 JMP14, JMP21 2X5 0.1x0.1" HTSW-150-08-G-D Samtec 83 1 JMP13 2X8 0.1x0.1" HTSW-150-08-G-D Samtec 84 2 JMP17, JMP22 2 X 20 0.1x0.1" HTSW-150-08-G-D Samtec 85 1 P2 Power Jack 2.1mm PJ-002AH CUI Inc 86 2 P1, P3 Banana Plug - Metal 4mm 108-0740 -001 Emerson Network Pwr Co 87 1 J2 USB - B Type B Type 897-43-004-90-000000 Mill-Max Manufacturing Co 88 9 J3, J4, J5, J6, J7, J8, J9, J10, J11 Surface Mount SMA T/H_SMT SMA 32K141-40ML5 Rosenberger 89 4 Screws 4-40/0.25"- Screws Philips PMSSS 440 0025 PH Building Fasteners 90 4 Standoff 1" Standoff Round Threaded 2031 Keystone Electronics 91 18 Shunt Shunt 0.1" SP 151-8000-E Kobiconn 92 36 R205, R206, R217, R218, R351, DNI R352, R197, R198, R19, R20, R21, R25, R26, R27, R28, R29, R30, R361, R362, R363, R367, R368, R369, R385, R386, R387, R388, R390, R391, R394, R395, R396, R199, R200, R213, R214 93 2 Q31, Q32 DNI TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM FPGA Daughterboard Layout www.ti.com 15 TLK10002EVM FPGA Daughterboard Layout 1 TLK10002 EVM FPGA DAUGHTER BOARD REV NA 6522851 JN Figure 54. Top Signal, Layer 1 SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 73 TLK10002EVM FPGA Daughterboard Layout www.ti.com 2 Figure 55. Internal Ground, Layer 2 74 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM FPGA Daughterboard Layout www.ti.com 3 Figure 56. Internal Signal, Layer 3 SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 75 TLK10002EVM FPGA Daughterboard Layout www.ti.com 4 Figure 57. Internal Ground, Layers 4, 6, 7, 9, 11, and 13 76 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM FPGA Daughterboard Layout www.ti.com 5 3P3V VCCINT_1P2V VCCMGT_1P2V Figure 58. Internal Power, Layer 5 SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 77 TLK10002EVM FPGA Daughterboard Layout www.ti.com 8 VCCO_1P8V 2P5V Figure 59. Internal Power, Layer 8 78 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM FPGA Daughterboard Layout www.ti.com 10 5V VCCAUX_2P5V VCCCLK_3P3V Figure 60. Internal Power, Layer 10 SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 79 TLK10002EVM FPGA Daughterboard Layout www.ti.com 12 Figure 61. Internal Signal, Layer 12 80 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM FPGA Daughterboard Layout www.ti.com 14 Figure 62. Bottom Signal, Layer 14, Top View SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 81 TLK10002EVM FPGA Daughterboard Layout www.ti.com Table 4. TLK10002EVM FPGA Daughterboard Layer Construction SUBCLASS NAME TOP L2_GND L3_SIG2 L4_GND L5_PWR L6_GND L7_GND L8_PWR L9_GND L10_PWR L11_GND L12_SIG3 L13_GND BOTTOM (1) 82 TYPE MATERIAL THICKNESS (MIL) DIELECTRIC CONSTANT LOSS TANGENT 1 WIDTH (MIL) SURFACE AIR CONDUCTOR COPPER DIELECTRIC FR-4 PLANE COPPER DIELECTRIC FR-4 CONDUCTOR COPPER DIELECTRIC FR-4 PLANE COPPER DIELECTRIC FR-4 CONDUCTOR COPPER DIELECTRIC FR-4 PLANE COPPER DIELECTRIC FR-4 PLANE COPPER DIELECTRIC PLANE DIELECTRIC FR-4 PLANE COPPER DIELECTRIC FR-4 PLANE COPPER DIELECTRIC FR-4 PLANE COPPER 1.2 1 0 DIELECTRIC FR-4 10 4.1 0.035 CONDUCTOR COPPER 1.2 1 0 DIELECTRIC FR-4 0.035 PLANE COPPER DIELECTRIC FR-4 CONDUCTOR COPPER SURFACE AIR COUPLING TYPE/SPACING (MIL) IMPEDANCE (Ω) (1) 0 1.96 4.1 0 5 4.1 0.035 1.2 1 0 5 4.1 0.035 1.2 1 0 10 4.1 0.035 1.2 1 0 0.035 5 4.1 1.2 1 0 5 4.1 0.035 1.2 1 0 5 4.1 0.035 1.2 1 0 FR-4 10 4.1 0.035 COPPER 1.2 1 0 5 4.1 0.035 1.2 1 0 0.035 5 4.1 1.2 1 0 5 4.1 0.035 5 4.1 1.2 1 0 5 4.1 0.035 1.96 1 0 6.00 Edge/5.00 97.298 5.00 NONE/NONE 49.7 5.0 NONE/NONE 49.7 9.50 NONE/NONE 48.425 The Impedance is set to be slightly less than 50 Ω or 100 Ω on the traces in order to compensate for slight over-etching during the manufacturing process. The end impedance after etching should result in a 50 or 100-Ω Impedance. Always consult with your board manufacturer for their process/design requirements to ensure the desired impedance is achieved. TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM SMA Breakout Board Schematics www.ti.com 16 TLK10002EVM SMA Breakout Board Schematics 5 1 2 3 4 RE VIS IONS NOTES : ECR NU M BER ECR DA TE xx/xx/ xx ------- 1. PLACE NET NAMES ON ALL JUMPERS A ND HEADERS . 2. PLACE ALL PA RTS OTHER THAN SMA CONNECTORS ON A 0 OR 90 DE GREE ORI ENTA TION. 3. SERIAL DATA SHOULDB E ROUTED A S 100 OHM DIFFE RENTIA LLY COUPLED ORS INGLE-ENDE D50 OHM TRANS MISS ION LI NE S ON OUTSI DE LAYERS. ROUTING DI STANCE SHOULD BE 5 INCHES OR LESS. ALL OTHER DATA LI NE S SHOULD BE 50 OHM I MPEDIA NCE ON INTERNAL OR EX TERNAL LAYE RS . ROUTE D POWE RS HOULD BE A MINIMUM OF 40 MILS WI DE . 4. USE FR4-370 MA TERI AL FOR ALL LAYERS. D D 5. SERIAL A ND REFCLK NETS MUST MA TCH WITHIN+/- 0.5 MI LS 6. MATCH DIFFERENTIAL TRACE WIDTHS OF SE RI AL AND REFCLK LINES WI TH SMP/ SMA PADS. 7. PLACE TI LOGO, BOARD NAME, J NCOMBO LOGO, AND THE BOARD NUMBER I N TOP SI DE METAL. SCHEMATIC SHEET INDEX: C C SH EET 01 : TL K10 002 EVM SMA BREAKOUT D AUGHTER BOARD COVER SHEET AND N OTES SH EET 02 : CH ANNEL A SIGN ALS SH EET 03 : CH ANNEL B SIGN ALS SH EET 04 : COMMON SIGNAL S B B TEXAS INSTRUMENTS A A SC HEM AT IC TITL E EN GIN EER J. NERGER D ATE TLK10002 EVM SMA BREAKOUT DAUGHTER BOARD 11/ 06/10 PAG E TITL E L AYO UT TLK 10002 DATA SHEET REV ISI ON: 0.7 J. NERGER DATA SHEET LA ST UPDATED ON: 09/ 27/10 RE L EASE D 5 J. NERGER 4 2 3 D ATE 11/ 06/10 D ATE 11/ 06/10 COVERPAGE AND NOTES SIZE DO CU M ENT N UM BE R REV B 6522851 NA SHE ET 1 of 4 1 Figure 63. Cover Page and Index, Sheet 1 of 4 SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 83 TLK10002EVM SMA Breakout Board Schematics www.ti.com 5 4 3 2 1 J2 INB0P SMA SURFACE J3 INB0N SMA SURFACE J4 D D OUTB0N SMA SURFACE J1B C J1A B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 J5 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 OUTB0P INB0P SMA SURFACE J6 INB0N INB1P SMA SURFACE OUTB0N OUTB0P J7 INB1N INB1P SMA SURFACE J8 INB1N OUTB1N SMA SURFACE OUTB1N OUTB1P J9 OUTB1P OUTB2N SMA SURFACE C OUTB2P INB2P INB2N J12 OUTB3N OUTB2N OUTB3P SMA SURFACE INB3P J13 INB3N OUTB2P SMA SURFACE CHB_CLKOUTP J10 CHB_CLKOUTN INB2P JMP1 LS_OK_IN_B LS_OK_OUT_B 1 3 SMA SURFACE 2 4 J11 Header 2x2 INB2N SMA SURFACE B SEAM_ASP-134488-01 SEAM_ASP-134488-01 B J16 OUTB3N SMA SURFACE J17 OUTB3P SMA SURFACE J14 INB3P SMA SURFACE J15 INB3N SMA SURFACE J18 A A CHB_CLKOUTP SMA SURFACE TEXAS INSTRUMENTS J19 CHB_CLKOUTN SMA SURFACE PAGE TITLE CHANNEL A SIGNALS 5 4 3 2 SIZE DOCUMENT NUMBER REV B 6522851 NA PAGE 2 of 4 1 Figure 64. Channel-A Signals, Sheet 2 of 4 84 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM SMA Breakout Board Schematics www.ti.com 5 4 3 2 1 J20 INA3N SMA SURFACE J21 INA3P SMA SURFACE J22 D D OUTA3P SMA SURFACE J1J C J1K J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J33 J34 J35 J36 J37 J38 J39 J40 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J33 J34 J35 J36 J37 J38 J39 J40 J23 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K40 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K40 OUTA3N INB0P SMA SURFACE J24 INB0N INA2N SMA SURFACE OUTB0N OUTB0P J25 INA2P INB1P SMA SURFACE J26 INB1N OUTA2P SMA SURFACE OUTB1N OUTB1P J27 OUTA2N OUTB2N SMA SURFACE C OUTB2P INB2P INB2N J30 OUTB3N OUTA1P OUTB3P SMA SURFACE INB3P J31 INB3N OUTA1N SMA SURFACE CHB_CLKOUTP J28 CHB_CLKOUTN INA1N JMP2 LS_OK_IN_A LS_OK_OUT_A 1 3 SMA SURFACE 2 4 J29 Header 2x2 INA1P SMA SURFACE B SEAM_ASP-134488-01 SEAM_ASP-134488-01 B J34 OUTA0P SMA SURFACE J35 OUTA0N SMA SURFACE J32 INA0N SMA SURFACE J33 INA0P SMA SURFACE J36 A A CHA_CLKOUTP SMA SURFACE TEXAS INSTRUMENTS J37 CHA_CLKOUTN PAGE TITLE SMA SURFACE CHANNEL B SIGNALS 5 4 3 2 SIZE DOCUMENT NUMBER REV B 6522851 NA PAGE 3 of 4 1 Figure 65. Channel-B Signals, Sheet 3 of 4 SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 85 TLK10002EVM SMA Breakout Board Schematics 5 www.ti.com 4 3 2 1 D D J1D C B J1H D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 J1F H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40 SEAM_ASP-134488-01 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40 SEAM_ASP-134488-01 JMP3 J1E F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 E36 E37 E38 E39 E40 SEAM_ASP-134488-01 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 E36 E37 E38 E39 E40 MDIO_POST_LS 1 3 Header 2x2 SEAM_ASP-134488-01 JMP4 J1C 2 4 MDC_POST_LS C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 JMP5 J1G 1 3 MDIO_PRE_LS 2 4 MDC_PRE_LS Header 2x2 SEAM_ASP-134488-01 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 I2C_SCL 1 3 2 4 I2C_SDA Header 2x2 C B SEAM_ASP-134488-01 J1I MOUNT1 MOUNT2 MOUNT3 MOUNT4 I1 I2 I3 I4 A A SEAM_ASP-134488-01 TEXAS INSTRUMENTS PAGE TITLE COMMON CONTROL SIGNALS 5 4 3 2 SIZE DOCUMENT NUMBER REV B 6522851 NA PAGE 4 of 4 1 Figure 66. Common Signals, Sheet 4 of 4 86 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM SMA Breakout Board Schematics www.ti.com Table 5. TLK10002EVM SMA Breakout Board Bill of Materials Item Qty Reference Value Part Part_Number Manufacturer 1 1 J1 Board to Board Connector SMT ASP-134488-01 Samtec 2 5 JMP1, JMP2, JMP3, JMP4, JMP5 2X2 0.1x0.1" HTSW-150-08-G-D Samtec 3 36 J2, J3, J4, J5, J6, J7, J8, J9, J10, J11, J12, J13, J14, J15, J16, J17, J18, J19, J20, J21, J22, J23, J24, J25, J26, J27, J28, J29, J30, J31, J32, J33, J34, J35, J36, J37 Surface Mount SMA T/H_SMT SMA 32K141-40ML5 Rosenberger 4 4 Screws 4-40/0.25"- Screws Philips PMSSS 440 0025 PH Building Fasteners 5 4 Standoff 1" Standoff Round Threaded 2031 Keystone Electronics 6 2 Shunt Shunt 0.1" SP 151-8000-E Kobiconn SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 87 TLK10002EVM SMA Breakout Board Layout 17 www.ti.com TLK10002EVM SMA Breakout Board Layout JN TLK10002 EVM SMA BREAKOUT DAUGHTER BOARD REV NA 6522852 Figure 67. Top Signal, Layer 1 88 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM SMA Breakout Board Layout www.ti.com Figure 68. Internal Ground, Layer 2 SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 89 TLK10002EVM SMA Breakout Board Layout www.ti.com Figure 69. Internal GND, Layers 3, 4, and 5 90 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback TLK10002EVM SMA Breakout Board Layout www.ti.com Figure 70. Bottom Signal, Layer 6 SLLU148 – May 2011 Submit Documentation Feedback TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated 91 TLK10002EVM SMA Breakout Board Layout www.ti.com Table 6. TLK10002EVM SMA Breakout Board Layer Construction SUBCLASS NAME TOP L2_GND1 L3_GND2 L4_GND3 L13_GND4 BOTTOM (1) 92 TYPE MATERIAL THICKNESS (MIL) DIELECTRIC CONSTANT LOSS TANGENT 1 WIDTH (MIL) SURFACE AIR CONDUCTOR COPPER DIELECTRIC FR-4 PLANE COPPER DIELECTRIC FR-4 PLANE COPPER DIELECTRIC FR-4 PLANE COPPER 1.2 1 0 DIELECTRIC FR-4 20 4.1 0.035 PLANE COPPER 1.2 1 0 DIELECTRIC FR-4 5 4.1 0.035 CONDUCTOR COPPER 1.96 1 0 SURFACE AIR COUPLING TYPE/SPACING (MIL) IMPEDANCE (Ω) (1) 0 1.96 4.1 0 5 4.1 0.035 1.2 1 0 5 4.1 0.035 1.2 1 0 4 4.1 0.035 6.00 Edge/5.00 97.298 9.50 NONE/NONE 48.425 The Impedance is set to be slightly less than 50 Ω or 100 Ω on the traces in order to compensate for slight over-etching during the manufacturing process. The end impedance after etching should result in a 50 or 100-Ω Impedance. Always consult with your board manufacturer for their process/design requirements to ensure the desired impedance is achieved. TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module Copyright © 2011, Texas Instruments Incorporated SLLU148 – May 2011 Submit Documentation Feedback Evaluation Board/Kit Important Notice Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards. 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