TLK10232CTR

TLK10232 www.ti.com SLLSEE1 – MAY 2013 DUAL-CHANNEL XAUI/10GBASE-KR TRANSCEIVER WITH CROSSPOINT Check for Samples: TLK10232 1 Introduction 1.1 Features 1 • Dual Channel Multi-Rate Transceiver • Supports 10GBASE-KR, XAUI, and 1GBASE-KX Ethernet Standards • Supports all CPRI and OBSAI Data Rates up to 10 Gbps • Supports Multi-Rate SERDES Operation with up to 10.3125 Gbps Data Rate on the High Speed Side and up to 5 Gbps on the Low Speed Side • Differential CML I/Os on Both High Speed and Low Speed Sides • Interface to Backplanes, Passive and Active Copper Cables, or SFP+ Optical Modules • Selectable Reference Clock per Channel with Multiple Output Clock Options • Integrated Crosspoint Switch Allows for Flexible Signal Routing and Redundant Outputs • Supports Data Retime Operation • Supports PRBS, CRPAT, CJPAT, High/Low/Mixed-Frequency Patterns, and KR Pseudo-Random Pattern Generation and Verification, Square-Wave Generation • Two Power Supplies: 1.0V (Core), and 1.5 or 1.8V (I/O) 1.2 • • Applications 10GBASE-KR Compliant Backplane Links 10 Gigabit Ethernet Switch, Router, and Network Interface Cards • No Power Supply Sequencing Requirements • Transmit De-emphasis and Receive Adaptive Equalization to Allow Extended Backplane/Cable Reach on Both High Speed and Low Speed Sides • Loss of Signal (LOS) Detection • Supports 10G-KR Link Training, Forward Error Correction, Auto-Negotiation • Jumbo Packet Support • JTAG; IEEE 1149.1 Test Interface • Industry Standard MDIO Control Interface • 65nm Advanced CMOS Technology • Industrial Ambient Operating Temperature (–40°C to 85°C) • Power Consumption: 800mW per Channel (Nominal) • Device Package: 13mm x 13mm, 144-pin PBGA, 1-mm Ball-Pitch • • spacing Proprietary Cable/Backplane Links High-Speed Point-to-Point Transmission Systems TLK10232 MAC XGXS XGXS 10 GBASE- KR CHANNEL A 10 GBASE- KR CHANNEL B XAUI CHANNEL B BACKPLANE XAUI CHANNEL A MDC MDIO 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated TLK10232 SLLSEE1 – MAY 2013 1.3 www.ti.com Description The TLK10232 is a dual-channel multi-rate transceiver intended for use in high-speed bi-directional pointto-point data transmission systems. This device supports three primary modes. It can be used as a XAUI to 10GBASE-KR transceiver, as a general-purpose 8b/10b multi-rate 4:1, 2:1, or 1:1 serializer/deserializer, or can be used in 1G-KX mode. While operating in the 10GBASE-KR mode, the TLK10232 performs serialization of the 8B/10B encoded XAUI data stream presented on its low speed (LS) side data inputs. The serialized 8B/10B encoded data is presented on the high speed (HS) side outputs in 64B/66B encoding format. Likewise, the TLK10232 performs deserialization of 64B/66B encoded data streams presented on its high speed side data inputs. The deserialized 64B/66B data is presented in XAUI 8B/10B format on the low speed side outputs. Link Training is supported in this mode as well as Forward Error Correction (FEC) for extended length applications. While operating in the General Purpose SERDES mode, the TLK10232 performs 2:1 and 4:1 serialization of the 8B/10B encoded data streams presented on its low speed (LS) side data inputs. The serialized 8B/10B encoded data is presented on the high speed (HS) side outputs. Likewise, the TLK10232 performs 1:2 and 1:4 deserialization of 8B/10B encoded data streams presented on its high speed side data inputs. The deserialized 8B/10B encoded data is presented on the low speed side outputs. Depending on the serialization/deserialization ratio, the low speed side data rate can range from 0.5 Gbps to 5 Gbps and the high speed side data rate can range from 1 Gbps to 10 Gbps. 1:1 retime mode is also supported but limited to 1 Gbps to 5 Gbps rates. The TLK10232 also supports 1G-KX (1.25 Gbps) mode with PCS (CTC) capabilities. This mode can be enabled via software provisioning or via auto negotiation. If software provisioning is used, data rates up to 3.125 Gbps are supported. The TLK10232 features a built-in crosspoint switch, allowing for redundant outputs and easy re-routing of data. Each output port (either high speed or low speed) can be configured to output data coming from any of the device’s input ports. The switching can be initiated through either a hardware pin or through software control, and can be configured to occur either immediately or after the end of the current packet. This allows for switching between data sources without packet corruption. Both low speed and high speed side data inputs and outputs are of differential current mode logic (CML) type with integrated termination resistors. The TLK10232 provides flexible clocking schemes to support various operations. They include the support for clocking with an externally-jitter-cleaned clock recovered from the high speed side. The device is also capable of performing clock tolerance compensation (CTC) in 10GBASE-KR and 1GBASE-KX modes, allowing for asynchronous clocking. The TLK10232 provides low speed side and high speed side loopback modes for self-test and system diagnostic purposes. The TLK10232 has built-in pattern generators and verifiers to help in system tests. The device supports generation and verification of various PRBS, High-/Low-/Mixed-Frequency, CRPAT long/short, CJPAT, and KR pseudo-random test patterns and square wave generation. The types of patterns supported on the low speed and high speed side are dependent on the operational mode chosen. The TLK10232 has an integrated loss of signal (LOS) detection function on both high speed and low speed sides. LOS is asserted in conditions where the input differential voltage swing is less than the LOS assert threshold. Both TLK10232 channels are fully independent. They can be operated with different reference clocks, at different data rates, and with different serialization/deserialization ratios. 2 Introduction Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 TLK10232 www.ti.com SLLSEE1 – MAY 2013 The low speed side of the TLK10232 is ideal for interfacing with an FPGA, ASIC, MAC, or network processor capable of handling lower-rate serial data streams. The high speed side is ideal for interfacing with remote systems through optical fibers, electrical cables, or backplane interfaces. The TLK10232 supports operation with SFP and SFP+ optical modules, as well as 10GBASE-KR compatible backplane systems. Introduction Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 3 TLK10232 SLLSEE1 – MAY 2013 www.ti.com 2 Physical Characteristics 2.1 Block Diagram Various interfaces of the TLK10232 device are shown in Figure 2-1 for Channel A. The implementation is the same for Channel B. A simplified one-channel block diagram of both the transmit and recive data path is shown in Figure 2-2. This low-power transceiver consists of two serializer/deserializer (SERDES) blocks, one on the low speed side and the other on the high speed side. The core logic block that lies between the two SERDES blocks carries out all the logic functions including channel synchronization, lane alignment, 8B/10B and 64B/66B encoding/decoding, as well as test pattern generation and verification. The TLK10232 provides a management data input/output (MDIO Clause 22/45) interface as well as a JTAG interface for device configuration, control, and monitoring. Detailed description of the TLK10232 pin functions is provided in Table 2-1. INA0P/N INA1P/N INA2P/N High Speed Outputs Low Speed Inputs HSTXAP/N INA3P/N DATA PATH (Channel A) High Speed Inputs OUTA0P/N OUTA1P/N OUTA2P/N Low Speed Outputs HSRXAP/N OUTA3P/N REFCLK0P/N CLOCKS CLKOUTAP/N REFCLK1P/N REFCLK_SEL LOSA PRTAD[4:0] LS_OK_IN_A MDC LS_OK_OUT_A MDIO MDIO PDTRX_N RESET_N CONTROL, STATUS, TEST ST MODE_SEL JTAG TESTEN TDO TMS PRBSEN TRST_N PRBS_PASS TCK GPI0 TDI Figure 2-1. TLK10232 Interfaces 4 Physical Characteristics Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 TLK10232 www.ti.com SLLSEE1 – MAY 2013 Figure 2-2. A Simplified One Channel Block Diagram of the TLK10232 Data Paths 2.2 Package A 13-mm x 13-mm, 144-pin PBGA package with a ball pitch of 1 mm is used. The device pin-out is as shown in Figure 2-3 and is described in detail in Table 2-1 and Table 2-2. 1 2 3 4 5 6 7 8 9 10 11 12 A INA1P VSS INA0N INA0P VSS OUTA0P OUTA0N PDTRXA_N CLKOUTBP CLKOUTBN VSS HSRXAN HSRXAP B INA1N INA2P VSS VSS OUTA1P OUTA1N VSS TM S PRBSEN LS_OK_IN_A VSS C VSS INA2N VDDRA_LS OUTA2P OUTA2N VSS VDDO0 TDI CLKOUTAP CLKOUTAN AM UXA VSS D INA3P VDDA_LS VSS AM UXB VSS TDO VPP TCK LS_OK_OUT_A VSS VSS HSTXAP E INA3N VSS OUTA3N VSS TRST_N VDDD DVDD VDDD LOSA PRTAD0 VDDRA_HS HSTXAN F VSS VDDA_LS OUTA3P VDDT_LS VSS VDDD DVDD VSS VDDT_HS VSS VDDA_HS VSS G VSS VDDA_LS VSS VDDT_LS VSS DVDD VSS DVDD PRTAD1 VDDA_HS VSS HSRXBN H INB0P VSS OUTB0N VSS RESET_N VDDD DVDD VDDD LS_OK_OUT_B M ODE_SEL VSS HSRXBP J INB0N VDDA_LS OUTB0P PDTRXB_N VSS PRTAD3 M DIO M DC PRBS_PASS GPI0 VDDRB_HS VSS K VSS INB1P VDDRB_LS OUTB1N OUTB1P VSS VDDO1 LOSB REFCLK1P REFCLK1N VSS HSTXBP L INB2P INB1N VSS VSS OUTB2N OUTB2P VSS LS_OK_IN_B PRTAD2 TESTEN VSS HSTXBN M INB2N VSS INB3P INB3N VSS OUTB3N OUTB3P PRTAD4 ST REFCLK0P REFCLK0N VSS Figure 2-3. The Pin-Out of the TLK10232 Physical Characteristics Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 5 TLK10232 SLLSEE1 – MAY 2013 2.3 www.ti.com Terminal Functions The details of the terminal functions of the TLK10232 are provided in Table 2-1 and Table 2-2. Table 2-1. Pin Description - Signal Pins TERMINAL BGA DIRECTION TYPE SUPPLY DESCRIPTION HSTXAP HSTXAN D12 E12 Output CML VDDA_HS High Speed Transmit Channel A Output. HSTXAP and HSTXAN comprise the high speed side transmit direction Channel A differential serial output signal. During device reset (RESET_N asserted low) these pins are driven differential zero. These CML outputs must be AC coupled. HSRXAP HSRXAN B12 A12 Input CML VDDA_HS High Speed Receive Channel A Input. HSRXAP and HSRXAN comprise the high speed side receive direction Channel A differential serial input signal. These CML input signals must be AC coupled. INA[3:0]P/N D1/E1 B2/C2 A1/B1 A4/A3 Input CML VDDA_LS Low Speed Channel A Inputs. INAP and INAN comprise the low speed side transmit direction Channel A differential input signals. These signals must be AC coupled. OUTA[3:0]P/N F3/E3 C4/C5 B5/B6 A6/A7 Output CML VDDA_LS Low Speed Channel A Outputs. OUTAP and OUTAN comprise the low speed side receive direction Channel A differential output signals. During device reset (RESET_N asserted low) these pins are driven differential zero. These signals must be AC coupled. SIGNAL CHANNEL A LOSA E9 Output LVCMOS 1.5V/1.8V VDDO0 40Ω Driver Channel A Receive Loss Of Signal (LOS) Indicator. LOSA=0: Signal detected. LOSA=1: Loss of signal. Loss of signal detection is based on the input signal level. When HSRXAP/N has a differential input signal swing of ≤75 mVpp, LOSA will be asserted (if enabled). If the input signal is greater than 150 mVp-p, LOS will be deasserted. Outside of these ranges, the LOS indication is undefined. Other functions can be observed on LOSA real-time, configured via MDIO During device reset (RESET_N asserted low) this pin is driven low. During pin based power down (PDTRXA_N asserted low), this pin is floating. During register based power down, this pin is floating. It is highly recommended that LOSA be brought to an easily accessible point on the application board (header) in the event that debug is required. B10 Input LVCMOS 1.5V/1.8V VDDO0 Channel A Receive Lane Alignment Status Indicator. Lane alignment status signal received from a Lane Alignment Slave on the link partner device. Valid in 10G General Purpose Serdes Mode. LS_OK_IN_A=0: Channel A link partner receive lanes not aligned. LS_OK_IN_A=1: Channel A link partner receive lanes aligned LS_OK_OUT_A D9 Output LVCMOS 1.5V/1.8V VDDO0 40Ω Driver Channel A Transmit Lane Alignment Status Indicator. Lane alignment status signal sent to a Lane Alignment Master on the link partner device. Valid in 10G General Purpose Serdes Mode. LS_OK_OUT_A=0: Channel A link partner transmit lanes not aligned. LS_OK_OUT_A=1: Channel A link partner transmit lanes aligned. PDTRXA_N A8 Input LVCMOS 1.5V/1.8V VDDO0 Transceiver Power Down. When this pin is held low (asserted), Channel A is placed in power down mode. When deasserted, Channel A operates normally. After deassertion, a software data path reset should be issued through the MDIO interface. HSTXBP HSTXBN K12 L12 Output CML VDDA_HS High Speed Transmit Channel B Output. HSTXBP and HSTXBN comprise the high speed side transmit direction Channel B differential serial output signal. During device reset (RESET_N asserted low) these pins are driven differential zero. These CML outputs must be AC coupled. HSRXBP HSRXBN H12 G12 Input CML VDDA_HS High Speed Receive Channel B Input. HSRXBP and HSRXBN comprise the high speed side receive direction Channel B differential serial input signal. These CML input signals must be AC coupled. INB[3:0]P/N M3/M4 L1/M1 K2/L2 H1/J1 Input CML VDDA_LS Low Speed Channel B Inputs. INBP and INBN comprise the low speed side transmit direction Channel B differential input signals. These signals must be AC coupled. OUTB[3:0]P/N M7/M6 L6/L5 K5/K4 J3/H3 Output CML VDDA_LS LS_OK_IN_A CHANNEL B 6 Low Speed Channel B Outputs. OUTBP and OUTBN comprise the low speed side receive direction Channel B differential output signals. During device reset (RESET_N asserted low) these pins are driven differential zero. These signals must be AC coupled. Physical Characteristics Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 TLK10232 www.ti.com SLLSEE1 – MAY 2013 Table 2-1. Pin Description - Signal Pins (continued) TERMINAL SIGNAL LOSB BGA K8 DIRECTION TYPE SUPPLY Output LVCMOS 1.5V/1.8V VDDO1 40Ω Driver DESCRIPTION Channel B Receive Loss Of Signal (LOS) Indicator. LOSB=0: Signal detected. LOSB=1: Loss of signal. Loss of signal detection is based on the input signal level. When HSRXBP/N has a differential input signal swing of ≤75 mVpp, LOSB will be asserted (if enabled). If the input signal is greater than 150 mVp-p, LOS will be deasserted. Outside of these ranges, the LOS indication is undefined. Other functions can be observed on LOSB real-time, configured via MDIO During device reset (RESET_N asserted low) this pin is driven low. During pin based power down (PDTRXB_N asserted low), this pin is floating. During register based power down, this pin is floating. It is highly recommended that LOSB be brought to easily accessible point on the application board (header), in the event that debug is required. L8 Input LVCMOS 1.5V/1.8V VDDO0 Channel B Receive Lane Alignment Status Indicator. Lane alignment status signal received from a Lane Alignment Slave on the link partner device. Valid in 10G General Purpose Serdes Mode. LS_OK_IN_B=0: Channel B Receive lanes not aligned. LS_OK_IN_B=1: Channel B Receive lanes aligned LS_OK_OUT_B H9 Output LVCMOS 1.5V/1.8V VDDO0 40Ω Driver Channel B Transmit Lane Alignment Status Indicator. Lane alignment status signal sent to a Lane Alignment Master on the link partner device. Valid in 10G General Purpose Serdes Mode. LS_OK_OUT_B=0: Channel B Transmit lanes not aligned. LS_OK_OUT_B=1: Channel B Transmit lanes aligned. PDTRXB_N J4 Input LVCMOS 1.5V/1.8V VDDO1 Transceiver Power Down. When this pin is held low (asserted), Channel B is placed in power down mode. When deasserted, Channel B operates normally. After deassertion, a software data path reset should be issued through the MDIO interface. LS_OK_IN_B REFERENCE CLOCKS, OUTPUT CLOCKS, AND CONTROL AND MONITORING SIGNALS REFCLK0P/N M10 M11 Input LVDS/ LVPECL DVDD Reference Clock Input Zero. This differential input is a clock signal used as a reference to channels A or B. The reference clock selection is done through MDIO. This input signal must be AC coupled. If unused, REFCLK0P/N should be pulled down to GND through a shared 100 Ω resistor. REFCLK1P/N K9 K10 Input LVDS/ LVPECL DVDD Reference Clock Input One. This differential input is a clock signal used as a reference to channels A or B. The reference clock selection is done through MDIO. This input signal must be AC coupled. If unused, REFCLK1P/N should be pulled down to GND through a shared 100 Ω resistor. CLKOUTAP/N CLKOUTBP/N Channel A/B Output Clock. By default, these outputs are enabled and output the high speed side Channel A recovered byte clock (high speed line rate divided by 16 or 20). Optionally, they can be configured to output the VCO clock divided by 2. (Note: for full rates, VCO/2 pre-divided clocks will be equivalent to the line rate divided by 8; for subrates, VCO/2 pre-divided clocks will be equivalent to the line rate divided by 4). Output CML DVDD C9/C10 A9/A10 These CML outputs must be AC coupled. During device reset (RESET_N asserted low), pin-based power down (PDTRXA_N and PDTRXB_N asserted low), or register-based power down, these pins are floating. PRBSEN PRBS_PASS B9 J9 Input LVCMOS 1.5V/1.8V VDDO0 Output LVCMOS 1.5V/1.8V VDDO1 40Ω Driver Enable PRBS: When this pin is asserted high, the internal PRBS generator and verifier circuits are enabled on both transmit and receive data paths on high speed and low speed sides of both channels. The PRBS 27-1 pattern is selected by default, and can be changed through MDIO. Receive PRBS Error Free (Pass) Indicator. When PRBS test is enabled (PRBSEN=1): PRBS_PASS=1 indicates that PRBS pattern reception is error free. PRBS_PASS=0 indicates that a PRBS error is detected. The channel, high speed or low speed side, and lane (for low speed side) that this signal refers to is chosen through MDIO. During device reset (RESET_N asserted low) this pin is driven high. During pin based power down (PDTRXA_N and PDTRXB_N asserted low), this pin is floating. During register based power down, this pin is floating. It is highly recommended that PRBS_PASS be brought to easily accessible point on the application board (header), in the event that debug is required. ST MODE_SEL M9 Input LVCMOS 1.5V/1.8V VDDO[1:0] H10 Input LVCMOS 1.5V/1.8V VDDO[1:0] MDIO Select. Used to select Clause 22 (=1) or Clause 45 (=0) operation. Note that selecting clause 22 will impact mode availability. See MODE_SEL. A hard or soft reset must be applied after a change of state occurs on this input signal. Device Operating Mode Select. Used together with ST pin to select device operating mode. See Table 2-3 for details. Physical Characteristics Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 7 TLK10232 SLLSEE1 – MAY 2013 www.ti.com Table 2-1. Pin Description - Signal Pins (continued) TERMINAL SIGNAL BGA DIRECTION TYPE SUPPLY DESCRIPTION MDIO Port Address. Used to select the MDIO port address. PRTAD[4:0] M8 J6 L9 G9 E10 PRTAD[4:1] selects the MDIO port address. The TLK10232 has two different MDIO port addresses. Selecting a unique PRTAD[4:1] per TLK10232 device allows 16 TLK10232 devices per MDIO bus. Each channel can be accessed by setting the appropriate port address field within the serial interface protocol transaction. Input LVCMOS 1.5V/1.8V VDDO[1:0] The TLK10232 will respond if the 4 MSB’s of the port address field on MDIO protocol (PA[4:1]) matches PRTAD[4:1]. If PA[0] = 1’b0, TLK10232 Channel A will respond. If PA[0] = 1’b1, TLK10232 Channel B will respond. PRTAD0 is not needed for port addressing, but can be used as a general purpose input pin to control the switching function or the stopwatch latency measurement. If these functions are not needed, PRTAD0 should be grounded on the application board. RESET_N H5 Input LVCMOS 1.5V/1.8V VDDO01 Low True Device Reset. RESET_N must be held asserted (low logic level) for at least 10us after device power stabilization. MDC J8 Input LVCMOS with Hysteresis 1.5V/1.8V VDDO1 MDIO Clock Input. Clock input for the MDIO interface. Note that an external pullup is generally not required on MDC except if driven by an opendrain/open-collector clock source. MDIO Data I/O. MDIO interface data input/output signal for the MDIO interface. This signal must be externally pulled up to VDDO using a 2kΩ resistor. During device reset (RESET_N asserted low) this pin is floating. During software initiated power down the management interface remains active for control register writes and reads. Certain status bits will not be deterministic as their generating clock source may be disabled as a result of asserting either power down input signal. During pin based power down (PDTRXA_N and PDTRXB_N asserted low), this pin is floating. During register based power down, this pin is driven normally. J7 Input/ Output LVCMOS 1.5V/1.8V VDDO1 25Ω Driver C8 Input LVCMOS 1.5V/1.8V VDDO0 (Internal Pullup) JTAG Input Data. TDI is used to serially shift test data and test instructions into the device during the operation of the test port. In system applications where JTAG is not implemented, this input signal may be left floating. During pin based power down (PDTRXA_N and PDTRXB_N asserted low), this pin is not pulled up. During register based power down, this pin is pulled up normally. D6 Output LVCMOS 1.5V/1.8V VDDO0 50Ω Driver JTAG Output Data. TDO is used to serially shift test data and test instructions out of the device during operation of the test port. When the JTAG port is not in use, TDO is in a high impedance state. During device reset (RESET_N asserted low) this pin is floating. During pin based power down (PDTRXA_N and PDTRXB_N asserted low), this pin is not pulled up. During register based power down, this pin is pulled up normally. TMS B8 Input LVCMOS 1.5V/1.8V VDDO0 (Internal Pullup) JTAG Mode Select. TMS is used to control the state of the internal test-port controller. In system applications where JTAG is not implemented, this input signal can be left unconnected. During pin based power down (PDTRXA_N and PDTRXB_N asserted low), this pin is not pulled up. During register based power down, this pin is pulled up normally. TCK D8 Input LVCMOS with Hysteresis 1.5V/1.8V VDDO0 JTAG Clock. TCK is used to clock state information and test data into and out of the device during boundary scan operation. In system applications where JTAG is not implemented, this input signal should be grounded. MDIO TDI TDO TRST_N E5 Input LVCMOS 1.5V/1.8V VDDO0 (Internal Pulldown) JTAG Test Reset. TRST_N is used to reset the JTAG logic into system operational mode. This input can be left unconnected in the application and is pulled down internally, disabling the JTAG circuitry. If JTAG is implemented on the application board, this signal should be deasserted (high) during JTAG system testing, and otherwise asserted (low) during normal operation mode. During pin based power down (PDTRXA_N and PDTRXB_N asserted low), this pin is not pulled up. During register based power down, this pin is pulled up normally. TESTEN L10 Input LVCMOS 1.5V/1.8V VDDO1 Test Enable. This signal is used during the device manufacturing process. It should be grounded through a resistor in the device application board. The application board should allow the flexibility of easily reworking this signal to a high level if device debug is necessary (by including an uninstalled resistor to VDDO). GPI0 J10 Input LVCMOS 1.5V/1.8V VDDO1 General Purpose Input. This signal is used during the device manufacturing process. It should be grounded through a resistor on the device application board. The application board should also allow the flexibility of easily reworking this signal to a high level if device debug is necessary (by including an uninstalled resistor to VDDO). AMUXA C11 Analog I/O SERDES Channel A Analog Testability I/O. This signal is used during the device manufacturing process. It should be left unconnected in the device application. AMUXB D4 Analog I/O SERDES Channel B Analog Testability I/O. This signal is used during the device manufacturing process. It should be left unconnected in the device application. 8 Physical Characteristics Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 TLK10232 www.ti.com SLLSEE1 – MAY 2013 Table 2-2. Pin Description - Power Pins TERMINAL SIGNAL VDDA_LS/HS BGA D2, F2, G2, J2, G10, F11 TYPE DESCRIPTION Power SERDES Analog Power. VDDA_LS and VDDA_HS provide supply voltage for the analog circuits on the low-speed and high-speed sides respectively. 1.0V nominal. Can be tied together on the application board. VDDT_LS/HS F4, G4, F9 Power SERDES Analog Power. VDDT_LS and VDDT_HS provide termination and supply voltage for the analog circuits on the low-speed and high-speed sides respectively. 1.0V nominal. Can be tied together on the application board. VDDD E6, F6, H6, E8, H8 Power SERDES Digital Power. VDDD provides supply voltage for the digital circuits internal to the SERDES. 1.0V nominal. DVDD G6, E7, F7, H7, G8 Power Digital Core Power. DVDD provides supply voltage to the digital core. 1.0V nominal. VDDRA_LS/HS C3 E11 Power SERDES Analog Regulator Power. VDDRA_LS and VDDRA_HS provide supply voltage for the internal PLL regulator for Channel A low speed and high speed sides respectively. 1.5V or 1.8V nominal. VDDRB_LS/HS K3 J11 Power SERDES Analog Regulator Power VDDRB_LS and VDDRB_HS provide supply voltage for the internal PLL regulator for Channel B low speed and high speed sides respectively. 1.5V or 1.8V nominal. VDDO[1:0] K7 C7 Power LVCMOS I/O Power. VDDO0 and VDDO1 provide supply voltage for the LVCMOS inputs and outputs. 1.5V or 1.8V nominal. Can be tied together on the application board. VPP D7 Power Factory Program Voltage. Used during device manufacturing. The application must connect this power supply directly to DVDD. VSS A2, A5, A11, B3, B4, B7, B11, C1, C6, C12, D3, D5, D10, D11, E2, E4, F1, F5, F8, F10, F12, G1, G3, G5, G7, G11, H2, H4, H11, J5, J12, K1, K6, K11, L3, L4, L7, L11, M2, M5, M12 Ground Ground. Common analog and digital ground. 2.4 Operating Modes The TLK10232 is a versatile high-speed transceiver device that is designed to perform various physical layer functions in three operating modes: 10GBASE-KR Mode, 1G-KX Mode, and General Purpose (10G) SERDES Mode. The three modes are described in three separate sections. The device operating mode is determined by the MODE_SEL and ST pin settings, as well as MDIO register 1E.0001 bit 10. Table 2-3. TLK10232 Operating Mode Selection ST = 0 (Clause 45) ST = 1 (Clause 22) 10G 10G {MODE_SEL pin, Register 1E.0001 bit 10} 1x 01 10G 10G 00 10G-KR/1G-KX (Determined by Auto Neg) 1G-KX (No Auto Neg) Physical Characteristics Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 9 TLK10232 SLLSEE1 – MAY 2013 www.ti.com 3 10GBASE-KR MODE FUNCTIONAL DESCRIPTION OUTx3P OUTx3N Training HSTXxP HSTXxN Auto-Neg Gearbox Serializer TX FEC Scrambler 64b/66b Encoder TX CTC Data Switch 8b/10b Decoder Deserializer Training Arbitration Gearbox RX FEC 64b/66b Decoder Data Switch RX CTC HSRXxP HSRXxN Auto-Neg 8b/10b Decoder 8b/10b Decoder XAUI Lane Alignment 8b/10b Encoder 8b/10b Encoder Channel Sync Channel Sync Channel Sync Channel Sync 8b/10b Decoder Descrambler OUTx2N 8b/10b Encoder OUTx2P 8b/10b Encoder OUTx1N XAUI Code Gen OUTx1P Serializer OUTx0P OUTx0N Serializer INx3P INx3N Serializer INx2N Serializer INx2P Deserializer INx1N Deserializer INx1P Deserializer INx0P INx0N Deserializer A simplified block diagram of the transmit and receive data paths in 10GBASE-KR mode is shown in Figure 3-1. This section gives a high-level overview of how data moves through these paths, then gives a more detailed description of each block’s functionality. Figure 3-1. A Simplified One Channel KR Data Path Block Diagram 3.1 10GBASE-KR Transmit Data Path Overview In 10GBASE-KR Mode, the TLK10232 takes in XAUI data on the four low speed input lanes. The serial data in each lane is deserialized into 10-bit parallel data, then byte aligned (channel synchronized) based on comma detection. The four XAUI lanes are then aligned with one another, and the aligned data is input to four 8B/10B decoders. The decoded data is then input to the transmit clock tolerance compensation (CTC) block which compensates for any frequency offsets between the incoming XAUI data and the local reference clock. The CTC block then delivers the data to a 64B/66B encoder and a scrambler. The resulting scrambled 10GBASE-KR data is then input to a transmit gearbox which in turn delivers it to the high speed side SERDES for serialization and output through the HSTX*P/N pins. 10 10GBASE-KR MODE FUNCTIONAL DESCRIPTION Submit Documentation Feedback Product Folder Links: TLK10232 Copyright © 2013, Texas Instruments Incorporated TLK10232 www.ti.com 3.2 SLLSEE1 – MAY 2013 10GBASE-KR Receive Data Path Overview In the receive direction, the TLK10232 will take in 64B/66B-encoded serial 10GBASE-KR data on the HSRX*P/N pins. This data is deserialized by a high speed SERDES, then input to a receive gearbox. After the gearbox, the data is aligned to 66-bit frames, descrambled, 64B/66B decoded, and then input to the receive CTC block. After CTC, the data is encoded by four 8B/10B encoders, and the resulting four 10-bit parallel words are serialized by the low speed SERDES blocks. The four serial XAUI output lanes are transmitted out the OUT*P/N pins. 3.3 Channel Synchronization Block When parallel data is clocked into a parallel-to-serial converter, the byte boundary that was associated with the parallel data is lost in the serialization of the data. When the serial data is received and converted to parallel format again, a method is needed to be able to recognize the byte boundary again. Generally, this is accomplished through the use of a synchronization pattern. This is a unique pattern of 1’s and 0’s that either cannot occur as part of valid data or is a pattern that repeats at defined intervals. 8B/10B encoding contains a character called the comma (b’0011111’ or b’1100000’) which is used by the comma detect circuit to align the received serial data back to its original byte boundary. The TLK10232 channel synchronization block detects the comma pattern found in the K28.5 character, generating a synchronization signal aligning the data to their 10-bit boundaries for decoding. It is important to note that the comma can be either a (b’0011111’) or the inverse (b’1100000’) depending on the running disparity. The TLK10232 decoder will detect both patterns. The TLK10232 performs channel synchronization per lane as shown in the flowchart of Figure 3-2. Copyright © 2013, Texas Instruments Incorporated 10GBASE-KR MODE FUNCTIONAL DESCRIPTION Submit Documentation Feedback Product Folder Links: TLK10232 11 TLK10232 SLLSEE1 – MAY 2013 www.ti.com Reset | LOS(Loss of Signal) Loss Of Sync (Enable Alignment) Sync Status Not Ok No Comma Comma Comma Detect 1 (Disable Alignment) !Comma & !Invalid Decode Invalid Decode Comma Comma Detect 2 !Comma & !Invalid Decode Invalid Decode Comma Comma Detect 3 !Comma & !Invalid Decode Invalid Decode Note: If HS_CH_SYNC_HYSTERESIS[1:0] is equal to 2'b00), machine operates as drawn. If HS_CH_SYNC_HYSTERESIS[1:0] is equal to 2'b01/2'b10/2'b11, then a transition from all Sync Acquired states occurs immediately upon detection of 1, 2, or 3 adjacent invalid code words or disparity errors respectively. Comma A Sync Acquired 1 (Sync Status Ok) B Invalid Decode Sync Acquired 2 (good cgs = 0) C Invalid Decode Sync Acquired 3 (good cgs = 0) Invalid Decode Sync Acquired 4 (good cgs = 0) Invalid Decode Sync Acquired 2A good cgs++ !Invalid Decode Invalid Decode Sync Acquired 3A good cgs++ !Invalid Decode Invalid Decode !invalid Decode & good_cgs=3 B Sync Acquired 4A good cgs++ !Invalid Decode Invalid Decode !invalid Decode & good_cgs=3 A C !invalid Decode & good_cgs=3 !Invalid Decode & good_cgs !=3 !Invalid Decode & good_cgs !=3 !Invalid Decode & good_cgs !=3 Figure 3-2. Channel Synchronization Flowchart 12 10GBASE-KR MODE FUNCTIONAL DESCRIPTION Submit Documentation Feedback Product Folder Links: TLK10232 Copyright © 2013, Texas Instruments Incorporated TLK10232 www.ti.com 3.4 SLLSEE1 – MAY 2013 8B/10B Encoder Embedded-clock serial interfaces require a method of encoding to ensure sufficient transition density for the receiving CDR to acquire and maintain lock. The encoding scheme also maintains the signal DC balance by keeping the number of ones and zeros balanced which allows for AC coupled data transmission. The TLK10232 uses the 8B/10B encoding algorithm that is used by the 10 Gbps and 1 Gbps Ethernet and Fibre Channel standards. This provides good transition density for clock recovery and improves error checking. The 8B/10B encoder converts each 8-bit wide data to a 10-bit wide encoded data character to improve its transition density. This transmission code includes /D/ characters, used for transmitting data, and /K/ characters, used for transmitting protocol information. Each /K/ or /D/ character code word can also have both a positive and a negative disparity version. The disparity of a code word is selected by the encoder to balance the running disparity of the serialized data stream. 3.5 8B/10B Decoder Once the Channel Synchronization block has identified the byte boundaries from the received serial data stream, the 8B/10B decoder converts 10-bit 8B/10B-encoded characters into their respective 8-bit formats. When a code word error or running disparity error is detected in the decoded data, the error is reported in the status register (1E.000F) and the LOS pin is asserted (depending on the LOS overlay selection). 3.6 64B/66B Encoder/Scrambler To facilitate the transmission of data received from the media access control (MAC) layer, the TLK10232 encodes data received from the MAC using the 64B/66B encoding algorithm defined in the IEEE802.32008 standard. The TLK10232 takes two consecutive transfers from the XAUI interface and encodes them into a 66-bit code word. The information from the two XAUI transfers includes 64 bits of data and 8 bits of control information after 8B/10B decoding. If the 64B/66B encoder detects an invalid packet format from the XAUI interface, it replaces erroneous information with appropriately-encoded error information. The resulting 66-bit code word is then sent on to the transmit gearbox. The encoding process implemented in the TLK10232 includes two steps: 1. an encoding step, which converts the 72 bits of data (8 data bytes plus 8 control-code indicators) received from the transmit CTC FIFO into a 66-bit code word 2. a scrambling step, which scrambles 64 bits of encoded data using the scrambler polynomial x58+x39+1. The 66 bits created by the encoder consists of 64 bits of data and a 2-bit synchronization field consisting of either 01 or 10. Only the 64 bits of data are scrambled, leaving the two synchronization bits unmodified. The two synchronization bits allow the receive gearbox to obtain frame alignment and, in addition, ensure an edge transition of at least once in 66 bits of data. The encoding process allows a limited amount of control information to be sent in-line with the data. 3.7 Forward Error Correction Optionally enabled, Forward Error Correction (FEC) follows the IEEE 802.3-2008 standard, and is able to correct a burst errors up to 11 bits. In the TX data path, the FEC logic resides between the scrambler and gearbox. In the RX datapath, FEC resides between the gearbox and descrambler. Frame alignment is handled inside the RX FEC block during FEC operation, and the RX gearbox sync header alignment is bypassed. Because latency is increased in both the TX and RX data paths with FEC enabled, it is disabled by default and must be enabled through MDIO programming. Note that FEC by nature will add latency due to frame storage. Copyright © 2013, Texas Instruments Incorporated 10GBASE-KR MODE FUNCTIONAL DESCRIPTION Submit Documentation Feedback Product Folder Links: TLK10232 13 TLK10232 SLLSEE1 – MAY 2013 3.8 www.ti.com 64B/66B Decoder/Descrambler The data received from the serial 10GBASE-KR is 64B/66B-encoded data. The TLK10232 decodes the data received using the 64B/66B decoding algorithm defined in the IEEE 802.3-2008 standard. The TLK10232 creates consecutive 72-bit data words from the encoded 66-bit code words for transfer over the XAUI interface to the MAC. The information for the two XAUI transfers includes 64 bits of data and 8 bits of control information before 8B/10B encoding. Not all 64B/66B block payloads are valid. Invalid block payloads are handled by the 64B/66B decoder block and appropriate error handling is provided, as defined in the IEEE 802.3-2008 standard. The decoding algorithm includes two steps: a descrambling step which descrambles 64 bits of the 66-bit code word with the scrambling polynomial x58+x39+1, and a decoding step which converts the 66 bits of data received into 64 bits of data and 8 bits of control information. These words are sent to the receive CTC FIFO. 3.9 Transmit Gearbox The function of the transmit gearbox is to convert the 66-bit encoded, scrambled data stream into a 16-bitwide data stream to be sent out to the serializer and ultimately to the physical medium attachment (PMA) device. The gearbox is needed because while the effective bit rate of the 66-bit data stream is equal to the effective bit rate of the 16-bit data, the clock rates of the two buses are of different frequencies. 3.10 Receive Gearbox While the transmit gearbox only performs the task of converting 66-bit data to be transported on to the 16bit serializer, the receive gearbox has more to do than just the reverse of this function. The receive gearbox must also determine where within the incoming data stream the boundaries of the 66-bit code words are. The receive gearbox has the responsibility of initially synchronizing the header field of the code words and continuously monitoring the ongoing synchronization. After obtaining synchronization to the incoming data stream, the gearbox assembles 66-bit code words and presents these to the 64B/66B decoder. Note that in FEC mode, the Receive Gearbox blindly converts 16-bit data to 66-bit data and depends on the RX FEC logic to frame align the data. 3.11 XAUI Lane Alignment / Code Gen (XAUI PCS) The XAUI interface standard is defined to allow for 21 UI of skew between lanes. This block is implemented to handle up to 30 UI (XAUI UI) of skew between lanes using /A/ characters. The state machine follows the standard 802.3-2008 defined state machine. 3.12 Inter-Packet Gap (IPG) Characters The XAUI interface transports information that consists of packets and inter-packet gap (IPG) characters. The IEEE 802.3-2008 standard defines that the IPG, when transferred over the XAUI interface, consists of alignment characters (/A/), control characters (/K/) and replacement characters (/R/). TLK10232 converts all AKR characters to IDLE characters, performs insertions or deletions on the IDLE characters, and transmits only encoded IDLE characters out to the 10GBASE-KR interface. The receive channel expects encoded IDLE characters to enter the 10GBASE-KR interface, and performs insertions and deletions on IDLE characters and then converts IDLE characters back to AKR characters. Any AKR characters received on the high speed interface are by default converted to IDLE characters for reconversion to AKR columns. Both the transmit and receive FIFOs rely upon a valid IDLE stream to perform clock tolerance compensation (CTC). 14 10GBASE-KR MODE FUNCTIONAL DESCRIPTION Submit Documentation Feedback Product Folder Links: TLK10232 Copyright © 2013, Texas Instruments Incorporated TLK10232 www.ti.com SLLSEE1 – MAY 2013 3.13 Clock Tolerance Compensation (CTC) The XAUI interface is defined to allow for separate clock domains on each side of the link. Though the reference clocks for two devices on a XAUI link have the same specified frequencies, there can be slight differences that, if not compensated for, will lead to over or under run of the FIFO’s on the receive/transmit data path. The TLK10232 provides compensation for these differences in clock frequencies via the insertion or the removal of idle (/I/) characters on all lanes, as shown in Figure 3-3 and Figure 3-4. Packet IPG LANE 0 K R S D D D D ... D D D D I I I K S D LANE 1 K R D D D D D ... D D D T I I I K D D LANE 2 K R D D D D D ... D D D I I I I K D D LANE 3 K R D D D D D ... D D D I I I I K D D LANE 0 I I S D D D D ... D D D D I I I I I S LANE 1 I I D D D D D ... D D D T I I I I I D LANE 2 I I D D D D D ... D D D I I I I I I D LANE 3 I I D D D D D ... D D D I I I I I I D Input Output S = Start of Packet, D = Data, T = End of Packet, I = Idle Added Column Figure 3-3. Clock Tolerance Compensation: Add Packet IPG LANE 0 K R S D D D D ... D D D D I I I K S D LANE 1 K R D D D D D ... D D D T I I I K D D LANE 2 K R D D D D D ... D D D I I I I K D D LANE 3 K R D D D D D ... D D D I I I I K D D Input Dropped Column LANE 0 I I S D D D D ... D D D D I I I LANE 1 I I D D D D D ... D D D T I I I D D D LANE 2 I I D D D D D ... D D D I I I I D D D LANE 3 I I D D D D D ... D D D I I I I D D D S D D Output S = Start of Packet, D = Data, T = End of Packet, I = Idle Figure 3-4. Clock Tolerance Compensation: Drop The TLK10232 allows for provisioning of both the CTC FIFO depth and the low/high watermark thresholds that trigger idle insertion/deletion beyond the standard requirements. This allows for optimization between maximum clock tolerance and packet length. For more information on the TLK10232 CTC provisioning, see Appendix A. Copyright © 2013, Texas Instruments Incorporated 10GBASE-KR MODE FUNCTIONAL DESCRIPTION Submit Documentation Feedback Product Folder Links: TLK10232 15 TLK10232 SLLSEE1 – MAY 2013 www.ti.com 3.14 10GBASE-KR Auto-Negotiation When TLK10232 is selected to operate in 10GKR/1G-KX mode (MODE_SEL pin held low), Clause 73 Auto-Negotiation will commence after power up or hardware or software reset. The data path chosen from the result of Auto-Negotiation will be the highest speed of 10G-KR or 1G-KX as advertised in the MDIO ability fields (set to 10G-KR by default). If 10G-KR is chosen, link training will commence immediately following the completion of Auto-Negotiation. Legacy devices that operate in 1G-KX mode and do not support Clause 73 Auto Negotiation will be recognized through the Clause 73 parallel detection mechanism. 3.15 10GBASE-KR Link Training Link training for 10G-KR mode is performed after auto-negotiation, and follows the procedure described in IEEE 802.3-2008. The high speed TX SERDES side will update pre-emphasis tap coefficients as requested through the Coefficient update field. Received training patterns are monitored for bit errors (MDIO configurable), and requests are made to update partner channel TX coefficients until optimal settings are achieved. The RX link training algorithm consists of sending a series of requests to move the link partner’s transmitter tap coefficients to the center point of an error free region. Once link training has completed, the 10G-KR data path is enabled. If link is lost, the entire process repeats with auto-negotiation, link training, and 10G-KR mode. TLK10232 also offers a manual mode whereby coefficient update requests are handled through external software management. 3.16 10GBASE-KR Line Rate, PLL Settings, and Reference Clock Selection The TLK10232 includes internal low-jitter high quality oscillators that are used as frequency multipliers for the low speed and high speed SERDES and other internal circuits of the device. Specific MDIO registers are available for SERDES rate and PLL multiplier selection to match line rates and reference clock (REFCLK0/1) frequencies for various applications. The external differential reference clock has a large operating frequency range allowing support for many different applications. A low-jitter reference clock should be used, and its frequency accuracy should be within ±200 PPM of the incoming serial data rate (±100 PPM of nominal data rate). When the TLK10232 device is set to operate in the 10GBASE-KR mode with a low speed side line rate of 3.125 Gbps and a high speed side line rate of 10.3125 Gbps, the reference clock choices are as shown in Table 3-1. In general, using a higher reference clock frequency results in improved jitter performance. Table 3-1. Specific Line Rate and Reference Clock Selection for the 10GBASE-KR Mode: LOW SPEED SIDE HIGH SPEED SIDE Line Rate (Mbps) SERDES PLL Multiplier Rate REFCLKP/N (MHz) Line Rate (Mbps) SERDES PLL Multiplier Rate REFCLKP/N (MHz) 3125 10 Full 156.25 10312.5 16.5 Full 156.25 3125 5 Full 312.5 10312.5 8.25 Full 312.5 3.17 10GBASE-KR Test Pattern Support The TLK10232 has the capability to generate and verify various test patterns for self-test and system diagnostic measurements. The following test patterns are supported: • High Speed (HS) Side: PRBS 27 – 1, PRBS 223 – 1, PRBS 231 – 1, Square Wave with Provisionable Length, and KR Pseudo-Random Pattern • Low Speed (LS) Side: PRBS 27 – 1, PRBS 223 – 1, PRBS 231 – 1, High Frequency, Low Frequency, Mixed Frequency, CRPAT, CJPAT. 16 10GBASE-KR MODE FUNCTIONAL DESCRIPTION Submit Documentation Feedback Product Folder Links: TLK10232 Copyright © 2013, Texas Instruments Incorporated TLK10232 www.ti.com SLLSEE1 – MAY 2013 The TLK10232 provides two pins: PRBSEN and PRBS_PASS, for additional control and monitoring of PRBS pattern generation and verification. When PRBSEN is asserted high, the internal PRBS generator and verifier circuits are enabled on both transmit and receive data paths on high speed and low speed sides of all channels. PRBS 27-1 is selected by default, and can be changed through MDIO. When PRBS test is enabled (PRBSEN=1): • PRBS_PASS = 1 indicates that PRBS pattern reception is error free. • PRBS_PASS = 0 indicates that a PRBS error is detected. The channel, the side (high speed or low speed), and the lane (for low speed side) that this signal refers to is chosen through MDIO. 3.18 10GBASE-KR Latency The latency through the TLK10232 in 10GBASE-KR mode is as shown in Figure 3-5. Note that the latency ranges shown indicate static rather than dynamic latency variance, i.e., the range of possible latencies when the serial link is initially established. During normal operation, the latency through the device is fixed. Figure 3-5. 10GBASE-KR Mode Latency Per Block Copyright © 2013, Texas Instruments Incorporated 1GBASE-KX MODE FUNCTIONAL DESCRIPTION Submit Documentation Feedback Product Folder Links: TLK10232 17 TLK10232 SLLSEE1 – MAY 2013 www.ti.com 4 1GBASE-KX MODE FUNCTIONAL DESCRIPTION Serializer Test Pattern Generation 8b/10b Encoder TX CTC Data Switch 8b/10b Decoder INx0N Deserializer INx0P 1G-KX Sync A simplified block diagram of the 1GBASE-KX data path is shown in Figure 4-1. HSTXxP HSTXxN Test Pattern Verification Deserializer 1G-KX Sync 8b/10b Decoder Data Switch RX CTC 8b/10b Encoder OUTx0P OUTx0N Serializer Test Pattern Verification HSRXxP HSRXxN Test Pattern Generation Figure 4-1. A Simplified One Channel Block Diagram of the 1GKX Data Path 4.1 Channel Sync Block This block is used to align the deserialized signals to the proper 10-bit word boundaries. The Channel Sync block generates a synchronization flag indicating incoming data is synchronized to the correct word boundary. This module implements the synchronization state machine found in Figure 36-9 of the IEEE 802.3-2008 Standard. A synchronization status signal, latched low, is available to indicate synchronization errors. 4.2 8b/10b Encoder and Decoder Blocks As in the 10GBASE-KR operating mode, these blocks are used to convert between 10-bit (encoded) data and 8-bit data words. They can be optionally bypassed. A code invalid signal, latched low, is available to indicate 8b/10b encode and decode errors. 4.3 TX CTC The transmit clock tolerance compensation (CTC) block acts as a FIFO with add and delete capabilities, adding and deleting 2 cycles each time to support ±200ppm during IFG (no errors) between the read and write clocks. This block implements a 12 deep asynchronous FIFO with a usable space 8 deep. It has two separate pointer tracking systems. One determines when to delete or insert and another determines when to reset. Inserts and deletes are only allowed during non-errored inter-frame gaps and occurs 2 cycles at a time. It has an auto reset feature once collision occurs. If a collision occurs, the indication is latched high until read by MDIO. 4.4 1GBASE-KX Line Rate, PLL Settings, and Reference Clock Selection When the TLK10232 is configured to operate in the 1GBASE-KX mode, the available line rates, reference clock frequencies, and corresponding PLL multipliers are summarized in Table 4-1. 18 1GBASE-KX MODE FUNCTIONAL DESCRIPTION Submit Documentation Feedback Product Folder Links: TLK10232 Copyright © 2013, Texas Instruments Incorporated TLK10232 www.ti.com SLLSEE1 – MAY 2013 Table 4-1. Specific Line Rate and Reference Clock Selection for the 1GBASE-KX Mode LOW SPEED SIDE HIGH SPEED SIDE Line Rate (Mbps) SERDES PLL Multiplier Rate REFCLKP/N (MHz) Line Rate (Mbps (1) ) SERDES PLL Multiplier Rate REFCLKP/N (MHz) 3125 (2) 10 Full 156.25 3125 (2) 10 Full 156.25 3125 (1) (2) 4.5 (2) 3125 (2) 5 Full 312.5 5 Full 312.5 1250 10 Half 125 (2) 1250 20 Quarter 125 (2) 1250 8 Half 156.25 1250 16 Quarter 156.25 1250 8 Quarter 312.5 1250 8 Quarter 312.5 High Speed Side SERDES runs at 2x effective data rate. Manual mode only, as auto negotiation does not support 125Mhz REFCLK or line rate of 3125Mbps. To disable automatic setting of PLL and rate modes, write 1'b1 to bit 13 of register 0x1E.001D. Test Pattern Generator In 1G-KX mode, this block can be used to generate test patterns allowing the 1G-KX channel to be tested for compliance while in a system environment or for diagnostic purposes. Test patterns generated are high/low/mixed frequency and CRPAT long or short. 4.6 Test Pattern Verifier The 1G-KX test pattern verifier performs the verification and error reporting for the CRPAT Long and Short test patterns specified in Annex 36A of the IEEE 802.3-2008 standard. Errors are reported to MDIO registers. 4.7 1GBASE-KX Mode Latency The latency through the TLK10232 in 1G-KX mode is as shown in Figure 4-2. Note that the latency ranges shown indicate static rather than dynamic latency variance, i.e., the range of possible latencies when the serial link is initially established. During normal operation, the latency through the device is fixed. Copyright © 2013, Texas Instruments Incorporated 1GBASE-KX MODE FUNCTIONAL DESCRIPTION Submit Documentation Feedback Product Folder Links: TLK10232 19 TLK10232 SLLSEE1 – MAY 2013 www.ti.com Figure 4-2. 1G-KX Mode Latency 20 GENERAL PURPOSE (10G) SERDES MODE FUNCTIONAL DESCRIPTION Submit Documentation Feedback Product Folder Links: TLK10232 Copyright © 2013, Texas Instruments Incorporated TLK10232 www.ti.com SLLSEE1 – MAY 2013 5 GENERAL PURPOSE (10G) SERDES MODE FUNCTIONAL DESCRIPTION Serializer 20-bit 8b/10b Encoder TPGEN TX FIFO 1 lane TX FIFO 2 or 4-lane Comma Lane Alignment 8b/10b decoder 8b/10b decoder Deserializer 20-bit ch_sync 20-bit 8b/10b Decoder RX FIFO (1 lane) 8b/10b encoder 8b/10b encoder 8b/10b decoder 8b/10b decoder ch_sync ch_sync ch_sync ch_sync HSTX*P HSTX*N HSRX*P HSRX*N TPVER OUT*3P OUT*3N RX FIFO (2 or 4-lane) OUT*2N Lane Alignment Gen OUT*2P 8b/10b encoder OUT*1P OUT*1N 8b/10b encoder OUT*0P OUT*0N serializer IN*3P IN*3N serializer IN*2P IN*2N serializer IN*1N serializer IN*1P deserializer deserializer IN*0N deserializer IN*0P deserializer A block diagram showing the transmit and receive data paths of the TLK10232 operating in General Purpose (10G) SerDes mode is shown in Figure 5-1. Figure 5-1. Block Diagram Showing General Purpose SerDes Mode 5.1 General Purpose SERDES Transmit Data Path The TLK10232 General Purpose SERDES low speed to high speed (transmit) data path with the device configured to operate in the normal transceiver (mission) mode is shown in the upper half of Figure 5-1. In this mode, 8B/10B encoded serial data (IN*P/N) in 2 or 4 lanes is received by the low speed side SERDES and deserialized into 10-bit parallel data for each lane. The data in each individual lane is then byte aligned (channel synchronized) and then 8B/10B decoded into 8-bit parallel data for each lane. The lane data is then lane aligned by the Lane Alignment Slave. 32 bits of lane aligned parallel data is input to a transmit FIFO which delivers it to an 8B/10B encoder, 16 data bits at a time. The resulting 20-bit 8B/10B encoded parallel data is sent to the high speed side SERDES for serialization and output through the HSTX*P/N pins. 5.2 General Purpose SERDES Receive Data Path With the device configured to operate in the normal transceiver (mission) mode, the high speed to low speed (receive) data path is shown in the lower half of Figure 5-1. 8B/10B encoded serial data (HSRX*P/N) is received by the high speed side SERDES and deserialized into 20-bit parallel data. The data is then byte aligned, 8B/10B decoded into 16-bit parallel data, and then delivered to a receive FIFO. The receive FIFO in turn delivers 32-bit parallel data to the Lane Alignment Master which splits the data into the same number of lanes as configured on the transmit data path. The lane data is then 8B/10B encoded and the resulting 10-bit parallel data for each lane is input to the low speed side SERDES for serialization and output through the OUT*P/N pins. Copyright © 2013, Texas Instruments Incorporated GENERAL PURPOSE (10G) SERDES MODE FUNCTIONAL DESCRIPTION Submit Documentation Feedback Product Folder Links: TLK10232 21 TLK10232 SLLSEE1 – MAY 2013 5.3 www.ti.com Channel Synchronization As in the 10GBASE-KR mode, the channel synchronization block is used in the 10G General Purpose SERDES mode to align received serial data to a defined byte boundary. The channel synchronization block detects the comma pattern found in the K28.5 character, and follows the synchronization flowchart shown in Figure 3-2. 5.4 8B/10B Encoder and Decoder As in the 10GBASE-KR and 1GBASE-KX modes, the 8B/10B encoder and decoder blocks are used to convert between 10-bit (encoded) and 8-bit (unencoded) data words. 5.5 Lane Alignment Scheme for 8b/10b General Purpose Serdes Mode Lower rate multi-lane serial signals per channel must be byte aligned and lane aligned such that high speed multiplexing (proper reconstruction of higher rate signal) is possible. For that reason, the TLK10232 implements a special lane alignment scheme on the low speed (LS) side for 8b/10b data that does not contain XAUI alignment characters. During lane alignment, a proprietary pattern (or a custom comma compliant data stream) is sent by the LS transmitter to the LS receiver on each active lane. This pattern allows the LS receiver to both delineate byte boundaries within a lower speed lane and align bytes across the lanes (2 or 4) such that the original higher rate data ordering is restored. Lane alignment completes successfully when the LS receiver asserts a “Link Status OK” signal monitored by the LS transmitter on the link partner device such as an FPGA. The TLK10232 sends out the “Link Status OK” signals through the LS_OK_OUT_A/B output pins, and monitors the “Link Status OK” signals from the link partner device through the LS_OK_IN_A/B input pins. If the link partner device does not need the TLK10232 Lane Alignment Master (LAM) to send proprietary lane alignment pattern, LS_OK_IN_A/B can be tied high on the application board or set through MDIO register bits. The lane alignment scheme is activated under any of the following conditions: • Device/System power up (after configuration/provisioning) • Loss of channel synchronization assertion on any enabled LS lane • Loss of signal assertion on any enabled LS lane • LS SERDES PLL Lock indication deassertion • After device configuration change • After software determined LS 8B/10B decoder error rate threshold exceeded • After device reset is deasserted • Any time the LS receiver deasserts “Link Status OK”. • Presence of reoccurring higher level / protocol framing errors All the above conditions are selectable through MDIO register provisioning. The block diagram of the lane alignment scheme is shown in Figure 5-2. 22 GENERAL PURPOSE (10G) SERDES MODE FUNCTIONAL DESCRIPTION Submit Documentation Feedback Product Folder Links: TLK10232 Copyright © 2013, Texas Instruments Incorporated TLK10232 www.ti.com SLLSEE1 – MAY 2013 Link Partner Device TLK10232 LS _OK_ OUT _A LAM Lane Alignment Master 8B à 10B CH SYNC 10Bà8B 8B à 10B CH SYNC 10Bà8B CH SYNC 10Bà8B CH SYNC 10Bà8B INA[3:0]P/N 8B à 10B 8B à 10B Lane Align LAS Lane Alignment Slave Low Speed Side SERDES Channel A (4 RX/ 4 TX) Low Speed Side SERDES Channel A (4 RX/ 4 TX) 8B ß 10B CH SYNC 8B ß 10B CH SYNC 8B ß 10B CH SYNC 10B ß 8B 8B ß 10B CH SYNC 10B ß 8B LAS Lane Alignment Slave OUTA[3:0]P/N Lane Align 10B ß 8B 10B ß 8B LAM Lane Alignment Master LS _OK _IN_A Figure 5-2. Block Diagram of the Lane Alignment Scheme 5.6 Lane Alignment Components • • Lane Alignment Master (LAM) – Responsible for generating proprietary LS lane alignment initialization pattern – Resides in the TLK10232 receive path (one instance per channel) • Responsible for bringing up LS receive link for the data sent from the TLK10232 to a link partner device • Monitors the LS_OK_IN pins for “Link Status OK” signals sent from the Lane Alignment Slave (LAS) of the link partner device – Resides in the link partner device (one instance per channel) • Responsible for bringing up LS transmit link for the data sent from the link partner device to the TLK10232 • Monitors the “Link Status OK” signals sent from the LS_OK_OUT pins of the Lane Alignment Slave (LAS) of the TLK10232 Lane Alignment Slave (LAS) – Responsible for monitoring the LS lane alignment initialization pattern – Performs channel synchronization per lane (2 or 4 lanes) through byte rotation – Performs lane alignment and realignment of bytes across lanes – Resides in the TLK10232 transmit path (one instance per channel) • Generates the “Link Status OK” signal for the LAM on the link partner device – Resides in the link partner device (one instance per channel) • Generates the “Link Status OK” signal for the LAM on the TLK10232 device. Reference code from Texas Instruments is available for the LAM and LAS modules for easy integration into FPGAs. 5.7 Lane Alignment Operation During lane alignment, the LAM sends a repeating pattern of 49 characters (control + data) simultaneously across all enabled LS lanes. These simultaneous streams are then encoded by 8B/10B encoders in parallel. The proprietary lane alignment pattern consists of the following characters: /K28.5/ (CTL=1, Data=0xBC) Copyright © 2013, Texas Instruments Incorporated GENERAL PURPOSE (10G) SERDES MODE FUNCTIONAL DESCRIPTION Submit Documentation Feedback Product Folder Links: TLK10232 23 TLK10232 SLLSEE1 – MAY 2013 www.ti.com Repeat the following sequence of 12 characters four times: /D30.5/ (CTL=0, Data=0xBE) /D23.6/ (CTL=0, Data=0xD7) /D3.1/ (CTL=0, Data=0x23) /D7.2/ (CTL=0, Data=0x47) /D11.3/ (CTL=0, Data=0x6B) /D15.4/ (CTL=0, Data=0x8F) /D19.5/ (CTL=0, Data=0xB3) /D20.0/ (CTL=0, Data=0x14) /D30.2/ (CTL=0, Data=0x5E) /D27.7/ (CTL=0, Data=0xFB) /D21.1/ (CTL=0, Data=0x35) /D25.2/ (CTL=0, Data=0x59) The above 49-character sequence is repeated until LS_OK_IN is asserted. Once LS_OK_IN is asserted, the LAM resumes transmitting traffic received from the high speed side SERDES immediately. The TLK10232 performs lane alignment across the lanes similar in fashion to the IEEE 802.3-2008 (XAUI) specification. XAUI only operates across 4 lanes while LAS operates with 2 or 4 lanes. The lane alignment state machine is shown in Figure 5-3. The TLK10232 uses the comma (K28.5) character for lane to lane alignment by default, but can be provisioned to use XAUI's /A/ character as well. Lane alignment checking is not performed by the LAS after lane alignment is achieved. After LAM detects that the LS_OK_IN signal is asserted, normal system traffic is carried instead of the proprietary lane alignment pattern. Channel synchronization is performed during lane alignment and normal system operation. 24 GENERAL PURPOSE (10G) SERDES MODE FUNCTIONAL DESCRIPTION Submit Documentation Feedback Product Folder Links: TLK10232 Copyright © 2013, Texas Instruments Incorporated TLK10232 www.ti.com SLLSEE1 – MAY 2013 Hard or Soft Reset Loss of Lane Alignment (enable deskew) Deassert LS_OK /C/ & CH_SYNC? no Align Detect 3 yes any deskew_err !deskew_err & /C/ no Align Detect 1 (disable deskew) yes any deskew_err !deskew_err & /C/ Lane Aligned (Assert LS_OK) no yes yes Align Detect 2 any deskew_err !deskew_err & /C/ no Any Lane Realign Conditions? no /C/ = Character matched In All Enabled Lanes deskew_err = Character matched in any lane, but not in all lanes at same time yes CH_SYNC = Channel Sync Asserted All Lanes Figure 5-3. Lane Alignment State Machine Copyright © 2013, Texas Instruments Incorporated GENERAL PURPOSE (10G) SERDES MODE FUNCTIONAL DESCRIPTION Submit Documentation Feedback Product Folder Links: TLK10232 25 TLK10232 SLLSEE1 – MAY 2013 5.8 www.ti.com Line Rate, SERDES PLL Settings, and Reference Clock Selection for the General Purpose SERDES Mode When the TLK10232 is set to operate in the General Purpose SERDES mode, the following tables show a summary of line rates and reference clock frequencies used for CPRI/OBSAI for 1:1, 2:1 and 4:1 operation modes. Table 5-1. Specific Line Rate Selection for the 1:1 General Purpose Operation Mode LOW SPEED SIDE Line Rate (Mbps) HIGH SPEED SIDE SERDES PLL Multiplier Rate REFCLKP/N (MHz) 122.88 SERDES PLL Multiplier Rate REFCLKP/N (MHz) Line Rate (Mbps) 4915.2 20 Full 122.88 4915.2 20 Half 3840 12.5 Full 153.6 3840 12.5 Half 153.6 3125 10 Full 156.25 3125 10 Half 156.25 3125 5 Full 312.5 3125 5 Half 312.5 3072 10 Full 153.6 3072 10 Half 153.6 2457.6 8/10 Full 153.6/122.88 2457.6 16/20 Quarter 153.6/122.88 1920 12.5 Half 153.6 1920 12.5 Quarter 153.6 1536 10 Half 153.6 1536 10 Quarter 153.6 1228.8 8/10 Half 153.6/122.88 1228.8 16/20 Eighth 153.6/122.88 Table 5-2. Specific Line Rate and Reference Clock Selection for the 2:1 General Purpose Operation Mode LOW SPEED SIDE Line Rate (Mbps) HIGH SPEED SIDE SERDES PLL Multiplier Rate REFCLKP/N (MHz) SERDES PLL Multiplier Rate REFCLKP/N (MHz) Line Rate (Mbps) 4915.2 20 Full 122.88 9830.4 20 Full 122.88 3840 12.5 Full 153.6 7680 12.5 Full 153.6 3072 10 Full 153.6 6144 10 Full 153.6 2457.6 8/10 Full 153.6/122.88 4915.2 16/20 Half 153.6/122.88 1920 12.5 Half 153.6 3840 12.5 Half 153.6 1536 10 Half 153.6 3072 10 Half 153.6 1228.8 8/10 Half 153.6/122.88 2457.6 16/20 Quarter 153.6/122.88 768 10 Quarter 153.6 1536 10 Quarter 153.6 614.4 8/10 Quarter 153.6/122.88 1228.8 16/20 Eighth 153.6/122.88 Table 5-3. Specific Line Rate and Reference Clock Selection for the 4:1 General Purpose Operation Mode LOW SPEED SIDE 26 HIGH SPEED SIDE Line Rate (Mbps) SERDES PLL Multiplier Rate REFCLKP/N (MHz) Line Rate (Mbps) SERDES PLL Multiplier Rate REFCLKP/N (MHz) 2457.6 8/10 Full 153.6/122.88 9830.4 16/20 Full 153.6/122.88 1536 10 Half 153.6 6144 10 Full 153.6 1228.8 8/10 Half 153.6/122.88 4915.2 16/20 Half 153.6/122.88 768 10 Quarter 153.6 3072 10 Half 153.6 614.4 8/10 Quarter 153.6/122.88 2457.6 16/20 Quarter 153.6/122.88 GENERAL PURPOSE (10G) SERDES MODE FUNCTIONAL DESCRIPTION Submit Documentation Feedback Product Folder Links: TLK10232 Copyright © 2013, Texas Instruments Incorporated TLK10232 www.ti.com SLLSEE1 – MAY 2013 Table 5-1, Table 5-2, and Table 5-3 indicate two possible reference clock frequencies for CPRI/OBSAI applications: 153.6MHz and 122.88MHz, which can be used based on the application preference. The SERDES PLL Multiplier (MPY) has been given for each reference clock frequency respectively. For each channel, the low speed side and the high speed side SERDES use the same reference clock frequency. Note that Channel A and B are independent and their application rates and references clocks are separate. For other line rates not shown in Table 5-1, Table 5-2, or Table 5-3, valid reference clock frequencies can be selected with the help of the information provided in Table 5-4 and Table 5-5 for the low speed and high speed side SERDES. The reference clock frequency has to be the same for the two SERDES and must be within the specified valid ranges for different PLL multipliers. Table 5-4. Line Rate and Reference Clock Frequency Ranges for the Low Speed Side SERDES (General Purpose Mode) SERDES PLL Multiplier (MPY) Reference Clock (MHz) Full Rate (Gbps) Half Rate (Gbps) Quarter Rate (Gbps) Min Max Min Max Min Max Min 4 250 425 2 3.4 1 1.7 0.5 Max 0.85 5 200 425 2 4.25 1 2.125 0.5 1.0625 6 166.667 416.667 2 5 1 2.5 0.5 1.25 8 125 312.5 2 5 1 2.5 0.5 1.25 10 122.88 250 2.4576 5 1.2288 2.5 0.6144 1.25 12 122.88 208.333 2.94912 5 1.47456 2.5 0.73728 1.25 12.5 122.88 200 3.072 5 1.536 2.5 0.768 1.25 15 122.88 166.667 3.6864 5 1.8432 2.5 0.9216 1.25 20 122.88 125 4.9152 5 2.4576 2.5 1.2288 1.25 RateScale: Full Rate = 0.5, Half Rate = 1, Quarter Rate = 2 Table 5-5. Line Rate and Reference Clock Frequency Ranges for the High Speed Side SERDES (General Purpose Mode) Full Rate (Gbps) Half Rate (Gbps) Min Max Min Max Min Max Min Max 4 375 425 6 6.8 3 3.4 1.5 1.7 5 300 425 6 8.5 3 4.25 1.5 6 250 416.667 6 10 3 5 1.5 8 187.5 312.5 6 10 3 5 10 150 250 6 10 3 12 125 208.333 6 10 12.5 153.6 200 7.68 15 122.88 166.667 16 122.88 20 122.88 SERDES PLL Multiplier (MPY) Reference Clock (MHz) Quarter Rate (Gbps) Eighth Rate (Gbps) Min Max 2.125 1.0 1.0625 2.5 1.0 1.25 1.5 2.5 1.0 1.25 5 1.5 2.5 1.0 1.25 3 5 1.5 2.5 1.0 1.25 10 3.84 5 1.92 2.5 1.0 1.25 7.3728 10 3.6864 5 1.8432 2.5 1.0 1.25 156.25 7.86432 10 3.932 5 1.966 2.5 1.0 1.25 125 9.8304 10 4.9152 5 2.4576 2.5 1.2288 1.25 RateScale: Full Rate = 0.25, Half Rate = 0.5, Quarter Rate = 1, Eighth Rate = 2 For example, in the 2:1 operation mode, if the low speed side line rate is 1.987Gbps, the high-speed side line rate will be 3.974Gbps. The following steps can be taken to make a reference clock frequency selection: 1. Determine the appropriate SERDES rate modes that support the required line rates. Table 5-4 shows that the 1.987Gbps line rate on the low speed side is only supported in the half rate mode (RateScale = 1). Table 5-5 shows that the 3.974Gbps line rate on the high speed side is only supported in the half rate mode (RateScale = 1). 2. For each SERDES side, and for all available PLL multipliers (MPY), compute the corresponding reference clock frequencies using the formula: Reference Clock Frequency = (LineRate x RateScale)/MPY Copyright © 2013, Texas Instruments Incorporated GENERAL PURPOSE (10G) SERDES MODE FUNCTIONAL DESCRIPTION Submit Documentation Feedback Product Folder Links: TLK10232 27 TLK10232 SLLSEE1 – MAY 2013 www.ti.com The computed reference clock frequencies are shown in Table 5-6 along with the valid minimum and maximum frequency values. 3. Mark all the common frequencies that appear on both SERDES sides. Note and discard all those that fall outside the allowed range. In this example, the common frequencies are highlighted in Table 5-6. The highest and lowest computed reference clock frequencies must be discarded because they exceed the recommended range. 4. Select any of the remaining marked common reference clock frequencies. Higher reference clock frequencies are generally preferred. In this example, any of the following reference clock frequencies can be selected: 397.4MHz, 331.167MHz, 248.375MHz, 198.7MHz, 165.583MHz, 158.96MHz, and 132.467MHz Table 5-6. Reference Clock Frequency Selection Example LOW SPEED SIDE SERDES HIGH SPEED SIDE SERDES REFERENCE CLOCK FREQUENCY (MHz) REFERENCE CLOCK FREQUENCY (MHz) SERDES PLL MULTIPLIER COMPUTED MIN MAX SERDES PLL MULTIPLIER COMPUTED MIN MAX 4 496.750 250 425 4 496.750 375 425 5 397.400 200 425 5 397.400 300 425 6 331.167 166.667 416.667 6 331.167 250 416.667 8 248.375 125 312.5 8 248.375 187.5 312.5 10 198.700 122.88 250 10 198.700 150 250 12 165.583 122.88 208.333 12 165.583 125 208.333 12.5 158.960 122.88 200 12.5 158.960 153.6 200 15 132.467 122.88 166.667 15 132.467 122.88 166.667 20 99.350 122.88 125 20 99.350 122.88 125 5.9 General Purpose SERDES Mode Test Pattern Support The TLK10232 has the capability to generate and verify various test patterns for self-test and system diagnostic measurements. Most of the same test pattern support is available for 10G General Purpose Mode as for 10G-KR. (See Register 1E.000B for details). 5.10 General Purpose SERDES Mode Latency The latency through the TLK10232 in General Purpose SERDES mode is as shown in Figure 5-4. Note that the latency ranges shown indicate static rather than dynamic latency variance, i.e., the range of possible latencies when the serial link is initially established. During normal operation, the latency through the device is fixed. 28 GENERAL PURPOSE (10G) SERDES MODE FUNCTIONAL DESCRIPTION Submit Documentation Feedback Product Folder Links: TLK10232 Copyright © 2013, Texas Instruments Incorporated TLK10232 www.ti.com SLLSEE1 – MAY 2013 Figure 5-4. General Purpose SERDES Mode Latency Copyright © 2013, Texas Instruments Incorporated GENERAL PURPOSE (10G) SERDES MODE FUNCTIONAL DESCRIPTION Submit Documentation Feedback Product Folder Links: TLK10232 29 TLK10232 SLLSEE1 – MAY 2013 www.ti.com 6 CLOCKING ARCHITECTURE (All Modes) REFCLK0P/N H igh Speed SERDES MDIO REG H igh Speed SERDES MDIO REG Clock Multiplier Clock Multiplier MDIO REG Clock Multiplier MDIO REG Clock Multiplier Channel B LS Low Speed SERDES Channel A LS Low Speed SERDES A simplified clocking architecture for the TLK10232 is captured in Figure 6-1. Each channel has an option of operating with a differential reference clock provided either on pins REFCLK0P/N or REFCLK1P/N. The choice is made either through MDIO or through REFCLK_SEL pins. The reference clock frequencies for each channel can be chosen independently. For each channel, the low speed side SERDES, high speed side SERDES and the associated part of the digital core can operate from the same reference clock. Channel A HS Channel B HS REFCLK1P/N Figure 6-1. Reference Clock Architecture The TLK10232 has two output clock ports - CLKOUTAP/N and CLKOUTBP/N. Both of these output ports can be configured to output the recovered byte clock of either channel's low speed or high speed sides. Output clocks can also be chosen to be synchronous with the transmit clock rate. Various divider values can be chosen using the MDIO interface. The maximum CLKOUT frequency is 500 MHz. 30 CLOCKING ARCHITECTURE (All Modes) Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 TLK10232 www.ti.com SLLSEE1 – MAY 2013 7 ADDITIONAL FEATURES 7.1 Integrated Smart Switch The TLK10232 allows for adjustable routing of data within the device. Each output port may be configured to output data corresponding to any input port. Figure 7-1 illustrates the different possible data path routings. Data Switch LS IN A Low Speed Deserialization and TX Logic (Synchronization, Decoding, etc.) LS OUT A Low Speed RX Logic (Encoding, etc.) and Serialization LS IN B Low Speed Deserialization and TX Logic (Synchronization, Decoding, etc.) LS OUT B Low Speed RX Logic (Encoding, etc.) and Serialization 00 10 11 01 High Speed TX Logic (Encoding, Scrambling, etc.) and Serialization HSTXA High Speed Deserialization and RX Logic (Decoding, Descrambling, etc.) HSRXA Ch. B HS Output Selection High Speed TX Logic (Encoding, Scrambling, etc.) and Serialization HSTXB Ch. A LS Output Selection High Speed Deserialization and RX Logic (Decoding, Descrambling, etc.) HSRXB Ch. A HS Output Selection Ch. A LS Output Selection 11 10 00 01 00 11 01 10 10 00 11 01 Figure 7-1. Signal Routings for Integrated Smart Switch 7.2 Intelligent Switching Modes The TLK10232 supports various switching modes that allow for the user to choose when changes in data routing take effect. There are three options: 1. Wait for the end of the current packet, insert IDLEs, then switch to the new channel at the start of its next packet. This option allows the current packet to complete so that data is not lost. 2. Drop current packet and insert a programmable character (such as Local Fault), then switch to the new channel at the start of its next packet. This can provide a more immediate switch-over at the expense of the current packet’s data. 3. Immediately switch lanes without packet monitoring. For more information on selecting different intelligent switching modes, see MDIO register bits 0x1E.0017 through 0x1E.001B. 7.3 Serial Loopback Modes The TLK10232 supports internal loopback of the serial output signals for self-test and system diagnostic purposes. Loopback mode can be enabled independently for each SERDES via MDIO register bits. When loopback mode is enabled for a particular SERDES, the serial output data will be internally routed to the SERDES’s serial input port. The output data will remain available for monitoring on the output pins. ADDITIONAL FEATURES Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 31 TLK10232 SLLSEE1 – MAY 2013 7.4 www.ti.com Latency Measurement Function (General Purpose SerDes Mode) The TLK10232 includes a latency measurement function to support CPRI and OBSAI type applications. There are two start and two stop locations for the latency counter as shown in Figure 7-2 for Channel A. The start and stop locations are selectable through MDIO register bits. The elapsed time from a comma detected at an assigned counter start location of a particular channel to a comma detected at an assigned counter stop location of the same channel is measured and reported through the MDIO interface. The function operates on one channel at a time. The following three control characters (containing commas) are monitored: 1. K28.1 (control = 1, data = 0x3C) 2. K28.5 (control = 1, data = 0xBC) 3. K28.7 (control = 1, data = 0xFC). The first comma found at the assigned counter start location will start up the latency counter. The first comma detected at the assigned counter stop location will stop the latency counter. The 20-bit latency counter result of this measurement is readable through the MDIO interface. The accuracy of the measurement is a function of the serial bit rate at which the channel being measured is operating. The register will return a value of 0xFFFFF if the duration between transmit and receive comma detection exceeds the depth of the counter. Only one measurement value is stored internally until the 20-bit results counter is read. The counter will return zero in cases where a transmit comma was never detected (indicating the results counter never began counting). In addition, the stopwatch counter can be configured to be started or stopped manually based on the state of the PRTAD0 pin (see MDIO register map for details). 10 10 LS PRBS Generator OUTA3P/N 10 10 16 Stop Counter 20 10 10 Receive Data Path Covered Start Counter 10 10 32 16 RX FIFO HS PRBS Generator HSTXAP /N High Speed Side SERDES Transmit Data Path Covered Latency Counter 8B/10 B Encode r Lane Align Ma ster 10 16 Pattern 16 Generator Stop Counter OUTA0P/N OUTA2P/N 10 Start Counter Low Speed Side SERDES OUTA1P/N 10 TX FIFO 8 B/10B Encoder INA2P/N INA3P/N 10 32 8B/10B Dec oder Channel Sync 10 Channel A 8B/10B Dec oder La ne Align Slave 10 10 Comma Detec tion for Latency Measurement INA1P/N LS PRBS Verifier Channe l Sync 10 INA0P/N 20 HS PRBS Verifier HSRXAP /N Pattern Verifier Figure 7-2. Location of TX and RX Comma Character Detection (Only Channel A Shown) In high speed side SERDES full rate mode, the latency measurement function runs off of an internal clock which is equal to the frequency of the transmit serial bit rate divided by 8. In half rate mode, the latency measurement function runs off of an internal clock which is equal to the serial bit rate divided by 4. In quarter rate mode, the latency measurement function runs off of an internal clock which is equal to the serial bit rate divided by 2. In eighth rate mode, the latency measurement function runs off of a clock which is equal to the serial bit rate. 32 ADDITIONAL FEATURES Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 TLK10232 www.ti.com SLLSEE1 – MAY 2013 The latency measurement does not include the low speed side transmit SERDES contribution as well as part of the channel synchronization block. The latency introduced by those two is up to (18 + 10) x N high speed side unit intervals (UIs), where N = 2, 4 is the multiplex factor. The latency measurement also doesn’t account for the low speed side receive SERDES contribution which is estimated to be up to 20 x N high speed side UIs. The latency measurement accuracy in all cases is equal to plus or minus one latency measurement clock period. The measurement clock can be divided down if a longer duration measurement is required, in which case the accuracy of the measurement is accordingly reduced. The high speed latency measurement clock is divided by either 1, 2, 4, or 8 via register settings. The measurement clock used is always selected by the channel under test. The high speed latency measurement clock may only be used when operating at one of the serial rates specified in the CPRI/OBSAI specifications. It is also possible to run the latency measurement function off of the recovered byte clock for the channel under test (giving a latency measurement clock frequency equal to the serial bit rate divided by 20). The accuracy for the standard based CPRI/OBSAI application rates is shown in Table 7-1, and assumes the latency measurement clock is not divided down per user selection (division is required to measure a duration greater than 682us). For each division of 2 in the measurement clock, the accuracy is also reduced by a factor of two. Table 7-1. CPRI/OBSAI Latency Measurement Function Accuracy (Undivided Measurement Clock) RATE LATENCY CLOCK FREQUENCY (GHz) ACCURACY (± ns) 1.2288 Eighth 1.2288 0.8138 1.536 Quarter 0.768 1.302 2.4576 Quarter 1.2288 0.8138 3.072 Half 0.768 1.302 3.84 Half 0.96 1.0417 4.9152 Half 1.2288 0.8138 6.144 Full 0.768 1.302 7.68 Full 0.96 1.0417 9.8304 Full 1.2288 0.8138 LINE RATE (Gbps) 7.5 Power Down Mode The TLK10232 can be put in power down either through device input pins or through MDIO control register 1E.0001. • PDTRXA_N: Active low, powers down channel A. • PDTRXB_N: Active low, powers down channel B. ADDITIONAL FEATURES Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 33 TLK10232 SLLSEE1 – MAY 2013 7.5.1 www.ti.com High Speed CML Output The high speed data output driver is implemented using Current Mode Logic (CML) with integrated pull up resistors. The transmit outputs must be AC coupled. HSTXAP HSRXAP 50 ohm transmission line 50 VTERM 50 GND 50 ohm transmission line HSTXAN TRANSMITTER HSRXAN MEDIA RECEIVER NOTE: Channel A HS Side is Shown Figure 7-3. Example of High Speed I/O AC Coupled Mode Current Mode Logic (CML) drivers often require external components. The disadvantage of the external component is a limited edge rate due to package and line parasitic. The CML driver on TLK10232 has onchip 50Ω termination resistors terminated to VDDT, providing optimum performance for increased speed requirements. The transmitter output driver is highly configurable allowing output amplitude and deemphasis to be tuned to a channel's individual requirements. Software programmability allows for very flexible output amplitude control. Only AC coupled output mode is supported. When transmitting data across long lengths of PCB trace or cable, the high frequency content of the signal is attenuated due to dielectric losses and the skin effect of the media. This causes a “smearing” of the data eye when viewed on an oscilloscope. The net result is reduced timing margins for the receiver and clock recovery circuits. In order to provide equalization for the high frequency loss, 4-tap finite impulse response (FIR) transmit de-emphasis is implemented. A highly configurable output driver maximizes flexibility in the end system by allowing de-emphasis and output amplitude to be tuned to a channel’s individual requirements. Output swing control is via MDIO. 7.5.2 High Speed Receiver The high speed receiver is differential CML with internal termination resistors. The receiver requires AC coupling. The termination impedances of the receivers are configured as 100 Ω with the center tap weakly tied to 0.7×VDDT, and a capacitor is used to create an AC ground (see Figure 7-3). TLK10232 serial receivers incorporate adaptive equalizers. This circuit compensates for channel insertion loss by amplifying the high frequency components of the signal, reducing inter-symbol interference. Equalization can be enabled or disabled per register settings. Both feed-forward equalization (FFE) and decision feedback equalization (DFE) are used to minimize the pre-cursor and post-cursor components (respectively) of intersymbol interference. 34 ADDITIONAL FEATURES Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 TLK10232 www.ti.com 7.5.3 SLLSEE1 – MAY 2013 Loss of Signal Output Generation (LOS) Loss of input signal detection is based on the voltage level of each serial input signal IN*P/N, HSRX*P/N. When LOS indication is enabled and a channel's differential serial receive input level is < 75mVpp, that channel's respective LOS indicator (LOSA or LOSB) will be asserted (high true). If the input signal is >150mVpp, the LOS indicator will be deasserted (low false). Outside of these ranges, the LOS indication is undefined. The LOS indicators can also directly be read through the MDIO interface. The following additional critical status conditions can be combined with the loss of signal condition enabling additional real-time status signal visibility on the LOS* outputs per channel: 1. Loss of Channel Synchronization Status – Logically OR’d with LOS condition(s) when enabled. Loss of channel synchronization can be optionally logically OR’d (disabled by default) with the internally generated LOS condition (per channel). 2. Loss of PLL Lock Status on LS and HS sides – Logically OR’d with LOS condition(s) when enabled. The internal PLL loss of lock status bit is optionally OR’d (disabled by default) with the other internally generated loss of signal conditions (per channel). 3. Receive 8B/10B Decode Error (Invalid Code Word or Running Disparity Error) – Logically OR’d with LOS condition(s) when enabled. The occurrence of an 8B/10B decode error (invalid code word or disparity error) is optionally OR’d (disabled by default) with the other internally generated loss of signal conditions (per channel). 4. AGCLOCK (Active Gain Control Currently Locked) – Inverted and Logically OR’d with LOS condition(s) when enabled. HS RX SERDES adaptive gain control unlocked indication is optionally OR’d (disabled by default) with the other internally generated loss of signal conditions (per channel). 5. AZDONE (Auto Zero Calibration Done) - Inverted and Logically OR’d with LOS conditions(s) when enabled. HS RX SERDES auto-zero not done indication is optionally OR’d (disabled by default) with the other internally generated loss of signal conditions (per channel). Refer to Figure 7-4, which shows the detailed implementation of the LOSA signal along with the associated MDIO control registers for the General Purpose SERDES mode. More details about LOS settings including configurations related to the 10GBASE-KR mode can be found in the Programmers Reference section. ADDITIONAL FEATURES Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 35 TLK10232 SLLSEE1 – MAY 2013 www.ti.com Figure 7-4. LOSA – Logic Circuit Implementation 36 ADDITIONAL FEATURES Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 TLK10232 www.ti.com 7.6 SLLSEE1 – MAY 2013 MDIO Management Interface The TLK10232 supports the Management Data Input/Output (MDIO) Interface as defined in Clauses 22 and 45 of the IEEE 802.3-2008 Ethernet specification. The MDIO allows register-based management and control of the serial links. The MDIO Management Interface consists of a bi-directional data path (MDIO) and a clock reference (MDC). The device identification and port address are determined by control pins (see Table 2-1). Also, whether the device responds as a Clause 22 or Clause 45 device is also determined by control pin ST (see Table 2-1). In Clause 45 (ST = 0) and Clause 22 (ST = 1), the top 4 control pins PRTAD[4:1] determine the device port address. In this mode, TLK10232 will respond if the PHY address field on the MDIO protocol (PA[4:1]) matches PRTAD[4:1] pin value. In both these modes the 2 individual channels in TLK10232 are classified as 2 different ports. So for any PRTAD[4:1] value there will be 2 ports per TLK10232. The LSB of PHY address field (PA[0]) will determine which channel/port within TLK10232 to respond. If PA[0] = 1’b0, TLK10232 Channel A will respond. If PA[0] = 1’b1, TLK10232 Channel B will respond. In Clause 22 (ST = 1) mode, only 32 (5’b00000 to 5’b11111) register addresses can be accessed through standard protocol. Due to this limitation, an indirect addressing method (More description in Clause 22 Indirect Addressing section) is implemented to provide access to all device specific control/status registers that cannot be accessed through the standard Clause 22 register address space. Write transactions which address an invalid register or device or a read only register will be ignored. Read transactions which address an invalid register or device will return a 0. 7.7 MDIO Protocol Timing Timing for a Clause 45 address transaction is shown in Figure 7-5. The Clause 45 timing required to write to the internal registers is shown in Figure 7-6. The Clause 45 timing required to read from the internal registers is shown in Figure 7-7. The Clause 45 timing required to read from the internal registers and then increment the active address for the next transaction is shown in Figure 7-8. The Clause 22 timing required to read from the internal registers is shown in Figure 7-9. The Clause 22 timing required to write to the internal registers is shown in Figure 7-10. MDC 0 MDIO 0 0 > 32 "1's" Preamble 0 Addr Code Start PA[4:0] PHY Addr DA[4:0] Dev Addr 1 0 Turn Around A15 A0 Reg Addr 1 Idle Figure 7-5. CL45 - Management Interface Extended Space Address Timing MDC 0 MDIO 0 > 32 "1's" Preamble Start 0 1 Write Code PA[4:0] PHY Addr DA[4:0] Dev Addr 1 0 Turn Around D15 D0 Data 1 Idle Figure 7-6. CL45 - Management Interface Extended Space Write Timing ADDITIONAL FEATURES Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 37 TLK10232 SLLSEE1 – MAY 2013 www.ti.com MDC 0 MDIO 0 1 > 32 "1's" Preamble 1 Read Code Start PA[4:0] PHY Addr DA[4:0] Dev Addr Z 0 Turn Around D15 D0 1 Idle Data Figure 7-7. CL45 - Management Interface Extended Space Read Timing MDC 0 MDIO 0 > 32 "1's" Preamble Start 1 0 PA[4:0] Read Inc Code PHY Addr DA[4:0] Dev Addr Z 0 Turn Around D15 D0 1 Idle Data Figure 7-8. CL45 - Management Interface Extended Space Read And Increment Timing MDC MDIO 0 1 1 > 32 "1's" Read Code Start Preamble 0 PA[4:0] PHY Addr RA4 RA0 REG Addr Z 0 Turn Around D15 D0 Data 1 Idle Figure 7-9. CL22 - Management Interface Read Timing MDC MDIO 0 1 > 32 "1's" Start Preamble 0 1 Write Code PA[4:0] PHY Addr RA4 RA0 REG Addr 1 0 Turn Around D15 D0 Data 1 Idle Figure 7-10. CL22 - Management Interface Write Timing The IEEE 802.3 Clause 22/45 specification defines many of the registers, and additional registers have been implemented for expanded functionality. 7.8 Clause 22 Indirect Addressing Due to Clause 22 register space limitations, an indirect addressing method is implemented so that the extended register space can be accessed through Clause 22. All the device specific control and status registers that cannot be accessed through Clause 22 direct addressing can be accessed through this indirect addressing method. To access this register space, an address control register (Reg 30, 5’h1E) should be written with the register address followed by a read/write transaction to address content register (Reg 31, 5’h1F) to access the contents of the address specified in address control register. Following timing diagrams illustrate an example write transaction to Register 16’h9000 using indirect addressing in Clause 22. 38 ADDITIONAL FEATURES Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 TLK10232 www.ti.com SLLSEE1 – MAY 2013 MDC MDIO 0 1 0 > 32 "1's" Write Code Start Preamble 1 PA[4:0] 5'h1E PHY Addr REG Addr 1 0 16'h9000 Turn Around Data 1 Idle Figure 7-11. CL22 – Indirect Address Method – Address Write MDC MDIO 0 1 0 > 32 "1's" Write Code Start Preamble 1 PA[4:0] 5'h1F PHY Addr REG Addr 1 0 DATA Turn Around Data 1 Idle Figure 7-12. CL22 - Indirect Address Method – Data Write Following timing diagrams illustrate an example read transaction to read contents of Register 16’h9000 using indirect addressing in Clause 22. MDC MDIO 0 1 0 > 32 "1's" Write Code Start Preamble 1 PA[4:0] 5'h1E PHY Addr REG Addr 1 0 16'h9000 Turn Around Data 1 Idle Figure 7-13. CL22 - Indirect Address Method – Address Write MDC MDIO 0 1 > 32 "1's" Preamble Start 1 0 Read Code PA[4:0] PHY Addr 5'h1F REG Addr Z 0 D15 Turn Around D0 Data 1 Idle Figure 7-14. CL22 - Indirect Address Method – Data Read 7.9 Programmers Reference Channel identification is based on PHY (Port) address field. Channel A can be accessed by setting LSB of PHY address to 0. Channel B can be accessed by setting LSB of PHY address to 1. ADDITIONAL FEATURES Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 39 TLK10232 SLLSEE1 – MAY 2013 www.ti.com 7.10 Register Bit Definitions RW: Read-Write User can write 0 or 1 to this register bit. Reading this register bit returns the same value that has been written. RW/SC: Read-Write Self-Clearing User can write 0 or 1 to this register bit. Writing a "1" to this register creates a high pulse. Reading this register bit always returns 0. RO: Read-Only This register can only be read. Writing to this register bit has no effect. Reading from this register bit returns its current value. RO/LH: Read-Only Latched High This register can only be read. Writing to this register bit has no effect. Reading a "1" from this register bit indicates that either the condition is occurring or it has occurred since the last time it was read. Reading a "0" from this register bit indicates that the condition is not occurring presently, and it has not occurred since the last time the register was read. A latched high register, when read high, should be read again to distinguish if a condition occurred previously or is still occurring. If it occurred previously, the second read will read low. If it is still occurring, the second read will read high. Reading this register bit automatically resets its value to 0. RO/LL: Read-Only Latched Low This register can only be read. Writing to this register bit has no effect. Reading a "0" from this register bit indicates that either the condition is occurring or it has occurred since the last time it was read. Reading a "1" from this register bit indicates that the condition is not occurring presently, and it has not occurred since the last time the register was read. A latched low register, when read low, should be read again to distinguish if a condition occurred previously or is still occurring. If it occurred previously, the second read will read high. If it is still occurring, the second read will read low. Reading this register bit automatically sets its value to 1. COR: Clear-On-Read This register can only be read. Writing to this register bit has no effect. Reading from this register bit returns its current value, then resets its value to 0. Counter value freezes at Max. Following code letters in Name field of each control/status register bit(s) indicate the mode that they are applicable/valid. R = Indicates control/status bit(s) valid in 10GKR mode X = Indicates control/status bit(s) valid in 1GKX mode G = Indicates control/status bit(s) valid in 10G general purpose serdes mode 40 ADDITIONAL FEATURES Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 TLK10232 www.ti.com SLLSEE1 – MAY 2013 8 DEVICE REGISTERS 8.1 Vendor Specific Device Registers Below registers can be accessed directly through Clause 22 and Clause 45. In Clause 45 mode, these registers can be accessed by setting device address field to 0x1E (DA[4:0] = 5’b11110). In Clause 22 mode, these registers can be accessed by setting 5 bit register address field to same value as 5 LSB bits of Register Address field specified for each register. For example, 16 bit register address 0x001C in clause 45 mode can be accessed by setting register address field to 5’h1C in clause 22 mode. Table 8-1. GLOBAL_CONTROL_1 (1) Device Address: 0x1E SPACER Register Address:0x0000 SPACER Default: 0x0610 Bit(s) Name Description GLOBAL_RESET (RXG) Global reset. 0 = Normal operation (Default 1’b0) 1 = Resets TX and RX data path including MDIO registers. Equivalent to asserting RESET_N. RW SC (2) PRTAD0_PIN_EN_SEL[2:0] (RXG) PRTAD0 pin selection control. Valid only when 1E.0000 bit 5 is 1. PRTAD0 is used for the assignment specified below. 000 = Channel A stopwatch (Default 3’b000) 001 = Channel B stopwatch 010 = Channel A Tx data switch 011 = Channel A Rx data switch 100 = Channel B Tx data switch 101 = Channel B Rx data switch 11x = Reserved RW GLOBAL_WRITE (RXG) Global write enable. 0 = Control settings are specific to channel addressed (Default 1’b0) 1 = Control settings in channel specific registers are applied to all 4 channels regardless of channel addressed RW 10:7 RESERVED For TI use only (Default 5’b1100) RW 6 RESERVED For TI use only. Always reads 0. RW 5 PRTAD0_PIN_EN (RXG) PRTAD0 pin enable control. 0 = Input pin (PRTAD0) is used for the assignment specified in 1E.0000 bits 14:12 (Default 1’b0) 1 = Input pin (PRTAD0) is not used for the assignment specified in 1E.0000 bits 14:12 RW 15 14:12 11 4:0 (1) (2) Access PRBS_PASS_OVERLAY[4:0] PRBS_PASS pin status selection. Applicable only when PRBS test pattern (RXG) verification is enabled on HS side or LS side. PRBS_PASS pin reflects PRBS verification status on selected Channel HS/LS side. PRBS_PASS pin reflects PRBS verification status on selected Channel HS/LS side. LS Serdes lanes 1/2/3 are not applicable in 1GKX modes. 1xx00 = PRBS_PASS reflects combined status of Channel A/B HS serdes PRBS verification. If PRBS verification fails on any channel HS serdes, PRBS_PASS will be asserted low. (Default 5’b10000) 00000 = Status from Channel A HS Serdes side 00001 = Reserved 0001x = Reserved 00100 = Status from Channel A LS Serdes side Lane 0 00101 = Status from Channel A LS Serdes side Lane 1 00110 = Status from Channel A LS Serdes side Lane 2 00111 = Status from Channel A LS Serdes side Lane 3 01000 = Status from Channel B HS Serdes side 01001 = Reserved 0101x = Reserved 01100 = Status from Channel B LS Serdes side Lane 0 01101 = Status from Channel B LS Serdes side Lane 1 01110 = Status from Channel B LS Serdes side Lane 2 01111 = Status from Channel B LS Serdes side Lane 3 RW This global register is channel independent. After reset bit is set to one, it automatically sets itself back to zero on the next MDC clock cycle. DEVICE REGISTERS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 41 TLK10232 SLLSEE1 – MAY 2013 www.ti.com Table 8-2. CHANNEL_CONTROL_1 Device Address: 0x1E SPACER Register Address:0x0001 SPACER Default: 0x0B00 Bit(s) Name Description 15 POWERDOWN (RXG) Setting this bit high powers down entire data path with exception that MDIO interface stays active. 0 = Normal operation (Default 1’b0) 1 = Power Down mode is enabled. RW 14 LT_TRAINING_CONTROL (XG) Link training control. Valid in 10G and 1GKX modes only. 0 = Link training disabled(Default 1’b0) 1 = Link training enable control dependent on LT_TRAINING_ENABLE (1E.0036 bit 1). RW 13 10G_RX_MODE_SEL (G) RX mode selection. Valid in 10G only. 0 = RX mode dependent upon RX_DEMUX_SEL(Default 1’b0) 1 = Enables 1 to 1 mode on receive channel. RW 12 10G_TX_MODE_SEL (G) TX mode selection Valid in 10G only. 0 = TX mode dependent upon TX_MUX_SEL (Default 1’b0) 1 = Enables 1 to 1 mode on transmit channel. RW 11 SW_PCS_SEL (RX) Applicable in Clause 45 mode only. Valid only when MODE_SEL pin is 0, AN_ENABLE (07.0000 bit 12) is 0 and SW_DEV_MODE_SEL (1E.0001 bit 10) is 0. 1 = Set device to 10G-KR mode(Default 1’b1) 0 = Set device to 1G-KX mode RW 10 SW_DEV_MODE_SEL (RXG) Valid only when MODE_SEL pin is 0 1 = Device set to 10G mode 0 = In clause 45 mode, device mode is set using Auto negotiation. In clause 22 mode, device set to 1G-KX mode(Default 1’b0) RW 9 10G_RX_DEMUX_SEL (G) RX De-Mux selection control for lane de-serialization on receive channel. Valid in 10G and when 10G_RX_MODE_SEL (1E.0001 bit 13) is LOW 0 = 1 to 2 1 = 1 to 4 (Default 1’b1) RW 8 10G_TX_MUX_SEL (G) TX Mux selection control for lane serialization on transmit channel. Valid in 10G and when 10G_TX_MODE_SEL (1E.0001 bit 12) is LOW 0 = 2 to 1 1 = 4 to 1 (Default 1’b1) RW 7:2 Access RESERVED For TI use only RO 1 REFCLK_SW_SEL (RXG) Channel HS Reference clock selection. 0 = Selects REFCLK_0_P/N as clock reference to Channel x HS side serdes macro(Default 1’b0) 1 = Selects REFCLK_1_P/N as clock reference to Channel x HS side serdes macro RW 0 LS_REFCLK_SEL (RXG) Channel LS Reference clock selection. 0 = LS side serdes macro reference clock is same as HS side serdes reference clock (E.g. If REFCLK_0_P/N is selected as HS side serdes macro reference clock, REFCLK_0_P/N is selected as LS side serdes macro reference clock and vice versa) (Default 1’b0) 1 = Alternate reference clock is selected as clock reference to Channel x LS side serdes macro (E.g. If REFCLK_0_P/N is selected as HS side serdes macro reference clock, REFCLK_1_P/N is selected as LS side serdes macro reference clock and vice versa) RW Table 8-3. HS_SERDES_CONTROL_1 Device Address: 0x1E SPACER Register Address:0x0002 SPACER Default: 0x831D Bit(s) Name Description 15:10 RESERVED For TI use only (Default 6’b100000) RW HS_LOOP_BANDWIDT H[1:0] (RXG) HS Serdes PLL Loop Bandwidth settings 00 = Medium Bandwidth 01 = Low Bandwidth 10 = High Bandwidth 11 = Ultra High Bandwidth. (Default 2'b11) RW RESERVED For TI use only (Default 1’b0) RW 9:8 7 42 Access DEVICE REGISTERS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 TLK10232 www.ti.com SLLSEE1 – MAY 2013 Table 8-3. HS_SERDES_CONTROL_1 (continued) Device Address: 0x1E SPACER Register Address:0x0002 SPACER Default: 0x831D Bit(s) Name Description 6 HS_VRANGE (RXG) HS Serdes PLL VCO range selection. 0 = VCO runs at higher end of frequency range (Default 1’b0) 1 = VCO runs at lower end of frequency range This bit needs to be set HIGH if VCO frequency (REFCLK *HS_PLL_MULT) is below 2.5 Ghz. RW 5 RESERVED For TI use only (Default 1’b0) RW 4 HS_ENPLL (RXG) HS Serdes PLL enable control. HS Serdes PLL is automatically disabled when PD_TRXx_N is asserted LOW or when register bit 1E.0001 bit 15 is set HIGH. 0 = Disables PLL in HS serdes 1 = Enables PLL in HS serdes (Default 1’b1) RW HS_PLL_MULT[3:0] (RXG) HS Serdes PLL multiplier setting (Default 4’b1101). Refer : Table 8-4 HS PLL multiplier control RW 3:0 Access Table 8-4. HS PLL Multiplier Control HS_PLL_MULT[3:0] HS_PLL_MULT[3:0] Value PLL Multiplier factor Value 0000 Reserved 1000 PLL Multiplier factor 12x 0001 Reserved 1001 12.5x 0010 4x 1010 15x 0011 5x 1011 16x 0100 6x 1100 16.5x 0101 8x 1101 20x 0110 8.25x 1110 25x 0111 10x 1111 Reserved Table 8-5. HS_SERDES_CONTROL_2 Device Address: 0x1E SPACER Register Address:0x0003 SPACER Default:0xA848 Bit(s) Name Description Access 15:12 HS_SWING[3:0] (RXG) Transmitter Output swing control for HS Serdes. (Default 4’b1010) Refer Table 8-6. RW 11 HS_ENTX (RXG) HS Serdes transmitter enable control. HS Serdes transmitter is automatically disabled when PD_TRXx_N is asserted LOW or when register bit 1E.0001 bit 15 is set HIGH. 0 = Disables HS serdes transmitter 1 = Enables HS serdes transmitter (Default 1’b1) RW 10 HS_EQHLD (RXG) HSRX Equalizer hold control. 0 = Normal operation (Default 1’b0) 1 = Holds equalizer and long tail correction in its current state RW 9:8 HS_RATE_TX [1:0] (RXG) HS Serdes TX rate settings. 00 = Full rate (Default 2’b00) 01 = Half rate 10 = Quarter rate 11 = Eighth rate RW 7:6 HS_AGCCTRL[1:0] (RXG) Adaptive gain control loop. 00 = Attenuator will not change after lock has been achieved, even if AGC becomes unlocked 01 = Attenuator will not change when in lock state, but could change when AGC becomes unlocked (Default 2’b01) 10 = Force the attenuator off 11 = Force the attenuator on RW 5:4 HS_AZCAL[1:0] (RXG) Auto zero calibration. 00 = Auto zero calibration initiated when receiver is enabled (Default 2’b00) 01 = Auto zero calibration disabled 10 = Forced with automatic update. 11 = Forced without automatic update RW DEVICE REGISTERS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 43 TLK10232 SLLSEE1 – MAY 2013 www.ti.com Table 8-5. HS_SERDES_CONTROL_2 (continued) Device Address: 0x1E SPACER Register Address:0x0003 SPACER Default:0xA848 Bit(s) 3 2:0 Name Description Access HS_ENRX (RXG) HS Serdes receiver enable control. HS Serdes receiver is automatically disabled when PD_TRXx_N is asserted LOW or when register bit 1E.0001 bit 15 is set HIGH. 0 = Disables HS serdes receiver 1 = Enables HS serdes receiver (Default 1’b1) RW HS_RATE_RX [2:0] (RXG) HS Serdes RX rate settings. This setting is automatically controlled and value set through these register bits is ignored unless REFCLK_FREQ_SEL_1 or related OVERRIDE bit is set. 000 = Full rate (Default 3’b000) 101 = Half rate 110 = Quarter rate 111 = Eighth rate 001 = Reserved 01x = Reserved 100 = Reserved RW Table 8-6. HSTX AC Mode Output Swing Control HS_SWING[3:0] AC MODE TYPICAL AMPLITUDE (mVdfpp) 44 0000 130 0001 220 0010 300 0011 390 0100 480 0101 570 0110 660 0111 750 1000 830 1001 930 1010 1020 1011 1110 1100 1180 1101 1270 1110 1340 1111 1400 DEVICE REGISTERS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 TLK10232 www.ti.com SLLSEE1 – MAY 2013 Table 8-7. HS_SERDES_CONTROL_3 Device Address: 0x1E SPACER Register Address:0x0004 SPACER Default:0x1500 Bit(s) Name Description 15 HS_ENTRACK (RXG) HSRX ADC Track mode. 0 = Normal operation (Default 1’b0) 1 = Forces ADC into track mode Access RW 14:12 HS_EQPRE[2:0] (RXG) Serdes Rx precursor equalizer selection 000 = 1/9 cursor amplitude 001 = 3/9 cursor amplitude (Default 3’b001) 010 = 5/9 cursor amplitude 011 = 7/9 cursor amplitude 100 = 9/9 cursor amplitude 101 =11/9 cursor amplitude 110 = 13/9 cursor amplitude 111 = Disable RW 11:10 HS_CDRFMULT[1:0 Clock data recovery algorithm frequency multiplication selection (Default 2'b01) ] 00 = First order. Frequency offset tracking disabled (RXG) 01 = Second order. 1x mode 10 = Second order. 2x mode 11 = Reserved RW 9:8 HS_CDRTHR[1:0] (RXG) Clock data recovery algorithm threshold selection (Default 2'b01) 00 = Four vote threshold 01 = Eight vote threshold 10 = Sixteen vote threshold 11 = Thirty two vote threshold RW 7 RESERVED For TI use only (Default 1’b0) RW 6 HS_PEAK_DISABL E (RXG) HS Serdes PEAK_DISABLE control 0 = Normal operation (Default 1’b0) 1 = Disables high frequency peaking. Suitable for 32 24 26 12/8 11 High High High NA 10 Mid-high Mid High 01 Mid Low Low 00 Low Low Low RW 9 RX_Q_CNT_IPG (R) 0 = Normal operation. (Default 1’b0) 1 = Sequence columns are counted as IPG. RW 8 RX_CTC_Q_DROP_EN (R) 0 = Normal operation. (Default 1’b0) 1 = Enable Q column drop in RX CTC. RW 7 XMIT_IDLE (R) 1 = Transmit idle pattern onto LS side 0 = Normal operation (Default 1’b0) RW 70 DEVICE REGISTERS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 TLK10232 www.ti.com SLLSEE1 – MAY 2013 Table 8-81. KR_VS_FIFO_CONTROL_1 (continued) Device Address: 0x01 SPACER Register Address: 0x8001 SPACER Default: 0xCC4C Bit(s) Name Description 6:4 TX_FIFO_DEPTH[2:0] (R) Access Tx CTC FIFO depth selection 1xx = 32 deep (Default 3’b100)011 = 24 deep 010 = 16 deep001 = 12 deep 000 = 8 deep (No CTC function) RW Water mark selection for receive CTC Works in conjunction with TX_FIFO_DEPTH_SEL setting (Default 2’b11) 3:2 TX_CTC_WMK_SEL[1:0] (R) Depth-> 32 24 26 12/8 11 High High High NA 10 Mid-high Mid High 01 Mid Low Low 00 Low Low Low RW 1 TX_Q_CNT_IPG (R) 0 = Normal operation. (Default 1’b0) 1 = Sequence columns are counted as IPG. RW 0 TX_CTC_Q_DROP_EN (R) 0 = Normal operation. (Default 1’b0) 1 = Enable Q column drop in TX CTC. RW Table 8-82. KR_VS_TP_GEN_CONTROL Device Address: 0x01SPACER Register Address:0x8002SPACER Default: 0x0000 Bit(s) Name Description Access 15:6 RESERVED For TI use only. Always reads 0. RW 5:4 RX_TPG_HLM_TEST_SEL[1:0] (R) XAUI based test pattern selection on LS side. See Test pattern procedures for more information. 00 = High Frequency test pattern(Default 2’b00) 01 = Low Frequency test pattern 10 = Mixed Frequency test pattern 11 = Normal operation RW 3 RX_TPG_CRPAT_TEST_EN (R) XAUI based test pattern selection on LS side. See Test pattern procedures for more information. 0 = Normal operation. (Default 1’b0) 1 = Enables CRPAT test pattern generation RW 2 RX_TPG_CJPAT_TEST_EN (R) XAUI based test pattern selection on LS side. See Test pattern procedures for more information. 0 = Normal operation. (Default 1’b0) 1 = Enables CJPAT test pattern generation RW 1 RX_TPG_10GFC_TEST_EN (R) XAUI based test pattern selection on LS side. See Test pattern procedures for more information. 0 = Normal operation. (Default 1’b0) 1 = Enables 10 GFC CJPAT test pattern generation RW 0 RX_TPG_HLM_TEST_EN (R) XAUI based test pattern selection on LS side. See Test pattern procedures for more information. 0 = Normal operation. (Default 1’b0) 1 = Enables H/L/M test pattern generation RW Table 8-83. KR_VS_TP_VER_CONTROL Device Address: 0x01 SPACER Register Address:0x8003 SPACER Default: 0x0000 Bit(s) Name Description 15:14 RESERVED For TI use only. Always reads 0. RW TX_TPV_HLM_TEST_SEL[1:0] (R) XAUI based test pattern selection on LS side. See Test pattern procedures for more information. 00 = High Frequency test pattern(Default 2’b00) 01 = Low Frequency test pattern 10 = Mixed Frequency test pattern 11 = Normal operation RW 13:12 Access DEVICE REGISTERS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 71 TLK10232 SLLSEE1 – MAY 2013 www.ti.com Table 8-83. KR_VS_TP_VER_CONTROL (continued) Device Address: 0x01 SPACER Register Address:0x8003 SPACER Default: 0x0000 Bit(s) Name Description Access 11 TX_TPV_CRPAT_TEST_EN (R) XAUI based test pattern selection on LS side. See Test pattern procedures for more information. 0 = Normal operation. (Default 1’b0) 1 = Enables CRPAT test pattern verification RW 10 TX_TPV_CJPAT_TEST_EN (R) XAUI based test pattern selection on LS side. See Test pattern procedures for more information. 0 = Normal operation. (Default 1’b0) 1 = Enables CJPAT test pattern verification RW 9 TX_TPV_10GFC_TEST_EN (R) XAUI based test pattern selection on LS side. See Test pattern procedures for more information. 0 = Normal operation. (Default 1’b0) 1 = Enables 10 GFC CJPAT test pattern verification RW 8 TX_TPV_HLM_TEST_EN (R) XAUI based test pattern selection on LS side. See Test pattern procedures for more information. 0 = Normal operation. (Default 1’b0) 1 = Enables HL/M test pattern verification RW 7:0 RESERVED For TI use only(Default 8’b00000000) RW Table 8-84. KR_VS_CTC_ERR_CODE_LN0 Device Address: 0x01 SPACER Register Address: 0x8005 SPACER Default: 0xCE00 Bit(s) Name Description 15:7 KR_CTC_ERR_CODE_LN0 (R) Applicable in 10G-KR mode only. XGMII code to be transmitted in case of error condition. This applies to both TX and RX data paths. The msb is the control bit; remaining 8 bits constitute the error code. The default value for lane 0 corresponds to 8’h9C with the control bit being 1’b1. The default values for lanes 0~3 correspond to ||LF|| Access RW 6:0 RESERVED For TI use only. Always reads 0. RW Table 8-85. KR_VS_CTC_ERR_CODE_LN1 Device Address: 0x01 SPACER Register Address: 0x8006 SPACER Default: 0x0000 Bit(s) Name Description 15:7 KR_CTC_ERR_CODE_LN1 (R) Applicable in 10G-KR mode only. XGMII code to be transmitted in case of error condition. This applies to both TX and RX data paths. The msb is the control bit; remaining 8 bits constitute the error code. The default value for lane 1 corresponds to 8’h00 with the control bit being 1’b0. The default values for lanes 0~3 correspond to ||LF|| Access RW 6:0 RESERVED For TI use only. Always reads 0. RW Table 8-86. KR_VS_CTC_ERR_CODE_LN2 Device Address: 0x01 SPACER Register Address: 0x8007 SPACER Default: 0x0000 Bit(s) Acces s Name Description 15:7 KR_CTC_ERR_CODE_LN2 (R) Applicable in 10G-KR mode only. XGMII code to be transmitted in case of error condition. This applies to both TX and RX data paths. The msb is the control bit; remaining 8 bits constitute the error code. The default value for lane 2 corresponds to 8’h00 with the control bit being 1’b0. The default values for lanes 0~3 correspond to ||LF|| RW 6:0 RESERVED For TI use only. Always reads 0. RW 72 DEVICE REGISTERS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 TLK10232 www.ti.com SLLSEE1 – MAY 2013 Table 8-87. KR_VS_CTC_ERR_CODE_LN3 Device Address: 0x01 SPACER Register Address: 0x8008 SPACER Default: 0x0080 Bit(s) Acces s Name Description 15:7 KR_CTC_ERR_CODE_LN3 (R) Applicable in 10G-KR mode only. XGMII code to be transmitted in case of error condition. This applies to both TX and RX data paths. The msb is the control bit; remaining 8 bits constitute the error code. The default value for lane 3 corresponds to 8’h01 with the control bit being 1’b0. The default values for lanes 0~3 correspond to ||LF|| RW 6:0 RESERVED For TI use only. Always reads 0. RW Table 8-88. KR_VS_LN0_EOP_ERROR_COUNTER Device Address: 0x01 SPACER Register Address: 0x8010 SPACER Default: 0xFFFD Bit(s) Name 15:0 KR_LN0_EOP_ERR_COUNT Lane 0 End of packet Error counter. (R) End of packet error is detected when Terminate character is in lane 0 and one or both of the following holds: Description Access COR ●Terminate character is not followed by /K/ characters in lanes 1, 2 and 3 ●The column following the terminate column is neither ||K|| nor ||A||. Counter value cleared to 16’h0000 when read. Table 8-89. KR_VS_LN1_EOP_ERROR_COUNTER Device Address: 0x01 SPACER Register Address: 0x8011 SPACER Default: 0xFFFD Bit(s) Name Description 15:0 KR_LN1_EOP_ERR_COUN T (R) Lane 1 End of packet Error counter. End of packet error is detected when Terminate character is in lane 1 and one or both of the following holds: Access COR ● Terminate character is not followed by /K/ characters in lanes 2 and 3 ● The column following the terminate column is neither ||K|| nor ||A||. Counter value cleared to 16’h0000 when read. Table 8-90. KR_VS_LN2_EOP_ERROR_COUNTER Device Address: 0x01 SPACER Register Address: 0x8012 SPACER Default: 0xFFFD Bit(s) Name Description 15:0 KR_LN2_EOP_ERR_COU NT (R) Lane 2 End of packet Error counter. End of packet error is detected when Terminate character is in lane 2 and one or both of the following holds: Access COR ● Terminate character is not followed by /K/ characters in lane 3 ● The column following the terminate column is neither ||K|| nor ||A||. Counter value cleared to 16’h0000 when read. Table 8-91. KR_VS_LN3_EOP_ERROR_COUNTER Device Address: 0x01 SPACER Register Address: 0x8013 SPACER Default: 0xFFFD Bit(s) Name Description 15:0 KR_LN3_EOP_ERR_COUNT (R) Lane 3 End of packet Error counter. End of packet error is detected when Terminate character is in lane 3 and the column following the terminate column is neither ||K|| nor ||A||. Counter value cleared to 16’h0000 when read. Access DEVICE REGISTERS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 COR 73 TLK10232 SLLSEE1 – MAY 2013 www.ti.com Table 8-92. KR_VS_TX_CTC_DROP_COUNT Device Address: 0x01 SPACER Register Address: 0x8014 SPACER Default: 0xFFFD Bit(s) Name Description 15:0 TX_CTC_DROP_COUNT (R) Counter for number of idle drops in the transmit CTC. Access COR Table 8-93. KR_VS_TX_CTC_INSERT_COUNT Device Address: 0x01 SPACER Register Address: 0x8015 SPACER Default: 0xFFFD Bit(s) Name Description 15:0 TX_CTC_INS_COUNT (R) Counter for number of idle inserts in the transmit CTC. Access COR Table 8-94. KR_VS_RX_CTC_DROP_COUNT Device Address: 0x01 SPACER Register Address: 0x8016 SPACER Default: 0xFFFD Bit(s) Name Description Access 15:0 RX_CTC_DROP_COUNT (R) Counter for number of idle drops in the receive CTC. COR Table 8-95. KR_VS_RX_CTC_INSERT_COUNT Device Address: 0x01 SPACER Register Address: 0x8017 SPACER Default: 0xFFFD Bit(s) Name Description 15:0 RX_CTC_INS_COUNT (R) Counter for number of idle inserts in the receive CTC. Access COR Table 8-96. KR_VS_STATUS_1 Device Address: 0x01 SPACER Register Address: 0x8018 SPACER Default: 0x0000 Bit(s) Name Description 15 TX_TPV_TP_SYNC (R) 0 = Test pattern sync is not achieved on on Tx side 1 = Test pattern sync is achieved on on Tx side Access 11 RESERVED For TI use only 5 INVALID_S_COL_ERR (R) 1 = Indicates invalid start (S) column error detected 4 INVALID_T_COL_ERR (R) 1 = Indicates invalid terminate (T) column error detected 3 INVALID_XGMII_LN3 (R) 1 = Indicates invalid XGMII character detected in Lane 3 2 INVALID_XGMII_LN2 (R) 1 = Indicates invalid XGMII character detected in Lane 2 1 INVALID_XGMII_LN1 (R) 1 = Indicates invalid XGMII character detected in Lane 1 0 INVALID_XGMII_LN0 (R) 1 = Indicates invalid XGMII character detected in Lane 0 RO RO/LH Table 8-97. KR_VS_TX_CRCJ_ERR_COUNT_1 Device Address: 0x01 SPACER Register Address: 0x8019 SPACER Default: 0xFFFF Bit(s) Name Description 15:0 TX_TPV_CR_CJ_ERR_COUNT[31:16] (R) Error Counter for CR/CJ test pattern verification on Tx side. MSBs [31:16] 74 DEVICE REGISTERS Access COR Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 TLK10232 www.ti.com SLLSEE1 – MAY 2013 Table 8-98. KR_VS_TX_CRCJ_ERR_COUNT_2 Device Address: 0x01 SPACER Register Address: 0x801A SPACER Default: 0xFFFD Bit(s) Name Description 15:0 TX_TPV_CR_CJ_ERR_COUNT[15:0] (R) Error Counter for CR/CJ test pattern verification on Tx side LSBs [15:0] Access COR Table 8-99. KR_VS_TX_LN0_HLM_ERR_COUNT Device Address: 0x01 SPACER Register Address: 0x801B SPACER Default: 0xFFFD Bit(s) Name Description 15:0 TX_TPV_LN0_ERR_COUNT[15:0] (R) Error Counter for H/L/M test pattern verification on Lane 0 of Tx side Access COR Table 8-100. KR_VS_TX_LN1_HLM_ERR_COUNT Device Address: 0x01 SPACER Register Address: 0x801C SPACER Default: 0xFFFD Bit(s) Name Description Access 15:0 TX_TPV_LN1_ERR_COUNT[15:0] (R) Error Counter for H/L/M test pattern verification on Lane 1 of Tx side COR Table 8-101. KR_VS_TX_LN2_HLM_ERR_COUNT Device Address: 0x01 SPACER Register Address: 0x801D SPACER Default: 0xFFFD Bit(s) Name Description 15:0 TX_TPV_LN2_ERR_COUNT[15:0] (R) Error Counter for H/L/M test pattern verification on Lane 2 of Tx side Access COR Table 8-102. KR_VS_TX_LN3_HLM_ERR_COUNT Device Address: 0x01 SPACER Register Address: 0x801E SPACER Default: 0xFFFD Bit(s) Name Description 15:0 TX_TPV_LN3_ERR_COUNT[15:0] (R) Error Counter for H/L/M test pattern verification on Lane 3 of Tx side Access COR Table 8-103. LT_VS_CONTROL_2 Device Address: 0x01 SPACER Register Address: 0x9001 SPACER Default: 0x0000 Bit(s) Name Description 15:14 RESERVED For TI use only (Default 2'b00) Access RW 13:12 RESERVED For TI use only (Default 2'b00) RW/SC 11:9 AP_SEARCH_MODE[2:0] (RXG) 000 = Auto search, autotrain disabled (Default 3'b000) 001 = Full region search, autotrain disabled 010 = Auto search, autotrain enabled 011 = Full region search, autotrain enabled 1xx = Manual search RW 8:0 RESERVED For TI use only (Default 9'b000000000) RW DEVICE REGISTERS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 75 TLK10232 SLLSEE1 – MAY 2013 8.3 www.ti.com PCS Registers The registers below can be accessed only in Clause 45 mode and with device address field set to 0x03 (DEVADD [4:0] = 5’b00011). Valid only when device is in 10GBASE-KR mode. Table 8-104. PCS_CONTROL Device Address: 0x03 SPACER Register Address: 0x0000 SPACER Default: 0x0000 Bit(s) Name Description Access 15 PCS_RESET (R) 1 = Resets datapath and MDIO registers of all channels. Equivalent to asserting RESET_N. 0 = Normal operation (Default 1’b0) RW/SC 14 PCS_LOOPBACK (R) 1 = Enables PCS loopback 0 = Normal operation (Default 1’b0) Requires Auto Negotiation and Link Training to be disabled. RW 13:12 RESERVED For TI use only. Always reads 0. RW 11 PCS_LP_MODE (R) 1 = Enable power down mode 0 = Normal operation (Default 1’b0) RW 10:0 RESERVED For TI use only. Always reads 0. RW Table 8-105. PCS_STATUS_1 Device Address: 0x03 SPACER Register Address: 0x0001 SPACER Default: 0x0002 Bit(s) Name Description 7 PCS_FAULT (R) 1 = Fault condition detected on either PCS TX or PCS RX 0 = No fault condition detected This bit is cleared after Register 03.0008 is read and no fault condition occurs after 03.0008 is read. Access 2 PCS_RX_LINK (R) 1 = PCS receive link is up 0 = PCS receive link is down 1 PCS_LP_ABILITY (R) Always reads 1. 1 = Supports low power mode 0 = Does not support low power mode RO RO/LL RO Table 8-106. PCS_STATUS_2 Device Address: 0x03 SPACER Register Address: 0x0008 SPACER Default: 0x8001 Bit(s) Name Description 15:14 DEV_PRESENT (R) Always reads 2’b10. 0x = No device responding at this address 10 = Device responding at this address 11 = No device responding at this address Access 11 PCS_TX_FAULT (R) 1 = Fault condition detected on transmit path 0 = No fault condition detected on transmit path RO/LH 10 PCS_RX_FAULT (R) 1 = Fault condition detected on receive path 0 = No fault condition detected on receive path RO/LH 0 PCS_10GBASER_CAPABLE (R) Always reads 1. 1 = PCS is able to support 10GBASE-R PCS type 0 = PCS not able to support 10GBASE-R PCS type RO RO Table 8-107. KR_PCS_STATUS_1 Device Address: 0x03 SPACER Register Address: 0x0020 SPACER Default: 0x0004 Bit(s) Name Description 12 PCS_RX_LINK_STATUS (R) 1 = 10GBASE-R PCS receive link up 0 = 10GBASE-R PCS receive link down RO 2 PCS_PRBS31_ABILITY (R) Always reads 1. 1 = PCS is able to support PRBS31 pattern testing 0 = PCS is not able to support PRBS31 testing RO 76 DEVICE REGISTERS Access Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 TLK10232 www.ti.com SLLSEE1 – MAY 2013 Table 8-107. KR_PCS_STATUS_1 (continued) Device Address: 0x03 SPACER Register Address: 0x0020 SPACER Default: 0x0004 Bit(s) Name Description Access 1 PCS_HI_BER (R) 1 = High BER condition detected 0 = High BER condition not detected RO 0 PCS_BLOCK_LOCK (R) 1 = PCS locked to receive blocks 0 = PCS not locked to receive blocks RO Table 8-108. KR_PCS_STATUS_2 Device Address: 0x03 SPACER Register Address: 0x0021 SPACER Default: 0x0000 Bit(s) Name Description 15 PCS_BLOCK_LOCK_LL (R) 1 = PCS locked to receive blocks 0 = PCS not locked to receive blocks Access RO/LL 14 PCS_HI_BER_LH (R) 1 = High BER condition detected 0 = High BER condition not detected RO/LH 13:8 PCS_BER_COUNT[5:0] (R) Value indicating number of times BER state machine enters BER_BAD_SH state COR 7:0 PCS_ERR_BLOCK_COUNT[7:0] (R) Value indicating number of times RX decode state machine enters RX_E state. Same value is also reflected in 1E.0010 and reading either register clears the counter value. COR Table 8-109. PCS_TP_SEED_A0 Device Address: 0x03 SPACER Register Address: 0x0022 SPACER Default: 0x0000 Bit(s) Name Description 15:0 PCS_TP_SEED_A[15:0] (R) Test pattern seed A bits 15-0 Access RW Table 8-110. PCS_TP_SEED_A1 Device Address: 0x03 SPACER Register Address: 0x0023 SPACER Default: 0x0000 Bit(s) Name Description 15:0 PCS_TP_SEED_A[31:16] (R) Test pattern seed A bits 31-16 Access RW Table 8-111. PCS_TP_SEED_A2 Device Address: 0x03 SPACER Register Address: 0x0024 SPACER Default: 0x0000 Bit(s) Name Description 15:0 PCS_TP_SEED_A[47:32] (R) Test pattern seed A bits 47-32 Access RW Table 8-112. PCS_TP_SEED_A3 Device Address: 0x03 SPACER Register Address: 0x0025 SPACER Default: 0x0000 Bit(s) Name Description 15:10 RESERVED For TI use only. Always reads 0. Access RW 9:0 PCS_TP_SEED_A[57:48] (R) Test pattern seed A bits 57-48 RW Table 8-113. PCS_TP_SEED_B0 Device Address: 0x03 SPACER Register Address: 0x0026 SPACER Default: 0x0000 Bit(s) Name Description 15:0 PCS_TP_SEED_B[15:0] (R) Test pattern seed B bits 15-0 Access RW DEVICE REGISTERS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 77 TLK10232 SLLSEE1 – MAY 2013 www.ti.com Table 8-114. PCS_TP_SEED_B1 Device Address: 0x03 SPACER Register Address: 0x0027 SPACER Default: 0x0000 Bit(s) Name Description 15:0 PCS_TP_SEED_B[31:16] (R) Test pattern seed B bits 31-16 Access RW Table 8-115. PCS_TP_SEED_B2 Device Address: 0x03 SPACER Register Address: 0x0028 SPACER Default: 0x0000 Bit(s) Name Description 15:0 PCS_TP_SEED_B[47:32] (R) Test pattern seed B bits 47-32 Access RW Table 8-116. PCS_TP_SEED_B3 Device Address: 0x03 SPACER Register Address: 0x0029 SPACER Default: 0x0000 Bit(s) Name Description Access 15:10 RESERVED For TI use only. Always reads 0. RW 9:0 PCS_TP_SEED_B[57:48] (R) Test pattern seed B bits 57-48 RW Table 8-117. PCS_TP_CONTROL Device Address: 0x03 SPACER Register Address: 0x002A SPACER Default: 0x0000 Bit(s) Name Description Access 15:6 RESERVED For TI use only. Always reads 0. RW 5 PCS_PRBS31_RX_TP_EN (R) 1 = Enable PRBS31 test pattern verification on receive path 0 = Normal operation (Default 1’b0) RW 4 PCS_PRBS31_TX_TP_EN (R) 1 = Enable PRBS31 test pattern generation on transmit path 0 = Normal operation (Default 1’b0) RW 3 PCS_TX_TP_EN (R) 1 = Enable transmit test pattern generation 0 = Normal operation (Default 1’b0) RW 2 PCS_RX_TP_EN (R) 1 = Enable receive test pattern verification 0 = Normal operation (Default 1’b0) RW 1 PCS_TP_SEL (R) 1 = Square wave test pattern 0 = Pseudo random test pattern (Default 1’b0) RW 0 PCS_DP_SEL (R) 1 = 0’S data pattern 0 = LF data pattern (Default 1’b0) RW Table 8-118. PCS_TP_ERR_COUNT Device Address: 0x03 SPACER Register Address: 0x002B SPACER Default: 0x0000 Bit(s) Name 15:0 PCS_TP_ERR_COUNT[15:0] Test pattern error counter. This counter reflects number of errors occurred during (R) the test pattern mode selected through PCS_TP_CONTROL. In PRBS31 test pattern verification mode, counter value indicates the number of received bytes that have 1 or more bit errors. Description Access COR Table 8-119. PCS_VS_CONTROL Device Address: 0x03 SPACER Register Address: 0x8000 SPACER Default: 0x00B0 Bit(s) Name Description Access 15:8 RESERVED For TI use only. Always reads 0. RW 7:4 PCS_SQWAVE_N (R) Sets number of repeating 0’s followed by repeating 1’s during square wave test pattern generation mode (Default 4’1011) RW 3 RESERVED For TI use only (Default 1’b0) RW 78 DEVICE REGISTERS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 TLK10232 www.ti.com SLLSEE1 – MAY 2013 Table 8-119. PCS_VS_CONTROL (continued) Device Address: 0x03 SPACER Register Address: 0x8000 SPACER Default: 0x00B0 Bit(s) Name Description Access 2 PCS_RX_DEC_CTRL_CHAR PCS RX Decode control character selection. Determines what control characters (R) are passed 0 = A/K/R control characters are changed to Idles. Reserved characters passed through (Default 1’b0) 1 = A/K/R control characters are passed through as is RW RW 1 PCS_DESCR_DISABLE (R) De-scrambler control in 10GKR RX PCS 1 = Disable descrambler 0 = Enable descrambler (Default 1’b0) RW 0 PCS_SCR_DISABLE (R) Scrambler control in 10GKR TX PCS 1 = Disable scrambler 0 = Enable scrambler (Default 1’b0) RW Table 8-120. PCS_VS_STATUS Device Address: 0x03 SPACER Register Address: 0x8010 SPACER Default: 0x00FD Bit(s) Name Description Access 13 UNCORR_ERR_STATUS (R) 1 = Uncorrectable block error found RO/LH 12 CORR_ERR_STATUS (R) 1 = Correctable block error found RO/LH 8 PCS_TP_ERR (R) PCS test pattern verification status PCS_SCR_DISABLE 1 = Error occurred during pseudo random test pattern verification Number of errors can be checked by reading PCS_TP_ERR_COUNT (03.002B) register RO/LH 7:0 RESERVED For TI use only. 8.4 COR Auto-Negotiation Registers The registers below can be accessed only in Clause 45 mode and with device address field set to 0x07 (DA[4:0] = 5’b00111) Table 8-121. AN_CONTROL Device Address: 0x07 SPACER Register Address: 0x0000 SPACER Default: 0x3000 Bit(s) Name Description Access 15 AN_RESET (RX) 1 = Resets Auto Negotiation 0 = Normal operation (Default 1’b0) RW/SC 14 RESERVED For TI use only. Always reads 0. RW 13 RESERVED For TI use only (Default 1’b1) RW 12 AN_ENABLE (RX) 1 = Enable Auto Negotiation (Default 1’b1) 0 = Disable Auto Negotiation RW 11:10 RESERVED For TI use only. Always reads 0. RW 9 AN_RESTART (RX) 1 = Restart Auto Negotiation 0 = Normal operation (Default 1’b0) If set, a read of this register is required to clear AN_RESTART bit. RESERVED For TI use only. Always reads 0. 8:0 (1) RW/SC (1) RW If set, a read of register 07.0000 is required to clear AN_RESTART bit. Table 8-122. AN_STATUS Device Address: 0x07 SPACER Register Address: 0x0001 SPACER Default: 0x0088 Bit(s) Name Description Access 9 AN_PAR_DET_FAULT (RX) 1 = Fault has been detected via parallel detection function 0 = Fault has not been detected via parallel detection function RO/LH 7 AN_EXP_NP_STATUS (RX) 1 = Extended next page is used 0 = Extended next page is not allowed RO DEVICE REGISTERS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 79 TLK10232 SLLSEE1 – MAY 2013 www.ti.com Table 8-122. AN_STATUS (continued) Device Address: 0x07 SPACER Register Address: 0x0001 SPACER Default: 0x0088 Bit(s) Name Description Access 6 AN_PAGE_RCVD (RX) 1 = A page has been received 0 = A page has not been received RO/LH 5 AN_COMPLETE (RX) 1 = Auto Negotiation process is completed 0 = Auto Negotiation process not completed 4 REMOTE_FAULT (RX) 1 = Remote fault detected by AN 0 = Remote fault not detected by AN 3 AN_ABILITY (RX) Always reads 1. 1 = Device is able to perform Auto Negotiation 0 = Device not able to perform Auto Negotiation 2 LINK_STATUS (RX) 1 = Link is up 0 = Link is down 0 AN_LP_ABILITY (RX) 1 = LP is able to perform Auto Negotiation 0 = LP not able to perform Auto Negotiation RO RO/LH RO RO/LL RO Table 8-123. AN_DEV_PACKAGE Device Address: 0x07 SPACER Register Address: 0x0005 SPACER Default: 0x0080 Bit(s) Name Description Access 7 AN_PRESENT (RX) Always reads 1 1 = Auto Negotiation present in the package 0 = Auto Negotiation not present in the package RO Table 8-124. AN_ADVERTISEMENT_1 Device Address: 0x07 SPACER Register Address: 0x0010 SPACER Default: 0x1001 Bit(s) Name Description Access 15 AN_NEXT_PAGE (RX) NP bit (D15) in base link codeword 1 = Next page available 0 = Next page not available (Default 1’b0) RW 14 AN_ACKNOWLEDGE (RX) Acknowledge bit (D14) in base link codeword. Always reads 0. RO 13 AN_REMOTE_FAULT (RX) RF bit (D13) in base link codeword 1 = Sets RF bit to 1 0 = Normal operation (Default 1’b0) RW 12:10 AN_CAPABILITY[2:0] (RX) Value to be set in D12:D10 bits of the base link codeword. Consists of abilities like PAUSE, ASM_DIR (Default 3’b100) RW 9:5 AN_ECHO_NONCE[4:0] (RX) Value to be set in D9:D5 bits of the base link codeword. Consists of Echo nonce value. Transmitted in base page only until local device and link Partner have exchanged unique Nonce values, at which time transmitted Echoed Nonce will change to Link Partner's Nonce value. Read value always reflects the value written, not the actual Echoed Nonce. (Default 5’b00000) RW 4:0 AN_SELECTOR[4:0] (RX) Value to be set in D4:D0 bits of the base link codeword. Consists of selector field value (Default 5’b00001) RW Table 8-125. AN_ADVERTISEMENT_2 Device Address: 0x07 SPACER Register Address: 0x0011 SPACER Default: 0x0080 Bit(s) Name Description 15:8 AN_ABILITY[10:3] (RX) Value to be set in D31:D24 bits of the base link codeword. Consists of technology ability field bits [10:3] (Default 9’b000000000) RW 7 AN_ABILITY[2] (RX) Value to be set in D23 bits of the base link codeword. Consists of technology ability field bits [2]. When set, indicates device supports 10GBASE-KR (Default 1’b1) RW 6 AN_ABILITY[1] (RX) Value to be set in D22 bits of the base link codeword. Consists of technology ability field bits [1]. Always set to 0 (Default 1’b0) RW 80 DEVICE REGISTERS Access Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 TLK10232 www.ti.com SLLSEE1 – MAY 2013 Table 8-125. AN_ADVERTISEMENT_2 (continued) Device Address: 0x07 SPACER Register Address: 0x0011 SPACER Default: 0x0080 Bit(s) Name Description Access 5 AN_ABILITY[0] (RX) Value to be set in D21 bits of the base link codeword. Consists of technology ability field bit [0]. When set, indicates device supports 1000BASE-KX (Default 1’b0) RW 4:0 AN_TRANS_NONCE_ FIELD[4:0] (RX) Not used. Transmitted Nonce field is generated by hardware random number generator. Read value always reflects value written, not the actual Transmitted Nonce (Default 5’b00000) RW Table 8-126. AN_ADVERTISEMENT_3 Device Address: 0x07 SPACER Register Address: 0x0012 SPACER Default: 0x4000 Bit(s) Name Description Access 15 AN_FEC_REQUESTED (RX) Value to be set in D47 bits of the base link codeword. When set, indicates a request to enable FEC on the link (Default 1’b0) 14 AN_FEC_ABILITY (RX) Value to be set in D46 bits of the base link codeword. When set, indicates 10GBASE-KR has FEC ability (Default 1’b1) 13:0 AN_ABILITY[24:11] (RX) Value to be set in D45:D32 bits of the base link codeword. Consists of technology ability field bits [24:11] (Default 14’b00000000000000) RW Table 8-127. AN_LP_ADVERTISEMENT_1 (1) Device Address: 0x07 SPACER Register Address: 0x0013 SPACER Default: 0x0001 Bit(s) Name Description 15 AN_LP_NEXT_PAGE (RX) NP bit (D15) in link partner base page 1 = Next page available in link partner 0 = Next page not available in link partner RO 14 AN_LP_ACKNOWLEDGE (RX) Acknowledge bit (D14) in link partner base page. RO 13 AN_LP_REMOTE_FAULT (RX) RF bit (D13) in link partner base page 1 = Remote fault detected in link partner 0 = Remote fault not detected in link partner RO 12:10 AN_ LP_CAPABILITY (RX) D12:D10 bits of the link partner base page. Consists of abilities like PAUSE, ASM_DIR RO 9:5 AN_ LP_ECHO_NONCE (RX) D9:D5 bits of the link partner base page. Consists of Echo nonce value RO 4:0 AN_LP_SELECTOR[4:0] (RX) D4:D0 bits of the link partner base page. Consists of selector field value Always reads 5’b00001 RO (1) Access To get accurate AN_LP_ADVERTISEMENT read value, Register 07.0013 should be read first before reading 07.0014 and 07.0015 Table 8-128. AN_LP_ADVERTISEMENT_2 Device Address: 0x07 SPACER Register Address: 0x0014 SPACER Default: 0x0000 Bit(s) Name Description 15:8 AN_ LP_ABILITY[10:3] (RX) D31:D24 bits of the link partner base page. Consists of technology ability field bits [10:3] Access 7 AN_LP_ABILITY[2] (RX) D23 bits of the link partner base page. Consists of technology ability field bits [2]. When high, indicates link partner supports 10GBASE-KR 6 AN_LP_ABILITY[1] (RX) D22 bits of the link partner base page. Consists of technology ability field bits [1]. 5 AN_LP_ABILITY[0] (RX) D21 bits of the link partner base page. Consists of technology ability field bit [0]. When high, indicates link partner supports 1000BASE-KX 4:0 AN_LP_TRANS_NONCE_ FIELD (RX) D20:D16 bits of the link partner base page. Consists of transmitted nonce value DEVICE REGISTERS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 RO 81 TLK10232 SLLSEE1 – MAY 2013 www.ti.com Table 8-129. AN_LP_ADVERTISEMENT_3 Device Address: 0x07 SPACER Register Address: 0x0015 SPACER Default: 0x0000 Bit(s) Name Description 15 AN_LP_FEC_REQUESTED (RX) D47 bits of the link partner base page. When high, indicates link partner request to enable FEC on the link Access 14 AN_LP_FEC_ABILITY (RX) D46 bits of the link partner base page. When high, indicates link partner has FEC ability 13:0 AN_LP_ABILITY[24:11] (RX) D45:D32 bits of the link partner base page. Consists of link partner technology ability field bits [24:11] RO Table 8-130. AN_XNP_TRANSMIT_1 Device Address: 0x07 SPACER Register Address: 0x0016 SPACER Default: 0x2000 Bit(s) Name Description 15 AN_XNP_NEXT_PAGE (RX) NP bit (D15) in next page code word 1 = Next page available 0 = Next page not available (Default 1’b0) Access 14 RESERVED Always reads 0. RO 13 AN_MP (RX) Message page bit (D13) in next page code word 1 = Sets MP bit to 1 indicating next page is a message page (Default 1’b1) 0 = Sets MP bit to 0 indicating next page is unformatted next page RW 12 AN_ACKNOWLEDGE_2 (RX) Value to be set in D12 bit of the next page code word. When set, indicates device is able to act on the information defined in the message (Default 1’b0) RW 11 AN_TOGGLE (RX) Not used. Toggle value is generated by hardware. Read value always reflects value written, not the actual Toggle field (Default 1’b0) RW 10:0 AN_CODE_FIELD (RX) Value to be set in D10:D0 bits of the next page code word. Consists of Message/Unformatted code field value (Default 11’b00000000000) RW RW Table 8-131. AN_XNP_TRANSMIT_2 Device Address: 0x07 SPACER Register Address: 0x0017 SPACER Default: 0x0000 Bit(s) Name Description Access 15:0 AN_MSG_CODE_1 (RX) Value to be set in D31:D16 bits of the next page code word. Consists of Message/Unformatted code field value (Default 16’b0000000000000000) RW Table 8-132. AN_XNP_TRANSMIT_3 Device Address: 0x07 SPACER Register Address: 0x0018 SPACER Default: 0x0000 Bit(s) Name Description 15:0 AN_MSG_CODE_2 (RX) Value to be set in D47:D32 bits of the next page code word. Consists of Message/Unformatted code field value (Default 16’b0000000000000000) Access RW Table 8-133. AN_LP_XNP_ABILITY_1 (1) Device Address: 0x07 SPACER Register Address: 0x0019 SPACER Default: 0x0000 Bit(s) Name Description 15 AN_LP_XNP_NEXT_PAGE (RX) NP bit (D15) in next page code word 1 = Next page available 0 = Next page not available (Default 1’b0) RO 14 AN_LP_XNP_ACKNOWLEDGE (RX) Value in D14 bit of the next page code word. When set, indicates device is able to act on the information defined in the message (Default 1’b0) RO 13 AN_LP_MP (RX) Message page bit (D13) in next page code word 1 = Sets MP bit to 1 indicating next page is a message page 0 = Sets MP bit to 0 indicating next page is unformatted next page (Default 1’b0) RO 12 AN_LP_ACKNOWLEDGE_2 (RX) Value in D12 bit of the next page code word. When set, indicates device is able to act on the information defined in the message (Default 1’b0) RO (1) 82 Access To get accurate AN_LP_XNP_ABILITYT read value, Register 07.0019 should be read first before reading 07.001A and 07.001B DEVICE REGISTERS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 TLK10232 www.ti.com SLLSEE1 – MAY 2013 Table 8-133. AN_LP_XNP_ABILITY_1(1) (continued) Device Address: 0x07 SPACER Register Address: 0x0019 SPACER Default: 0x0000 Bit(s) Name Description Access 11 AN_LP_TOGGLE (RX) Value of D11 bit of the next page code word. Consists of Toggle field value(Default 1’b0) RO 10:0 AN_ LP_CODE_FIELD (RX) Value in D10:D0 bits of the next page code word. Consists of Message/Unformatted code field value (Default 11’b00000000000) RO Table 8-134. AN_LP_XNP_ABILITY_2 Device Address: 0x07 SPACER Register Address: 0x001A SPACER Default: 0x0000 Bit(s) Name Description 15:0 AN_LP_MSG_CODE_1 (RX) Value to be set in D31:D16 bits of the next page code word. Consists of Message/Unformatted code field value (Default 16’b0000000000000000) Access RO Table 8-135. AN_LP_XNP_ABILITY_3 Device Address: 0x07 SPACER Register Address: 0x001B SPACER Default: 0x0000 Bit(s) Name Description 15:0 AN_LP_MSG_CODE_2 (RX) Value to be set in D47:D32 bits of the next page code word. Consists of Message/Unformatted code field value (Default 16’b0000000000000000) Access RO Table 8-136. AN_BP_STATUS Device Address: 0x07 SPACER Register Address: 0x0030 SPACER Default: 0x0001 Bit(s) Name Description Access 4 AN_10G_KR_FEC (RX) 1 = PMA/PMD is negotiated to perform 10GBASE-KR FEC 3 AN_10G_KR (RX) 1 = PMA/PMD is negotiated to perform 10GBASE-KR 1 AN_1G_KX (RX) 1 = PMA/PMD is negotiated to perform 1000BASE-KX 0 AN_BP_AN_ABILITY (RX) Always reads 1. 1 = Indicates 1000BASE-KX, 10GBASE-KR is implemented RO Table 8-137. TI_Reserved Control and Status Registers Register Name Register Address Default Value Access Register Name Register Address Default Value Access TI_RESERVED_CONTROL 1E.8000 0x04C0 RW TI_RESERVED_STATUS 1E.A014 0x0000 RO TI_RESERVED_CONTROL 1E.8001 0x0207 RW TI_RESERVED_STATUS 1E.A015 0x0000 RO TI_RESERVED_CONTROL 1E.8002 0x02FE RW TI_RESERVED_STATUS 1E.A016 0x0000 RO TI_RESERVED_CONTROL 1E.8005 0x0000 RW TI_RESERVED_STATUS 1E.A017 0x0000 RO TI_RESERVED_CONTROL 1E.8006 0x0000 RW TI_RESERVED_STATUS 1E.A018 0x0000 RO TI_RESERVED_CONTROL 1E.8007 0x8000 RW TI_RESERVED_CONTROL 1E.A116 0x0000 RW TI_RESERVED_CONTROL 1E.8008 0x0000 RW TI_RESERVED_CONTROL 1E.A117 0x0000 RW TI_RESERVED_CONTROL 1E.8009 0xFC00 RW TI_RESERVED_STATUS 1E.A118 0x0000 RO TI_RESERVED_CONTROL 1E.800A 0xBC3C RW TI_RESERVED_STATUS 1E.A119 0x0000 RO TI_RESERVED_CONTROL 1E.800B 0x0000 RW TI_RESERVED_CONTROL 01.8000 0x4800 RW TI_RESERVED_CONTROL 1E.800C 0x0000 RW TI_RESERVED_STATUS 01.801F 0xFFFD COR TI_RESERVED_CONTROL 1E.800D 0x01FC RW TI_RESERVED_STATUS 01.8020 0xFFFD COR TI_RESERVED_CONTROL 1E.800E 0x0000 RW TI_RESERVED_STATUS 01.8021 0xFFFD COR TI_RESERVED_CONTROL 1E.800F 0x00C0 RW TI_RESERVED_STATUS 01.8022 0xFFFD COR TI_RESERVED_CONTROL 1E.8011 0x7F00 RW TI_RESERVED_STATUS 01.8023 0xFFFF COR TI_RESERVED_STATUS 1E.8012 0xFFFD COR TI_RESERVED_STATUS 01.8024 0xFFFD COR DEVICE REGISTERS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 83 TLK10232 SLLSEE1 – MAY 2013 www.ti.com Table 8-137. TI_Reserved Control and Status Registers (continued) Register Name Register Address Default Value Access Register Name Register Address Default Value Access TI_RESERVED_STATUS 1E.8013 TI_RESERVED_STATUS 1E.8014 0xFFFD COR TI_RESERVED_CONTROL 01.9000 0x0249 RW 0x0000 RO/LH TI_RESERVED_CONTROL 01.9002 0x1335 TI_RESERVED_STATUS 1E.8015 RW 0x0000 RO TI_RESERVED_CONTROL 01.9003 0x5E29 RW TI_RESERVED_CONTROL 1E.8019 0xFC00 RW TI_RESERVED_CONTROL 01.9004 0x007F RW TI_RESERVED_CONTROL 1E.801A 0xBC3C RW TI_RESERVED_CONTROL 01.9005 0x1C00 RW TI_RESERVED_CONTROL 1E.801C 0x0000 RW TI_RESERVED_CONTROL 01.9006 0x0000 RW TI_RESERVED_CONTROL 1E.801D 0x01FC RW TI_RESERVED_CONTROL 01.9007 0x5120 RW TI_RESERVED_CONTROL 1E.801E 0x0000 RW TI_RESERVED_CONTROL 01.9008 0xC018 RW TI_RESERVED_CONTROL 1E.801F 0x00C0 RW TI_RESERVED_CONTROL 01.9009 0xE667 RW TI_RESERVED_CONTROL 1E.8020 0x0200 RW TI_RESERVED_CONTROL 01.900A 0x5E8F RW TI_RESERVED_CONTROL 1E.8022 0x0000 RW TI_RESERVED_CONTROL 01.900B 0xAFAF RW TI_RESERVED_CONTROL 1E.8023 0x0000 RW TI_RESERVED_CONTROL 01.900C 0x0800 RW TI_RESERVED_CONTROL 1E.8024 0x0000 RW TI_RESERVED_CONTROL 01.900D 0x461A RW TI_RESERVED_CONTROL 1E.8025 0xF000 RW TI_RESERVED_CONTROL 01.900E 0x1723 RW TI_RESERVED_STATUS 1E.8030 0x0000 RO TI_RESERVED_CONTROL 01.900F 0x7003 RW TI_RESERVED_STATUS 1E.8031 0x0000 RO TI_RESERVED_CONTROL 01.9010 0x0851 RW TI_RESERVED_STATUS 1E.8032 0x0000 RO TI_RESERVED_CONTROL 01.9011 0x1EFF RW TI_RESERVED_STATUS 1E.8033 0x0000 RO TI_RESERVED_STATUS 01.9020 0x0000 RO TI_RESERVED_STATUS 1E.8034 0x0000 RO TI_RESERVED_STATUS 01.9021 0xFFFD COR TI_RESERVED_STATUS 1E.8035 0x0000 RO TI_RESERVED_STATUS 01.9022 0x0000 RO TI_RESERVED_CONTROL 1E.8050 0x0000 RW TI_RESERVED_STATUS 01.9023 0x0000 RO TI_RESERVED_CONTROL 1E.8102 0xF280 RW TI_RESERVED_STATUS 01.9024 0x0000 RO TI_RESERVED_CONTROL 1E.A000 0x0000 RW TI_RESERVED_STATUS 01.9025 0x0000 RO TI_RESERVED_STATUS 1E.A010 0x0000 RO TI_RESERVED_STATUS 01.9026 0x0000 RO TI_RESERVED_STATUS 1E.A011 0x0000 RO TI_RESERVED_STATUS 01.9027 0x0000 RO TI_RESERVED_STATUS 1E.A012 0x0000 RO TI_RESERVED_STATUS 01.9028 0x0000 RO TI_RESERVED_STATUS 1E.A013 0x0000 RO TI_RESERVED_STATUS 01.9029 0x0000 RO 84 DEVICE REGISTERS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 TLK10232 www.ti.com SLLSEE1 – MAY 2013 9 ELECTRICAL CHARACTERISTICS 9.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) VALUE UNIT MIN MAX DVDD, VDDA_LS/HS, VDDT_LS/HS, VPP, VDDD –0.3 1.4 V VDDRA/B_LS/HS, VDDO[1:0] –0.3 2.2 V Input Voltage, VI, (LVCMOS/CML/Analog) –0.3 Supply + 0.3 V Storage temperature –65 150 °C Supply voltage Operating Junction Temperature Electrostatic Discharge: HBM CDM Characterized free-air operating temperature range (1) (2) 9.2 –40 TEST CONDITIONS Digital / analog supply voltages VDDD, VDDA_LS/HS, DVDD, VDDT_LS/HS, VPP V 85 °C SERDES PLL regulator voltage VDDRA_LS/HS, VDDRB_LS/HS LVCMOS I/O supply voltage VDDO[1:0] Supply current NOM MAX UNIT 0.95 1.00 1.05 V 1.5V Nominal 1.425 1.5 1.575 1.8V Nominal 1.71 1.8 1.89 1.5V Nominal 1.425 1.5 1.575 1.8V Nominal 1.71 1.8 1.89 10.3 Gbps 650 DVDD + VPP 700 VDDT_LS/HS 600 VDDRA/B_LS 70 VDDRA/B_HS 70 mA 1.6 Worst case supply voltage, temperature, and process. 10GBASE-KR, Both channels active, default swing and Clkout settings VDDD 2.3 W 300 VDDA 85 DVDD + VPP 250 PD* Asserted VDDT 65 VDDRA_HS/LS + VDDRB_HS/LS 7 VDDO 5 REFCLK0P/N, REFCLK1P/N Random Jitter V 10 Power dissipation Shutdown current V 650 VDDA_LS/HS Nominal JR 500 MIN VDDO[1:0] ISD kV Recommended Operating Conditions VDDD PD °C 1 Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to ground (VSS). PARAMETER IDD 105 12kHz to 20MHz 1 ELECTRICAL CHARACTERISTICS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 mA ps 85 TLK10232 SLLSEE1 – MAY 2013 9.3 www.ti.com High Speed Side Serial Transmitter Characteristics PARAMETER TX Output differential peak-to-peak voltage swing, transmitter enabled VOD(p-p) MIN NOM MAX SWING = 0000 TEST CONDITIONS 50 130 220 SWING = 0001 110 220 320 SWING = 0010 180 300 430 SWING = 0011 250 390 540 SWING = 0100 320 480 650 SWING = 0101 390 570 770 SWING = 0110 460 660 880 SWING = 0111 530 750 1000 SWING = 1000 590 830 1100 SWING = 1001 660 930 1220 SWING = 1010 740 1020 1320 SWING = 1011 820 1110 1430 SWING = 1100 890 1180 1520 SWING = 1101 970 1270 1610 SWING = 1110 1060 1340 1680 SWING = 1111 1090 1400 1740 Transmitter disabled TX Output pre/post cursor emphasis voltage See register bits TWPOST1, TWPOST2, and TWPRE for deemphasis settings. See Figure 9-2 VCMT TX Output common mode voltage 100-Ω differential termination. DCcoupled. tskew Intra-pair output skew Serial Rate = 9.8304 Gbps Tr, Tf Differential output signal rise, fall time (20% to 80%), Differential Load = 100Ω Serial output total jitter (CPRI LV/LV-II/LV-III, OBSAI and 10GBASE-KR Rates) Serial Rate ≤ 3.072Gbps 0.35 JT1 Serial Rate > 3.072Gbps 0.28 Serial output deterministic jitter (CPRI LV/LV-II/LV-III, OBSAI and 10GBASE-KR Rates) Serial Rate ≤ 3.072Gbps 0.17 JD1 Serial Rate > 3.072Gbps 0.15 JR1 Serial output random jitter (CPRI LV/LV-II/LV-III, OBSAI and 10GBASE-KR Rates) Serial Rate > 3.072Gbps 0.15 JT2 Serial output total jitter (CPRI E.12.HV) Serial output deterministic jitter (CPRI E.12.HV) SDD22 Differential output return loss SCC22 Common-mode output return loss T(LATENCY) (1) (2) 86 Transmit path latency mVpp 30 Vpre/post JD2 UNIT –17.5/ –37.5% +17.5/ +37.5% VDDT - 0.25 * VOD(p-p) mV 0.045 24 UI ps UIpp UIpp UIpp 0.279 Serial Rate = 1.2288Gbps UIpp 0.14 50 MHz < f < 2.5 GHz 9 dB (1) dB 50 MHz < f < 2.5 GHz 6 dB 2.5 GHz < f < 7.5 GHz (2) dB 2.5 GHz < f < 7.5 GHz See See 10GBASE-KR mode see Figure 3-5 1GBASE-KX mode see Figure 4-2 General Purpose mode see Figure 5-4 Differential input return loss, SDD22 = 9 – 12 log10(f / 2500MHz)) dB Common-mode output return loss, SDD22 = 6 – 12 log10(f / 2500MHz)) dB ELECTRICAL CHARACTERISTICS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 TLK10232 www.ti.com SLLSEE1 – MAY 2013 0.5 * VDE * VOD(pp) VCMT 0.5 * VOD(pp) 0.25 * VDE * VOD (pp) bit time tr , t f 0.25 * VOD (pp) Figure 9-1. Transmit Output Waveform Parameter Definitions +V 0/0 +V pst +Vpre +Vss 0 -Vss -Vpre -V pst -V 0/0 UI h -1 = TWPRE (0% -17 .5% for typical application) setting h 1 = TWPOST1 (0 % -37.5 % for typical application) setting h 0 = 1 - |h 1| - |h -1 | V0 /0 = Output Amplitude with TWPRE = 0% , TWPOST = 0 %. Vss = Steady State Output Voltage = V0/0 * | h1 + h 0 + h- 1| Vpre = PreCursor Output Voltage = V0 /0 * | -h 1 – h 0 + h -1| Vpst = PostCursor Output Voltage = V0/0 * | - h1 + h 0 + h- 1| Figure 9-2. Pre/Post Cursor Swing Definitions 9.4 High Speed Side Serial Receiver Characteristics PARAMETER TEST CONDITIONS VID RX Input differential voltage, |RXP – RXN| VID(pp) RX Input differential peak-to-peak voltage swing, 2×|RXP – RXN| CI RX Input capacitance JTOL Differential input return loss tskew Intra-pair input skew (1) NOM MAX 50 600 Half/Quarter/Eighth Rate, AC Coupled 50 800 Full Rate, AC Coupled 100 1200 Half/Quarter/Eighth Rate, AC Coupled 100 1600 2 10GBASE-KR Jitter tolerance, test channel with mTC =1 (see Figure 9-3 for attenuation curve), PRBS31 test pattern at 10.3125 Gbps SDD11 MIN Full Rate, AC Coupled Applied sinusoidal jitter 0.115 Applied random jitter 0.130 Applied duty cycle distortion 0.035 Broadband noise amplitude (RMS) mV mVpp pF UIpp 5.2 50 MHz < f < 2.5 GHz 2.5 GHz < f < 7.5 GHz UNIT 9 See dB (1) 0.23 UI Differential input return loss, SDD11 = 9 – 12 log10(f / 2.5GHz)) dB ELECTRICAL CHARACTERISTICS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 87 TLK10232 SLLSEE1 – MAY 2013 www.ti.com High Speed Side Serial Receiver Characteristics (continued) PARAMETER t(LATENCY) TEST CONDITIONS Receive path latency MIN NOM 10GBASE-KR mode see Figure 3-5 1GBASE-KX mode see Figure 4-2 General Purpose mode see Figure 5-4 MAX UNIT UNIT 40 Fitted Attenuation (dB) 35 30 25 20 15 10 5 0 1000 2000 3000 4000 Frequency (MHz) 5000 6000 G001 Figure 9-3. 10GBASE-KR Fitted Channel Attenuation Limit 9.5 Low Speed Side Serial Transmitter Characteristics PARAMETER VOD(pp) DE Transmitter output differential peak-to-peak voltage swing Transmitter output de-emphasis voltage swing reduction VCMT Transmitter output common mode voltage tskew Intra-pair output skew 88 MIN NOM MAX SWING = 000 TEST CONDITIONS 110 190 280 SWING = 001 280 380 490 SWING = 010 420 560 700 SWING = 011 560 710 870 SWING = 100 690 850 1020 SWING = 101 760 950 1150 SWING = 110 800 1010 1230 SWING = 111 830 1050 1270 DE = 0000 0 DE = 0001 0.42 DE = 0010 0.87 DE = 0011 1.34 DE = 0100 1.83 DE = 0101 2.36 DE = 0110 2.92 DE = 0111 3.52 DE = 1000 4.16 DE = 1001 4.86 DE = 1010 5.61 DE = 1011 6.44 DE = 1100 7.35 DE = 1101 8.38 DE = 1110 9.54 DE = 1111 10.87 100-Ω differential termination. DCcoupled. dB VDDT - 0.5 * VOD(p-p) mV 0.045 ELECTRICAL CHARACTERISTICS mVpp UI Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 TLK10232 www.ti.com SLLSEE1 – MAY 2013 Low Speed Side Serial Transmitter Characteristics (continued) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT tR, tF Differential output signal rise, fall time (20% to 80%) Differential Load = 100Ω JT Serial output total jitter 0.35 UI JD Serial output deterministic jitter 0.17 UI tskew Lane-to-lane output skew 50 ps 9.6 30 Low Speed Side Serial Receiver Characteristics PARAMETER TEST CONDITIONS VID Receiver input differential voltage, |INP – INN| VID(pp) Receiver input differential peak-to-peak voltage swing 2×|INP – INN| CI Receiver input capacitance Jitter tolerance, total jitter at serial input (DJ + RJ) (BER 10-15) JDR Serial input deterministic jitter (BER 10-15) tskew Intra-pair input skew tlane-skew Lane-to-lane input skew PARAMETER Frequency FHSoffset Accuracy DC Duty cycle VID Differential input voltage CIN Input capacitance RIN Differential input impedance TRISE Rise/fall time Half/Quarter Rate, AC Coupled 50 800 Full Rate, AC Coupled 100 1200 Half/Quarter Rate, AC Coupled 100 1600 Zero crossing, Half/Quarter Rate 0.66 Zero crossing, Full Rate 0.65 Zero crossing, Half/Quarter Rate 0.50 Zero crossing, Full Rate 0.35 TEST CONDITIONS MIN mV mVdfpp pF UIp-p UIp-p 0.23 UI 30 UI MAX UNIT 425 MHz Relative to Nominal HS Serial Data Rate –100 100 Relative to Incoming HS Serial Data Rate –200 200 High Time 45% NOM 50% 250 10% to 90% 2000 50 ppm 55% mVpp 1 pF 350 ps MAX UNIT Ω 100 Differential Output Clock Characteristics (CLKOUTA/BP/N) TEST CONDITIONS MIN Peak to peak TRISE Output rise time 10% to 90%, 2pF lumped capacitive load, AC-Coupled RTERM Output termination CLKOUT×P/N to DVDD F Output frequency NOM 1000 2000 mVdfpp 350 ps 500 MHz MAX UNIT Ω 50 0 LVCMOS Electrical Characteristics (VDDO): PARAMETER VOH UNIT 122.88 Differential output voltage 9.9 MAX 600 PARAMETER VOD NOM 50 Reference Clock Characteristics (REFCLK0P/N, REFCLK1P/N) F 9.8 MIN Full Rate, AC Coupled 2 JTOL 9.7 ps TEST CONDITIONS MIN NOM IOH = 2 mA, Driver Enabled (1.8V) VDDO – 0.45 VDDO IOH = 2 mA, Driver Enabled (1.5V) 0.75 × VDDO VDDO High-level output voltage V ELECTRICAL CHARACTERISTICS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 89 TLK10232 SLLSEE1 – MAY 2013 www.ti.com LVCMOS Electrical Characteristics (VDDO): (continued) PARAMETER TEST CONDITIONS MIN NOM MAX IOL = –2 mA, Driver Enabled (1.8V) 0 0.45 IOL = –2 mA, Driver Enabled (1.5V) 0 0.25 × VDDO UNIT VOL Low-level output voltage VIH High-level input voltage 0.65 × VDDO VDDO + 0.3 V VIL Low-level input voltage –0.3 0.35 × VDDO V IIH, IIL Receiver only Low/High Input Current ±170 µA Driver only Driver Disabled Driver/Receiver With Pullup/Pulldown Driver disabled With Pull Up/Down Enabled IOZ CIN V ±25 ±195 Input capacitance 3 µA pF 9.10 MDIO Timing Requirements over recommended operating conditions (unless otherwise noted) PARAMETER tperiod MDC period tsetup MDIO setup to ↑ MDC thold MDIO hold to ↑ MDC Tvalid MDIO valid from MDC ↑ TEST CONDITIONS MIN See Figure 9-4 NOM MAX UNIT 100 ns 10 ns 10 ns 0 40 ns MDC tPERIOD tSETUP tHOLD MDIO Figure 9-4. MDIO Read/Write Timing 9.11 JTAG Timing Requirements over recommended operating conditions (unless otherwise noted) PARAMETER TPERIOD TCK period TSETUP TDI/TMS/TRST_N setup to ↑ TCK THOLD TDI/TMS/TRST_N hold from ↑ TCK TVALID TDO delay from TCK Falling 90 TEST CONDITIONS MIN NOM MAX UNIT 66.67 See Figure 9-5 5 0 ELECTRICAL CHARACTERISTICS ns 3 10 ns Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 TLK10232 www.ti.com SLLSEE1 – MAY 2013 TCK tPERIOD tSETUP tHOLD TDI/TMS/ TRST_N tVALID TDO Figure 9-5. JTAG Timing 9.12 Power Sequencing Guidelines The TLK10232 allows either the core or I/O power supply to be powered up for an indefinite period of time while the other supply is not powered up, if all of the following conditions are met: 1. All maximum ratings and recommending operating conditions are followed 2. Bus contention while 1.5/1.8V power is applied (>0V) must be limited to 100 hours over the projected lifetime of the device. 3. Junction temperature is less than 105°C during device operation. Note: Voltage stress up to the absolute maximum voltage values for up to 100 hours of lifetime operation at a TJ of 105°C or lower will minimally impact reliability. The TLK10232 LVCMOS I/O are not failsafe (i.e. cannot be driven with the I/O power disabled). TLK10232 inputs should not be driven high until their associated power supply is active. ELECTRICAL CHARACTERISTICS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 91 TLK10232 SLLSEE1 – MAY 2013 www.ti.com 10 MECHANICAL AND THERMAL DATA 10.1 Package Thermal Dissipation Ratings Table 10-1 details the thermal characteristics of the TLK10232 package. Table 10-1. Package Thermal Characteristics JEDEC STANDARD BOARD PARAMETER VALUE ΘJA Theta-JA 25.5 ΨJT Psi-JT 1.8 ΨJB Psi-JB CUSTOM TYPICAL APPLICATION BOARD ΘJA (1) 13.7 (1) Theta-JA 24.5 ΨJT Psi-JT 0.9 ΨJB Psi-JB 11 Custom Typical Application Board Characteristics: • 10x15 inches • 12 layer • 8 power/ground layers – 95% copper (1oz) • 4 signal layers – 20% copper (1oz) SPACER ΨJB = (TJ – TB)/(Total Device Power Dissipation) ΨJB = (TJ TJ = Device Junction Temperature ΨJB = (TJ TB = Temperature of PCB 1 mm from device edge. SPACER ΨJT = (TJ – TC)/(Total Device Power Dissipation) ΨJB = (TJ TJ = Device Junction Temperature ΨJB = (TJ TC = Hottest temperature on the case of the package. Table 10-2. ORDERING INFORMATION 92 Generic Part Number Orderable Part Number TLK10232 TLK10232CTR MECHANICAL AND THERMAL DATA Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 TLK10232 www.ti.com SLLSEE1 – MAY 2013 11 APPENDIX A: PROVISIONABLE XAUI CLOCK TOLERANCE COMPENSATION The XAUI interface is defined to allow for separate clock domains on each side of the link. Though the reference clocks for two devices on a XAUI/KR link have the same specified frequencies, there are slight differences that, if not compensated for, will lead to over or under run of the FIFOs on the receive/transmit data paths. The XAUI CTC block performs the clock domain transition and rate compensation by utilizing a FIFO that is 32 deep and 40-bits wide. The usable FIFO size in the RX and TX directions is dependent upon the RX_FIFO_DEPTH and TX_FIFO_DEPTH MDIO fields, respectively. The word format is illustrated in Figure 11-1. data_ln0_in[8:0] lane 0 ctrl[0] data_ln1_in[8:0] lane 1 ctrl[1] data_ln2_in[8:0] lane 2 data_ln3_in[8:0] ctrl[2] 0 lane 3 ctrl[3] 39 Figure 11-1. XAUI CTC FIFO Word Format The XAUI CTC performs one of the following operations to compensate the clock rate difference: 1. Delete Idle column from the data stream 2. Delete Sequence column from the data stream (enabled via MDIO) 3. Insert Idle column to the data stream. The following rules apply for insertion/removal: • Idle insertion/deletion occurs in groups of 4 idle characters (i.e., in columns) • Idle characters are added following Idle or Sequence ordered_set • Idle characters are not added while data is being received • When deleting Idle characters, minimum IPG of 5 characters is maintained. /T/ characters are counted towards IPG. • The first Idle column after /T/ is never deleted • Sequence ordered_sets are deleted only when two consecutive Sequence columns are received. In this case, only one of the two Sequence columns will be deleted. Insertion: When the FIFO fill level is at or below LOW watermark (insertion is triggered), the XAUI CTC needs to insert an IDLE column. It does so by skipping a read from the FIFO and inserting IDLE column to the data stream. It continues the insertion until the FIFO fill level is above the mid point. This occurs on the read side of the FIFO. Removal: When the FIFO fill level is at or above HIGH watermark (deletion is triggered), the XAUI CTC needs to remove an IDLE column. It does so by skipping a write to the FIFO and discarding the IDLE column or Sequence ordered_set. It continues the deletion until the FIFO fill level is below the mid point. This occurs on the write side of the FIFO. On the write side of the XAUI CTC FIFO a 40-bit write is performed at every cycle of the 312.5 MHz clock except during removal when it discards the IDLE or sequence ordered_set. On the read side of the XAUI CTC FIFO a 40-bit read is performed at every cycle of the 312.5 MHz clock except during insertion when it generates IDLE columns to the output while not reading the FIFO at all. Copyright © 2013, Texas Instruments Incorporated APPENDIX A: PROVISIONABLE XAUI CLOCK TOLERANCE COMPENSATION Submit Documentation Feedback Product Folder Links: TLK10232 93 TLK10232 SLLSEE1 – MAY 2013 www.ti.com In IEEE 802.3-2008 the XAUI clock rate tolerance is given as 3.125 GHz ± 100 ppm, the XGMII clock rate tolerance is given as 156.25 MHz ± 0.02% (which is equivalent to 200ppm), and the Jumbo packet size is 9600 bytes which is equivalent to 2400 cycles of 312.5 MHz clock. The average inter-frame gap is 12 bytes (3 columns), which implies that there is one opportunity to insert/delete a column in between every packet on average. This gives one column deletion/insertion in every 2400 columns which results in a 400 ppm tolerance capability. If the IPG increases, then more clock rate variance or larger packet size can be supported. Note that the maximum frequency tolerance is limited by the frequency accuracy requirement of the reference clock. The number of words in the FIFO (fifo_depth[2:0]) and the HIGH/LOW watermark levels (wmk_sel[1:0]) are set through MDIO register 01.8001, and determine the allowable difference between the write clock and the read clock as well as the maximum packet size that can be processed without FIFO collision. At these watermarks the drop and insert start respectively and must happen before it hits overflow/underflow condition. Although the FIFO is supposed to never overflow/underflow given the average IPG, if it ever happens the overflow/underflow indications signal the error to the MDIO interface and the FIFO is reset. Note that the overflow/underflow status indications are latched high and cleared when read. Table 11-1 shows XAUI CTC FIFO configuration and capabilities: wmk_sel[1:0] LOW Watermark HIGH Watermark Max Latency (Cycles) Nom Latency (Cycles) Min Latency (Cycles) Max pkt size (400ppm) Max pkt size (200ppm) Max pkt size (100ppm) Max pkt size (50ppm) 32 11 15 18 28 16 4 100KB 200KB 400KB 800KB 011 010 24 16 001 12 000 8 IPG to support the max pkt size FIFO Depth 1xx Min #of removable columns in fifo_depth[2:0] Table 11-1. XAUI CTC FIFO Configurations 10 10 13 20 28 16 4 80KB 160KB 320KB 640KB 8 01 10 23 28 16 4 50KB 100KB 200KB 400KB 5 00 6 27 28 16 4 10KB 20KB 40KB 80KB 1 11 11 14 20 12 4 60KB 120KB 240KB 480KB 6 10 9 16 20 12 4 40KB 80KB 160KB 320KB 4 0x 6 19 20 12 4 10KB 20KB 40KB 80KB 1 1x 7 10 13 8 3 30KB 60KB 120KB 240KB 3 0x 5 12 13 8 3 10KB 20KB 40KB 80KB 1 xx 5 8 9 6 3 10KB 20KB 40KB 80KB 1 7 4 1 Plain FIFO, No CTC default No limit on pkt size (needs 0 ppm to work) Note: To support the max packet sizes as shown in Table 11-1, it is assumed that there are enough IDLE columns in IPG for deletion. Below is one example: Configure the FIFO to be 32-deep (fifo_depth[2:0] = 3’b1xx) and set the LOW/HIGH Watermarks to 10/23 (wmk_sel[1:0] = 2’b01). If the write clock is faster than the read clock by 200ppm, to support the max packet size of 100KB, a minimum of 5 removable columns in IPG is required (either IDLE columns or Sequence ordered_sets). If there are only 4 removable columns in IPG, the max packet size supported is dropped to 80KB. If there are only 3 removable columns in IPG, the max packet size supported is dropped to 60KB, and so on. As a rule of thumb, one removable column in IPG corresponds to 10KB at 400ppm, 20KB at 200ppm, 40KB at 100ppm, and 80KB at 50ppm The following figures illustrate XAUI CTC FIFO configuration and capabilities. The green region (the middle of the FIFO fill level) indicates that the FIFO is operating stably without insertion or deletion. The more green bars in the figure, the more clock wander it can tolerate. The more yellow bars in the figure, the bigger packet size it can support. 94 APPENDIX A: PROVISIONABLE XAUI CLOCK TOLERANCE COMPENSATION Submit Documentation Feedback Product Folder Links: TLK10232 Copyright © 2013, Texas Instruments Incorporated TLK10232 www.ti.com SLLSEE1 – MAY 2013 32 words (fifo_depth=3'b1xx, wmk_sel=2'b00) 40 bits Underflow Drop Overflow Insert HIGH Watermark LOW Watermark Figure 11-2. Organization of the XAUI CTC FIFO (32-Deep, Low Watermark) 32 words (fifo_depth=3'b1xx, wmk_sel=2'b01) 40 bits Underflow LOW Watermark Insert Drop Overflow HIGH Watermark Figure 11-3. Organization of the XAUI CTC FIFO (32-Deep, Mid Watermark) Copyright © 2013, Texas Instruments Incorporated APPENDIX A: PROVISIONABLE XAUI CLOCK TOLERANCE COMPENSATION Submit Documentation Feedback Product Folder Links: TLK10232 95 TLK10232 SLLSEE1 – MAY 2013 www.ti.com 32 words (fifo_depth=3'b1xx, wmk_sel=2'b10) 40 bits Underflow Insert Drop Overflow HIGH Watermark LOW Watermark Figure 11-4. Organization of the XAUI CTC FIFO (32-Deep, Mid-High Watermark) 32 words (fifo_depth=3'b1xx, wmk_sel=2'b11) 40 bits Underflow Insert LOW Watermark Drop Overflow HIGH Watermark Figure 11-5. Organization of the XAUI CTC FIFO (32-Deep, High Watermark) 96 APPENDIX A: PROVISIONABLE XAUI CLOCK TOLERANCE COMPENSATION Submit Documentation Feedback Product Folder Links: TLK10232 Copyright © 2013, Texas Instruments Incorporated TLK10232 www.ti.com SLLSEE1 – MAY 2013 24 words (fifo_depth=3'b011, wmk_sel=2'b0x) 40 bits Underflow Insert Drop LOW Watermark Overflow HIGH Watermark Figure 11-6. Organization of the XAUI CTC FIFO (24-Deep, Low Watermark) 24 words (fifo_depth=3'b011, wmk_sel=2'b10) 40 bits Underflow Insert Drop LOW Watermark Overflow HIGH Watermark Figure 11-7. Organization of the XAUI CTC FIFO (24-Deep, Mid Watermark) 24 words (fifo_depth=3'b011, wmk_sel=2'b11) 40 bits Underflow LOW Watermark Insert Drop Overflow HIGH Watermark Figure 11-8. Organization of the XAUI CTC FIFO (24-Deep, High Watermark) Copyright © 2013, Texas Instruments Incorporated APPENDIX A: PROVISIONABLE XAUI CLOCK TOLERANCE COMPENSATION Submit Documentation Feedback Product Folder Links: TLK10232 97 TLK10232 SLLSEE1 – MAY 2013 www.ti.com 16 words (fifo_depth=3'b010 wmk_sel=2'b0x) 40 bits Underflow Insert Overflow Drop HIGH Watermark LOW Watermark Figure 11-9. Organization of the XAUI CTC FIFO (16-Deep, Low Watermark) 16 words (fifo_depth=3'b010 wmk_sel=2'b1x) 40 bits Underflow Insert LOW Watermark Overflow Drop HIGH Watermark Figure 11-10. Organization of the XAUI CTC FIFO (16-Deep, High Watermark) 98 APPENDIX A: PROVISIONABLE XAUI CLOCK TOLERANCE COMPENSATION Submit Documentation Feedback Product Folder Links: TLK10232 Copyright © 2013, Texas Instruments Incorporated TLK10232 www.ti.com SLLSEE1 – MAY 2013 12 words (ctc_depth=3'b001) 40 bits Underflow Insert LOW Watermark Overflow Drop HIGH Watermark Figure 11-11. Organization of the XAUI CTC FIFO (12-Deep) 8 words (ctc_depth=3'b000), no CTC 40 bits Underflow Overflow Figure 11-12. Organization of the XAUI CTC FIFO (8-Deep) Copyright © 2013, Texas Instruments Incorporated APPENDIX A: PROVISIONABLE XAUI CLOCK TOLERANCE COMPENSATION Submit Documentation Feedback Product Folder Links: TLK10232 99 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TLK10232CTR ACTIVE FCBGA CTR 144 119 RoHS & Green SNAGCU Level-4-260C-72 HR -40 to 85 TLK10232 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of