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TLV07
SBOS832A – JULY 2017 – REVISED AUGUST 2017
TLV07 36-V Precision, Rail-to-Rail Output Operational Amplifier
1 Features
3 Description
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The TLV07 device is a 36-V, single-supply, low-noise,
precision
operational
amplifier
(op
amp)
manufactured using TI’s laser trim operational
amplifier technology. Each amplifiers' input offset
voltage is trimmed in production to obtain a low offset
voltage of 100 µV (maximum).
1
•
Low Offset Voltage: 100 µV (Maximum)
Rail-to-Rail Output
Low Noise: 19 nV / √Hz
Unity-Gain Stable
RFI Filtered Inputs
Input Range Includes Negative Supply
Rail-to-Rail Output
Gain Bandwidth: 1 MHz
Low Quiescent Current: 930 µA
Full Industrial Temperature Range:
–40°C to +125°C
Offered in the Industry-Standard 8-Pin SOIC
Package
The TLV07 offers outstanding dc precision and ac
performance, including rail-to-rail output, low offset
voltage (±100 µV, maximum) and 1-MHz bandwidth.
The TLV07 is stable at G = 1 with capacitive loads up
to 200 pF. The input can operate 100 mV below the
negative rail and within 2 V of the positive rail. This
wide input voltage range, combined with a high
CMRR of 120 dB, make the TLV07 well-suited when
operated in the non-inverting configuration.
The TLV07 op amp is specified from –40°C to
+125°C.
2 Applications
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Device Information(1)
Battery Testers
Tracking Amplifier in Power Modules
Merchant Power Supplies
Transducer Amplifiers
Temperature Measurements
Strain Gauge Amplifiers
PART NUMBER
TLV07
PACKAGE
SOIC (8)
BODY SIZE (NOM)
4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
space
space
Single Pole Low-Pass Filter With Gain
RG
RF
R1
VOUT
VIN
C1
f-3 dB =
(
RF
VOUT
= 1+
RG
VIN
((
1
1 + sR1C1
1
2pR1C1
(
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV07
SBOS832A – JULY 2017 – REVISED AUGUST 2017
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information: TLV07 .....................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ...................................... 13
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 16
8
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Application .................................................. 17
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 20
11 Device and Documentation Support ................. 21
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
22
22
22
22
22
12 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (July 2017) to Revision A
•
2
Page
First release of production-data data sheet ........................................................................................................................... 1
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SBOS832A – JULY 2017 – REVISED AUGUST 2017
5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
(1)
NC(1)
1
8
NC(1)
-IN
2
7
V+
+IN
3
6
OUT
V-
4
5
NC(1)
NC- no internal connection
Pin Functions: TLV07
NAME
–IN
NO.
I/O
2
I
Negative (inverting) input
DESCRIPTION
Positive (non-inverting) input
+IN
3
I
NC
1, 5, 8
—
No internal connection (can be left floating)
OUT
6
O
Output
V+
7
—
Positive (highest) power supply
V–
4
—
Negative (lowest) power supply
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range, unless otherwise noted. (1)
MIN
MAX
UNIT
–20
20
V
40
V
Signal input pin voltage
(V–) – 0.5
(V+) + 0.5
V
Signal input pin current
–10
10
mA
125
°C
150
°C
150
°C
Supply voltage
Single supply voltage
Output short-circuit current (2)
Continuous
Operating ambient temperature, TA
–40
Junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VS
Supply voltage (VS = V+ – V–)
2.7
36
UNIT
V
TA
Operating temperature
–40
125
°C
6.4 Thermal Information: TLV07
TLV07
THERMAL METRIC
D (SOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
149.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
97.9
°C/W
RθJB
Junction-to-board thermal resistance
87.7
°C/W
ψJT
Junction-to-top characterization parameter
35.5
°C/W
ψJB
Junction-to-board characterization parameter
89.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
4
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6.5 Electrical Characteristics
at TA = 25°C, V+ = +15 V, V- = -15 V, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
50
±100
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
Input offset voltage drift
TA = –40°C to 125°C
PSRR
Input offset voltage vs power supply
VS = 2.7 V to 36 V
µV
±0.9
µV/°C
0.3
µV/V
±40
pA
±3
nA
±4
pA
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
TA = –40°C to 125°C
NOISE
en
Input voltage noise
ƒ = 0.1 Hz to 10 Hz
2.7
µVPP
Input voltage noise density
ƒ = 1 kHz
19
nV/√Hz
INPUT VOLTAGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
(V–) – 0.1
VS = ±18 V, (V–) - 0.1 V < VCM < (V+) – 2 V
104
(V+) – 2
V
120
dB
INPUT IMPEDANCE
Differential
100 || 3
Common-mode
MΩ || pF
6 || 3
1012 Ω || pF
130
dB
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
(V–) + 0.35 V < VO < (V+) – 0.35 V
110
FREQUENCY RESPONSE
GBP
Gain bandwidth product
SR
Slew rate
1
MHz
G=1
0.4
V/µs
To 0.1%, VS = ±18 V, G = +1, 10-V step
20
µs
Settling time
To 0.01% (12-bit), VS = ±18 V
G=1
10-V step
28
µs
VO
Voltage output swing from rail
RL = 10 kΩ
120
mV
ISC
Short-circuit current
17
mA
ƒ = 1 MHz
IO = 0 A
900
Ω
IO = 0 A
930
tS
OUTPUT
RO
Open-loop output resistance
POWER SUPPLY
IQ
Quiescent current per amplifier
1800
µA
TEMPERATURE
Specified range
–40
125
°C
Operating range
–40
125
°C
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6.6 Typical Characteristics
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted)
Table 1. Characteristic Performance Measurements
DESCRIPTION
FIGURE
Offset Voltage Production Distribution
Figure 1
Offset Voltage Drift Distribution
Figure 2
Offset Voltage vs Temperature
Figure 3
Offset Voltage vs Common-Mode Voltage
Figure 4
Offset Voltage vs Power Supply
Figure 5
IB and IOS vs Common-Mode Voltage
Figure 6
Input Bias Current vs Temperature
Figure 7
Output Voltage Swing vs Output Current (Maximum Supply)
Figure 8
CMRR and PSRR vs Frequency (Referred-to-Input)
Figure 9
CMRR vs Temperature
Figure 10
PSRR vs Temperature
Figure 11
0.1-Hz to 10-Hz Noise
Figure 12
Input Voltage Noise Spectral Density vs Frequency
Figure 13
THD+N Ratio vs Frequency
Figure 14
THD+N vs Output Amplitude
Figure 15
Quiescent Current vs Temperature
Figure 16
Quiescent Current vs Supply Voltage
Figure 17
Open-Loop Gain and Phase vs Frequency
Figure 18
Closed-Loop Gain vs Frequency
Figure 19
Open-Loop Gain vs Temperature
Figure 20
Open-Loop Output Impedance vs Frequency
Figure 21
No Phase Reversal
Figure 22
Positive Overload Recovery
Figure 23
Negative Overload Recovery
Figure 24
Small-Signal Step Response
Figure 25, Figure 26
Large-Signal Step Response
Figure 27, Figure 28
Large-Signal Settling Time
Figure 29
Short-Circuit Current vs Temperature
Figure 30
Maximum Output Voltage vs Frequency
Figure 31
EMIRR IN+ vs Frequency
Figure 32
6
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30
25
20
20
Amplifiers (%)
15
10
15
10
5
5
3
1.8
-0.6
-3
100
70
40
10
-20
-50
-80
Offset Voltage (µV)
0.6
0
0
-1.8
Amplifiers (%)
25
Input Offset Voltage Drift (µV/ƒC)
C001
C002
Figure 1. Input Offset Voltage Distribution
Figure 2. Input Offset Voltage Drift Distribution
Input-referred Offset Voltage ( V)
Input-referred Offset Voltage ( V)
1000
800
600
400
200
0
±200
±400
±600
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
VCM = 16 V
VCM = ± 18.1 V
±20
±15
±10
±5
0
5
10
15
Input Common-mode Voltage (V)
C001
Figure 3. Input Offset Voltage vs Temperature
20
C003
Figure 4. Input Offset Voltage vs Common-Mode Voltage
60.0
150
40.0
100
Input Bias Current (pA)
Input-referred Offset Voltage ( V)
50
45
40
35
30
25
20
15
10
5
0
±5
±10
±15
±20
±25
±30
±35
±40
20.0
0.0
±20.0
±40.0
IBN
50
IBP
0
±50
IOS
±100
VS = 4.5 V
±60.0
0
9
18
27
36
Supply Voltage (V)
±150
±20
C001
Figure 5. Offset Voltage vs Power Supply
±15
±10
±5
0
5
10
15
Input Common-mode Voltage (V)
20
C001
Figure 6. IB and IOS vs Common Mode Voltage
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100.0
18
Output Voltage (V)
Input Current (nA)
17
10.0
IBP
1.0
16
15
14.5
-14.5
-15
-16
IBN
0.1
-17
IOS
-18
0.0
±75
±50
±25
0
25
50
75
100
125
0
150
3
4
5
6
7
8
9
Common-Mode Rejection Ratio (dB)
140
+PSRR
120
±PSRR
100
80
60
40
20
0
0.01
150
140
0.1
130
120
1
110
100
10
100
1k
10k
100k
1M
Frequency (Hz)
10M
Common-mode Rejection Ratio (µV/V)
160
CMRR
1
10
Figure 8. Output Voltage Swing vs Output Current
(Maximum Supply)
160
10
±75 ±50 ±25
0
25
50
75
100 125 150
Temperature (ƒC)
C004
Figure 9. CMRR and PSRR vs Frequency
C001
Figure 10. CMRR vs Temperature
Input-referred Voltage Noise (1 uV/div)
50
Power-Supply Rejection Ratio (µV/V)
2
C001
Figure 7. Input Bias Current vs Temperature
40
30
20
10
0
-10
±75
±50
±25
0
25
50
75
100
Temperature (ƒC)
125
150
Time (1 s/div)
C017
C001
Figure 12. 0.1-Hz to 10-Hz Noise
Figure 11. PSRR vs Temperature
8
1
Output Current (mA)
Temperature (ƒC)
Rejection Ratio (dB)
-40°C
+25°C
+125°C
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1
Total Harmonic Distortion + Noise (%)
1000
100
10
0.1
-60
0.01
-80
0.001
-100
0.0001
-120
-140
20k
0.00001
1
1
10
100
1k
10k
Frequency (Hz)
20
Frequency (Hz)
0.1
-60
-80
0.01
-100
0.001
0.00001
0.01
G = -1, 600- Load
G = -1, 2k- Load
G = -1, 10k- Load
G = +1, 600- Load
G = +1, 2k- Load
G = +1, 10k- Load
0.1
-120
-140
1
C004
1200
1100
Quiescent Current ( A)
-40
2k
Figure 14. THD + N Ratio vs Frequency
Total Harmonic Distortion + Noise (dB)
1
0.0001
200
C002
Figure 13. Input Voltage Noise Spectral Density vs
Frequency
Total Harmonic Distortion + Noise (%)
-40
G = -1, 2k- Load
G = -1, 600- Load
G = -1, 10k- Load
G = +1, 2k- Load
G = +1, 600- Load
G = +1, 10k- Load
Total Harmonic Distortion + Noise (dB)
Voltage Noise Spectral Density (nv/¥Hz)
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VS = ± 15 V
1000
900
VS = ± 2.25 V
800
700
600
10
±75
Output Amplitude (VRMS)
±50
±25
0
25
50
75
100
125
150
Temperature (ƒC)
C004
Figure 15. THD + N vs Output Amplitude
C001
Figure 16. Quiescent Current vs Temperature
1200
180
120
Open-loop Gain
Gain (dB)
800
600
VS = 4.5 V
100
150
80
120
60
90
60
40
Phase
400
200
20
30
0
0
±20
0
0
9
18
Supply Voltage (V)
27
36
1
100
1k
10k
100k
1M
-30
10M
Frequency (Hz)
C001
Figure 17. Quiescent Current vs Supply Voltage
10
Phase (ƒ)
Quiescent Current ( A)
1000
C001
Figure 18. Open-Loop Gain and Phase vs Frequency
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160
G = +1
G= -1
G= +10
150
Gain (dB)
20
0
-20
140
0.1
130
120
1
Open-loop Gain (µV/V)
Open-loop Gain (dB)
40
0.01
110
-40
100
100
1k
10k
100k
1M
10M
Frequency (Hz)
10
±75 ±50 ±25
0
25
50
75
100 125 150
Temperature (ƒC)
C004
Figure 19. Closed-Loop Gain vs Frequency
C001
Figure 20. Open-Loop Gain vs Temperature
10k
Output Voltage (5 V/div)
ZO (W)
1k
100
10
1
1m
1
10
100
1k
10k
100k
1M
Time (1 ms/div)
10M
Frequency (Hz)
C017
Figure 22. No Phase Reversal
Figure 21. Open-Loop Output Impedance vs Frequency
VIN
VOUT
5 V/div
5 V/div
VIN
VOUT
Time (10 µs/div)
Time (10 µs/div)
C017
C017
Figure 23. Positive Overload Recovery
10
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Figure 24. Negative Overload Recovery
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2.5 mV/div
2.5 mV/div
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Input
Output
Input
Output
Time (20 µs/div)
Time (20 µs/div)
C017
C017
G = +1 V/V
G = –1 V/V
Figure 26. Small-Signal Step Response
2 V/div
2 V/div
Figure 25. Small-Signal Step Response
Output
Output
Input
Input
Time (10 µs/div)
Time (10 µs/div)
C017
C017
G = +1 V/V
G = –1 V/V
Figure 27. Large-Signal Step Response
Figure 28. Large-Signal Step Response
30
25
20
15
10
ISC (mA)
1 mV/div
.01% Settling = “1 mV
Time (20 µs/div)
ISC, Source
ISC, Sink
5
0
−5
−10
−15
−20
−25
−30
−50
C017
−25
0
25
50
75
Temperature (°C)
100
125
150
G034
10-V positive step
Figure 29. Large-Signal Settling Time
Figure 30. Short-Circuit Current vs Temperature
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140
40
VS = ±15V
120
30
EMIRR IN+ (dB)
Output Voltage (VPP)
35
Maximum output voltage without
slew-rate induced distortion.
25
20
15
10
5
VS = ±2.25V
80
60
40
1k
10k
100k
1M
Frequency (Hz)
0
10M
C001
Figure 31. Maximum Output Voltage vs Frequency
12
PRP = -10dBm
VS = ±18V
VCM = 0V
20
0
100
100
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100M
1G
10G
Frequency (Hz)
Figure 32. EMIRR IN+ vs Frequency
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7 Detailed Description
7.1 Overview
The TLV07 operational amplifier provides high overall performance, making the device suitable for many generalpurpose applications. The excellent offset drift of only 0.9 μV/°C provides excellent stability over the entire
temperature range. In addition, the device offers very good overall performance with high CMRR, PSRR, and
AOL.
7.2 Functional Block Diagram
PCH
FF Stage
Ca
Cb
+IN
PCH
Input Stage
2nd Stage
Output
Stage
OUT
-IN
NCH
Input Stage
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7.3 Feature Description
7.3.1 Operating Characteristics
The TLV07 op amp is specified for operation from 2.7 V to 36 V (±1.35 V to ±18 V). Many of the specifications
apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are shown in Typical Characteristics.
7.3.2 Phase-Reversal Protection
Output Voltage (5 V/div)
The TLV07 has an internal phase-reversal protection. Many operational amplifiers exhibit a phase reversal when
the input drives beyond the linear common-mode range. This condition is most often encountered in noninverting
circuits when the input drives beyond the specified common-mode voltage range, which causes the output to
reverse into the opposite rail. The input of the TLV07 prevents phase reversal with excessive common-mode
voltage. Instead, the output limits into the appropriate rail. This performance is shown in Figure 33.
Time (1 ms/div)
C017
Figure 33. No Phase Reversal
7.3.3 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
The questions typically focus on the device inputs, but may involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Internal electrostatic discharge (ESD) protection is built into the circuits to protect the circuits from accidental
ESD events before and during product assembly.
A good understanding of this basic ESD circuitry and the relevance of the circuitry to an electrical overstress
event is helpful. Figure 34 shows the ESD circuits contained in the TLV07 (indicated by the dashed line area).
The ESD protection circuitry involves several current-steering diodes connected from the input and output pins
and routed back to the internal power-supply lines, where the diodes meet at the power-supply ESD cell, an
absorption device, internal to the operational amplifier. This protection circuitry is intended to remain inactive
during normal circuit operation.
14
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Feature Description (continued)
TVS
+
±
RF
+VS
R1
IN±
2.5N Ÿ
RS
IN+
2.5k
Ÿ
+
Power-Supply
ESD Cell
ID
VIN
RL
+
±
+
±
±VS
TVS
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Figure 34. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, highcurrent pulse when discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more
steering diodes. Depending on the path that the current takes, the absorption device can activate. The absorption
device has a trigger, or threshold voltage, that is above the normal operating voltage of the TLV07, but below the
device breakdown voltage level. When this threshold is exceeded, the absorption device quickly activates and
clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit (see Figure 34), the ESD protection components are
intended to remain inactive and do not become involved in the application circuit operation. However,
circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. If this
condition occurs, there is a risk that some internal ESD protection circuits can turn on and conduct current. Any
such current flow occurs through steering-diode paths and rarely involves the absorption device.
Figure 34 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+) by
500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can sink the
current, one of the upper input steering diodes conducts and directs current to V+. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN sources current to the operational amplifier and becomes
the source of positive supply voltage. The danger in this case is that the voltage can rise to levels that exceed
the operational amplifier absolute maximum ratings.
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Feature Description (continued)
Another common question involves what happens to the amplifier if an input signal is applied to the input when
the power supplies (V+ or V–) are at 0 V. This question depends on the supply characteristic when at 0 V, or at a
level below the input signal amplitude. If the supplies appear as high impedance, then the input source supplies
the operational amplifier current through the current-steering diodes. This state is not a normal bias condition;
most likely, the amplifier does not operate normally. If the supplies are low impedance, then the current through
the steering diodes can become quite high. The current level depends on the ability of the input source to deliver
current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, add external Zener diodes to the
supply pins; see Figure 34. Select the Zener voltage so that the diode does not turn on during normal operation.
However, the Zener voltage must be low enough so that the Zener diode conducts if the supply pin begins to rise
above the safe-operating, supply-voltage level.
The TLV07 input pins are protected from excessive differential voltage with back-to-back diodes; see Figure 34.
In most circuit applications, the input protection circuitry has no effect. However, in low-gain or G = 1 circuits,
fast-ramping input signals can forward-bias these diodes because the output of the amplifier cannot respond
rapidly enough to the input ramp. If the input signal is fast enough to create this forward-bias condition, limit the
input signal current to 10 mA or less. If the input signal current is not inherently limited, use an input series
resistor to limit the input signal current.
7.4 Device Functional Modes
7.4.1 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from the saturated state to
the linear state. The output devices of the op amp enter the saturation region when the output voltage exceeds
the rated operating voltage resulting from the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices must have time to return back to the normal state.
After the charge carriers return back to the equilibrium state, the device begins to slew at the normal slew rate.
As a result, the propagation delay (in case of an overload condition) is the sum of the overload recovery time and
the slew time. The overload recovery time for the TLV07 is approximately 2 µs.
16
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV07 op amp provides high overall performance in a large number of general-purpose applications. As with
all amplifiers, applications with noisy or high-impedance power supplies require decoupling capacitors placed
close to the device pins. In most cases, 0.1-µF capacitors are adequate. Follow the additional recommendations
in Layout Guidelines to achieve the maximum performance from this device. Many applications may introduce
capacitive loading to the output of the amplifier, potentially causing instability. Add an isolation resistor between
the amplifier output and the capacitive load to stabilize the amplifier. Typical Application shows the design
process for selecting this resistor.
8.2 Typical Application
This circuit can drive capacitive loads such as cable shields, reference buffers, MOSFET gates, and diodes. The
circuit uses an isolation resistor (RISO) to stabilize the output of an op amp. RISO modifies the open-loop gain of
the system to ensure the circuit has sufficient phase margin.
+VS
VOUT
RISO
+
VIN
+
±
CLOAD
-VS
Figure 35. Unity-Gain Buffer With RISO Stability Compensation
8.2.1 Design Requirements
The design requirements are:
• Supply voltage: 30 V (±15 V)
• Capacitive loads: 100 pF, 1000 pF, 0.01 μF, 0.1 μF, and 1 μF
• Phase margin: 45° and 60°
8.2.2 Detailed Design Procedure
Figure 35 shows a unity-gain buffer driving a capacitive load. Equation 1 shows the transfer function for the
circuit in Figure 35. Figure 35 does not show the open-loop output resistance of the op amp (RO).
1 + CLOAD × RISO × s
T(s) =
1 + Ro + RISO × CLOAD × s
(1)
The transfer function shown in Equation 1 has a pole and a zero. (RO + RISO) and CLOAD determine the frequency
of the pole (fp). The RISO and CLOAD components determine the frequency of the zero (fz). A stable system is
obtained by selecting RISO such that the rate of closure (ROC) between the open-loop gain (AOL) and 1/β is 20
dB/decade.
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Typical Application (continued)
ROC stability analysis is typically simulated. The validity of the analysis depends on multiple factors, especially
the accurate modeling of R O. In addition to simulating the ROC, a robust stability analysis includes a
measurement of overshoot percentage and ac gain peaking of the circuit using a function generator,
oscilloscope, and gain and phase analyzer. These measurements then calculate phase margin. Table 2 shows
the overshoot percentage and ac gain peaking that correspond to phase margins of 45° and 60°. For more
details on this design and other alternative devices that can be used in place of the TLV07, see Capacitive Load
Drive Solution Using an Isolation Resistor
Table 2. Phase Margin versus Overshoot and AC Gain
Peaking
PHASE
MARGIN
OVERSHOOT
AC GAIN PEAKING
45°
23.3%
2.35 dB
60°
8.8%
0.28 dB
8.2.3 Application Curve
The values of RISO that yield phase margins of 45° and 60° for various capacitive loads are determined using the
described methodology Figure 36 shows the results.
10000
45° Phase Margin
Isolation Resistor (RISO,
)
60° Phase Margin
1000
100
10
0.1
1
10
100
Capacitive Load (nF)
1000
C002
Figure 36. Isolation Resistor Required for Various Capacitive Loads to Achieve a Target Phase Margin
9 Power Supply Recommendations
The TLV07 is specified for operation from 2.7 V to 36 V (±1.35 V to ±18 V); many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in Typical Characteristics.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see Absolute
Maximum Ratings.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see Layout
Guidelines.
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the op amp
itself. Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the
analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are typically devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Take care to physically
separate digital and analog grounds, paying attention to the flow of the ground current.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much
better than in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in Figure 38, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
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10.2 Layout Example
+
VIN
VOUT
RG
RF
Figure 37. Schematic Representation of a Non-inverting Amplifier
Run the input traces
as far away from
the supply lines
as possible
Place components close
to device and to each
other to reduce parasitic
errors
RF
VS+
N/C
N/C
GND
±IN
V+
VIN
+IN
OUTPUT
V±
N/C
RG
GND
GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitors
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Figure 38. Operational Amplifier Board Layout for a Noninverting Configuration
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
11.1.2.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™ is
a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a
range of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency
domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the WEBENCH® Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.1.2.2 DIP Adapter EVM
The DIP Adapter EVM tool provides an easy, low-cost way to prototype small surface mount devices. The
evaluation tool these TI packages: D or U (SOIC-8), PW (TSSOP-8), DGK (MSOP-8), DBV (SOT23-6, SOT23-5
and SOT23-3), DCK (SC70-6 and SC70-5), and DRL (SOT563-6). The DIP Adapter EVM may also be used with
terminal strips or may be wired directly to existing circuits.
11.1.2.3 Universal Op Amp EVM
The Universal Op Amp EVM is a series of general-purpose, blank circuit boards that simplify prototyping circuits
for a variety of device package types. The evaluation module board design allows many different circuits to be
constructed easily and quickly. Five models are offered, with each model intended for a specific package type.
PDIP, SOIC, MSOP, TSSOP and SOT-23 packages are all supported.
NOTE
These boards are unpopulated, so users must provide their own devices. TI recommends
requesting several op amp device samples when ordering the Universal Op Amp EVM.
11.1.2.4 TI Precision Designs
TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the
theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and
measured performance of many useful circuits. TI Precision Designs are available online at
http://www.ti.com/ww/en/analog/precision-designs/.
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Device Support (continued)
11.1.2.5 WEBENCH® Filter Designer
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The
WEBENCH® Filter Designer allows the user to create optimized filter designs using a selection of TI operational
amplifiers and passive components from TI's vendor partners.
Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows the
user to design, optimize, and simulate complete multistage active filter solutions within minutes.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following (available for download from www.ti.com) :
• Feedback Plots Define Op Amp AC Performance
• Capacitive Load Drive Solution Using an Isolation Resistor
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV07IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLV07
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
