TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
features
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Fast Throughput Rate: 1.25 MSPS at 5 V,
625 KSPS at 3 V
Wide Analog Input: 0 V to AVDD
Differential Nonlinearity Error: < ± 1 LSB
Integral Nonlinearity Error: < ± 1 LSB
8-to-1 Analog MUX – TLV1578
Internal OSC
Single 2.7-V to 5.5-V Supply Operation
Low Power: 12 mW at 3 V and 35 mW at 5 V
Auto Power Down of 1 mA Max
Software Power Down: 10 µA Max
Hardware Configurable
DSP and Microcontroller Compatible
Parallel Interface
Binary/Twos Complement Output
Hardware Controlled Extended Sampling
Channel Sweep Mode Operation and
Channel Select
Hardware or Software Start of Conversion
applications
D
D
D
D
D
D
Mass Storage and HDD
Automotive
Digital Servos
Process Control
General-Purpose DSP
Image Sensor Processing
TLV1578
DA PACKAGE
(TOP VIEW)
CH0
CH1
CH2
CH3
CS
WR
RD
CLK
DGND
DVDD
INT/EOC
D0
D1
D2
D3
D4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CH7
CH6
CH5
CH4
MO
AIN
AVDD
AGND
REFM
REFP
CSTART
D9/A1
D8/A0
D7
D6
D5
TLV1571
DW OR PW PACKAGE
(TOP VIEW)
CS
WR
RD
CLK
DGND
DVDD
INT/EOC
D0
D1
D2
D3
D4
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
NC
AIN
AVDD
AGND
REFM
REFP
CSTART
D9/A1
D8/A0
D7
D6
D5
NC – No internal connection
description
The TLV1571/1578 is a 10-bit data acquisition system that combines an 8-channel input multiplexer (MUX), a
high-speed 10-bit ADC, and a parallel interface. The device contains two on-chip control registers allowing
control of channel selection, software conversion start, and power down via the bidirectional parallel port. The
control registers can be set to a default mode by applying a dummy RD signal when WR is tied low. This allows
the TLV1571/1578 to be configured by hardware. The MUX is independently accessible. This allows the user to
insert a signal conditioning circuit such as an antialiasing filter or an amplifier, if required, between the MUX and
the ADC. Therefore, one signal conditioning circuit can be used for all eight channels. The TLV1571 is a single
channel analog input device with all the same functions as the TLV1578.
The TLV1571/TLV1578 operates from a single 2.7-V to 5.5-V power supply. It accepts an analog input range
from 0 V to AVDD and digitizes the input at a maximum 1.25 MSPS throughput rate at 5 V. The power dissipations
are only 12 mW with a 3-V supply or 35 mW with a 5-V supply. The device features an auto power-down mode
that automatically powers down to 1 mA 50 ns after conversion is performed. In software power-down mode, the
ADC is further powered down to only 10 µA.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
description (continued)
Very high throughput rate, simple parallel interface, and low power consumption make the TLV1571/TLV1578
an ideal choice for high-speed digital signal processing requiring multiple analog inputs.
AVAILABLE OPTIONS
PACKAGE
TA
32 TSSOP
(DA)
0°C to 70°C
TLV1578CDA
TLV1571CDW
TLV1571CPW
– 40°C to 85°C
TLV1578IDA
TLV1571IDW
TLV1571IPW
24 SOP
(DW)
24 TSSOP
(PW)
functional block diagram – TLV1571/78
MO
CH0 – CH7
REFP
AVDD AIN
REFM
DVDD
MUX
10-BIT
SAR ADC
TLV1578 Only
Internal
Clock
Three
State
Latch
D0 – D7
D8/A0
D9/A1
MUX
CLK
CS
RD
WR
CSTART
Input Registers
and Control Logic
AGND
2
POST OFFICE BOX 655303
INT/EOC
DGND
• DALLAS, TEXAS 75265
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
Terminal Functions
NAME
TERMINAL
NO.
I/O
DESCRIPTION
TLV1571
TLV1578
AGND
21
25
AIN
23
27
AVDD
22
26
CH0 – CH7
–
1– 4,
29–32
I
Analog input channels
CLK
4
8
I
External clock input
Analog ground
I
ADC analog input (used as single analog input channel for TLV1571)
Analog supply voltage, 2.7 V to 5.5 V
CS
1
5
I
Chip select. A logic low on CS enables the TLV1571/ TLV1578.
CSTART
18
22
I
Hardware sample and conversion start input. The falling edge of CSTART starts sampling and
the rising edge of CSTART starts conversion.
DGND
5
9
DVDD
Digital ground
6
10
8 –12,
13 –15
12 –16,
17–19
I/O
Bidirectional 3-state data bus
D8/A0
16
20
I/O
Bidirectional 3-state data bus. D8/A0 along with D9/A1 is used as address lines to access CR0
and CR1 for initialization.
D9/A1
17
21
I/O
Bidirectional 3-state data bus. D9/A1 along with D8/A0 is used as address lines to access CR0
and CR1 for initialization.
INT/EOC
7
11
O
End-of-conversion/interrupt
28
O
On-chip MUX analog output
D0 – D7
MO
NC
Digital supply voltage, 2.7 V to 5.5 V
24
Not connected
RD
3
7
I
Read data. A falling edge on RD enables a read operation on the data bus when CS is low.
REFM
20
24
I
Lower reference voltage (nominally ground). REFM must be supplied or REFM pin must be
grounded.
REFP
19
23
I
Upper reference voltage (nominally AVDD). The maximum input voltage range is determined by
the difference between the voltage applied to REFP and REFM.
WR
2
6
I
Write data. A rising edge on the WR latches in configuration data when CS is low. When using
software conversion start, a rising edge on WR also initiates an internal sampling start pulse.
When WR is tied to ground, the ADC in nonprogrammable (hardware configuration mode).
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
detailed description
Ain
Charge
Redistribution
DAC
_
+
REFM
SAR
Register
ADC Code
Control
Logic
Figure 1. Analog-to-Digital SAR Converter
The TLV1571/78 is a successive-approximation ADC utilizing a charge redistribution DAC. Figure 1 shows a
simplified version of the ADC.
The sampling capacitor acquires the signal on AIN during the sampling period. When the conversion process
starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is
balanced, the conversion is complete and the ADC output code is generated.
sampling frequency, fs
The TLV1571/TLV1578 requires 16 CLKs for each conversion, (assuming the read cycle takes 1 CLK). The
equivalent maximum sampling frequency achievable with a given CLK frequency is:
fs(max) = (1/17) fCLK
The TLV1571 and TLV1578 are software configurable. The first two MSB bits, D(9,8) are used to address which
register to set. The rest of the eight bits are used as control data bits. There are two control registers, CR0 and
CR1, that are user configurable. All of the register bits are written to the control register during write cycles. A
description of the control registers is shown in Figure 2.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
detailed description (continued)
control registers
A1
A0
A(1:0)=00
D7
D6
Control Register Zero (CR0)
D7
D6
D5
STARTSEL PROGEOC CLKSEL
0:
0:
HARDWARE INT
START
(CSTART)
1:
EOC
1:
SOFTWARE
START
A(1:0)=01
D5
D4
D3
D2
D4
SWPWDN
D3
MODESEL
D2
0:
NORMAL
0:
Internal
Clock
1:
External
Clock
1:
Power
Down
0:
Single
Channel
1:
Sweep
Mode
Control Register One (CR1)
D7‡
D6
D3
D5‡
D4‡
RESERVED OSCSPD 0 Reserved 0 Reserved OUTCODE
0:
Reserved
Bit
Always
Write 0
0:
INT. OSC.
SLOW
1:
INT. OSC.
FAST
0:
Reserved
Bit
Always
Write 0
0:
Reserved
Bit,
Always
Write 0
D1
D0
D1
CHSEL(2–0)†
D0
D(2– 0)
Single
Input
Channels Swept
0h
0
0,1
1h
1
0,1,2,3
2h
2
0,1,2,3,4,5,
3h
3
0,1,2,3,4,5,6,7
4h
4
N/A
5h
5
N/A
6h
6
N/A
7h
7
N/A
D2
READREG
D1
STEST1
0:
Binary
0:
Enable Self
Test
1:
1:
Enable
2s
Register
Complement Read back
CR1.(1–0)
0h
1h
2h
3h
0h
D0
STEST0
IF READREG = 0
ACTION
Output =
CONVERSION result
Output =
SELF TEST 1 result
Output =
SELF TEST 2 result
Output =
SELF TEST 3 result
IF READREG = 1
Output Contents of
CR0
1h
Output Contents of
CR1
2h
RESERVED
3h
RESERVED
† Don’t care for TLV1571
‡ When in read back mode, the values read from the control register reserved bits are don’t care.
Figure 2. Input Data Format
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
detailed description (continued)
hardware configuration option
The TLV1571/TLV1578 can configure itself. This option is enabled when the WR pin is tied to ground and a
dummy RD signal is applied. The ADC is now fully configured. Zeros or default values are applied to both control
registers. The ADC is configured ideally for 3-V operation, which means the internal OSC is set at 10 MHz, single
channel input mode, and hardware start of conversion using CSTART.
ADC conversion modes
The TLV1571/TLV1578 provides two conversion modes and two start of conversion modes. In single channel
input mode, a single channel is continuously sampled and converted. In sweep mode (only available for the
TLV1578), a predetermined set of channels is continuously sampled and converted. Table 1 explains these
modes in more detail.
Table 1. Conversion Modes
MODES
Single
Channel
Input†
CR0.D3 = 0
CR1.D7 = 0
Channel
Sweep
CR0.D3 = 1
CR1.D7 = 0
START OF
CONVERSION
OPERATION
Hardware
Start
(CSTART)
CR0.D7 = 0
•
•
•
•
•
Software
Start
CR0.D7 = 1
• Repeated conversions from a selected channel
• WR rising edge to start sampling initially. Thereafter, sampling occurs at the rising
edge of RD.
• Conversion begins after 6 clocks after sampling has begun. Thereafter, if in INT
mode, one INT pulse is generated after each conversion
• If in EOC mode, EOC will go high to low at start of conversion and return high at
end of conversion.
With external clock, WR
and RD rising edge must be
a minimum 5 ns before or
after CLK rising edge.
Hardware
Start
(CSTART)
CR0.D7 = 0
•
•
•
•
•
CSTART rising edge must
be applied a minimum of
5 ns before or after CLK
rising edge.
Software
Start
CR0.D7 = 1
• One conversion per channel from a sequence of channels
• WR rising edge to start sampling
• ADC proceeds to sample next channel at rising edge of RD. Conversion begins
after 6 clocks and lasts 10 clocks
• If in INT mode, one INT pulse generated after each conversion
• If in EOC mode, EOC will go high to low at start of conversion and return high at
end of conversion.
Repeated conversions from a selected channel
CSTART falling edge to start sampling
CSTART rising edge to start conversion
If in INT mode, one INT pulse generated after each conversion
If in EOC mode, EOC will go high to low at start of conversion, and return high
at end of conversion.
One conversion per channel from a predetermined sequence of channels
CSTART falling edge to start sampling
CSTART rising edge to start conversion
If in INT mode, one INT pulse generated after each conversion
If in EOC mode, EOC will go high to low at start of conversion, and return high
at end of conversion.
† Single channel input mode repeatedly samples and converts from the channel until WR is applied.
6
COMMENT–SET BITS
CR0.D(2–0) FOR INPUT
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CSTART rising edge must
be applied a minimum of
5 ns before or after CLK
rising edge.
With external clock, WR
and RD rising edge must be
a minimum 5 ns before or
after CLK rising edge.
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
detailed description (continued)
configure the device
The device can be configured by writing to control registers CR0 and CR1.
Table 2. TLV1571/TLV1578 Programming Examples
INDEX
REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
COMMENT
0
0
0
0
0
0
0
0
0
Single channel
0
1
0
0
0
0
0
1
0
0
Single Input
CR0
0
0
0
1
1
0
1
0
1
1
Sweep mode
CR1
0
1
0
0
0
0
1
1
0
0
2s complement output
D9
D8
CR0
0
CR1
EXAMPLE1
EXAMPLE2
register read back
Control data written to the TLV1571/78 can be read back from the control registers CR0 and CR1. See Figure 2.
NOTE:
Data read out of CR1 reserved bits is don’t care.
power down
The TLV1571/TLV1578 offers two power down modes, auto power down and software power down. This device
will automatically proceed to auto power-down mode if RD is not present one clock after conversion. Software
power down is controlled directly by the user by pulling CS to DVDD.
Table 3. Power Down Modes
PARAMETERS/MODES
AUTO POWER DOWN
SOFTWARE POWER DOWN
(CS = DVDD)
1 mA
10 µA
Comparator
Power down
Power down
Clock buffer
Maximum power down dissipation current
Power down
Power down
Reference
Active
Power down
Control registers
Saved
Saved
Minimum power down time
1 CLK
2 CLK
Minimum resume time
1 CLK
2 CLK
self-test modes
The TLV1571/TLV1578 provides three self test modes. These modes can be used to check whether the ADC
itself is working properly without having to supply an external signal. There are three tests that are controlled
by writing to CR1(D1,D0) (see Table 4).
Table 4. Self Tests
CR1(D1,D0)
SELF TEST VOLTAGE APPLIED
DIGITAL OUTPUT
0h
Normal, no self test applied
N/A
1h
VREFM applied to ADC input internally
000h
2h
(VREFP–VREFM)/2 applied to ADC input internally
200h
3h
VIN = VREFP applied to ADC input internally
3FFh
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
detailed description (continued)
reference voltage input
The TLV1571/TLV1578 has two reference input pins: REFP and REFM. The voltage levels applied to these pins
establish the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading
respectively. The values of REFP, REFM, and the analog input should not exceed the positive supply or be less
than GND consistent with the specified absolute maximum ratings. The digital output is at full scale when the
input signal is equal to or higher than REFP and is at zero when the input signal is equal to or lower than REFM.
sampling/conversion
All sampling, conversion, and data output in the device are started by a trigger. This could be the RD, WR, or
CSTART signal depending on the mode of conversion and configuration. The rising edge of RD, WR, and
CSTART signal are extremely important, since they are used to start the conversion. These edges need to stay
close to the rising edge of the external clock (if external clock is used as source of conversion clock). The
minimum setup and hold time with respect to the rising edge of the external clock should be 5 ns minimum. When
the internal clock is used, this is not an issue since these two edges will start the internal clock automatically.
Therefore, the setup time is always met. Software controlled sampling lasts 6 clock cycles. This is done via the
CLK input or the internal oscillator if enabled. The input clock frequency can be 1 MHz to 20 MHz, translating
into a sampling time from 0.6 µs to 0.3 µs. The internal oscillator frequency is 9 MHz minimum (oscillator
frequency is between 9 MHz to 22 MHz), translating into a sampling time from 0.6 µs to 0.3 µs. Conversion
begins immediately after sampling and lasts 10 clock cycles. This is again done using the external clock input
(1 MHz–20 MHz) or the internal oscillator (9 MHz minimum) if enabled. Hardware controlled sampling, via
CSTART, begins on falling CSTART lasts the length of the active CSTART signal. This allows more control over
the sampling time, which is useful when sampling sources with large output impedances. On rising CSTART,
conversion begins. Conversion in hardware controlled mode also lasts 10 clock cycles. This is done using the
external clock input (1 MHz–20 MHz) or the internal oscillator (9 MHz minimum) as is the case in software
controlled mode.
ExtClk
th(WRL_EXTCLKH) ≥5 ns
tsu(WRH_EXTCLKH) ≥5 ns
WR
OR
th(RDL_EXTCLKH) ≥5 ns
tsu(RDH_EXTCLKH) ≥5 ns
RD
OR
th(CSTARTL_EXTCLKH) ≥5 ns
td(EXTCLK_CSTARTL) ≥5 ns
tsu(CSTARTH_EXTCLKH) ≥5 ns
CSTART
NOTE: tsu = setup time, th = hold time
Figure 3. Trigger Timing – Software Start Mode Using External Clock
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
start of conversion mechanism
There are two ways to convert data: hardware and software. In the hardware conversion mode the ADC begins
sampling at the falling edge of CSTART and begins conversion at the rising edge of CSTART. Software start
mode ADC samples for 6 clocks, then conversion occurs for ten clocks. The total sampling and conversion
process lasts only 16 clocks in this case. If RD is not detected during the next clock cycle, the ADC automatically
proceeds to a power-down state. Data is valid on the rising edge of INT in both conversion modes.
hardware CSTART conversion
external clock
With CS low and WR low, data is written into the ADC. The sampling begins at the falling edge of CSTART and
conversion begins at the rising edge of CSTART. At the end of conversion, EOC goes from low to high, telling
the host that conversion is ready to be read out. The external clock is active and is used as the reference at all
times. With this mode, it is required that CSTART is not applied at the rising edge of the clock (see Figure 4).
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
15
16
t su(CSL_WRL)
t h(WRH_CSH)
t su(CSL_RDL)
t su(CSL_RDL)
CS
WR
t h(RDH_CSH)
t d(CSH_CSTARTL)
t(sample)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
(Channel 0)
(see Note A)
tc
tc
(10 I/O CLKs)
t(sample)
(Channel 0)
(see Note A)
CSTART
RD
t
su(DAV_WRH)
t
D[0:9]
t d(EOC_RDL)
t dis(RDH_DAV)
h(WRH_DAV)
Config
Data
ADC
ADC
t en(RDL_DAV)
t en(RDL_DAV)
INT
OR
EOC
Auto Power Down
NOTE A: AIN for TLV1571; channels sweep according to register settings.
Figure 4. Multichannel Input Mode Conversion – Hardware CSTART, External Clock
TLV1571, TLV1578
2.7 V to 5.5 V, 1-/8-CHANNEL, 10-BIT,
RARALLEL ANALOG-TO-DIGITAL CONVERTERS
6
CLK
SLAS170D – MARCH 1999 – REVISED JULY 2000
10
start of conversion mechanism (continued)
internal clock
In single channel input mode, with CS low and WR low, data is written into the ADC. The sampling begins at the falling edge of CSTART, and
conversion begins at the rising edge of CSTART. The internal clock turns on at the rising edge of CSTART. The internal clock is disabled after
each conversion.
t su(CSL_WRL)
t h(WRH_CSH)
t su(CSL_RDL)
t su(CSL_RDL)
CS
t
d(CSH_CSTARTL)
WR
t (STARTOSC)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
t(sample)
(Channel 0)
(see Note A)
t h(RDH_CSH)
tc
CSTART
0
1
9
tc
(Channel 1)
(see Note A)
10
t (STARTOSC)
RD
t su(DAV_WRH)
t d(EOC_RDL)
t h(WRH_DAV)
D[0:9]
t dis(RDH_DAV)
Config
Data
ADC
Data
ADC
Data
t en(RDL_DAV)
INT
tc
OR
EOC
Auto Power Down
Auto Power Down
NOTE A: AIN for TLV1571; channels sweep according to register settings.
11
Figure 5. Multichannel Input Mode Conversion – Hardware CSTART, Internal Clock
SLAS170D – MARCH 1999 – REVISED JULY 2000
t en(RDL_DAV)
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
INTCLK
With CS low and WR low, data is written into the ADC. Sampling begins at the rising edge of WR. The conversion process begins 6 clocks
after sampling begins. At the end of conversion, INT goes low telling the host that conversion is ready to be read out. EOC is low during the
conversion and makes a high-to-low transition at the end of the conversion. The external clock is active and is used as the reference at all
times. With this mode, WR and RD should not be applied at the rising edge of the clock (see Figure 3).
0
1
5
6
7
15
16
0
4
5
15
CLK
t su(CSL_WRL)
t su(CSL_RDL)
t h(WRH_CSH)
t h(RDH_CSH)
t su(CSL_RDL)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CS
WR
RD
t(sample)
(Channel 0)
(see Note A)
t su(DAV_WRH)
t(sample)
(Channel 1)
(see Note A)
tc
t d(EOC_RDL)
t dis(RDH_DAV)
t h(WRH_DAV)
D[0:9]
Config
Data
tc
ADC Data
ADC Data
t en(RDL_DAV)
t en(RDL_DAV)
INT
OR
EOC
Auto Powerdown
NOTE A: AIN for TLV1571; channels sweep according to register settings.
Figure 6. Multichannel Input Mode Conversion – Software Start, External Clock
TLV1571, TLV1578
2.7 V to 5.5 V, 1-/8-CHANNEL, 10-BIT,
RARALLEL ANALOG-TO-DIGITAL CONVERTERS
external clock
SLAS170D – MARCH 1999 – REVISED JULY 2000
12
software START conversion
software START conversion (continued)
internal clock
With CS low and WR low, data is written into the ADC. Sampling begins at the rising edge of WR. Conversion begins 6 clocks after sampling
begins. The internal clock begins at the rising edge of WR. The internal clock is disabled after each conversion. Subsequent sampling begins
at the rising edge of RD.
t su(CSL_RDL)
t su(CSL_WRL)
t h(RDH_CSH)
CS
t h(WRH_CSH)
WR
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
RD
t (STARTOSC)
4
5
6
15
16
0
4
5
15
INTCLK
t(sample)
(Channel 0)
(see Note A)
t d(EOC_RDL)
t su(DAV_WRH)
t h(WRH_DAV)
D[0:9]
t(sample)
(Channel 1)
(see Note A)
t dis(RDH_DAV)
tc
ADC
Data
ADC
t en(RDL_DAV)
INT
OR
EOC
Auto Powerdown
NOTE A: AIN for TLV1571; channels sweep according to register settings.
Figure 7. Multichannel Input Mode Conversion – Software Start, Internal Clock
Auto Powerdown
13
SLAS170D – MARCH 1999 – REVISED JULY 2000
Config
Data
tc
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
0
t (STARTOSC)
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
software START conversion (continued)
system clock source
The TLV1571/TLV1578 internally derives multiple clocks from the SYSCLK for different tasks. SYSCLK is used
for most conversion subtasks. The source of SYSCLK is programmable via control register zero bit 5. The
source of SYSCLK is changed at the rising edge of WR of the cycle when CR0.D5 is programmed.
internal clock (CR0.D5 = 0, SYSCLK = internal OSC)
The TLV1571/TLV1578 has a built-in 10 MHz OSC. When the internal OSC is selected as the source of
SYSCLK, the internal clock starts with a delay (one half of the OSC period max) after the falling edge of the
conversion trigger (either WR, RD, or CSTART). The OSC speed can be set to 10 ± 1 MHz or 20 ± 2 MHz by
setting register bit CR1.6.
external clock (CR0.D5 = 1, SYSCLK = external clock)
The TLV1571/TLV1578 is designed to accept an external clock input (CMOS/TTL logic) with frequencies from
1 MHz to 20 MHz.
host processor interface
The TLV1571/TLV1578 provides a generic high-speed parallel interface that is compatible with
high-performance DSPs and general-purpose microprocessors. The interface includes D(0–9), INT/EOC, RD,
and WR.
output format
The data output format is unipolar (code 0 to 1023) when the device is operated in single-ended input mode.
The output code format can be either binary or twos complement by setting register bit CR1.D3.
power up and initialization
After power up, CS must be low to begin an I/O cycle. INT/EOC is initially high. The TLV1571/TLV1578 requires
two write cycles to configure the two control registers. The first conversion after the device has returned from
the power-down state may be invalid and should be disregarded.
definitions of specifications and terminology
integral nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.
The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level
1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to
the true straight line between these two points.
differential nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.
A differential nonlinearity error of less than ±1 LSB ensures no missing codes.
zero offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.
gain error
The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition
should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual
difference between first and last code transitions and the ideal difference between first and last code transitions.
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
software START conversion (continued)
signal-to-noise ratio + distortion (SINAD)
Signal-to-noise ratio + distortion is the ratio of the rms value of the measured input signal to the rms sum of all
other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
effective number of bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
N = (SINAD – 1.76)/6.02
it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, the effective
number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its
measured SINAD.
total harmonic distortion (THD)
Total harmonic distortion is the ratio of the rms sum of the first six harmonic components to the rms value of the
measured input signal and is expressed as a percentage or in decibels.
spurious free dynamic range (SFDR)
Spurious free dynamic range is the difference in dB between the rms amplitude of the input signal and the peak
spurious signal.
DSP interface
The TLV1571/TLV1578 is a 10-bit 1-/8-analog input channel analog-to-digital converter with throughput up to
1.25 MSPS at 5 V and up to 625 KSPS at 3 V. To achieve 1.25 MSPS throughput, the ADC must be clocked
at 20 MHz. Likewise to achieve 625 KSPS throughout, the ADC must be clocked at 10 MHz. The
TLV1571/TLV1578 can be easily interfaced to microcontrollers, ASICs, and DSPs. Figure 8 shows the pin
connections to interface the TLV1571/TLV1578 to the TMS320C6x DSP.
TMS320C6X
A0–A15
TLV1571/78
EN
Address
Decoder
CS
CH(1– 8)†
REF
HW
WR
HR
RD
EOC
INTx
REFP
REFM
D0– D9
D0– D15
† The TLV1571 has only one analog input (AIN).
Figure 8. TMS320C6x DSP Interface
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
grounding and decoupling considerations
General practices should apply to the PCB design to limit high frequency transients and noise that are fed back
into the supply and reference lines. This requires that the supply and reference pins be sufficiently bypassed.
In most cases 0.1-µF ceramic chip capacitors are adequate to keep the impedance low over a wide frequency
range. Since their effectiveness depends largely on the proximity to the individual supply pin, they should be
placed as close to the supply pins as possible.
To reduce high frequency and noise coupling, it is highly recommended that digital and analog grounds be
shorted immediately outside the package. This can be accomplished by running a low impedance line between
DGND and AGND under the package.
DVDD
AVDD
TLV1571/78
AVDD
100 nF
DVDD
100 nF
DGND
AGND
VREFP
REFP
VREFM
100 nF
REFM
Figure 9. Placement for Decoupling Capacitors
power supply ground layout
Printed-circuit boards that use separate analog and digital ground planes offer the best system performance.
Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected
together at the low-impedance power-supply source. The best ground connection may be achieved by
connecting the ADC AGND terminal to the system analog ground plane making sure that analog ground
currents are well managed.
Driving Source†
TLV1571/78
MO
Rs
VS
VI
Ri(MUX)
AIN
Ri(ADC)
VC
Ci
15 pF
VI = Input Voltage at AIN
VS = External Driving Source Voltage
Rs = Source Resistance
Ri(ADC)= Input Resistance of ADC
Ri(MUX)= Input Resistance (MUX on resistance)
Ci = Input Capacitance
VC = Capacitance Charging Voltage
† Driving source requirements:
• Noise and distortion for the source must be equivalent to the resolution of the converter.
• Rs must be real at the input frequency.
Figure 10. Equivalent Input Circuit Including the Driving Source
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
simplified analog input analysis
Using the equivalent circuit in Figure 9, the time required to charge the analog input capacitance from 0 to VS
within 1/2 LSB, tch(1/2 LSB), can be derived as follows.
ǒ
Ǔ
The capacitance charging voltage is given by:
V
C(t)
+ VS 1–e–tchńRtCi
Where:
(1)
Rt = Rs + Ri
Ri = Ri(ADC) + Ri(MUX)
tch = Charge time
The input impedance Ri is 718 Ω at 5 V, and is higher (~ 1.25 kΩ) at 2.7 V. The final voltage to 1/2 LSB is given
by:
(2)
VC (1/2 LSB) = VS – (VS /2048)
ǒ
Ǔ
Equating equation 1 to equation 2 and solving for cycle time tc gives:
V
S
ǒ
Ǔ
* VSń2048 + VS 1–e–tchńRtCi
and time to change to 1/2 LSB (minimum sampling time) is:
(3)
tch (1/2 LSB) = Rt × Ci × ln(2048)
Where:
ln(2048) = 7.625
Therefore, with the values given, the time for the analog input signal to settle is:
tch (1/2 LSB) = (Rs + 718 Ω) × 15 pF × ln(2048)
(4)
This time must be less than the converter sample time shown in the timing diagrams, which is 6x SCLK.
tch (1/2 LSB) ≤ 6x 1/f(SCLK)
(5)
Therefore the maximum SCLK frequency is:
Max(f(SCLK) ) = 6 / tch (1/2 LSB) = 6/(ln(2048) × Rt × Ci )
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
(6)
17
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, GND to VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 6.5 V
Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to AVDD + 0.3 V
Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVDD + 0.3 V
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to DVDD + 0.3 V
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C
Operating free-air temperature range, TA: TLV1571C, TLV1578C . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
TLV1571I, TLV1578I . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
power supplies
MIN
MAX
UNIT
Analog supply voltage, AVDD
2.7
5.5
V
Digital supply voltage, DVDD
2.7
5.5
V
NOTE 1: Abs (AVDD – DVDD) < 0.5 V
analog inputs
Analog input voltage, AIN
MIN
MAX
UNIT
AGND
VREFP
V
digital inputs
MIN
NOM
2.1
2.4
MAX
UNIT
High-level input voltage, VIH
DVDD = 2.7 V to 5.5 V
Low level input voltage, VIL
DVDD = 2.7 V to 5.5 V
0.8
V
DVDD = 4.5 V to 5.5 V
20
MHz
DVDD = 2.7 V to 3.3 V
10
MHz
Input CLK frequency
Pulse duration
duration, CLK high
high, tw(CLKH)
(CLKH)
Pulse duration
duration, CLK low
low, tw(CLKL)
V
DVDD = 4.5 V to 5.5 V, fCLK = 20 MHz
23
ns
DVDD = 2.7 V to 3.3 V, fCLK = 10 MHz
46
ns
DVDD = 4.5 V to 5.5 V, fCLK = 20 MHz
23
ns
DVDD = 2.7 V to 3.3 V, fCLK = 10 MHz
46
ns
Rise time, I/O and control, CLK, CS
50 pF output load
4
Fall time, I/O and control, CLK, CS
50 pF output load
4
ns
reference specifications
MIN
External reference voltage
VREFP
AVDD = 3 V
AVDD = 5 V
VREFM
AVDD = 3 V
AVDD = 5 V
VREFP – VREFM
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MAX
UNIT
AVDD
AVDD
V
2.5
AGND
1
V
AGND
2
V
2
AVDD–AGND
V
2
NOM
V
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
electrical characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted)
digital specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Logic inputs
IIH
IIL
High-level input current
DVDD = 5 V, DVDD = 3 V, Input = DVDD
–1
1
µA
Low-level input current
DVDD = 5 V, DVDD = 3 V, Input = 0 V
–1
1
µA
Ci
Input capacitance
15
pF
10
Logic outputs
VOH
VOL
High-level output voltage
Low-level output voltage
IOH = 50 µA to 0.5 mA
IOL = 50 µA to 0.5 mA
IOZ
IOL
High-impedance-state output current
DVDD = 5 V, DVDD = 3 V, Input = DVDD
Low-impedance-state output current
DVDD = 5 V, DVDD = 3 V, Input = 0 V
Co
Output capacitance
Internal clock
DVDD– 0.4
V
0.4
V
1
µA
–1
µA
5
pF
3 V, AVDD = DVDD
9
10
11
5 V, AVDD = DVDD
18
20
22
MHz
dc specifications
PARAMETER
TEST CONDITIONS
MIN
Resolution
TYP
MAX
10
UNIT
Bits
Accuracy
Integral nonlinearity, INL
Best fit
Differential nonlinearity, DNL
± 0.5
±1
LSB
± 0.5
±1
LSB
Missing codes
EO
EG
0
Offset error
± 0.1%
± 0.15%
FSR
Gain error
± 0.1%
± 0.2%
FSR
Analog input
Ci
Input capacitance
Ilkg
Input leakage current
ri
Input MUX ON resistance
AIN, AVDD = 3 V, AVDD = 5 V
15
pF
MUX input, AVDD = 3 V, AVDD = 5 V
25
pF
±1
VAIN = 0 to AVDD
AVDD = DVDD = 3 V
240
680
AVDD = DVDD = 5 V
215
340
µA
Ω
Voltage reference input
ri
Input resistance
Ci
Input capacitance
2
kΩ
300
pF
Power supply
PD
IPD
Operating supply current,
current IDD + IREF
AVDD = DVDD = 3 V, fCLK = 10 MHz
AVDD = DVDD = 5 V, fCLK = 20 MHz
Power dissipation
AVDD+DVDD = 3 V
AVDD+DVDD = 5 V
4
5.5
mA
7
8.5
mA
12
17
mW
35
43
mW
Software
IDD + IREF
AVDD = 3 V
AVDD = 5 V
1
8
µA
2
10
µA
Auto
IDD + IREF
AVDD = 3 V
AVDD = 5 V
0.5
1
mA
0.5
1
mA
Supply current in power-down
power down mode
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
electrical characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted) (continued)
ac specifications, AVDD = DVDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fI = 100 kHz,,
80% of FS
Signal to noise ratio,
Signal-to-noise
ratio SNR
Signal to noise ratio + distortion,
Signal-to-noise
distortion SINAD
fI = 100 kHz,,
80% of FS
distortion THD
Total harmonic distortion,
fI = 100 kHz,,
80% of FS
Effective number of bits,
bits ENOB
fI = 100 kHz,,
80% of FS
range SFDR
Spurious free dynamic range,
fI = 100 kHz,,
80% of FS
MIN
TYP
fs = 1.25 MSPS, AVDD = 5 V
fs = 625 KSPS, AVDD = 3 V
fs = 1.25 MSPS, AVDD = 5 V
56
60
dB
58
60
dB
55
60
dB
fs = 625 KSPS, AVDD = 3 V
fs = 1.25 MSPS, AVDD = 5 V
fs = 625 KSPS, AVDD = 3 V
55
fs = 1.25 MSPS, AVDD = 5 V
fs = 625 KSPS, AVDD = 3 V
fs = 1.25 MSPS, AVDD = 5 V
9
9.3
Bits
9
9.3
Bits
fs = 625 KSPS,
AVDD = 3 V
MAX
60
UNIT
dB
–60
–56
dB
–60
–56
dB
–63
–56
dB
–63
–56
dB
Analog input
Channel-to-channel cross talk
Full power bandwidth
Full-power
Small-signal bandwidth
Sampling
Sam
ling rate,
rate fs
20
– 75
–1 dB
Full-scale 0 dB input sine wave
–3 dB
Full-scale 0 dB input sine wave
–1 dB
–20 dB input sine wave
–3 dB
–20 dB input sine wave
12
15
dB
18
MHz
30
MHz
20
MHz
35
MHz
AVDD = 4.5 V to 5.5 V
0.0625
1.25
MSPS
AVDD = 2.7 V to 3.3 V
0.0625
0.625
MSPS
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
timing requirements, AVDD = DVDD = 5 V (unless otherwise noted)
PARAMETER
tc(CLK)
Cycle time
time, CLK
t(sample)
Reset and sampling time
tc
TEST CONDITIONS
MIN
DVDD = 4.5 V to 5.5 V
50
TYP
MAX
UNIT
ns
DVDD = 2.7 V to 3.3 V
100
ns
6
SYSCLK
Cycles
Total conversion time
10
SYSCLK
Cycles
twL(EOC)
Pulse width, end of conversion, EOC
10
SYSCLK
Cycles
twL(INT)
Pulse width, interrupt
1
SYSCLK
Cycles
t(STARTOSC)
Start-up time, internal oscillator
td(CSH_ CSTARTL)
Delay time, CS high to CSTART low
100
ns
10
ns
DVDD = 5 V at 50 pF
20
ns
DVDD = 3 V at 50 pF
40
ns
DVDD = 5 V at 50 pF
5
ns
DVDD = 3 V at 50 pF
10
ns
ten(RDL_DAV)
en(RDL DAV)
Enable time,
time data out
tdis(RDH_DAV)
dis(RDH DAV)
Disable time
time, data out
tsu(CSL_WRL)
Setup time, CS to WR
5
th(WRH_CSH)
Hold time, CS to WR
5
ns
ns
tw(WR)
Pulse width, write
1
Clock
Period
tw(RD)
Pulse width, read
1
Clock
Period
tsu(DAV_WRH)
Setup time, data valid to WR
10
ns
th(WRH_DAV)
Hold time, data valid to WR
5
tsu(CSL_RDL)
Setup time, CS to RD
5
ns
th(RDH_CSH)
Hold time, CS to RD
5
ns
th(WRL_EXTXLKH)
Hold time WR to clock high
5
ns
th(RDL_EXTCLKH)
Hold time RD to clock high
5
ns
th(CSTARTL_EXTCLKH)
Hold time CSTART to clock high
5
ns
tsu(WRH_EXTCLKH)
Setup time WR high to clock high
5
ns
tsu(RDH_EXTCLKH)
Setup time RD high to clock high
5
ns
tsu(CSTARTH_EXTCLKH)
Setup time CSTART high to clock high
5
ns
td(EXTCLK_CSTARTL)
Delay time clock low to CSTART low
5
ns
5
ns
td(EOC_RDL)
Delay time, conversion end to RD ↓
NOTE: Specifications subject to change without notice.
Data valid is denoted as DAV.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
ns
21
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
TYPICAL CHARACTERISTICS
ANALOG MUX INPUT RESISTANCE
vs
INPUT CHANNEL NUMBER
SUPPLY CURRENT
vs
FREE AIR TEMPERATURE
600
I CC – Supply Current – mA
Analog MUX Input Resistance – Ω
700
500
400
300
200
AVDD = DVDD = 2.7 V
100
AVDD = DVDD = 5 V
0
0
1
2
3
4
5
6
7
8.0
7.5 AV
DD = DVDD = 5 V
7.0
6.5
6.0
5.5
5.0
4.5
4.0
AVDD = DVDD = 3 V
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80
TA – Free Air Temperature – °C
Input Channel Number
Figure 11
Figure 12
ANALOG INPUT BANDWIDTH
vs
FREQUENCY
SUPPLY CURRENT
vs
CLOCK FREQUENCY
1
7
0
AVDD = DVDD = 5 V
Analog Input Bandwidth – dB
I CC – Supply Current – mA
6
5
4
3
AVDD = DVDD = 3 V
2
–1
–2
–3
–4
AVDD = DVDD = 5 V,
AIN = 90% of FS,
REF = 5 V,
1
–5
0
0
2
4
6
8
10
12
14
16
18
20
TA = 25°C
–6
0.1
Figure 13
Figure 14
POST OFFICE BOX 655303
10
f – Frequency – MHz
fclock – Clock Frequency – MHz
22
1
• DALLAS, TEXAS 75265
100
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
TYPICAL CHARACTERISTICS
DNL – Differential Nonlinearity – LSB
DIFFERENTIAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
1.0
0.5
0.0
AVDD = DVDD = 3 V,
External Ref = 3 V,
CLK = 10 MHz,
TA = 25°C
–0.5
–1.0
0
256
512
768
1023
Digital Output Code
Figure 15
INL – Integral Nonlinearity – LSB
INTEGRAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
1.0
AVDD = DVDD = 3 V,
External Ref = 3 V,
CLK = 10 MHz,
TA = 25°C
0.5
0.0
–0.5
–1.0
0
256
512
768
1023
Digital Output Code
Figure 16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
TYPICAL CHARACTERISTICS
DNL – Differential Nonlinearity – LSB
DIFFERENTIAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
1.0
0.5
0.0
AVDD = DVDD = 5 V,
External Ref = 5 V,
CLK = 20 MHz,
TA = 25°C
–0.5
–1.0
0
256
512
768
1023
Digital Output Code
Figure 17
INL – Integral Nonlinearity – LSB
INTEGRAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
1.0
0.5
0.0
AVDD = DVDD = 5 V,
External Ref = 5 V,
CLK = 20 MHz,
TA = 25°C
–0.5
–1.0
0
256
512
Digital Output Code
Figure 18
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
768
1023
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
TYPICAL CHARACTERISTICS
EFFECTIVE NUMBER OF BITS
vs
FREQUENCY
ENOB – Effective Number of Bits – BITS
10
9
AVDD = DVDD = 3 V,
External Ref = 3 V
8
7
6
5
4
3
2
1
0
50
100
150
200
f – Frequency – kHz
250
Figure 19
EFFECTIVE NUMBER OF BITS
vs
FREQUENCY
ENOB – Effective Number of Bits – BITS
10
9
AVDD = DVDD = 5 V,
External Ref = 5 V
8
7
6
5
4
3
2
1
0
50
100 150 200 250 300 350 400 450 500
f – Frequency – kHz
Figure 20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
TYPICAL CHARACTERISTICS
FAST FOURIER TRANSFORM MAGNITUDE
vs
FREQUENCY
Magnitude – dB
0
AIN = 200 KHz
–20
CLK = 10 MHz
–40
AVDD = DVDD = 3 V
External Ref = 3 V
–60
–80
–100
–120
0
25
50
75
100
125
150
175
200
225
250
275
450
500
550
f – Frequency – kHz
Figure 21
FAST FOURIER TRANSFORM MAGNITUDE
vs
FREQUENCY
Magnitude – dB
0
AIN = 200 KHz
–20
CLK = 20 MHz
–40
AVDD = DVDD = 5 V
External Ref = 5 V
–60
–80
–100
–120
0
50
100
150
200
250
300
350
400
f – Frequency – kHz
Figure 22
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
MECHANICAL DATA
DA (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
38 PINS SHOWN
0,30
0,19
0,65
38
0,13 M
20
6,20
NOM
8,40
7,80
0,15 NOM
Gage Plane
1
19
0,25
A
0°– 8°
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
28
30
32
38
A MAX
9,80
11,10
11,10
12,60
A MIN
9,60
10,90
10,90
12,40
DIM
4040066 / D 11/98
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
MECHANICAL DATA
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PINS SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
16
0.010 (0,25) M
9
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.293 (7,45)
Gage Plane
0.010 (0,25)
1
8
0°– 8°
A
0.050 (1,27)
0.016 (0,40)
Seating Plane
0.104 (2,65) MAX
0.012 (0,30)
0.004 (0,10)
PINS **
0.004 (0,10)
16
20
24
28
A MAX
0.410
(10,41)
0.510
(12,95)
0.610
(15,49)
0.710
(18,03)
A MIN
0.400
(10,16)
0.500
(12,70)
0.600
(15,24)
0.700
(17,78)
DIM
4040000 / C 07/96
NOTES: A.
B.
C.
D.
28
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MS-013
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TLV1571CDW
ACTIVE
SOIC
DW
24
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
TLV1571C
Samples
TLV1571IDW
ACTIVE
SOIC
DW
24
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLV1571I
Samples
TLV1578CDA
ACTIVE
TSSOP
DA
32
46
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
TLV1578
Samples
TLV1578CDAR
ACTIVE
TSSOP
DA
32
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
TLV1578
Samples
TLV1578IDA
ACTIVE
TSSOP
DA
32
46
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TLV1578I
Samples
TLV1578IDAG4
ACTIVE
TSSOP
DA
32
46
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TLV1578I
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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