TLV1861DBVR

TLV1851, TLV1861 SNOSDE7A – DECEMBER 2022 – REVISED AUGUST 2023 TLV185x and TLV186x Family of 40 V, Nanopower Comparators 1 Features • • • • • • • • • • Low supply current: 440 nA per channel Wide supply range: 1.8 V to 40 V Over-the-rail inputs: common-mode range extends 40 V above (V-) independent of (V+) Fail-safe: high impedance inputs with no supply Power-on-reset provides a known startup condition No phase reversal for overdriven inputs Reverse battery protection up to 40 V Push-pull output option (TLV185x) Open-drain output option (TLV186x) Temperature range: -40°C to +125°C 2 Applications • • • • • • • • All devices include a Power-On Reset (POR) feature that ensures the output is in a known state until the minimum supply voltage has been reached before the output responds to the inputs, thus preventing false outputs during system power-up and power-down. The inputs have over-the-rail capability where both inputs can exceed the supply voltage up to 40 V and still operate properly. This makes the comparators well suited for both high and low supply voltage systems without limiting the range of input voltages that can be compared. Likewise, the internal reverse battery protection feature prevents damage to the comparator in the event of improper battery installation to the supply pins. The TLV185x comparators have a push-pull output stage where as the TLV186x comparators have an open-drain output stage, making it appropriate for level translation. Mobile phones & tablets Headsets/headphones & earbuds PC & notebooks Gas detector Smoke & heat detector Motion Detector Gas meter Servo drive position sensor Device Information PART NUMBER TLV1851, TLV1861 3 Description TLV1852, TLV1862 The TLV185x and TLV186x are a family of nanopower, 40 Volt comparators with single, dual and quad channel options. The family offers fail-safe (FS) inputs with push-pull and open-drain output options. These features coupled with nanopower operation over the wide supply range of 1.8 V to 40 V make this family well-suited for house-keeping functions such as voltage and temperature monitoring in low-power, always-on systems. TLV1854, TLV1864 PACKAGE (1) BODY SIZE (NOM) SOT-23 (5) 1.60 mm x 2.90 mm SOIC (8) (Preview) 3.91 mm × 4.90 mm VSSOP (8) (Preview) 3.00 mm × 3.00 mm SOIC (14) (Preview) 3.91 mm x 8.65 mm TSSOP (14) (Preview) 4.40 mm x 5.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. V+ Open-Drain only IN+ + IN- - Output Control SNAPBACK ESD CLAMPS V- OUT V- V- Power-On Reset Bias V- Block Diagram Supply Current vs. Supply Voltage An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. TLV1851, TLV1861 www.ti.com SNOSDE7A – DECEMBER 2022 – REVISED AUGUST 2023 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 Pin Configuration: TLV1851 and TLV1861........................3 Pin Configurations: TLV1852 and TLV1862...................... 4 Pin Configurations: TLV1854 and TLV1864...................... 5 6 Specifications.................................................................. 6 6.1 Absolute Maximum Ratings........................................ 6 6.2 ESD Ratings............................................................... 6 6.3 Thermal Information....................................................6 6.4 Recommended Operating Conditions.........................7 6.5 Electrical Characteristics.............................................8 6.6 Switching Characteristics............................................9 6.7 Typical Characteristics.............................................. 10 7 Detailed Description......................................................16 7.1 Overview................................................................... 16 7.2 Functional Block Diagrams....................................... 16 7.3 Feature Description...................................................16 7.4 Device Functional Modes..........................................16 8 Application and Implementation.................................. 20 8.1 Application Information............................................. 20 8.2 Typical Applications.................................................. 23 8.3 Power Supply Recommendations.............................25 9 Layout.............................................................................27 9.1 Layout Guidelines..................................................... 27 9.2 Layout Example........................................................ 27 10 Device and Documentation Support..........................28 10.1 Documentation Support.......................................... 28 10.2 Receiving Notification of Documentation Updates..28 10.3 Support Resources................................................. 28 10.4 Trademarks............................................................. 28 10.5 Electrostatic Discharge Caution..............................28 10.6 Glossary..................................................................28 11 Mechanical, Packaging, and Orderable Information.................................................................... 28 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (December 2022) to Revision A (January 2023) Page • Production Data Release of the TLV1851.......................................................................................................... 1 2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV1851 TLV1861 TLV1851, TLV1861 www.ti.com SNOSDE7A – DECEMBER 2022 – REVISED AUGUST 2023 5 Pin Configuration and Functions Pin Configuration: TLV1851 and TLV1861 1 V- 2 IN+ 3 5 V+ 4 IN- + OUT DBV Package SOT-23-5 Top View (Standard "north west" pinout) Table 5-1. Pin Functions: TLV1851 and TLV1861 PIN NAME NO. I/O DESCRIPTION OUT 1 O Output V- 2 - Negative supply voltage IN+ 3 I Non-inverting (+) input IN- 4 I Inverting (-) input V+ 5 - Positive supply voltage Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV1851 TLV1861 3 TLV1851, TLV1861 www.ti.com SNOSDE7A – DECEMBER 2022 – REVISED AUGUST 2023 Pin Configurations: TLV1852 and TLV1862 OUT1 1 8 V+ IN1± 2 7 OUT2 IN1+ 3 6 IN2± V± 4 5 IN2+ D, DGK Packages 8-Pin SOIC, VSSOP Top View Table 5-2. Pin Functions: TLV1852 and TLV1862 PIN NAME 4 NO. I/O DESCRIPTION OUT1 1 O Output pin of the comparator 1 IN1– 2 I Inverting input pin of comparator 1 IN1+ 3 I Noninverting input pin of comparator 1 V- 4 — IN2+ 5 I Noninverting input pin of comparator 2 IN2– 6 I Inverting input pin of comparator 2 OUT2 7 O Output pin of the comparator 2 V+ 8 — Positive supply voltage Negative supply voltage Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV1851 TLV1861 TLV1851, TLV1861 www.ti.com SNOSDE7A – DECEMBER 2022 – REVISED AUGUST 2023 Pin Configurations: TLV1854 and TLV1864 OUT1 1 14 OUT4 IN1- 2 13 IN4- IN1+ 3 12 IN4+ V+ 4 11 V- IN2+ 5 10 IN3+ IN2- 6 9 IN3- OUT2 7 8 OUT3 Not to scale D, PW Packages 14-Pin SOIC, TSSOP Top View Table 5-3. Pin Functions: TLV1854 and TLV1864 PIN NAME NO. I/O DESCRIPTION OUT1 1 O Output pin of the comparator 1 IN1- 2 I Negative input pin of the comparator 1 IN1+ 3 I Positive input pin of the comparator 1 V+ 4 - Positive supply voltage IN2+ 5 I Positive input pin of the comparator 2 IN2- 6 I Negative input pin of the comparator 2 OUT2 7 O Output pin of the comparator 2 OUT3 8 O Output pin of the comparator 3 IN3- 9 I Negative input pin of the comparator 3 IN3+ 10 I Positive input pin of the comparator 3 V- 11 - Negative supply voltage IN4+ 12 I Positive input pin of the comparator 4 IN4- 13 I Negative input pin of the comparator 4 OUT4 14 O Output pin of the comparator 4 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV1851 TLV1861 5 TLV1851, TLV1861 www.ti.com SNOSDE7A – DECEMBER 2022 – REVISED AUGUST 2023 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX Supply voltage: VS = (V+) – (V–) UNIT 42 V V Differential Input Voltage, VID –42 42 Input pins (IN+, IN–) from (V–)(2) –0.3 42 V Current into Input pins (IN+, IN–)(3) –10 10 mA Output (Open-drain version only) from (V–)(4) –0.3 42 V Output (OUT) (Push-Pull) from (V–) –0.3 (V+) + 0.3 -10 10 mA 150 °C 150 °C Output short circuit current(5) Junction temperature, TJ Storage temperature, Tstg (1) (2) (3) (4) (5) –65 V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Input terminals are diode-clamped to (V–). Inputs (IN+, IN–) can be greater than (V+) and OUT as long as it is within the –0.3 V to 42 V range Input terminals are diode-clamped to (V–). Input signals that swing more than 0.3 V below (V–) must be current-limited to 10 mA or less. Output (OUT) for open drain can be greater than (V+) and inputs (IN+, IN–) as long as it is within the –0.3 V to 42 V range Short-circuit to (V–) or (V+). 6.2 ESD Ratings VALUE Electrostatic discharge V(ESD) (1) (2) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±1500 UNIT V JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. 6.3 Thermal Information TLV185x/6x THERMAL METRIC(1) D (SOIC) DGK (VSSOP) PW (TSSOP) D (SOIC) 14 Pins 14 Pins UNIT 5 Pins 8 Pins 8 Pins RqJA Junction-to-ambient thermal resistance 168.1 121.6 163.1 °C/W RqJC(top) Junction-to-case (top) thermal resistance 68.1 64.6 55.5 °C/W RqJB Junction-to-board thermal resistance 37.4 65.1 84.7 °C/W yJT Junction-to-top characterization parameter 11.4 18.1 5.7 °C/W yJB Junction-to-board characterization parameter 37.1 64.3 83.1 °C/W RqJC(bot) Junction-to-case (bottom) thermal resistance (1) 6 DBV (SOT-23 ) °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV1851 TLV1861 TLV1851, TLV1861 www.ti.com SNOSDE7A – DECEMBER 2022 – REVISED AUGUST 2023 6.4 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX 1.8 40 V –0.1 40 V 0 40 V Output voltage for open drain from (V–) –0.1 40 V Ambient temperature, TA –40 125 °C Supply voltage: VS = (V+) – (V–) Input voltage range from (V–) Common-mode input voltage range from (V–) UNIT Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV1851 TLV1861 7 TLV1851, TLV1861 www.ti.com SNOSDE7A – DECEMBER 2022 – REVISED AUGUST 2023 6.5 Electrical Characteristics For VS = (V+) – (V–) = 12V, VCM = VS/2 at TA = 25°C (Unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT –3.6 ±0.25 3.6 mV 4.4 mV OFFSET VOLTAGE VOS Input offset voltage VOS Input offset voltage dVIO/dT Input offset voltage drift VHYS Input hysteresis voltage 1 VCM-Range Common-mode V = 1.8 V to 40 V voltage range from S TA = –40°C to +125°C (V–) 0 TA = –40°C to +125°C –4.4 3 2.8 µV/°C 5 mV 40 V 750 nA 1000 nA 640 nA 850 nA POWER SUPPLY IQ Quiescent current per comparator (output high) Push Pull Output Option IQ Quiescent current per comparator (output high) Push Pull Output Option, TA = –40 °C to 125°C IQ Quiescent current per comparator (output high) Open Drain Output option, no pull-up resistor IQ Quiescent current per comparator (output high) Open Drain Output option, no pull-up resistor, TA = –40 °C to 125°C During power on, VS must exceed VPOR for tON before the output will reflect the input. VPOR 520 440 1.5 V INPUT BIAS CURRENT 1 IB Input bias current (1) TA = –40°C to +125°C IOS Input offset current (1) TA = –40°C to +125°C VOL Voltage swing from (V–) ISINK = 2 µA 1 Voltage swing from (V–) ISINK = 50 µA 20 VOL VOH Voltage swing from (V+) (Push Pull only) VOH Voltage swing from (V+) (Push Pull only) ILKG Open-drain output VID = +0.1 V, VPULLUP = (V+) leakage current IOL Short-circuit current 0.1 250 pA 1500 pA 100 pA 1000 pA OUTPUT 8 ISINK = 50 µA TA = –40°C to +125°C ISOURCE = 2 µA 1 ISOURCE = 50 µA 25 ISOURCE = 50 µA TA = –40°C to +125°C Sinking TA = –40°C to +125°C Submit Document Feedback mV 60 mV 100 mV mV 60 mV 100 mV 0.3 pA 7 mA Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV1851 TLV1861 TLV1851, TLV1861 www.ti.com SNOSDE7A – DECEMBER 2022 – REVISED AUGUST 2023 6.5 Electrical Characteristics (continued) For VS = (V+) – (V–) = 12V, VCM = VS/2 at TA = 25°C (Unless otherwise noted) PARAMETER Short-circuit current IOH (1) TEST CONDITIONS MIN TYP Sourcing (for Push-Pull only) TA = –40°C to +125°C MAX 5 UNIT mA This parameter is ensured by design and/or characterization and is not tested in production. 6.6 Switching Characteristics For VS = (V+) – (V–) = 12 V, VCM = VS / 2 at TA = 25°C (Unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT VOD = 10 mV, CL = 25 pF, VSTEP = 100 mV 45 µs VOD = 50mV, CL = 25 pF, VSTEP = 100 mV 16 µs VOD = 100mV, CL = 25 pF, VSTEP = 200 mV 13 µs TPD-LH Propagation delay time, low-toVOD = 10 mV, CL = 10 pF, VSTEP = 100 mV high (Push-Pull output) 34 µs TPD-LH Propagation delay time, low-toVOD = 50 mV, CL = 10 pF, VSTEP = 100 mV high (Push-Pull output) 16 µs TPD-LH Propagation delay time, low-to- VOD = 100 mV, CL = 10 pF, VSTEP = 200 high (Push-Pull output) mV 14 µs VOD = 10 mV, CL = 25 pF, RP = 1 MΩ, VSTEP = 100 mV 57 µs Propagation delay time, low-to- VOD = 50 mV, CL = 25 pF, RP = 1 MΩ, high (Open-Drain output) VSTEP = 100 mV 36 µs VOD = 100 mV, CL = 25 pF, RP = 1 MΩ, VSTEP = 200 mV 35 µs TPD-HL Propagation delay time, highto-low TPD-LH TRISE Output Rise Time, 20% to 80%, push-pull output CL = 25 pF 0.2 µs TFALL Output Fall Time, 80% to 20% CL = 25 pF 0.2 µs 3 ms POWER ON TIME TON Power on-time Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV1851 TLV1861 9 TLV1851, TLV1861 www.ti.com SNOSDE7A – DECEMBER 2022 – REVISED AUGUST 2023 6.7 Typical Characteristics At TA = 25°C, VS = 12 V, VCM = VS/2 V, RP = 1MΩ (Open Drain only), CL = 25 pF, VOVERDRIVE = 100 mV unless otherwise noted. 4 3.8 Hysteresis (mV) 3.6 3.4 3.2 3 2.8 2.6 2.4 VS = 1.8V VS = 12V VS = 40V 2.2 2 -40 Figure 6-1. Offset vs. Temperature -10 5 20 35 50 65 Temperature (C) 80 95 110 125 Figure 6-2. Hysteresis vs. Temperature 5 5 For 29 units 4 4.6 3 4.2 2 3.8 Hysteresis (mV) Input Offset Voltage (mV) -25 1 0 -1 -2 3.4 3 2.6 2.2 -40C 25C 85C 125C 1.8 -3 1.4 -4 1 -5 0 0.5 1 1.5 2 2.5 3 3.5 4 Input Common-Mode Voltage (V) 4.5 5 Figure 6-3. Offset vs. Common-Mode, 1.8 V 0 0.5 1 1.5 2 2.5 3 3.5 4 Input Common-Mode Voltage (V) 4.5 5 Figure 6-4. Hysteresis vs. Common-Mode, 1.8 V 5 For 29 units Input Offset Voltage (mV) 4 3 2 1 0 -1 -2 -3 -4 -5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Input Common-Mode Voltage (V) Figure 6-5. Offset vs. Common-Mode, 12 V 10 Figure 6-6. Hysteresis vs. Common-Mode, 12 V Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV1851 TLV1861 TLV1851, TLV1861 www.ti.com SNOSDE7A – DECEMBER 2022 – REVISED AUGUST 2023 6.7 Typical Characteristics (continued) 5 5 For 29 units 4.6 3 4.2 2 3.8 Hysteresis (mV) Input Offset Voltage (mV) 4 1 0 -1 -2 3.4 3 2.6 2.2 -3 1.8 -4 1.4 -5 0 4 8 12 16 20 24 28 32 Input Common-Mode Voltage (V) 36 -40C 25C 85C 125C 1 40 0 Figure 6-7. Offset vs. Common-Mode, 40 V 12 16 20 24 28 32 Input Common-Mode Voltage (V) 36 40 100 -40C 25C 85C 125C 80 70 -40C 25C 85C 125C 90 80 Input Bias Current (nA) 90 Input Bias Current (nA) 8 Figure 6-8. Hysteresis vs. Common-Mode, 40 V 100 60 50 40 30 20 70 60 50 40 30 20 10 10 0 0 -10 -10 0 0.5 1 1.5 2 2.5 3 3.5 4 Input Common-Mode Voltage (V) 4.5 0 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Input Common-Mode Voltage (V) Figure 6-10. Bias Current vs. Common-Mode, 12 V Figure 6-9. Bias Current vs. Common-Mode, 1.8 V 100 1n -40C 25C 85C 125C 90 80 70 100p Leakage Current (A) Input Bias Current (nA) 4 60 50 40 30 20 10 10p 1p 100 VPU = 1.8V VPU = 12V VPU = 40V 0 -10 0 4 8 12 16 20 24 28 32 Input Common-Mode Voltage (V) 36 Figure 6-11. Bias Current vs. Common-Mode, 40 V 40 10 -40 -25 -10 5 20 35 50 65 Temperature (C) 80 95 110 125 Figure 6-12. Leakage Current vs. Temperature (Open Drain only) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV1851 TLV1861 11 TLV1851, TLV1861 www.ti.com SNOSDE7A – DECEMBER 2022 – REVISED AUGUST 2023 100 10 10 1 100m 10m 1m Push-Pull Only 100 1 10 100 1m Output Sourcing Current (A) -40C 25C 85C 125C 10m 100 1 100 10 10 1 100m 10m Push-Pull Only 100 1 10 100 1m Output Sourcing Current (A) -40C 25C 85C 125C 10m 100 1 10 1m Push-Pull Only 100 1 10 100 1m Output Sourcing Current (A) -40C 25C 85C 125C 10m Figure 6-17. Output Voltage vs. Output Sourcing Current, 40V -40C 25C 85C 125C 10 100 1m Output Sinking Current (A) 10m Figure 6-16. Output Voltage vs. Output Sinking Current, 12 V 10 10m 10m 100m 100 100m 100 1m Output Sinking Current (A) 1 100 1 10 1m 10m Figure 6-15. Output Voltage vs. Output Sourcing Current, 12V -40C 25C 85C 125C Figure 6-14. Output Voltage vs. Output Sinking Current, 1.8 V Output Voltage to V- (V) Output Voltage to V+ (V) 100m 100 1m Output Voltage to V+ (V) 1 1m 10m Figure 6-13. Output Voltage vs. Output Sourcing Current, 1.8V 12 Output Voltage to V- (V) 100 Output Voltage to V- (V) Output Voltage to V+ (V) 6.7 Typical Characteristics (continued) 1 100m 10m -40C 25C 85C 125C 1m 100 1 10 100 1m Output Sinking Current (A) 10m Figure 6-18. Output Voltage vs. Output Sinking Current, 40 V Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV1851 TLV1861 TLV1851, TLV1861 www.ti.com SNOSDE7A – DECEMBER 2022 – REVISED AUGUST 2023 750 700 650 600 550 500 450 400 350 300 250 200 150 100 Supply Current (nA) Supply Current (nA) 6.7 Typical Characteristics (continued) -40C 25C 85C 125C 0 4 8 12 16 20 24 28 Supply Voltage (V) 32 36 40 Supply Current (nA) Figure 6-19. Supply Current vs. Supply Voltage (Output Low), Push-Pull 650 600 550 500 450 400 350 300 250 200 150 100 50 0 -40C 25C 85C 125C 0 4 8 12 16 20 24 28 Supply Voltage (V) 32 36 40 Figure 6-20. Supply Current vs. Supply Voltage (Output High), Push-Pull -40C 25C 85C 125C 0 4 8 12 16 20 24 28 Supply Voltage (V) 32 36 40 Figure 6-21. Supply Current vs. Supply Voltage (Output Low), Open Drain Figure 6-22. Supply Current vs. Supply Voltage (Output High), Open Drain 800 800 700 700 600 600 Supply Current (nA) Supply Current (nA) 750 700 650 600 550 500 450 400 350 300 250 200 150 100 500 400 300 200 400 300 200 VS = 1.8V VS = 12V VS = 40V 100 0 -40 500 -25 -10 5 20 35 50 65 Temperature (C) 80 95 110 125 Figure 6-23. Supply Current vs. Temperature (Output Low), Push-Pull VS = 1.8V VS = 12V VS = 40V 100 0 -40 -25 -10 5 20 35 50 65 Temperature (C) 80 95 110 125 Figure 6-24. Supply Current vs. Temperature (Output High), Push-Pull Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV1851 TLV1861 13 TLV1851, TLV1861 www.ti.com SNOSDE7A – DECEMBER 2022 – REVISED AUGUST 2023 650 600 550 500 450 400 350 300 250 200 150 100 50 0 -40 VS = 1.8V VS = 12V VS = 40V -25 -10 5 20 35 50 65 Temperature (C) 80 95 110 125 Propagation Delay, Low to High (us) Figure 6-25. Supply Current vs. Temperature (Output Low), Open Drain 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 -40C 25C 85C 125C 20 30 40 50 70 100 200 300 Input Overdrive (mV) 500 7001,000 Figure 6-26. Supply Current vs. Temperature (Output High), Open Drain Propagation Delay, Low to High (us) Supply Current (nA) 6.7 Typical Characteristics (continued) 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 -40C 25C 85C 125C 20 30 40 50 70 100 200 300 Input Overdrive (mV) 500 7001,000 Figure 6-28. Propagation Delay, Low to High, 1.8 V, Push-Pull 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 -40C 25C 85C 125C 20 30 40 50 70 100 200 300 Input Overdrive (mV) 500 7001,000 Propagation Delay, Low to High (us) Propagation Delay, Low to High (us) Figure 6-27. Propagation Delay, Low to High, 1.8 V, Open Drain 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 -40C 25C 85C 125C 20 30 40 50 70 100 200 300 Input Overdrive (mV) 500 7001,000 Figure 6-30. Propagation Delay, Low to High, 12 V, Push-Pull Figure 6-29. Propagation Delay, Low to High, 12 V, Open Drain 14 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV1851 TLV1861 TLV1851, TLV1861 www.ti.com SNOSDE7A – DECEMBER 2022 – REVISED AUGUST 2023 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 -40C 25C 85C 125C 20 30 40 50 70 100 200 300 Input Overdrive (mV) 500 7001,000 Propagation Delay, Low to High (us) Propagation Delay, Low to High (us) 6.7 Typical Characteristics (continued) 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 -40C 25C 85C 125C 20 30 40 50 70 100 200 300 Input Overdrive (mV) 500 7001,000 Figure 6-32. Propagation Delay, Low to High, 40 V, Push-Pull Propagation Delay, High to Low (us) Figure 6-31. Propagation Delay, Low to High, 40 V, Open Drain Propagation Delay, High to Low (us) Figure 6-33. Propagation Delay, High to Low, 1.8 V 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 -40C 25C 85C 125C 20 30 40 50 70 100 200 300 Input Overdrive (mV) 500 7001,000 Figure 6-34. Propagation Delay, High to Low, 12 V -40C 25C 85C 125C 20 30 40 50 70 100 200 300 Input Overdrive (mV) 500 7001,000 Figure 6-35. Propagation Delay, High to Low, 40 V Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV1851 TLV1861 15 TLV1851, TLV1861 www.ti.com SNOSDE7A – DECEMBER 2022 – REVISED AUGUST 2023 7 Detailed Description 7.1 Overview The TLV185x and TLV186x devices are nanopower comparators with push-pull and open-drain output options. Operating down to 1.8 V while only consuming only 440 nA per channel, the TLV185x and TLV186x are well suited for voltage, current, and temperature sensing in low and high voltage low-power, always-on systems. An internal power-on reset circuit ensures that the output remains in a known state during power-up and power-down. Inputs have fail-safe inputs that can tolerate input transients without damage or false outputs. 7.2 Functional Block Diagrams V+ Open-Drain only IN+ + IN- - Output Control SNAPBACK ESD CLAMPS V- OUT V- V- Power-On Reset Bias V- Figure 7-1. Block Diagram 7.3 Feature Description The TLV185x (push-pull output) and TLV186x (open-drain output) devices are nano-power comparators that are capable of operating at high voltages. This family of comparators feature a fail safe input stage and over the rail operating condition mode capable of operating up to 40 V, independent of V+. The comparators also have an internal reverse battery protection feature and Power-On-Reset for known start-up conditions. 7.4 Device Functional Modes 7.4.1 Inputs 7.4.1.1 Operating Common-Mode Ranges The TLV185x and TLV186x devices have two operating common-mode ranges: within-the-rail and over-the-rail. Within-the-Rail Operation: IN+ and IN- are less than (V+) When an input pin is operating less than (V+), there are two operating regions defined where input voltages can be compared: low common-mode and high-common mode. In low-common mode which extends typically from 0 V to (V+) - 1 V, the typical input bias current is less than 1 pA. In high common-mode which extends typically from (V+) - 1 V to (V+), the typical input bias current is less than 14 nA. Over-the-Rail Operation: IN+ and/or IN- are greater than (V+) The TLV185x and TLV186x devices have a distinctive input stage that allows the input common mode range to extend from 0 V to 40 V independent of the supply voltage. This feature means that operation at low supply 16 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV1851 TLV1861 TLV1851, TLV1861 www.ti.com SNOSDE7A – DECEMBER 2022 – REVISED AUGUST 2023 voltages does not limit the range of input voltages that can be compared. When an input pin is operating over-the-rail (above (V+)), the bias current increases to a typical value of 55 nA. See Figure 6-9 to 6-11 in the Typical Characteristics section for input bias current vs. common-mode voltages. 7.4.1.2 Fail-Safe Inputs A feature of the TLV185x and TLV186x family is that the inputs are fail safe up to 40 V, independent of (V+). The inputs are maintained as high input impedance and can be of any value between -0.1 V and 40 V, even while (V+) is unpowered or below the minimum supply voltage. This feature avoids power sequencing or transient issues since the inputs are not diode clamped to (V+). 7.4.1.3 Unused Inputs If a channel is not to be used, DO NOT tie the inputs together. Due to the high equivalent bandwidth and low offset voltage, tying the inputs directly together can cause high frequency oscillations as the device triggers on it's own internal wideband noise. Instead, the inputs should be tied to any available voltage that resides within the specified input voltage range and provides a minimum of 50mV differential voltage. For example, one input can be grounded and the other input connected to a reference voltage, or even (V+). 7.4.2 Internal Hysteresis The device hysteresis transfer curve is shown in Figure 7-2. This curve is a function of three components: VTH, VOS, and VHYST: • VTH is the actual set voltage or threshold trip voltage. • VOS is the internal offset voltage between VIN+ and VIN–. This voltage is added to VTH to form the actual trip point at which the comparator must respond to change output states. • VHYST is the internal hysteresis (or trip window) that is designed to reduce comparator sensitivity to noise. (2.8 mV for the TLV185x/6x family) VTH + VOS ± (VHYST / 2) VTH + VOS VTH + VOS + (VHYST / 2) Figure 7-2. Hysteresis Transfer Curve 7.4.3 Outputs 7.4.3.1 TLV185x Push-Pull Output The TLV185x features a push-pull output stage capable of both sinking and sourcing current. This allows driving loads such as LED's and MOSFET gates, as well as eliminating the need for a power-wasting external pull-up resistor. The push-pull output must never be connected to another output. Directly shorting the output to the supply rails ((V+) when output "low" or (V-) when output "High") can result in thermal runaway and eventual device destruction at high (>12 V) supply voltages. If output shorts are possible, a series current limiting resistor is recommended to limit the power dissipation. Unused push-pull outputs should be left floating, and never tied to a supply, ground, or another output. 7.4.3.2 TLV186x Open-Drain Output The TLV186x features an open-drain (also commonly called open collector) sinking-only output stage enabling the output logic levels to be pulled up to an external voltage from 0 V up to 40 V, independent of the comparator supply voltage (V+). The open-drain output also allows logical OR'ing of multiple open drain outputs and logic Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV1851 TLV1861 17 TLV1851, TLV1861 www.ti.com SNOSDE7A – DECEMBER 2022 – REVISED AUGUST 2023 level translation. TI recommends setting the pull-up resistor current to less than 100 uA to optimize VOL logic levels. Lower pull-up resistor values will help increase the rising edge risetime, but at the expense of increasing VOL and higher power dissipation. The risetime will be dependent on the time constant of the total pull-up resistance and total load capacitance. Large value pull-up resistors (>1 MΩ) will create an exponential rising edge due to the output RC time constant and increase the risetime. Directly shorting the output to (V+) can result in thermal runaway and eventual device destruction at high (>12 V) pull-up voltages. If output shorts are possible, a series current limitng resistor is recommended to limit the power dissipation. Unused open drain outputs should be left floating, or can be tied to the (V-) pin if floating pins are not desired. 7.4.4 ESD Protection 7.4.4.1 Inputs The fail-safe inputs incorporates internal ESD protection circuits on all pins. The fail-safe inputs have ESD protection from each pin to (V-) which allows these pins to exceed the supply voltage (V+) up to 40 V. If input voltages are to exceed 40 V, an external clamp would be required. Likewise, negative voltages on the inputs are ESD clamped to (V-) and should be limited to less than -0.1 V. If the inputs are to be connected to a low impedance source, such as a power supply or buffered reference line, TI recommends adding a current-limiting resistor in series with the input to limit any transient currents should the clamps conduct. The current should be limited to 10 mA or less. This series resistance can be part of any resistive input dividers or networks. 7.4.4.2 Outputs The TLV185x push-pull output protection also contains a conventional diode-type ESD clamps between the output and (V-), as the output should not exceed the supply rails. The TLV186x open-drain output ESD protection also consists of a snapback ESD clamp between the output and (V-) to allow the output to be pulled above (V+) to a maximum of 40 V. 7.4.5 Power-On Reset (POR) The TLV185x and TLV186x devices have an internal Power-on-Reset (POR) circuit for known start-up or powerdown conditions. While the power supply (V+) is ramping up or ramping down, the POR circuitry will be activated for up to 2 ms after the VPOR of 1.5 V is crossed. When the supply voltage is equal to or greater than the minimum supply voltage, and after the delay period, the comparator output reflects the state of the differential input (VID). For the TLV185x push-pull output devices, the output is held low during the POR period (ton). For the TLV186x open drain output devices, the POR circuit will keep the output high impedance (Hi-Z) during the POR period (ton). tON GND VCC GND + 1.5V VOH/2 GND OUT Figure 7-3. Power-On Reset Timing Diagram Note that it the nature of an open collector output that the output will rise with the pull-up voltage during the POR period. 18 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV1851 TLV1861 www.ti.com TLV1851, TLV1861 SNOSDE7A – DECEMBER 2022 – REVISED AUGUST 2023 7.4.6 Reverse Battery Protection The TLV185x and TLV186x devices have an internal reverse battery protection feature that prevents damage to the comparator in the event of improper battery installation to the supply pins. This protection feature works up to 40 V. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV1851 TLV1861 19 TLV1851, TLV1861 www.ti.com SNOSDE7A – DECEMBER 2022 – REVISED AUGUST 2023 8 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information 8.1.1 Basic Comparator Definitions 8.1.1.1 Operation The basic comparator compares the input voltage (VIN) on one input to a reference voltage (VREF) on the other input. In the Figure 8-1 example below, if VIN is less than VREF, the output voltage (VO) is logic low (VOL). If VIN is greater than VREF, the output voltage (VO) is at logic high (VOH). Table 8-1 summarizes the output conditions. The output logic can be inverted by simply swapping the input pins. Table 8-1. Output Conditions Inputs Condition Output IN+ > IN- HIGH (VOH) IN+ = IN- Indeterminate (chatters - see Hysteresis) IN+ < IN- LOW (VOL) 8.1.1.2 Propagation Delay There is a delay between from when the input crosses the reference voltage and the output responds. This is called the Propagation Delay. Propagation delay can be different between high-to low and low-to-high input transitions. This is shown as tpLH and tpHL in Figure 8-1 and is measured from the mid-point of the input to the midpoint of the output. Figure 8-1. Comparator Timing Diagram 20 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TLV1851 TLV1861 TLV1851, TLV1861 www.ti.com SNOSDE7A – DECEMBER 2022 – REVISED AUGUST 2023 8.1.1.3 Overdrive Voltage The overdrive voltage, VOD, is the amount of input voltage beyond the reference voltage (and not the total input peak-to-peak voltage). The overdrive voltage is 100 mV as shown in the Figure 8-1 example. The overdrive voltage can influence the propagation delay (tp). The smaller the overdrive voltage, the longer the propagation delay, particularly when