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TLV170, TLV2170, TLV4170
ZHCSFO7A – NOVEMBER 2016 – REVISED MAY 2018
TLVx170 面向成本敏感型系统的 36V 单电源、抗 EMI 型低功耗运算放大
器
1 特性
•
•
•
•
•
•
•
•
•
•
1
3 说明
电源电压范围：2.7V 至 36V，±1.35V 至 ±18V
低噪声：22 nV/√Hz
电磁干扰 (EMI) 滤波器和内部射频 (RF)
输入范围包括负电源
单位增益稳定：200pF 容性负载
轨至轨输出
增益带宽：1.2MHz
低静态电流：每个放大器 125µA
高共模抑制：110dB
低偏置电流：10pA（典型值）
2 应用
•
•
•
•
•
•
•
•
•
点钞机
AC-DC 转换器
电源模块内的跟踪放大器
服务器电源
逆变器
测试设备
电池供电的仪器
变频器放大器
线路驱动器或线路接收器
TLVx170 系列抗电磁干扰型 36V 单电源低噪声运算放
大器在 1kHz 下的 THD+N 为 0.0002%，能够在 2.7V
(±1.35V) 至 36V (±18V) 的电源电压范围内运行。这些
特性结合低噪声和超高电源抑制比 (PSRR) 使得单通
道 TLV170、双通道 TLV2170 和四通道 TLV4170 成
为毫伏级信号放大的理想选择。TLVx170 系列器件还
具有良好的失调电压、温漂和带宽以及低静态电流特
性。
大多数运算放大器仅有一个指定的电源电
压，TLVx170 系列运算放大器则有所不同，其可在
2.7V 至 36V 的电压范围内额定运行，超过电源轨的输
入信号摆幅不会导致反相。TLVx170 系列同时也是单
位增益稳定的精密运算放大器，容性负载为 200pF，
带宽为 1.2MHz，转换率为 0.4V/μs，非常适用于电流电压转换器。
器件输入可在负电源轨以下 100mV 以及正电源轨 2V
之内正常运行，但满轨到轨输入的性能会受到影响。
TLVx170 器件的额定运行温度范围为 -40°C 至 +125°
C。
器件信息(1)
36V 运算放大器的最小封装
Package Footprint Comparison (to Scale)
器件型号
TLV170
TLV2170
TLV4170
封装
封装尺寸（标称值）
SOIC (8)
4.90mm × 3.91mm
SOT-23 (5)
2.90mm × 1.60mm
SOIC (8)
4.90mm × 3.91mm
VSSOP (8)
3.00mm × 3.00mm
SOIC (14)
8.65mm × 3.91mm
TSSOP (14)
5.00mm × 4.40mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
Package Height Comparison (to Scale)
D (SO-8)
DBV (SOT23-5)
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS782
TLV170, TLV2170, TLV4170
ZHCSFO7A – NOVEMBER 2016 – REVISED MAY 2018
www.ti.com.cn
目录
1
2
3
4
5
6
特性 ..........................................................................
应用 ..........................................................................
说明 ..........................................................................
修订历史记录 ...........................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
1
1
1
2
4
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information: TLV170 ................................... 8
Thermal Information: TLV2170 ................................. 8
Thermal Information: TLV4170 ................................. 8
Electrical Characteristics........................................... 9
Typical Characteristics: Table of Graphs ................ 10
Typical Characteristics ............................................ 11
Detailed Description ............................................ 16
7.1 Overview ................................................................. 16
7.2 Functional Block Diagram ...................................... 16
7.3 Feature Description................................................. 17
7.4 Device Functional Modes........................................ 20
8
Application and Implementation ........................ 21
8.1 Application Information............................................ 21
8.2 Typical Application .................................................. 21
9 Power Supply Recommendations...................... 23
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 24
11 器件和文档支持 ..................................................... 25
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
器件支持................................................................
文档支持................................................................
相关链接................................................................
接收文档更新通知 .................................................
社区资源................................................................
商标 .......................................................................
静电放电警告.........................................................
术语表 ...................................................................
25
26
26
26
26
26
26
26
12 机械、封装和可订购信息 ....................................... 26
4 修订历史记录
Changes from Original (November 2016) to Revision A
Page
•
Updated the Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application figure........................................... 18
2
Copyright © 2016–2018, Texas Instruments Incorporated
TLV170, TLV2170, TLV4170
www.ti.com.cn
ZHCSFO7A – NOVEMBER 2016 – REVISED MAY 2018
Table 1. Device Comparison
PART NUMBER
NO OF
CHANNELS
PACKAGE-LEAD
SOT23-5
D
VSSOP
(micro size)
TSSOP
—
TLV170
1
5
8
—
TLV2170
2
—
8
8
—
TLV4170
4
—
14
—
14
Copyright © 2016–2018, Texas Instruments Incorporated
3
TLV170, TLV2170, TLV4170
ZHCSFO7A – NOVEMBER 2016 – REVISED MAY 2018
www.ti.com.cn
5 Pin Configuration and Functions
TLV170: DBV Package
5-Pin SOT-23
Top View
V±
2
+IN
3
5
V+
±
1
+
OUT
TLV170: D Package
8-Pin SOIC
Top View
4
NC
1
±IN
2
+IN
3
V±
4
8
NC
±
7
V+
+
6
OUT
5
NC
±IN
Not to scale
Not to scale
Pin Functions: TLV170
PIN
NAME
TLV170
I/O
DESCRIPTION
SOT-23
D
–IN
4
2
I
Negative (inverting) input
+IN
3
3
I
Positive (noninverting) input
NC
(1)
—
1, 5, 8
—
No internal connection (can be left floating)
OUT
1
6
O
Output
V–
2
4
—
Negative (lowest) power supply
V+
5
7
—
Positive (highest) power supply
(1)
4
NC indicates no internal connection.
Copyright © 2016–2018, Texas Instruments Incorporated
TLV170, TLV2170, TLV4170
www.ti.com.cn
ZHCSFO7A – NOVEMBER 2016 – REVISED MAY 2018
TLV2170: D and DGK Packages
8-Pin SOIC and VSSOP
Top View
OUT A
1
8
V+
±IN A
2
7
OUT B
+IN A
3
6
±IN B
V±
4
5
+IN B
Not to scale
Pin Functions: TLV2170
PIN
TLV2170
NAME
I/O
DESCRIPTION
SOIC
VSSOP
(micro size)
–IN A
2
2
I
Inverting input, channel A
–IN B
6
6
I
Inverting input, channel B
+IN A
3
3
I
Noninverting input, channel A
+IN B
5
5
I
Noninverting input, channel B
OUT A
1
1
O
Output, channel A
OUT B
7
7
O
Output, channel B
V–
4
4
—
Negative (lowest) power supply
V+
8
8
—
Positive (highest) power supply
Copyright © 2016–2018, Texas Instruments Incorporated
5
TLV170, TLV2170, TLV4170
ZHCSFO7A – NOVEMBER 2016 – REVISED MAY 2018
www.ti.com.cn
TLV4170: D and PW Packages
14-Pin SOIC and TSSOP
Top View
OUT A
1
14
OUT D
±IN A
2
13
±IN D
+IN A
3
12
+IN D
V+
4
11
V±
+IN B
5
10
+IN C
±IN B
6
9
±IN C
OUT B
7
8
OUT C
Not to scale
Pin Functions: TLV4170
PIN
I/O
DESCRIPTION
NAME
SOIC
TSSOP
–IN A
2
2
I
Inverting input, channel A
–IN B
6
6
I
Inverting input, channel B
–IN C
9
9
I
Inverting input, channel C
–IN D
13
13
I
Inverting input, channel D
+IN A
3
3
I
Noninverting input, channel A
+IN B
5
5
I
Noninverting input, channel B
+IN C
10
10
I
Noninverting input, channel C
+IN D
12
12
I
Noninverting input, channel D
OUT A
1
1
O
Output, channel A
OUT B
7
7
O
Output, channel B
OUT C
8
8
O
Output, channel C
OUT D
14
14
O
Output, channel D
V–
11
11
—
Negative (lowest) power supply
V+
4
4
—
Positive (highest) power supply
6
Copyright © 2016–2018, Texas Instruments Incorporated
TLV170, TLV2170, TLV4170
www.ti.com.cn
ZHCSFO7A – NOVEMBER 2016 – REVISED MAY 2018
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
Supply voltage, [(V+) – (V−)]
Voltage
Single-supply voltage
Signal input pin
Signal input pin
Current
Output short-circuit
Temperature
(2)
V
(V+) + 0.5
–10
10
mA
Continuous
–55
Junction, TJ
150
150
Storage, Tstg
(1)
40
(V−) − 0.5
(2)
Operating, TA
UNIT
40
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
Voltage
Supply, VS = (V+) – (V–)
2.7
36
V
TA
Specified temperature
–40
125
°C
TA
Operating temperature
–55
150
°C
Copyright © 2016–2018, Texas Instruments Incorporated
UNIT
7
TLV170, TLV2170, TLV4170
ZHCSFO7A – NOVEMBER 2016 – REVISED MAY 2018
www.ti.com.cn
6.4 Thermal Information: TLV170
TLV170
THERMAL METRIC (1)
D (SOIC)
DBV (SOT-23)
8 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
149.5
245.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
97.9
133.9
°C/W
RθJB
Junction-to-board thermal resistance
87.7
83.6
°C/W
ψJT
Junction-to-top characterization parameter
35.5
18.2
°C/W
ψJB
Junction-to-board characterization parameter
89.5
83.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: TLV2170
TLV2170
THERMAL METRIC (1)
D (SOIC)
DGK (VSSOP)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
134.3
180
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
72.1
55
°C/W
RθJB
Junction-to-board thermal resistance
60.6
130
°C/W
ψJT
Junction-to-top characterization parameter
18.2
5.3
°C/W
ψJB
Junction-to-board characterization parameter
53.8
120
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: TLV4170
TLV4170
THERMAL METRIC
(1)
D (SOIC)
PW (TSSOP)
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
93.2
106.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
51.8
24.4
°C/W
RθJB
Junction-to-board thermal resistance
49.4
59.3
°C/W
ψJT
Junction-to-top characterization parameter
13.5
0.6
°C/W
ψJB
Junction-to-board characterization parameter
42.2
54.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
8
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2016–2018, Texas Instruments Incorporated
TLV170, TLV2170, TLV4170
www.ti.com.cn
ZHCSFO7A – NOVEMBER 2016 – REVISED MAY 2018
6.7 Electrical Characteristics
at TA = 25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.5
±2.5
UNIT
OFFSET VOLTAGE
TA = 25°C
VOS
Input offset voltage
dVOS/dT
Input offset voltage drift
TA = –40°C to +125°C
PSRR
Power-supply rejection ratio
VS = 4 V to 36 V, TA = –40°C to +125°C
TA = –40°C to +125°C
±2.7
±2
90
Channel separation, dc
mV
µV/°C
105
dB
5
µV/V
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
TA = 25°C
TA = –40°C to +125°C
±10
pA
±1
nA
TA = 25°C
±10
TA = –40°C to +125°C
±50
pA
NOISE
Input voltage noise
en
Input voltage noise density
f = 0.1 Hz to 10 Hz
2
f = 100 Hz
27
f = 1 kHz
22
µVPP
nV/√Hz
INPUT VOLTAGE
Common-mode voltage range (1)
VCM
CMRR
Common-mode rejection ratio
(V–) – 0.1
VS = ±2 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
TA = –40°C to +125°C
VS = ±18 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
TA = –40°C to +125°C
(V+) – 2
V
100
dB
95
110
INPUT IMPEDANCE
Differential
100 || 3
Common-mode
MΩ || pF
6 || 3
1012 Ω || pF
130
dB
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
VS = 36 V,
(V–) + 0.35 V < VO < (V+) – 0.35 V,
TA = –40°C to +125°C
94
FREQUENCY RESPONSE
GBP
Gain bandwidth product
SR
Slew rate
1.2
MHz
G = +1
0.4
V/µs
To 0.1%, VS = ±18 V, G = +1, 10-V step
20
28
tS
Settling time
To 0.01% (12-bit), VS = ±18 V, G = +1,
10-V step
THD+N
Total harmonic distortion + noise
G = +1, f = 1 kHz, VO = 3 VRMS
µs
0.0002%
OUTPUT
VS = ±18 V, RL = 10 kΩ; TA = –40°C to +125°C
VO
Voltage output swing from rail
ISC
Short-circuit current
CLOAD
Capacitive load drive
RO
Open-loop output resistance
RL = 10 kΩ, AOL ≥ 94 dB,
TA = –40°C to +125°C
(V–) + 0.2
(V+) – 0.3
(V–) + 0.35
(V+) – 0.35
–20
17
See Typical Characteristics: Table of
Graphs
f = 1 MHz, IO = 0 A
900
V
mA
pF
Ω
POWER SUPPLY
VS
Specified voltage range
IQ
Quiescent current per amplifier
(1)
2.7
IO = 0 A, TA = –40°C to +125°C
125
36
V
175
µA
The input range can be extended beyond (V+) – 2 V up to V+. See the Typical Characteristics: Table of Graphs and Application and
Implementation sections for additional information.
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TLV170, TLV2170, TLV4170
ZHCSFO7A – NOVEMBER 2016 – REVISED MAY 2018
www.ti.com.cn
6.8 Typical Characteristics: Table of Graphs
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
表 2. Characteristic Performance Measurements
DESCRIPTION
FIGURE
Offset Voltage Production Distribution
图1
Offset Voltage vs Common-Mode Voltage
图2
Offset Voltage vs Common-Mode Voltage (Upper Stage)
图3
Input Bias Current vs Temperature
图4
Output Voltage Swing vs Output Current (Maximum Supply)
图5
CMRR and PSRR vs Frequency (Referred-to-Input)
图6
0.1-Hz to 10-Hz Noise
图7
Input Voltage Noise Spectral Density vs Frequency
图8
Quiescent Current vs Supply Voltage
图9
Open-Loop Gain and Phase vs Frequency
图 10
Closed-Loop Gain vs Frequency
图 11
Open-Loop Gain vs Temperature
图 12
Open-Loop Output Impedance vs Frequency
图 13
Small-Signal Overshoot vs Capacitive Load
图 14, 图 15
No Phase Reversal
图 16
Small-Signal Step Response (100 mV)
图 17, 图 18
Large-Signal Step Response
图 19, 图 20
Large-Signal Settling Time
图 21, 图 22
Short-Circuit Current vs Temperature
图 23
Maximum Output Voltage vs Frequency
图 24
EMIRR IN+ vs Frequency
图 25
10
版权 © 2016–2018, Texas Instruments Incorporated
TLV170, TLV2170, TLV4170
www.ti.com.cn
ZHCSFO7A – NOVEMBER 2016 – REVISED MAY 2018
6.9 Typical Characteristics
20
16
14
Offset Voltage (mV)
Percentage of Amplifiers (%)
18
12
10
8
6
4
VCM = - 18.1 V
2
−1200
−1100
−1000
−900
−800
−700
−600
−500
−400
−300
−200
−100
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
0
Offset Voltage (µV)
Common-Mode Voltage (V)
G001
5 typical units shown
Distribution taken from 400 amplifiers
图 2. Offset Voltage vs Common-Mode Voltage
图 1. Offset Voltage Production Distribution
2000
IB+
IBIOS
Input Bias Current (pA)
Offset Voltage (mV)
1500
Normal
Operation
1000
500
0
-500
-1000
-75
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Common-Mode Voltage (V)
5 typical units shown
图 4. Input Bias Current vs Temperature
图 3. Offset Voltage vs Common-Mode Voltage
(Upper Stage)
140
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
18
Output Voltage (V)
17
16
15
14.5
-14.5
-15
-40°C
+25°C
+125°C
-16
-17
120
100
80
60
40
+PSRR
-PSRR
CMRR
20
0
-18
0
1
2
3
4
5
6
7
8
9
10
Output Current (mA)
图 5. Output Voltage Swing vs Output Current (Maximum
Supply)
版权 © 2016–2018, Texas Instruments Incorporated
1
10
100
1k
10k
100k
1M
Frequency (Hz)
图 6. CMRR and PSRR vs Frequency
(Referred-to Input)
11
TLV170, TLV2170, TLV4170
ZHCSFO7A – NOVEMBER 2016 – REVISED MAY 2018
www.ti.com.cn
Typical Characteristics (接
接下页)
1 mV/div
Voltage Noise Density (nV/ Hz)
1000
100
10
1
1
10
100
1k
10k
Frequency (Hz)
100k
1M
G014
图 8. Input Voltage Noise Spectral Density vs Frequency
图 7. 0.1-Hz to 10-Hz Noise
140
135
120
90
Gain
45
Gain (dB)
80
0
Phase
60
-45
40
-90
20
-135
0
-180
-20
-225
-40
0.1
1
10
100
1k
10k
100k
1M
Phase (°)
Quiescent Current (mA)
100
-270
10M
Frequency (Hz)
图 10. Open-Loop Gain and Phase vs Frequency
图 9. Quiescent Current vs Supply Voltage
3
50
VS = 2.7 V
40
Open-Loop Gain (mV/V)
2.5
Gain (dB)
30
20
10
0
1k
10k
1.5
1
0
100k
1M
Frequency (Hz)
10M
图 11. Closed-Loop Gain vs Frequency
12
VS = 36 V
2
0.5
G = −1
G=1
G = 100
−10
−20
VS = 4 V
100M
G020
-75
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
图 12. Open-Loop Gain vs Temperature
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TLV170, TLV2170, TLV4170
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ZHCSFO7A – NOVEMBER 2016 – REVISED MAY 2018
Typical Characteristics (接
接下页)
Open-Loop Output Impedance (W)
10k
1k
100
10
18 V
ROUT
1
W
W
W
1m
1
10
100
1k
10k
100k
1M
RL
-18 V
CL
10M
Frequency (Hz)
100-mV output step, RL = 10 kΩ, G = +1
图 13. Open-Loop Output Impedance vs Frequency
图 14. Small-Signal Overshoot vs Capacitive Load
18 V
5 V/div
-18 V
37-VPP
Sine Wave
(±18.5 V)
RI = 10 kW
RF = 10 kW
18 V
ROUT
W
W
W
CL
-18 V
Time (100 ms/div)
100-mV output step, RL = 10 kΩ, G = –1
图 16. No Phase Reversal
20 mV/div
20 mV/div
图 15. Small-Signal Overshoot vs Capacitive Load
+18 V
-18 V
RL
RI
= 2 kW
RF
= 2 kW
18 V
CL
CL
-18 V
Time (5 ms/div)
Time (5 ms/div)
RL = 10 kΩ, CL = 10 pF, G = +1
RL = 10 kΩ, CL = 10 pF, G = –1
图 17. Small-Signal Step Response (100 mV)
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图 18. Small-Signal Step Response (100 mV)
13
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2 V/div
2 V/div
Typical Characteristics (接
接下页)
Time (50 μs/div)
Time (50 ms/div)
G = +1, RL = 10 kΩ, CL = 10 pF
G = –1, RL = 10 kΩ, CL = 10 pF
图 20. Large-Signal Step Response
10
10
8
8
6
6
4
D From Final Value (mV)
D From Final Value (mV)
图 19. Large-Signal Step Response
12-Bit Settling
2
0
-2
(±1/2LSB = ±0.012%)
-4
-6
4
0
-2
-6
-8
-10
-10
10
20
30
40
50
60
70
80
90
(±1/2 LSB = ±0.012%)
-4
-8
0
12-Bit Settling
2
0
100
10
20
40
50
60
10-V negative step, G = –1
10-V positive step, G = +1
图 22. Large-Signal Settling Time
图 21. Large-Signal Settling Time
15
30
Short-Circuit Current, Source
Short-Circuit Current, Sink
24
VS = ±15 V
12.5
18
Output Voltage (VPP )
Short-Circuit Current (mA)
30
Time (ms)
Time (ms)
12
6
0
-6
-12
-18
Maximum output range without
slew−rate induced distortion
10
7.5
VS = ±5 V
5
2.5
VS = ±1.35 V
-24
-30
-50
0
-30
-10
10
30
50
70
90
Temperature (q C)
110
130
图 23. Short-Circuit Current vs Temperature
14
150
1k
10k
100k
Frequency (Hz)
1M
D002
10M
G035
图 24. Maximum Output Voltage vs Frequency
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Typical Characteristics (接
接下页)
140
EMIRR IN+ (dB)
120
100
80
60
40
20
0
10M
100M
1G
10G
Frequency (Hz)
PRP = –10 dBm, VS = ±18 V, VCM = 0 V
图 25. EMIRR IN+ vs Frequency
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7 Detailed Description
7.1 Overview
The TLVx170 family of op amps provides high overall performance, making the devices ideal for many generalpurpose applications. The excellent offset drift of only 2 μV/°C provides excellent stability over the entire
temperature range. In addition, the family offers very good overall performance with high CMRR, PSRR, and AOL.
7.2 Functional Block Diagram
PCH
FF Stage
Ca
Cb
+IN
PCH
Input Stage
2nd Stage
Output
Stage
OUT
-IN
NCH
Input Stage
16
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7.3 Feature Description
7.3.1 Operating Characteristics
The TLVx170 family of amplifiers is specified for operation from 2.7 V to 36 V (±1.35 V to ±18 V). Many of the
specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are presented in the Typical Characteristics: Table of Graphs section.
7.3.2 Phase-Reversal Protection
The TLVx170 family has an internal phase-reversal protection. Many op amps exhibit a phase reversal when the
input is driven beyond the linear common-mode range. This condition is most often encountered in noninverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The input of the TLVx170 prevents phase reversal with excessive common-mode
voltage. Instead, the output limits into the appropriate rail. This performance is shown in 图 26.
18 V
5 V/div
-18 V
37-VPP
Sine Wave
(±18.5 V)
Time (100 ms/div)
图 26. No Phase Reversal
7.3.3 Electrical Overstress
Designers often ask questions about the capability of an op amp to withstand electrical overstress. These
questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output pin. Each
of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics
of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal
electrostatic discharge (ESD) protection is built into these circuits for protection from accidental ESD events both
before and during product assembly.
A good understanding of this basic ESD circuitry and the relevance to an electrical overstress event is helpful. 图
27 illustrates the ESD circuits contained in the TLVx170 (indicated by the dashed line area). The ESD protection
circuitry involves several current-steering diodes connected from the input and output pins and routed back to the
internal power-supply lines, where the diodes meet at an absorption device internal to the op amp. This
protection circuitry is intended to remain inactive during normal circuit operation.
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Feature Description (接
接下页)
TVS
+
±
RF
+VS
R1
IN±
RS
IN+
2.5 NŸ
2.5 NŸ
+
Power-Supply
ESD Cell
ID
VIN
RL
+
±
+
±
±VS
TVS
图 27. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, highcurrent pulse when discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the op amp core to prevent damage. The energy absorbed by the protection
circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more
steering diodes. Depending on the path that the current takes, the absorption device can activate. The absorption
device has a trigger, or threshold voltage, that is above the normal operating voltage of the TLVx170 but below
the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly activates
and clamps the voltage across the supply rails to a safe level.
When the op amp connects into a circuit, as shown in 图 27, the ESD protection components are intended to
remain inactive and do not become involved in the application circuit operation. However, circumstances can
arise where an applied voltage exceeds the operating voltage range of a given pin. If this condition occurs, there
is a risk that some internal ESD protection circuits can turn on and conduct current. Any such current flow occurs
through steering-diode paths and rarely involves the absorption device.
图 27 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+) by 500
mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can sink the
current, then one of the upper input steering diodes conducts and directs current to V+. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN can begin sourcing current to the op amp and then take
over as the source of positive supply voltage. The danger in this case is that the voltage can rise to levels that
exceed the op amp absolute maximum ratings.
18
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Feature Description (接
接下页)
Another common question involves what happens to the amplifier if an input signal is applied to the input when
the power supplies (V+ or V–) are at 0 V. Again, this question depends on the supply characteristic when at 0 V,
or at a level below the input signal amplitude. If the supplies appear as high impedance, then the input source
supplies the op amp current through the current-steering diodes. This state is not a normal bias condition; most
likely, the amplifier does not operate normally. If the supplies are low impedance, then the current through the
steering diodes can become quite high. The current level depends on the ability of the input source to deliver
current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, add external Zener diodes to the
supply pins; see 图 27. Select the Zener voltage so that the diode does not turn on during normal operation.
However, the Zener voltage must be low enough so that the Zener diode conducts if the supply pin begins to rise
above the safe-operating, supply-voltage level.
The TLVx170 input pins are protected from excessive differential voltage with back-to-back diodes; see 图 27. In
most circuit applications, the input protection circuitry has no effect. However, in low-gain or G = 1 circuits, fastramping input signals can forward-bias these diodes because the output of the amplifier cannot respond rapidly
enough to the input ramp. If the input signal is fast enough to create this forward-bias condition, limit the input
signal current to 10 mA or less. If the input signal current is not inherently limited, an input series resistor can be
used to limit the input signal current. This input series resistor degrades the low-noise performance of the
TLVx170. 图 27 illustrates an example configuration that implements a current-limiting feedback resistor.
7.3.4 Capacitive Load and Stability
The dynamic characteristics of the TLVx170 are optimized for common operating conditions. The combination of
low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and can lead to gain
peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output. The simplest way
to achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in series with the output. 图
28 and 图 29 show graphs of small-signal overshoot versus capacitive load for several values of ROUT. Also, see
the Feedback Plots Define Op Amp AC Performance application report for details of analysis techniques and
application circuits.
18 V
RI = 10 kW
RF = 10 kW
ROUT
18 V
W
W
W
-18 V
RL
CL
100-mV output step, RL = 10 kΩ, G = +1
图 28. Small-Signal Overshoot vs Capacitive Load
版权 © 2016–2018, Texas Instruments Incorporated
W
W
W
ROUT
CL
-18 V
100-mV output step, RL = 10 kΩ, G = –1
图 29. Small-Signal Overshoot vs Capacitive Load
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7.4 Device Functional Modes
7.4.1 Common-Mode Voltage Range
The input common-mode voltage range of the TLVx170 family extends 100 mV below the negative rail and within
2 V of the top rail for normal operation.
This device can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within
2 V of the top rail. The typical performance in this range is summarized in 表 3.
表 3. Typical Performance for Common-Mode Voltages Within 2 V of the Positive Supply
PARAMETER
Input common-mode voltage
Offset voltage
MIN
TYP
(V+) – 2
MAX
(V+) + 0.1
UNIT
V
7
mV
Offset voltage vs temperature
12
µV/°C
Common-mode rejection ratio
65
dB
Open-loop gain
60
dB
Gain-bandwidth product
0.3
MHz
Slew rate
0.3
V/µs
7.4.2 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from the saturated state to
the linear state. The output devices of the op amp enter the saturation region when the output voltage exceeds
the rated operating voltage, either resulting from the high input voltage or the high gain. After the device enters
the saturation region, the charge carriers in the output devices need time to return back to the normal state. After
the charge carriers return back to the equilibrium state, the device begins to slew at the normal slew rate. Thus,
the propagation delay in case of an overload condition is the sum of the overload recovery time and the slew
time. The overload recovery time for the TLVx170 is approximately 2 µs.
20
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLVx170 family of op amps provides high overall performance in a large number of general-purpose
applications. As with all amplifiers, applications with noisy or high-impedance power supplies require decoupling
capacitors placed close to the device pins. In most cases, 0.1-µF capacitors are adequate. Follow the additional
recommendations in the Layout Guidelines section in order to achieve the maximum performance from this
device. Many applications can introduce capacitive loading to the output of the amplifier (potentially causing
instability). One method of stabilizing the amplifier in such applications is to add an isolation resistor between the
amplifier output and the capacitive load. The design process for selecting this resistor is given in the Typical
Application section.
8.2 Typical Application
This circuit can be used to drive capacitive loads (such as cable shields, reference buffers, MOSFET gates, and
diodes). The circuit uses an isolation resistor (RISO) to stabilize the output of an op amp. RISO modifies the openloop gain of the system to ensure the circuit has sufficient phase margin.
+VS
VOUT
RISO
+
VIN
+
±
CLOAD
-VS
Copyright © 2016, Texas Instruments Incorporated
图 30. Unity-Gain Buffer With RISO Stability Compensation
8.2.1 Design Requirements
The design requirements are:
• Supply voltage: 30 V (±15 V)
• Capacitive loads: 100 pF, 1000 pF, 0.01 μF, 0.1 μF, and 1 μF
• Phase margin: 45° and 60°
8.2.2 Detailed Design Procedure
图 30 shows a unity-gain buffer driving a capacitive load. 公式 1 shows the transfer function for the circuit in 图
30. Not shown in 图 30 is the open-loop output resistance of the op amp, Ro.
1 + CLOAD × RISO × s
T(s) =
1 + Ro + RISO × CLOAD × s
(1)
The transfer function in 公式 1 has a pole and a zero. The frequency of the pole (fp) is determined by (Ro + RISO)
and CLOAD. Components RISO and CLOAD determine the frequency of the zero (fz). A stable system is obtained by
selecting RISO such that the rate of closure (ROC) between the open-loop gain (AOL) and 1/β is 20 dB per
decade; see 图 31. The 1/β curve for a unity-gain buffer is 0 dB.
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Typical Application (接
接下页)
120
AOL
100
1
fp
2 u Πu RISO
Gain (dB)
80
60
Ro
u CLOAD
40 dB
fz
40
1
2 u Πu RISO u CLOAD
1 dec
1/
20
ROC
20 dB
dec
0
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
图 31. TIPD128 Unity-Gain Amplifier With RISO Compensation
ROC stability analysis is typically simulated. The validity of the analysis depends on multiple factors, especially
the accurate modeling of Ro. In addition to simulating the ROC, a robust stability analysis includes a
measurement of overshoot percentage and ac gain peaking of the circuit using a function generator,
oscilloscope, and gain and phase analyzer. Phase margin is then calculated from these measurements. 表 4
shows the overshoot percentage and ac gain peaking that correspond to phase margins of 45° and 60°. For
more details on this design and other alternative devices that can be used in place of the TLV170, see the
Capacitive Load Drive Solution Using an Isolation Resistor precision design.
表 4. Phase Margin versus Overshoot and AC Gain
Peaking
PHASE
MARGIN
OVERSHOOT
AC GAIN PEAKING
45°
23.3%
2.35 dB
60°
8.8%
0.28 dB
8.2.3 Application Curve
Using the described methodology, the values of RISO that yield phase margins of 45º and 60º for various
capacitive loads were determined. The results are shown in 图 32.
10000
45° Phase Margin
Isolation Resistor (RISO,
)
60° Phase Margin
1000
100
10
0.1
1
10
100
Capacitive Load (nF)
1000
C002
图 32. Isolation Resistor Required for Various Capacitive Loads to Achieve a Target Phase Margin
22
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9 Power Supply Recommendations
The TLVx170 is specified for operation from 2.7 V to 36 V (±1.35 V to ±18 V); many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics: Table of Graphs section.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
section.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically
separate digital and analog grounds, paying attention to the flow of the ground current.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much
better than in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in 图 34, keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
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10.2 Layout Example
+
VIN
VOUT
RG
±
RF
图 33. Schematic Representation
Run the input traces
as far away from
the supply lines
as possible
Place components close
to device and to each
other to reduce parasitic
errors
VS+
RF
NC
NC
GND
±IN
V+
VIN
+IN
OUTPUT
V±
NC
Use a low-ESR,
ceramic bypass
capacitor
RG
VS±
GND
GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
图 34. Op Amp Board Layout for a Noninverting Configuration
24
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11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 TINA-TI™（免费软件下载）
TINA-TI™ 是一款基于 SPICE 引擎的电路仿真程序，简单易用并且功能强大。 TINA-TI™是 TINA-TI™ 软件的一款
免费全功能版本，除了一系列无源和有源模型外，此版本软件还预先载入了一个宏模型库。TINA-TI™ 提供所有传
统的 SPICE 直流、瞬态和频域分析，以及其他设计功能。
TINA-TI™ 提供全面的后处理能力，便于用户以多种方式获得结果，用户可从 Analog eLab Design Center（模拟
电子实验室设计中心）免费下载。虚拟仪器提供选择输入波形和探测电路节点、电压以及波形的功能，从而构建一
个动态的快速入门工具。
注
这些文件需要安装 TINA 软件（由 DesignSoft™提供）或者 TINA-TI™ 软件。请下载 TINATI™ 文件夹中的免费 TINA-TI™ 软件。
11.1.1.2 DIP 适配器 EVM
DIP 适配器 EVM 工具为小型表面贴装器件的原型设计提供了一种简易的低成本方法。评估工具使用以下 TI 封
装：D 或 U (SOIC-8)、PW (TSSOP-8)、DGK (VSSOP-8)、DBV（SOT23-6、SOT23-5 和 SOT23-3）、DCK
（SC70-6 和 SC70-5）以及 DRL (SOT563-6)。DIP 适配器 EVM 也可搭配引脚排使用，或者直接与现有电路相
连。
11.1.1.3 通用运放 EVM
通用运放 EVM 是一系列通用空白电路板，可简化采用各种器件封装类型的电路板原型设计。借助评估模块电路板
设计，可以轻松快速地构造多种不同电路。共有 5 个模型可供选用，每个模型都对应一种特定封装类型。支持
PDIP、SOIC、VSSOP、TSSOP 和 SOT23 封装。
注
这些电路板均为空白电路板，用户必须自行提供相关器件。TI 建议您在订购通用运放 EVM
时申请几个运放器件样品。
11.1.1.4 TI 高精度设计
TI 高精度设计是由 TI 公司高精度模拟 应用 专家创建的模拟解决方案，提供了许多实用电路的工作原理、组件选
择、仿真、完整印刷电路板 (PCB) 电路原理图和布局布线、物料清单以及性能测量结果。TI 高精度设计可从
www.ti.com/ww/en/analog/precision-designs/ 在线获取。
11.1.1.5 WEBENCH®滤波器设计器
WEBENCH® 滤波器设计器是一款简单、功能强大且便于使用的有源滤波器设计程序。借助 WEBENCH® 滤波器
设计器，您可以使用一系列 TI 运算放大器和 TI 供应商合作伙伴提供的无源组件来构建最佳滤波器设计方案。
WEBENCH® 设计中心以基于网络的工具形式提供 WEBENCH® 滤波器设计器。用户通过该工具可在短时间内完
成多级有源滤波器解决方案的设计、优化和仿真。
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11.2 文档支持
11.2.1 相关文档
请参阅如下相关文档：
《反馈曲线图定义运算放大器交流性能》（文献编号：SBOA015）
11.3 相关链接
表 5 列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的快速链
接。
表 5. 相关链接
器件
产品文件夹
样片与购买
技术文档
工具与软件
支持和社区
TLV170
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
TLV2170
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
TLV4170
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
11.4 接收文档更新通知
如需接收文档更新通知，请访问 TI.com.cn 上的器件产品文件夹。单击右上角的“通知我”进行注册，即可每周接收
产品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.5 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.6 商标
TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
DesignSoft is a trademark of DesignSoft, Inc.
11.7 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.8 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
26
版权 © 2016–2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
17-Jun-2025
PACKAGING INFORMATION
Orderable part number
Status
Material type
(1)
(2)
Package | Pins
Package qty | Carrier
RoHS
(3)
Lead finish/
Ball material
MSL rating/
Peak reflow
(4)
(5)
NIPDAU | SN | NIPDAU Level-2-260C-1 YEAR
Op temp (°C)
Part marking
(6)
TLV170IDBVR
Active
Production
SOT-23 (DBV) | 5
3000 | LARGE T&R
Yes
-40 to 125
14QT
TLV170IDBVR.A
Active
Production
SOT-23 (DBV) | 5
3000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
14QT
TLV170IDBVRG4.A
Active
Production
SOT-23 (DBV) | 5
3000 | LARGE T&R
-
Call TI
Call TI
-40 to 125
TLV170IDBVT
Active
Production
SOT-23 (DBV) | 5
250 | SMALL T&R
Yes
TLV170IDBVT.A
Active
Production
SOT-23 (DBV) | 5
250 | SMALL T&R
Yes
NIPDAU | SN | NIPDAU Level-2-260C-1 YEAR
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
14QT
14QT
TLV170IDR
Active
Production
SOIC (D) | 8
2500 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLV170
TLV170IDR.A
Active
Production
SOIC (D) | 8
2500 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLV170
TLV170IDR.B
Active
Production
SOIC (D) | 8
2500 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLV170
TLV2170IDGKR
Active
Production
VSSOP (DGK) | 8
2500 | LARGE T&R
Yes
NIPDAU | SN
| NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
14NV
TLV2170IDGKR.A
Active
Production
VSSOP (DGK) | 8
2500 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
14NV
TLV2170IDGKRG4
Active
Production
VSSOP (DGK) | 8
2500 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
14NV
TLV2170IDGKRG4.A
Active
Production
VSSOP (DGK) | 8
2500 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
14NV
TLV2170IDGKT
Active
Production
VSSOP (DGK) | 8
250 | SMALL T&R
Yes
NIPDAU | SN
| NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
14NV
TLV2170IDGKT.A
Active
Production
VSSOP (DGK) | 8
250 | SMALL T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
14NV
TLV2170IDR
Active
Production
SOIC (D) | 8
2500 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TL2170
TLV2170IDR.A
Active
Production
SOIC (D) | 8
2500 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TL2170
TLV2170IDR.B
Active
Production
SOIC (D) | 8
2500 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TL2170
TLV2170IDRG4
Active
Production
SOIC (D) | 8
2500 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TL2170
TLV2170IDRG4.A
Active
Production
SOIC (D) | 8
2500 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TL2170
TLV2170IDRG4.B
Active
Production
SOIC (D) | 8
2500 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TL2170
TLV4170ID
Active
Production
SOIC (D) | 14
50 | TUBE
Yes
NIPDAU
Level-3-260C-168 HR
-40 to 125
TLV4170
TLV4170ID.A
Active
Production
SOIC (D) | 14
50 | TUBE
Yes
NIPDAU
Level-3-260C-168 HR
-40 to 125
TLV4170
TLV4170IDR
Active
Production
SOIC (D) | 14
2500 | LARGE T&R
Yes
NIPDAU
Level-3-260C-168 HR
-40 to 125
TLV4170
TLV4170IDR.A
Active
Production
SOIC (D) | 14
2500 | LARGE T&R
Yes
NIPDAU
Level-3-260C-168 HR
-40 to 125
TLV4170
TLV4170IDR.B
Active
Production
SOIC (D) | 14
2500 | LARGE T&R
Yes
NIPDAU
Level-3-260C-168 HR
-40 to 125
TLV4170
TLV4170IPWR
Active
Production
TSSOP (PW) | 14
2000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLV4170
TLV4170IPWR.A
Active
Production
TSSOP (PW) | 14
2000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLV4170
TLV4170IPWR.B
Active
Production
TSSOP (PW) | 14
2000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLV4170
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable part number
(1)
17-Jun-2025
Status
Material type
(1)
(2)
Package | Pins
Package qty | Carrier
RoHS
(3)
Lead finish/
Ball material
MSL rating/
Peak reflow
(4)
(5)
Op temp (°C)
Part marking
(6)
TLV4170IPWRG4
Active
Production
TSSOP (PW) | 14
2000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLV4170
TLV4170IPWRG4.A
Active
Production
TSSOP (PW) | 14
2000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLV4170
TLV4170IPWRG4.B
Active
Production
TSSOP (PW) | 14
2000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLV4170
Status: For more details on status, see our product life cycle.
(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.
(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.
(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.
(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.
(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.
Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jun-2025
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
TLV170IDBVR
SOT-23
DBV
5
3000
180.0
8.4
TLV170IDBVT
SOT-23
DBV
5
250
180.0
TLV170IDBVT
SOT-23
DBV
5
250
180.0
W
Pin1
(mm) Quadrant
3.2
3.2
1.4
4.0
8.0
Q3
8.4
3.2
3.2
1.4
4.0
8.0
Q3
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TLV170IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLV2170IDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
TLV2170IDGKRG4
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
TLV2170IDGKT
VSSOP
DGK
8
250
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
TLV2170IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLV2170IDRG4
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLV4170IDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TLV4170IPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TLV4170IPWRG4
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jun-2025
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV170IDBVR
SOT-23
DBV
5
3000
210.0
185.0
35.0
TLV170IDBVT
SOT-23
DBV
5
250
210.0
185.0
35.0
TLV170IDBVT
SOT-23
DBV
5
250
210.0
185.0
35.0
TLV170IDR
SOIC
D
8
2500
356.0
356.0
35.0
TLV2170IDGKR
VSSOP
DGK
8
2500
356.0
356.0
35.0
TLV2170IDGKRG4
VSSOP
DGK
8
2500
356.0
356.0
35.0
TLV2170IDGKT
VSSOP
DGK
8
250
356.0
356.0
35.0
TLV2170IDR
SOIC
D
8
2500
356.0
356.0
35.0
TLV2170IDRG4
SOIC
D
8
2500
356.0
356.0
35.0
TLV4170IDR
SOIC
D
14
2500
356.0
356.0
35.0
TLV4170IPWR
TSSOP
PW
14
2000
356.0
356.0
35.0
TLV4170IPWRG4
TSSOP
PW
14
2000
356.0
356.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jun-2025
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name
Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
TLV4170ID
D
SOIC
14
50
506.6
8
3940
4.32
TLV4170ID.A
D
SOIC
14
50
506.6
8
3940
4.32
Pack Materials-Page 3
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
A
5
(0.1)
2X 0.95
1.9
0.1 C
B
3.05
2.75
1.9
2
(0.15)
4
0.5
5X
0.3
0.2
3
C A B
NOTE 5
4X 0 -15
(1.1)
0.15
TYP
0.00
1.45
0.90
4X 4 -15
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/K 08/2024
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/K 08/2024
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/K 08/2024
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DGK0008A
VSSOP - 1.1 mm max height
SCALE 4.000
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
A
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
6X 0.65
8
1
2X
3.1
2.9
NOTE 3
1.95
4
5
8X
B
3.1
2.9
NOTE 4
0.38
0.25
0.13
C A B
0.23
0.13
SEE DETAIL A
0.25
GAGE PLANE
1.1 MAX
0 -8
0.15
0.05
0.7
0.4
DETAIL A
A 20
TYPICAL
4214862/A 04/2023
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
DGK0008A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
SYMM
8X (1.4)
8X (0.45)
(R0.05) TYP
1
8
SYMM
6X (0.65)
5
4
SEE DETAILS
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4214862/A 04/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
DGK0008A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
SYMM
(R0.05) TYP
8X (1.4)
8X (0.45)
1
8
SYMM
6X (0.65)
5
4
(4.4)
SOLDER PASTE EXAMPLE
SCALE: 15X
4214862/A 04/2023
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0014A
SOIC - 1.75 mm max height
SCALE 1.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
6.2
TYP
5.8
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
12X 1.27
14
1
2X
7.62
8.75
8.55
NOTE 3
7
8
B
4.0
3.8
NOTE 4
SEE DETAIL A
14X
0.51
0.31
0.25
C A B
1.75 MAX
0.25
TYP
0.13
0.25
GAGE PLANE
0 -8
0.25
0.10
1.27
0.40
DETAIL A
TYPICAL
4220718/A 09/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side.
5. Reference JEDEC registration MS-012, variation AB.
www.ti.com
EXAMPLE BOARD LAYOUT
D0014A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
14X (1.55)
SYMM
1
14
14X (0.6)
12X (1.27)
SYMM
8
7
(R0.05)
TYP
(5.4)
LAND PATTERN EXAMPLE
SCALE:8X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220718/A 09/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0014A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
14X (1.55)
SYMM
1
14
14X (0.6)
12X (1.27)
SYMM
7
8
(5.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:8X
4220718/A 09/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
PW0014A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
12X 0.65
14
1
2X
5.1
4.9
NOTE 3
3.9
4X (0 -12 )
7
8
14X
B
4.5
4.3
NOTE 4
0.30
0.17
0.1
C A B
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220202/B 12/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0014A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
14X (1.5)
(R0.05) TYP
1
14
14X (0.45)
SYMM
12X (0.65)
8
7
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220202/B 12/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0014A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
14X (1.5)
SYMM
(R0.05) TYP
1
14X (0.45)
14
SYMM
12X (0.65)
8
7
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220202/B 12/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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